CN102194773B - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN102194773B
CN102194773B CN201110071731.1A CN201110071731A CN102194773B CN 102194773 B CN102194773 B CN 102194773B CN 201110071731 A CN201110071731 A CN 201110071731A CN 102194773 B CN102194773 B CN 102194773B
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CN
China
Prior art keywords
film
semiconductor device
dielectric film
separating tank
metal film
Prior art date
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Active
Application number
CN201110071731.1A
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English (en)
Chinese (zh)
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CN102194773A (zh
Inventor
理崎智光
中西章滋
岛崎洸一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ablic Inc
Original Assignee
Seiko Instruments Inc
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Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Publication of CN102194773A publication Critical patent/CN102194773A/zh
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Publication of CN102194773B publication Critical patent/CN102194773B/zh
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/40—Encapsulations, e.g. protective coatings characterised by their materials
    • H10W74/47—Encapsulations, e.g. protective coatings characterised by their materials comprising organic materials, e.g. plastics or resins
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01354—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
    • H10P52/40—Chemomechanical polishing [CMP]
    • H10P52/402—Chemomechanical polishing [CMP] of semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00—Cutting or separating of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7402—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/121—Arrangements for protection of devices protecting against mechanical damage
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/015—Manufacture or treatment of bond wires

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Dicing (AREA)
  • Semiconductor Integrated Circuits (AREA)
CN201110071731.1A 2010-03-15 2011-03-15 半导体装置及其制造方法 Active CN102194773B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2010-058449 2010-03-15
JP2010058449A JP5638818B2 (ja) 2010-03-15 2010-03-15 半導体装置およびその製造方法

Publications (2)

Publication Number Publication Date
CN102194773A CN102194773A (zh) 2011-09-21
CN102194773B true CN102194773B (zh) 2015-08-19

Family

ID=44559162

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201110071731.1A Active CN102194773B (zh) 2010-03-15 2011-03-15 半导体装置及其制造方法

Country Status (5)

Country Link
US (1) US9299629B2 (enExample)
JP (1) JP5638818B2 (enExample)
KR (1) KR101765928B1 (enExample)
CN (1) CN102194773B (enExample)
TW (1) TWI527104B (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017028056A (ja) * 2015-07-21 2017-02-02 トヨタ自動車株式会社 半導体装置の製造方法
KR102428328B1 (ko) * 2017-07-26 2022-08-03 삼성전자주식회사 반도체 장치
JP7240149B2 (ja) * 2018-08-29 2023-03-15 キオクシア株式会社 半導体装置
KR20230031712A (ko) 2021-08-27 2023-03-07 삼성전자주식회사 크랙 방지 구조를 포함한 반도체 소자

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5136354A (en) * 1989-04-13 1992-08-04 Seiko Epson Corporation Semiconductor device wafer with interlayer insulating film covering the scribe lines

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0750700B2 (ja) * 1989-06-27 1995-05-31 三菱電機株式会社 半導体チップの製造方法
JPH05315076A (ja) * 1992-05-14 1993-11-26 Toshiba Corp 端面発光型ｅｌ素子のピクセル形成方法
JP3182891B2 (ja) * 1992-07-03 2001-07-03 セイコーエプソン株式会社 半導体装置
JP3269536B2 (ja) * 1993-02-19 2002-03-25 株式会社デンソー 半導体装置
JP2894165B2 (ja) * 1993-07-24 1999-05-24 ヤマハ株式会社 半導体装置
US7087452B2 (en) * 2003-04-22 2006-08-08 Intel Corporation Edge arrangements for integrated circuit chips
US7566634B2 (en) * 2004-09-24 2009-07-28 Interuniversitair Microelektronica Centrum (Imec) Method for chip singulation
JP2006148007A (ja) * 2004-11-24 2006-06-08 Sharp Corp 半導体装置の製造方法とその製造方法によって製造された半導体装置
US7615469B2 (en) * 2007-05-25 2009-11-10 Semiconductor Components Industries, L.L.C. Edge seal for a semiconductor device and method therefor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5136354A (en) * 1989-04-13 1992-08-04 Seiko Epson Corporation Semiconductor device wafer with interlayer insulating film covering the scribe lines

Also Published As

Publication number Publication date
JP2011192846A (ja) 2011-09-29
TW201203338A (en) 2012-01-16
KR101765928B1 (ko) 2017-08-07
CN102194773A (zh) 2011-09-21
US20110221043A1 (en) 2011-09-15
KR20110103881A (ko) 2011-09-21
US9299629B2 (en) 2016-03-29
TWI527104B (zh) 2016-03-21
JP5638818B2 (ja) 2014-12-10

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Effective date of registration: 20160322

Address after: Chiba County, Japan

Patentee after: DynaFine Semiconductor Co.,Ltd.

Address before: Chiba, Chiba, Japan

Patentee before: Seiko Instruments Inc.

CP01 Change in the name or title of a patent holder
CP01 Change in the name or title of a patent holder

Address after: Chiba County, Japan

Patentee after: ABLIC Inc.

Address before: Chiba County, Japan

Patentee before: DynaFine Semiconductor Co.,Ltd.

CP02 Change in the address of a patent holder
CP02 Change in the address of a patent holder

Address after: Nagano

Patentee after: ABLIC Inc.

Address before: Chiba County, Japan

Patentee before: ABLIC Inc.