CN102157474B - 晶片级堆叠裸片封装 - Google Patents
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- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
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Abstract
本文献尤其是论述一种包含制造于半导体衬底中的第一和第二离散组件的IC封装。所述第一和第二离散组件可在所述半导体衬底中彼此邻近,且集成电路裸片可安装于所述半导体衬底上并耦合到所述第一和第二离散组件。
Description
背景技术
例如手机、个人数据助理、数码相机、膝上型计算机等电子装置大体上包含若干封装的半导体集成电路(IC)芯片和表面安装组件,所述芯片和组件组装到互连衬底上。将更多的功能性和特征并入到电子装置中,同时减小电子装置的尺寸,是持续的市场需求。这又对互连衬底的设计、尺寸和组装提出增加的需求。随着组装的组件数目增加,衬底面积和成本增加,同时对较小形状因数的需求增加。
发明内容
本文献尤其论述一种IC封装,其包含上面安装有IC裸片的单片电路,其中模制化合物安置于IC裸片上方以形成IC封装。所述单片电路可包含制造于半导体衬底中的彼此邻近的第一和第二离散组件。IC裸片可安装到半导体衬底的无源侧且通过多个穿衬底通孔耦合到第一和第二离散组件。IC封装可包含位于半导体衬底的有源侧上的多个接合垫,用于将IC封装安装到互连衬底。
希望此概述提供本专利申请案的标的物的概述。不希望其提供本发明的专门或详尽解释。包含详细描述内容以提供关于本专利申请案的更多信息。
附图说明
图式不一定按比例绘制,在图中,相同标号可在不同视图中描述相似的组件。具有不同字母后缀的相同标号可表示相似组件的实例。图式借助于实例而不是限制来大体上说明本文献中论述的各种实施例。
图1大体上说明晶片级堆叠裸片IC封装的实例的横截面图。
图2大体上说明图1的晶片级堆叠裸片IC封装的仰视横截面图。
图3大体上说明图1的晶片级堆叠裸片IC封装的俯视横截面图。
图4说明制造于单个半导体晶片中的第一和第二离散组件的实例。
图5说明安装到膜载体以用于IC封装建构期间的支撑的图4的半导体晶片的实例。
图6说明经薄化以暴露穿衬底通孔的图5的半导体晶片的实例。
图7说明添加到图6的半导体晶片的经图案化导电层的实例。
图8说明在图7的半导体晶片中蚀刻的凹槽的实例。
图9说明用电绝缘材料填充以形成隔离间隙的图8的凹槽的实例。
图10说明安装到图9的半导体晶片的IC裸片倒装芯片的实例。
图11说明围绕图10的IC裸片和半导体晶片安置的电绝缘材料的实例。
具体实施方式
本发明人已尤其认识到可通过在半导体衬底(例如,硅晶片)中制造至少一个离散组件且在半导体衬底上安装IC裸片来产生紧凑的IC封装。可接着用电绝缘材料(例如,模制化合物)覆盖IC裸片并切开IC裸片以形成IC封装。在一实例中,IC封装可包含多个触点区以用于以倒装芯片方式安装到互连衬底(例如,印刷电路板)。
在一实例中,将IC封装内的IC裸片以倒装芯片方式安装到半导体衬底的无源侧且电耦合到离散组件。半导体衬底可包含多个穿衬底通孔,其可将IC裸片电耦合到离散组件且电耦合到半导体衬底的有源侧的所述多个触点区。
图1大体上说明IC封装100的实例的横截面图。IC封装100可包含第一离散组件102和第二离散组件104,所述组件被制造到半导体衬底106中。换句话说,第一和第二离散组件102、104连同半导体衬底106形成单片集成电路。在一实例中,半导体衬底106可包含硅晶片。在其它实例中,半导体衬底106可包含锗、砷化镓、碳化硅或分层半导体衬底(例如,绝缘体上硅)。在一些实例中,半导体衬底106可经掺杂,如所属领域的技术人员已知。如本文中提及,半导体衬底106包含有源侧108和无源侧110。半导体衬底106的有源侧108可包含半导体衬底106的表面,在其中制造有第一和第二离散组件102、104。半导体衬底106的无源侧110与有源侧108相对。
在一实例中,第一和第二离散组件102、104在半导体衬底106内彼此邻近。在一实例中,半导体衬底106可包含隔离间隙112,其安置于第一与第二离散组件102、104之间以用于电隔离第一离散组件102与第二离散组件104。在一实例中,通过在半导体衬底106中蚀刻凹槽且在凹槽中沉积电绝缘材料来形成隔离间隙112。在一实例中,电绝缘材料可包含模制化合物,例如环氧树脂、硅树脂、聚酰亚胺或这些材料中的一者或一者以上的组合。在一实例中,隔离间隙112的宽度可基于第一和第二离散组件102、104处存在的电压。值得注意的是,当较高电压可存在于第一或第二离散组件102、104处时,隔离间隙112应较宽以提供增大的电绝缘。
在一实例中,IC封装100还可包含多个穿衬底通孔122,其与导电层116和124组合地将半导体衬底106的有源侧108上的第一和第二离散组件102、104电耦合到半导体衬底106的无源侧110上的元件。换句话说,所述多个穿衬底通孔122(例如,当半导体衬底106为硅时为穿硅通孔(TSV))穿过半导体衬底106提供有源侧108与无源侧110之间的电耦合。通过穿过半导体衬底106蚀刻孔隙且在所述孔隙内沉积导电材料来形成所述多个穿衬底通孔122中的每一者。在一些实例中,导电材料可包含钨。
在某些实例中,IC封装100可包含IC裸片114,其安装在半导体衬底106上且电耦合到第一和第二离散组件102、104。IC裸片114以及第一和第二离散组件102、104形成用于IC封装100的电路。在一实例中,IC裸片114安装在半导体衬底106的无源侧110上。IC裸片114借助所述多个穿衬底通孔122电耦合到第一和第二离散组件102、104。
在一实例中,第一经图案化导电层116可安置在半导体衬底106的无源侧108上。第一经图案化导电层116提供IC裸片114到所述多个穿衬底通孔122的电耦合。第一经图案化导电层还可提供IC裸片114上的不同触点之间的耦合。在一实例中,第一经图案化导电层制造于半导体衬底106的无源侧110上,使得经图案化导电层116的一部分安置在IC裸片114与半导体衬底106之间。第一经图案化导电层116可包含多个迹线以用于将IC裸片114电耦合到所述多个穿衬底通孔122。在一实例中,第一经图案化导电层116还可包含多个导电区(例如,接合垫)以用于将IC裸片114安装并电耦合到经图案化导电层116。在一实例中,IC裸片114可以倒装芯片方式安装到经图案化导电层116。在一实例中,IC裸片114可使用球形栅格阵列的焊球118来在电学上和在物理上将IC裸片114耦合到第一经图案化导电层116。
IC裸片114可使用所述多个穿衬底通孔中的至少一者电耦合到第一和第二离散组件102、104。举例来说,IC裸片114可耦合到第一经图案化导电层116,所述经图案化导电层116耦合到穿衬底通孔122。穿衬底通孔122可接着耦合到第一和第二离散组件102、104。在一实例中,第二经图案化导电层124制造于半导体衬底106的有源侧108上以用于将多个穿衬底通孔122耦合到第一和第二离散组件102、104。
在一实例中,IC封装100可包含多个导电区以用于将IC封装100物理安装且电耦合到互连衬底(例如,印刷电路板)。在一实例中,所述多个导电区可为第二经图案化导电层124的外部暴露部分。在一实例中,第二经图案化导电层124将IC裸片114电耦合到所述多个导电区中的至少一者以实现外部电连接。虽然IC裸片114经展示为耦合到半导体衬底106的无源侧110,但在其它实例中,IC裸片114可耦合到半导体衬底106的有源侧108,且用于将IC封装100耦合到互连衬底的多个导电区安置在半导体衬底106的无源侧110上。在一实例中,用于IC裸片114的输入/输出引脚借助所述多个穿衬底通孔122中的一者(或一者以上)耦合到触点区124。
在一实例中,电绝缘材料120安置于IC裸片114和半导体衬底106的无源侧110的至少一部分上方。电绝缘材料120使IC裸片114电绝缘以免受外部影响。在一实例中,电绝缘材料120可包含模制化合物,例如环氧树脂、硅树脂、聚酰亚胺或这些材料中的一者或一者以上的组合。在一实例中,电绝缘材料120经安置以使得IC裸片114背侧(底部)表面被暴露以实现较好的热耗散。
在一实例中,第一和第二离散组件102、104可包含晶体管,且IC裸片114可包含用于所述晶体管的控制器。明确地说,第一和第二离散组件可包含高侧和低侧金属氧化物半导体场效应晶体管(MOSF7T),其连同IC裸片114一起形成功率转换器。在特定实例中,功率转换器可包含降压转换器。
图2大体上说明来自图1的IC封装100的实例的仰视横截面图。图2说明半导体衬底106的有源侧108,其展示第二经图案化导电层124和多个穿衬底通孔122。在一实例中,第二经图案化导电层124的第一源极区202可耦合到高侧MOSFET的源极。另外,在一实例中,第二源极区204耦合到低侧MOSFET的源极。
在一实例中,高侧和低侧MOSFET的漏极耦合到穿衬底通孔122以用于耦合到半导体衬底106的无源侧110。在一实例中,高侧MOSFET的漏极耦合到第一群组(大体上在区206处展示)的穿衬底通孔122,且低侧MOSFET的漏极耦合到第二群组(大体上在区208处展示)的穿衬底通孔122。在一实例中,第二经图案化导电层124将高侧源极电耦合到低侧漏极。因此,低侧晶体管的漏极电耦合到第一源极区202。在一实例中,第一源极区202和第二源极区204可包含大表面区域。半导体衬底106的有源侧108上的耦合到高侧和低侧MOSFET的源极的大表面区域可归因于可用于外部接合垫放置的大热耗散区域(例如,所述多个导电区)而提供良好热性能。另外,在一实例中,将多个导电区放置在半导体衬底106的有源侧108上使得将高侧和低侧MOSFET放置在多个导电区附近以有效地从高侧和低侧MOSFET移除热量。
如图2所示,使用多个穿衬底通孔122(说明为正方形)来将IC裸片114耦合到IC封装100的外部接合垫。另外,图2说明隔离间隙112。隔离间隙112可包含越过半导体衬底106在高侧MOSFET与低侧MOSFET之间延伸的凹槽。图2还说明耦合到高侧MOSFET的栅极的高侧栅极区210。还展示低侧栅极区212,且其耦合到低侧MOSFET的栅极。
图3说明IC封装100的无源侧110的实例的大体上俯视横截面图。图3说明半导体衬底106的无源侧110上的第一经图案化导电层116。如图所示,第一群组206的穿衬底通孔122耦合到第一经图案化导电层116的第一漏极区302(其用于高侧漏极)。第一漏极区302又耦合到控制器114(虚线展示控制器114在无源侧110上的位置。类似地,第二群组304的穿衬底通孔122耦合到用于低侧漏极和高侧源极的第二漏极区304。IC裸片114在区306处耦合到高侧MOSFET的栅极,且在区308处耦合到低侧MOSFET的栅极。IC裸片114可用栅极区306和308来控制高侧MOSFET和低侧MOSFET。
图4到图11说明用于制作晶片级堆叠裸片IC封装(例如IC封装100)的方法。在图4中,将第一和第二离散半导体102、104制造在单个半导体晶片(例如衬底106)中。在一实例中,制造可包含掩蔽和蚀刻半导体晶片以及沉积适当材料以在半导体晶片中形成第一和第二离散半导体的多个步骤。接着通过蚀刻和沉积金属(例如钨)以形成穿衬底通孔122来修正有源侧108。接下来,将第二经图案化导电层124添加到有源侧108。在图5处,将半导体晶片安装到在IC封装构造期间用于支撑的膜载体502。在图6处,使半导体晶片的无源侧110变薄,以使穿衬底通孔122暴露。在一实例中,使半导体晶片变薄到约25微米。在图7处,将第一经图案化导电层116添加到半导体衬底106的无源侧110。添加第一经图案化导电层116可包含为漏极区302、304以及用于耦合到穿衬底通孔122的区添加较厚的具有图案的铜金属化。在图8处,在半导体衬底106的无源侧中,在第一离散组件102与第二离散组件104之间,等离子蚀刻半导体衬底106中用于隔离间隙112的凹槽802。在图9处,用电绝缘材料填充凹槽802,以形成隔离间隙112。在一些实例中,电绝缘材料可包含高强度环氧树脂或高强度玻璃。在图10处,IC裸片114为安装到半导体衬底106的倒装芯片。在图11处,将电绝缘材料安置在IC裸片114周围以及半导体衬底106的无源侧110上。图4到图10中所说明的过程在单个晶片上的多个位置中完成,且接着锯开所述晶片以产生个别IC封装100。
额外附注
上文的详细描述包含对附图的参考,附图形成详细描述的一部分。图式以说明的方式展示可实践本发明的具体实施例。这些实施例在本文也称为“实例”。此些实例可包含除所展示和描述的元件之外的元件。然而,本发明人也预期仅提供所展示和描述的元件的实例。
本文献中所提到的所有公开案、专利和专利文献均以全文引用的方式并入本文中,就像以引用的方式个别地并入本文中一样。如果本文献与以引用的方式并入的文献之间出现不一致的用法,那么应将所并入参考中的用法视为本文献的用法的补充;对于不能调和的不一致,以本文献中的用法为主。
如在专利文献中常见,在本文献中,使用属于“一”来包含一个或一个以上,与“至少一个”或“一个或一个以上”的任何其它实例或用法无关。在本文献中,使用术语“或”来指代非独占性或,使得“A或B”包含“A但不是B”、“B但不是A”以及“A和B”,除非另有指示。在所附权利要求书中,使用术语“包含”和“在其中”作为相应术语“包括”和“其中”的易懂均等物。另外,在所附权利要求书中,术语“包含”和“包括”是无限制的,即包含权利要求中除此术语之后列出的元素之外的元素的系统、装置、物品或过程仍被认为术语所述权利要求的范围。此外,在所附权利要求书中,仅将术语“第一”、“第二”和“第三”等用作标签,且无意对其对象强加数字要求。
另外,在本文献中,当称第一元件(例如材料或IC裸片)“在”第二元件“上”(例如安装在第二元件上)时,第一元件可直接在第二元件上,或也可存在介入元件。在本文献中,当称第一元件(例如层、区或衬底)“耦合到”第二元件时,第一元件可直接耦合到第二元件,或可存在一个或一个以上介入元件。相反,当称第一元件“直接在”另一元件“上”或“直接耦合到”另一元件时,不存在介入元件。
本文所描述的方法实例可至少部分地由机器或计算机实施。一些实例可包含编码有指令的计算机可读媒体或机器可读媒体,所述指令可操作以配置电子装置以执行如上述实例中所描述的方法。此些方法的实施方案可包含代码,例如微码、汇编语言码、高级语言码等。此代码可包含用于执行各种方法的计算机可读指令。所述代码可形成计算机程序产品的若干部分。另外,所述代码可在执行期间或在其它时间有形地存储在一个或一个以上易失性或非易失性计算机可读媒体上。这些计算机可读媒体可包含(但不限于)硬盘、可装卸磁盘、可装卸光盘(例如压缩光盘和数字视频盘)、磁带、存储卡或存储棒、随机存取存储器(RAM)、只读存储器(ROM)等。
上述描述既定是说明性的而非限制性的。举例来说,上述实例(或其一个或一个以上方面)可彼此结合而使用。举例来说,所属领域的技术人员在回顾以上描述后就可使用其它实施例。提供说明书摘要以遵守37C.F.R.§1.72(b),以允许读者快速地确定技术揭示内容的本质。应理解,提出说明书摘要并不是为了将其用于解释或限制所附权利要求书的范围或意义。此外,在以上的具体实施方式中,可将各种特征分组在一起以将揭示内容连成一个整体。这不应被解释为希望未主张的所揭示特征对任一权利要求是不可或缺的。相反,本发明的标的物可在于特定所揭示实施例的并非所有特征。因此,所附权利要求书特此并入具体实施方式中,其中每一权利要求独立地作为一单独实施例。应参考所附权利要求书以及此权利要求书有权具有的均等物的完整范围,来确定本发明的范围。
Claims (19)
1.一种集成电路IC封装,其包括:
半导体衬底;
制造于所述半导体衬底中的第一离散组件;
制造于所述半导体衬底中的第二离散组件,其中所述第一离散组件邻近于所述第二离散组件;以及
安装于所述半导体衬底上且耦合到所述第一离散组件和所述第二离散组件的集成电路IC裸片,
其中所述半导体衬底包含有源侧和与所述有源侧对置的无源侧,所述有源侧包括所述第一和第二离散组件,且
其中所述IC裸片安装到所述半导体衬底的所述无源侧。
2.根据权利要求1所述的IC封装,其中所述半导体衬底包含硅晶片。
3.根据权利要求1和权利要求2中任一权利要求所述的IC封装,其中所述IC封装包含多个穿衬底通孔,其中第一穿衬底通孔耦合到所述第一离散组件,且第二穿衬底通孔耦合到所述第二离散组件;以及
位于所述半导体衬底的所述无源侧上的经图案化导电层,所述经图案化导电层耦合到所述第一和第二穿衬底通孔,其中所述IC裸片通过所述经图案化导电层耦合到所述第一穿衬底通孔和所述第二穿衬底通孔。
4.根据权利要求3所述的IC封装,其包括位于所述半导体衬底的所述有源侧上的用于耦合到外部互连衬底的多个导电区,其中至少一个穿衬底通孔将所述IC裸片耦合到至少一个导电区。
5.根据权利要求3所述的IC封装,其中所述第一离散组件包含第一晶体管,所述第二离散组件包含第二晶体管,且所述IC裸片包含用于控制所述第一和第二晶体管的操作以使得所述IC封装作为功率转换器而操作的控制器。
6.根据权利要求5所述的IC封装,其中所述第一晶体管包含高侧金属氧化物半导体场效应晶体管(MOSFET),且第二晶体管包含低侧MOSFET,其中至少一个穿衬底通孔将所述高侧MOSFET的源极耦合到所述低侧MOSFET的漏极。
7.根据权利要求1所述的IC封装,其包括位于所述半导体衬底中在所述第一离散组件与所述第二离散组件之间的隔离间隙。
8.根据权利要求7所述的IC封装,其中所述隔离间隙包含蚀刻于所述半导体衬底中的凹槽,绝缘物沉积于所述凹槽中。
9.根据权利要求1所述的IC封装,其中所述IC裸片以倒装芯片方式安装到所述半导体衬底。
10.根据权利要求1所述的IC封装,其包括安置于所述IC裸片和所述半导体衬底的所述无源侧的至少一部分上的电绝缘材料。
11.一种制作集成电路(IC)封装的方法,其包括:
在半导体衬底中制造第一和第二离散组件,其中所述第一离散组件邻近于所述第二离散组件;
将集成电路(IC)裸片安装于所述半导体衬底的第一侧上,其中所述IC裸片耦合到所述第一和第二离散组件;以及
使电绝缘材料固化于所述IC裸片和所述半导体衬底的所述第一侧的至少一部分上,
其中制造所述第一和第二离散组件包含在所述半导体衬底的第二侧上制造所述第一和第二离散组件。
12.根据权利要求11所述的方法,其包括:
在所述半导体衬底中制造多个穿衬底通孔,其中第一穿衬底通孔耦合到所述第一离散组件,第二穿衬底通孔耦合到所述第二离散组件,且第三衬底通孔耦合到所述IC裸片。
13.根据权利要求12所述的方法,其包括:
在半导体衬底的所述第一侧上沉积经图案化导电层,所述经图案化导电层耦合到所述多个穿衬底通孔中的至少一者;
其中所述安装所述IC裸片包含将所述IC裸片耦合到所述经图案化导电层。
14.根据权利要求13所述的方法,其中所述沉积所述经图案化导电层包含将耦合到所述第一离散组件的所述第一穿衬底通孔耦合到所述IC裸片和将耦合到所述第二离散组件的所述第二穿衬底通孔耦合到所述IC裸片。
15.根据权利要求14所述的方法,其包括:
在所述半导体衬底的所述第二侧上形成用于耦合到外部电路的多个导电区。
16.根据权利要求11到权利要求15中任一权利要求所述的方法,其包括:
在所述半导体衬底中在所述第一与第二离散组件之间蚀刻凹槽;以及
在所述凹槽中沉积绝缘材料。
17.根据权利要求11到权利要求15中任一权利要求所述的方法,其中所述安装包含将所述IC裸片以倒装芯片方式安装到所述半导体衬底。
18.一种功率转换器系统,其包括:
具有有源侧和无源侧的硅晶片;
制造于所述硅晶片的所述有源侧中的高侧晶体管;
制造于所述硅晶片的所述有源侧中的低侧晶体管,所述低侧晶体管邻近于所述高侧晶体管;
形成于所述硅晶片中在所述高侧晶体管与所述低侧晶体管之间的隔离间隙;
多个穿硅通孔,其中第一穿硅通孔耦合到所述高侧晶体管的漏极,且第二穿硅通孔耦合到所述低侧晶体管的漏极;
沉积于所述硅晶片的所述无源侧上的经图案化导电层;
安装到所述硅晶片的所述无源侧且耦合到所述经图案化导电层的集成电路(IC)裸片,所述IC裸片包含用于所述高侧晶体管和所述低侧晶体管的控制器,其中所述第一和第二离散组件是通过将所述第一和第二穿硅通孔耦合到所述IC裸片的所述经图案化导电层而耦合到所述IC裸片;
安置于所述IC裸片和所述硅晶片的所述无源侧的至少一部分上的电绝缘材料;以及
位于所述硅晶片的所述有源侧上的用于耦合到印刷电路板的多个接合垫,至少一个接合垫耦合到所述高侧晶体管,至少一个接合垫耦合到所述低侧晶体管,且至少一个接合垫耦合到耦合于所述IC裸片的穿硅通孔。
19.根据权利要求18所述的功率转换器系统,其中所述多个接合垫经配置以用于以倒装芯片方式安装到印刷电路板。
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US12/683,058 US8115260B2 (en) | 2010-01-06 | 2010-01-06 | Wafer level stack die package |
US12/683,058 | 2010-01-06 |
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CN102157474A CN102157474A (zh) | 2011-08-17 |
CN102157474B true CN102157474B (zh) | 2015-10-21 |
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KR (1) | KR101834389B1 (zh) |
CN (1) | CN102157474B (zh) |
DE (1) | DE102011008457A1 (zh) |
TW (1) | TWI528504B (zh) |
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US8115260B2 (en) | 2010-01-06 | 2012-02-14 | Fairchild Semiconductor Corporation | Wafer level stack die package |
US8384430B2 (en) * | 2010-08-16 | 2013-02-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | RC delay detectors with high sensitivity for through substrate vias |
JP5988192B2 (ja) * | 2011-12-06 | 2016-09-07 | 不二越機械工業株式会社 | ワーク貼着方法およびワーク貼着装置 |
US9460972B2 (en) * | 2012-01-09 | 2016-10-04 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming reduced surface roughness in molded underfill for improved C-SAM inspection |
TWI538125B (zh) * | 2012-03-27 | 2016-06-11 | 南茂科技股份有限公司 | 半導體封裝結構的製作方法 |
US9613917B2 (en) | 2012-03-30 | 2017-04-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package-on-package (PoP) device with integrated passive device in a via |
US20140070329A1 (en) * | 2012-09-07 | 2014-03-13 | Fairchild Semiconductor Corporation | Wireless module with active and passive components |
US9165887B2 (en) | 2012-09-10 | 2015-10-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device with discrete blocks |
US8975726B2 (en) | 2012-10-11 | 2015-03-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | POP structures and methods of forming the same |
US9391041B2 (en) | 2012-10-19 | 2016-07-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fan-out wafer level package structure |
CN103441124B (zh) * | 2013-08-27 | 2016-01-06 | 矽力杰半导体技术(杭州)有限公司 | 电压调节器的叠层封装方法及相应的叠层封装装置 |
US9373527B2 (en) | 2013-10-30 | 2016-06-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Chip on package structure and method |
US9679839B2 (en) | 2013-10-30 | 2017-06-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Chip on package structure and method |
JP2015216263A (ja) * | 2014-05-12 | 2015-12-03 | マイクロン テクノロジー, インク. | 半導体装置 |
JP2016058655A (ja) * | 2014-09-11 | 2016-04-21 | 株式会社ジェイデバイス | 半導体装置の製造方法 |
KR102505189B1 (ko) * | 2015-07-22 | 2023-03-02 | 인텔 코포레이션 | 다층 패키지 |
US10050025B2 (en) * | 2016-02-09 | 2018-08-14 | Texas Instruments Incorporated | Power converter monolithically integrating transistors, carrier, and components |
CN106098643A (zh) * | 2016-08-10 | 2016-11-09 | 江阴芯智联电子科技有限公司 | 双向集成芯片重布线埋入式基板结构及其制作方法 |
US10312194B2 (en) * | 2016-11-04 | 2019-06-04 | General Electric Company | Stacked electronics package and method of manufacturing thereof |
US10840216B2 (en) * | 2019-03-05 | 2020-11-17 | Cerebras Systems Inc. | Systems and methods for powering an integrated circuit having multiple interconnected die |
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- 2011-01-06 CN CN201110005659.2A patent/CN102157474B/zh not_active Expired - Fee Related
- 2011-01-06 TW TW100100511A patent/TWI528504B/zh active
- 2011-01-06 DE DE102011008457A patent/DE102011008457A1/de not_active Withdrawn
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Also Published As
Publication number | Publication date |
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KR101834389B1 (ko) | 2018-03-05 |
DE102011008457A1 (de) | 2011-07-28 |
CN102157474A (zh) | 2011-08-17 |
KR20110081097A (ko) | 2011-07-13 |
US20120088331A1 (en) | 2012-04-12 |
TWI528504B (zh) | 2016-04-01 |
TW201135878A (en) | 2011-10-16 |
US8211747B2 (en) | 2012-07-03 |
US20110163391A1 (en) | 2011-07-07 |
US8115260B2 (en) | 2012-02-14 |
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