CN101465346A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN101465346A
CN101465346A CNA2008101878821A CN200810187882A CN101465346A CN 101465346 A CN101465346 A CN 101465346A CN A2008101878821 A CNA2008101878821 A CN A2008101878821A CN 200810187882 A CN200810187882 A CN 200810187882A CN 101465346 A CN101465346 A CN 101465346A
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silicon epitaxy
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金相喆
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Oregon global strategy advisor, Limited by Share Ltd.
Adeia Semiconductor Technologies LLC
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    • H—ELECTRICITY
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
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    • H01—ELECTRIC ELEMENTS
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
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Abstract

本发明实施例涉及一种半导体器件及其制造方法。根据本发明实施例，一种半导体器件可以包括：第一器件；形成在第一器件上和/或上方的硅外延层；形成在硅外延层上和/或上方的第二器件；以及穿过硅外延层形成的连接通孔，该连接通孔可以将第一器件和第二器件电互连。根据本发明实施例，一种制造半导体器件的方法可以包括：形成第一器件；在第一器件上和/或上方形成硅外延层；穿过硅外延层形成连接通孔；以及在硅外延层上和/或上方形成第二器件，以便第二器件可以电连接至连接通孔。

Description

半导体器件及其制造方法
本申请基于35U.S.C119要求第10-2007-0135834号(于2007年12月21日递交)韩国专利申请的优先权，其全部内容结合于此作为参考。
技术领域
本发明涉及一种半导体器件，更具体地，涉及一种半导体器件及其制造方法，该半导体器件及其制造方法能够将多个器件垂直地层叠到单个封装(single package)内。
背景技术
一种能减小所安装部件的尺寸的技术可以包括片上系统(SoC)技术和系统级封装(SIP)技术，其中片上系统(SoC)技术用于将多个单独的器件制造在一个芯片内，而系统级封装(SIP)技术用于将多个单独的器件集成在单个封装内。可能需要这些系统(system)来减小半导体器件的重量和尺寸。
SIP技术可以是一种将多个硅芯片水平地和垂直地安装到单个封装内的技术。SIP技术可以是相关技术的多芯片组件(multi-chipmodule)(MCM)概念的延伸。根据相关技术的MCM，在制造封装时主要实施水平的安装。对于SIP来说，另一方面，可以主要实施用于垂直层叠多个芯片的技术。
垂直层叠多个芯片的相关技术可以包括这样一种方法，即在第一半导体衬底和第二半导体衬底上和/或上方形成预定的半导体器件，以及使用粘合剂将第一半导体衬底和第二半导体衬底粘合(bonding)。
通道孔(Via hole)可以贯穿第一半导体衬底和第二半导体衬底，并且可以在各个通道孔中形成通道孔电极(via electrode)。从而，第一半导体衬底和第二半导体衬底可以相互电连接。
相关技术的SIP技术可能具有各种问题。例如，可能很难将第一半导体衬底和第二半导体衬底粘合。此外，由于对第二半导体衬底的背面进行打磨(grinding)的技术的限制，可能很难形成通道孔以及通道孔电极以将第一半导体衬底和第二半导体衬底电互连。
发明内容
本发明实施例涉及一种半导体器件，以及涉及一种半导体器件及其制造方法，该半导体器件及其制造方法可以能够将多个器件垂直地层叠在单个封装内。
根据本发明实施例，一种半导体器件可以包括以下中的至少之一：第一器件；形成于第一器件上和/或上方的硅外延层；形成于硅外延层上和/或上方的第二器件；连接通孔(connection via)，形成穿过硅外延层，该连接通孔将第一器件与第二器件电互连(electrically interconnect)。
根据本发明实施例，一种制造半导体器件的方法可以以下中的至少之一：形成第一器件；在第一器件上和/或上方形成硅外延层；穿过硅外延层形成连接通孔；在硅外延层上和/或上方形成第二器件以便第二器件可以电连接至连接通孔。
附图说明
实例图1到图6是示出一种根据本发明实施例的半导体器件及其制造方法的附图。
具体实施方式
根据本发明实施例，一种半导体器件及其制造方法的特征可以在于，可以在其上形成有第一器件的第一半导体衬底上和/或上方形成外延层。可以在外延层上和/或上方设置第二器件。这可以不同于相关技术的方法，其中该相关技术的方法用于将其上形成有第一器件的第一半导体衬底粘合到其上形成有第二器件的第二半导体衬底以形成单个封装。根据本发明实施例，可以使与粘合强度相关的问题和/或与通道孔电极形成相关的问题最小化。
实例图1到图6是示出根据本发明实施例的半导体器件及其制造方法的附图。参照实例图1，可以形成第一器件100。可以在半导体衬底110上和/或上方形成多个第一晶体管120。根据本发明实施例，可以在半导体衬底110上和/或上方形成多层的第一层间绝缘膜130，其中多层的第一层间绝缘膜130可以包括多个第一金属导线140和第一接触件125，第一接触件125用来使第一金属导线140互连。
根据本发明实施例，第一器件100可以是CPU、SRAM、DRAM、闪存、逻辑器件、功率IC(powerIC)、RF IC以及传感器芯片中的至少一种。根据本发明实施例，第一器件100可以是具有任何任意功能(any arbitrary function)的半导体器件。
根据本发明实施例，第一器件可以进一步包括保护膜150，该保护膜150可以形成在多层的第一层间绝缘膜130上和/或上方。可以由与第一层间绝缘膜130相同的材料形成保护膜150。
参照实例图2，可以在第一器件100的顶部形成刻蚀停止层(etch stop layer)210。根据本发明实施例，可以通过例如使用CVD沉积SiN基或SiC基材料(SiN-based or a SiC-based material)来形成刻蚀停止层210。当形成用来电连接第二器件和第一器件100的连接通孔时，可以使用刻蚀停止层210，其中第二器件可以形成在第一器件100上和或上方。刻蚀停止层210可以防止电流从第二器件200流到第一器件100。
参照实例图3，可以在刻蚀停止层210上和或上方形成硅(Si)单层220。硅单层(Si monolayer)220可以用作硅外延层的籽晶层(seed layer)，其中该硅外延层可以在随后形成。例如，可以通过将硅烷(SiH4)气体注入到CVD腔内并利用硅烷气体实施均热处理(soaking process)来在刻蚀停止层210的顶部形成硅单层220。
参照实例图4，例如，通过外延工艺，可以在Si单层220上和/或上方生长硅外延层230。根据本发明实施例，硅外延层230可以具有大约为
Figure A200810187882D00091
到
Figure A200810187882D00092
的厚度。根据本发明实施例，可以根据由浅沟槽隔离(STI)(shallow trench isolation)形成的隔离层的厚度来选择硅外延层230的厚度，其中该隔离层可以形成在硅外延层230上和/或上方。
参照实例图5，可以穿过硅外延层230形成连接通孔240。连接通孔240可以电连接至第一器件100。
根据本发明实施例，例如，可以通过光刻工艺来在硅外延层230上和/或上方形成光刻胶图样。光刻胶图样可以暴露与第一金属导线140中的至少一个相对应的硅外延层230。随后，可以使用该光刻胶图样作为刻蚀掩膜来顺序地刻蚀硅外延层230和刻蚀停止层210。这样可以形成通道孔。然后，可以去除光刻胶图样。根据本发明实施例，可以用诸如钨(W)、铜(Cu)、铝(Al)或银(Ag)的金属来填充这些通道孔。这可以通过化学气相沉积(CVD)、物理气相沉积(PVD)或电镀铜(electro copper plating)(ECP)来完成，并从而可以形成连接通孔240。
根据本发明实施例，可以使用Ti基或Ta基材料(Ti-based orTa-based material)作为连接通孔240的扩散防止膜(diffusionpreventing film)。例如，可以使用TaN、TiN、Ti以及TiSiN中的至少一种作为扩散防止膜。
根据本发明实施例，可以在硅外延层230上和/或上方形成第二器件200(实例图6)。可以在硅外延层230上和/或上方形成第二晶体管270，其中每个第二晶体管可以包括栅极图样、隔离体以及源极区/漏极区290。可以形成每个源极区/漏极区290，以便每个源极区/漏极区290可以与对应的连接通孔240交叠(overlap)。这可以通过将杂质离子注入到硅外延层230内来完成。
根据本发明实施例，第二晶体管270可以电连接至相应的连接通孔240。根据本发明实施例，可以硅化每个第二晶体管270的源极区表面或漏极区表面。这可以减小与对应的连接通孔240的接触电阻。
参照实例图6，可以在其上形成有第二晶体管270的硅外延层230上和/或上方形成多层的第二层间绝缘膜250。根据本发明实施例，多层的第二层间绝缘膜250可以包括多个第二金属导线280和第二接触件260，其中该第二接触件260可以使第二金属导线280互连。根据本发明实施例，第二器件200可以包括第二晶体管270、多个第二金属导线280、多个第二接触件260以及多层的第二层间绝缘膜250，其中第二晶体管270形成于硅外延层230上和/或上方。
根据本发明实施例，第二器件200可以是CPU、SRAM、DRAM、闪存、逻辑器件、功率IC、控制IC、RFIC以及传感器芯片中的至少一种。根据本发明实施例，第二器件200可以是具有任何任意功能(any arbitrary function)的半导体器件。
根据本发明实施例，一种半导体器件及其制造方法的特征可以在于，可以在第一器件100上和/或上方形成硅外延层230。可以在硅外延层230上和/或上方形成第二器件200。根据本发明实施例，第一器件100或第二器件200可以是这样的半导体器件，即该半导体器件可以至少包括晶体管、金属导线以及STI。
根据本发明实施例，在半导体器件及其制造方法中，可以不使用粘合剂来将两个器件彼此相连。根据本发明实施例，可以在第一器件100和第二器件200之间形成硅外延层230，该硅外延层230可以包括连接通孔240。根据本发明实施例，可以通过连接通孔240来将第一器件100和第二器件200进行电连接和封装而不用另外的粘合工艺(bonding process)。
根据本发明实施例，在半导体器件及其制造方法中，硅外延层230的厚度可以相对较小。因此，可以减小连接通孔的长度和第二器件200的厚度，这对于集成是有利的。
根据本发明实施例，一种半导体器件及其制造方法可以用于将多个器件垂直地层叠在单个封装内。
可以在所公开的实施例中作出各种修改和改变，这对于本领域技术人员而言是显然的和显而易见的。因此，本发明所公开的实施例意在涵盖处于所附权利要求及其等同替换的范围内的这些显然的和显而易见的修改和改变。

Claims (20)

1.一种器件，包括：
第一器件；
硅外延层，形成于所述第一器件上方；
第二器件，形成于所述硅外延层上方；以及
连接通孔，所述连接通孔形成穿过所述硅外延层以将所述第一器件和所述第二器件电互连。
2.根据权利要求1所述的器件，其中，每个所述第一器件和所述第二器件均包括：
多个晶体管，形成于衬底上方；
多层的层间绝缘膜，形成于所述衬底上方，其中在所述衬底上形成有所述晶体管；
多个金属导线，形成于所述层间绝缘膜中；以及
多个接触件，形成于所述层间绝缘膜中以使所述金属导线互连。
3.根据权利要求2所述的器件，其中，所述第二器件中的所述多个晶体管中的至少一个通过所述连接通孔连接至所述第一器件的所述多个金属导线中的至少一个。
4.根据权利要求2所述的器件，其中，所述第二器件中的所述多个晶体管中的至少一个的源极区/漏极区与所述连接通孔交叠。
5.根据权利要求1所述的器件，其中，每个所述第一器件和所述第二器件均包括CPU、SRAM、DRAM、闪存、逻辑器件、功率IC、控制IC、RF IC以及传感器芯片中的至少一种。
6.根据权利要求1所述的器件，包括形成于所述硅外延层与所述第一器件之间的刻蚀停止层。
7.根据权利要求6所述的器件，其中，所述刻蚀停止层包括SiN基材料和SiC基材料中的至少一种。
8.根据权利要求1所述的器件，其中，所述硅外延层具有大约为2000
Figure A200810187882C0003162619QIETU
到20000
Figure A200810187882C0003162619QIETU
的厚度。
9.根据权利要求1所述的器件，其中，根据由浅沟槽隔离形成的隔离层的厚度来确定所述硅外延层的厚度，所述隔离层形成于所述硅外延层上方。
10.一种方法，包括：
制备第一器件；
在所述第一器件上方形成硅外延层；
穿过所述硅外延层形成连接通孔；以及
在所述硅外延层上方形成第二器件以便所述第二器件电连接至所述连接通孔。
11.根据权利要求10所述的方法，包括在所述第一器件上方形成所述硅外延层之前，在所述第一器件上方形成刻蚀停止层。
12.根据权利要求11所述的方法，包括通过使用CVD沉积SiN基材料和SiC基材料中的至少一种来形成所述刻蚀停止层。
13.根据权利要求11所述的方法，其中，形成所述硅外延层包括：
在所述刻蚀停止层上方形成硅单层；以及
在所述硅单层上方生长硅外延层。
14.根据权利要求13所述的方法，其中，形成所述硅单层包括将硅烷(SiH4)气体注入到CVD腔内并利用所述硅烷气体实施均热处理来形成所述硅单层。
15.根据权利要求11所述的方法，其中，制备所述第一器件包括：在衬底上方形成多个晶体管，在其上形成有所述晶体管的所述衬底上方形成多层的层间绝缘膜，在所述层间绝缘膜中形成多个金属导线，以及在所述层间绝缘膜中形成接触件以使所述金属导线互连。
16.根据权利要求15所述的方法，其中，穿过所述硅外延层形成所述连接通孔包括：
在所述硅外延层上实施光刻工艺以形成光刻胶图样来暴露与所述多个金属导线中的至少一个相对应的所述硅外延层；
使用所述光刻胶图样作为刻蚀掩膜，顺序地刻蚀所述硅外延层和所述刻蚀停止层，以形成通道孔；
去除所述光刻胶图样；以及
用金属填充所述通道孔以形成所述连接通孔。
17.根据权利要求16所述的方法，其中，填充所述通道孔的所述金属包括钨(W)、铜(Cu)、铝(Al)以及银(Ag)中的至少一种。
18.根据权利要求10所述的方法，其中，每个所述第一器件和所述第二器件均包括CPU、SRAM、DRAM、闪存、逻辑器件、功率IC、控制IC、RF IC以及传感器芯片中的至少一种。
19.根据权利要求10所述的方法，包括形成所述硅外延层以使所述硅外延层具有大约为
Figure A200810187882C0005162657QIETU
到
Figure A200810187882C00052
的厚度。
20.根据权利要求10所述的方法，其中，根据由浅沟槽隔离形成的隔离层的厚度来确定所述硅外延层的厚度，所述隔离层形成于所述硅外延层上方。
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DE102008062492A1 (de) 2009-10-08
KR100909562B1 (ko) 2009-07-27
US7968965B2 (en) 2011-06-28
CN101465346B (zh) 2011-04-13

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