CN1723601A - 集成的半桥功率电路 - Google Patents

集成的半桥功率电路 Download PDF

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CN1723601A
CN1723601A CNA2003801055459A CN200380105545A CN1723601A CN 1723601 A CN1723601 A CN 1723601A CN A2003801055459 A CNA2003801055459 A CN A2003801055459A CN 200380105545 A CN200380105545 A CN 200380105545A CN 1723601 A CN1723601 A CN 1723601A
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fet
low
converter
ldmos
side switch
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A·W·鲁迪克休泽
J·范德波尔
R·J·戈罗维
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Koninklijke Philips NV
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Abstract

一种包括集成电路的下变频器，其包括控制FET(CF)和同步整流器FET(SF)。控制FET是横向双扩散的(LDMOS)FET，且LDMOS FET的导电类型和衬底的导电类型相同。

Description

集成的半桥功率电路
本发明总体涉及使用半桥的集成功率变换电路，尤其涉及用于具有改善的开关特性的下变频器电源的集成功率晶体管。
功率变换器常用于电源、功率放大器和电机驱动中。包括Buck变换器的下变频器常用于将输入电压变换到较低的电压，用于为负载如微处理器提供能量。这些微处理器适用于个人计算机(PC)以及其它电子器件中。在PC应用中，变换器的输入电压为12V的数量级，且需要的输出约为1.4V的数量级，或约下降为十分之一。而且，将这些变换器所需的输出电流增加到50A以上，进一步增加这些电路和其器件的设计考虑。
下变频器电路常包括控制晶体管和同步整流器。这些器件常为金属氧化物半导体(MOS)晶体管，其为硅基场效应晶体管(FET)。使用控制FET(CF)和同步整流器FET(SF)具有一些优点。然而，在公知的电路中，这些器件是分立元件或设置为模块。这种电路具有一些缺点。例如，随着更快开关频率的需求增加，为了满足这些需求，这种器件的寄生效应会对CF和SF的能力具有有害的影响。
使与下变频器开关的开与关有关的损耗尽可能有利地减小。这具有一些好处，如PC内的电池寿命提高和热散逸减小。由器件的电阻和质量因数部分地确定MOSFET的变换损耗，其与接通电阻Ron和栅-漏电荷Qgd成比例。
根据本发明的示范性实施例，下变频器包括具有控制FET(CF)和同步整流器FET(SF)的集成电路，其中控制FET是横向双扩散的(LDMOS)FET，且LDMOS FET的导电类型和衬底的导电类型相同。
随着本说明继续将变得更清楚，经由在此描述的示范性实施例提高接通电阻和栅-漏电荷。实施例的其它优点是减小的寄生现象、选择用于接口电路的集成(用于更好地控制功率器件的开关)和降低的制造成本。
当参考附图的各图阅读时，自下面详细的描述将更好地理解本发明。要强调的是，各种部件不需按比例绘制。事实上，为了讨论清楚起见，可任意地增加或减小尺寸。
图1是根据本发明示范性实施例的下变频器的示意图。
图2a是在根据本发明示范性实施例的下变频器中使用的集成CF和SF的剖面图。
图2b是示出在根据本发明示范性实施例的下变频器的CF-开关的单元(源极/漏极指状物)内部的多个导电插塞的剖面图。
图3是在根据本发明示范性实施例的下变频器中使用的集成CF和SF的剖面图。
图4是在根据本发明示范性实施例的下变频器中使用的集成CF和SF的剖面图。
图5是在根据本发明示范性实施例的下变频器中使用的集成CF和SF的剖面图。
在下面的详细描述中，为了说明的目的且不用于限制，为了提供本发明的透彻理解，提出了公开具体细节的示范性实施例。然而，对于掌握本发明公开优点的本领域普通技术人员显而易见的是，脱离在此公开的具体细节，可在其它的实施例中实践本发明。而且，可忽略公知的器件、方法和材料的描述，以便不使本发明的描述晦涩。
图1示出了根据本发明示范性实施例的下变频器电路100。说明性地，电路100为具有CF 101和SF 102的Buck变换器电路。输入电压来自电压源或电源(未示出)，且施加在输入端103和104上，说明性地输入电压为约12V的数量级。输出端105和106分别连接电感器107和接地。负载是大的存储电容器108和电阻109。电阻109代表连接到下变频器100的多种电子器件中的一种。例如，电阻109可以是微处理器。然而，要注意的是，使用该示范性实施例的下变频器电路100不局限于基于微处理器的应用。例如，变换器电路可用于开关模式(音频)放大器中。对于掌握本公开优点的本领域技术人员来说，变换器电路100的其它应用将是显而易见的。
通常，当将增加的电流提供给负载时，对下变频器如电路100的需求在于提供在负载处日益降低的输出电压。这些需求与很低的欧姆开关的需求耦合。此外，在紧凑的、高速度的下变频器应用(例如，约300kHz至约2MHz的数量级，具有纳秒数量级的瞬态)方面希望减小电感器107和电容108的物理尺寸和值(通常为几mF数量级)，且需要电流到负载的快的接通/断开开关时间。虽然需要将功率有效地、快速地提供给负载，但下变频器电路100有效地减小了电寄生现象。
如在有效的高速功率器件和电路中公知的，寄生效应最大的来源是寄生电阻和电感，其使器件的效率和开关速度恶化。因此，有助于减小在总的开关路径中(例如，晶体管、传输线、封装等)的所有寄生现象(电阻和电感)。如随着本说明继续进行将变得更清楚，经由在此描述的示范性实施例的集成电路减小了这些寄生现象。
示范性实施例包括在半导体器件结构(芯片)中的CF 101和SF 102的集成，通过各种方法和结构减小了不希望的电寄生现象。而且，利用最小量的处理步骤，这些实施例促进了在集成封装中或者直接在负载的电路板(例如，在微处理器应用中的PC板)上制造CF 101和SF102，因此通过减小处理的复杂性相对地减小了器件的总成本。最后，除了通过晶体管选择和设计减小寄生电阻和电感外，示范性实施例减小了晶体管之间的间隔，以实现减小寄生现象。
图2a示出了根据本发明示范性实施例的集成电路(IC)200。要注意的是，各种材料和掺杂的极性指的是示范性实施例的例证。清楚地，其它的材料、元件和掺杂极性可用于实现示范性实施例。而且，注意的是，公知的材料和半导体处理技术可用于实现IC 200。同样地，为了简要和清楚地说明示范性实施例，通常省略这些公知的材料和技术。
说明性地，IC 200是半桥电路且包括在共用的n+衬底201上制造的器件，其说明性地为n掺杂的硅。垂直的双扩散MOS(VDMOS)晶体管202包括具有栅极触点205、漏极触点223的栅极219、n+源极216和经由源极触点203与源极216短接的p主体218。在n掺杂的外延(epi)阱206中形成了VDMOS。VDMOS结构的漏极由重掺杂的(n+)漏极204和n外延阱206组成。在下文VDMOS漏极将称作为漏极204。
在本示范性实施例中，配置VDMOS晶体管202用作下变频器电路100的SF整流器102，如随着本说明继续将变得更清楚。有利地，VDMOSFET 202是沟槽-栅极结构，其通常提供相比其它的FET器件更低的接通电阻(例如，对于工作电压约25V的器件，为10mOhm*mm2的数量级)。
LDMOS晶体管207形成在掩埋的p阱221中，且包括栅极211、与p主体217短接的n+源极214和形成在n型阱220中的n-漏极215。栅极触点205和211每个都连接至控制部分(未示出)，驱动栅极219和211用于使FET 202和207导通和断开。在示范性实施例中，LDMOSFET用作下变频器电路100的CF。
IC 200还可包括NMOS FET 226和PMOS FET 227，其可用于IC的各种应用中。可使用FET与接口电路(未示出)协作，用于更好地控制开关，和在栅极-驱动电路中减小的电感。这些和其它器件还可与示范性实施例一致的IC结合。
说明性地，在地与约5V至约12V之间驱动栅极219。在LDMOS FET207的栅电压和源电压之间驱动栅极211。源极触点208将源极214连接至输出端208和漏极204，其在输入电压(约12V)和逆程电压(一般约-0.2V)之间循环。因此，由外部电容提供的控制块来驱动栅极211，其说明性地由自举电路和/或电荷抽取电路(未示出)充电。
如上所述，有助于提供包括功率晶体管(FET)的电路100，该功率晶体管(FET)具有相比公知的器件减小的寄生电感和接通电阻。说明性地，依靠IC 200，包括示范性实施例半桥IC 200的电路100的寄生电感约为1.0nH的数量级，而接通电阻为约5mOhms至约10mOhms的数量级。减小的寄生电感引起负载(例如，电容108和电阻109)的提高的开关速度(接通/断开时间)，而减小的接通电阻引起IC导通损耗减小。
半导体器件结构和IC 200的设计由于包括IC 200的器件减小的寄生现象而实现了部分减小寄生现象的优点。为了说明的目的，VDMOSFET 202提供了相对低的接通电阻，说明性地对于25V的器件为10mOhms*mm2和合理的Qgd。LDMOS FET 207还提供了合理的低接通电阻(说明性地，对于25V器件为25mOhm*mm2)和低的Qgd；对于LDMOS FET207，乘积(Ron*Qgd)说明性地为约12mOhm*nC的数量级。当然这仅是说明性的，且依赖于应用经由示范性实施例可实现其它相似提高的值。
在图2a示出的示范性实施例中，漏极触点209连接至下变频器电路100的电压输入(例如，如上所述12V)，而源极触点208连接至VDMOS FET的漏极触点223，其在本示范性实施例中还是SF 102的漏极。说明性地，在衬底201中经由深连接如导电的n+插塞210(或重掺杂的下沉物)连接源极触点208。可选地，可将n+插塞210设置在蚀刻的沟槽或斜坡中；或者可将金属短路(或通孔)设置在蚀刻的沟槽中以实现该目的。无论如何，这提供了与小横向尺寸的低欧姆连接。然后将导电插塞210或相似的器件应用到LDMOS器件单元内的多个位置上，(如图2b所示)由此仅利用相对薄的第一金属的触点222，将低电阻的源极触点208连接到重掺杂的漏极204上，其允许精细的图案在单元内。这对于允许厚的(第二)功率金属用于在具有粗糙图案的IC顶侧上的203和209，以及厚的功率金属(漏极触点223)用于在底侧处的输出端(即，在衬底的下面)是有利的。
如意识到的，LDMOS FET 202的源极触点208和VDMOS FET 207的漏极触点223现在具有对芯片(IC)的低欧姆连接，且连接至下变频器的电感器，如图1的电感器107。有利地，相比其它结构这促进了寄生现象的减小。最后，以相对直接的方式进行其它的连接，因此将IC 200连接到下变频器电路100的其它元件上。
利用公知的半导体处理技术，如下说明性地制造IC 200。n+硅层形成衬底201，以n-外延约3-4μm厚度形成n阱206。处理结束该外延层约为2-3μm厚。该步骤之后首先紧接着进行P阱注入和扩散，以分别形成NMOS和PMOS FET 226和227的p阱221和p阱224和225。进行N阱注入，以形成LDMOS漂移区的n阱220和PMOS FETn阱228。这之后紧接着掺杂剂扩散。如果希望，则然后注入深的n+插塞210，紧接着进行扩散。其后为VDMOS FET 202蚀刻沟槽。
可选地，可利用在其底部具有另外的n+注入的沟槽来制造深N型插塞210用于表面接触n+晶片，以形成漏极触点204。接下来经由硅的局部氧化(LOCOS)进行任选的场氧化步骤。还可生长或淀积和蚀刻该场氧化物(未示出)。其后，进行栅氧化形成(例如，通过氧化生长)步骤，以形成VDMOS FET 202和LDMOS FET 207的栅氧化物。这些栅氧化物依赖于所需的栅-源电压(Vgs)具有约15至约40nm的厚度，该栅-源电压说明性地为约5V至约12V。
其后，进行多晶硅淀积和n+掺杂，其紧接着进行多晶的构图。在完成多晶淀积后，实现了浅p型DMOS主体注入以形成主体218(例如，具有Latid-Boron，具有Arsenic link)。接下来，通过标准的处理技术形成(氧化物)间隔物(未示出)。该处理产生了短的沟道和与源极相连的良好的链路，其对于LDMOS FET 207促进了低的Ron。接下来，注入和激活浅n+区和浅p+区，紧接着进行场氧化(FOX)淀积、接触-窗(未示出)、第一金属氧化物或氮化物淀积、通孔(未示出)、具有通过保护层覆盖且向焊接垫(未示出)敞开的籽晶层和电镀铜10-15μm的厚的第二金属(未示出)。
工作时，如果LDMOS FET 207(CF)接通，则它将n+衬底充电到输入电压(例如，12V)，由此在负载-电感107中提供电流。如果CF关闭，则依赖VDMOS FET 202的导通时间，负载-电感107将n+衬底从12V拉向约-0.1V或至约-0.7V。下变频器中的电流通常从源极214、经由负载-电感107流向负载。因此，n+衬底上的电位将不在+12V以上；依赖于电感，209上的电位会上升到该值以上。最后，注意在此描述的实施例中，可进一步利用表面焊料凸块和倒装芯片封装来减小电感。
图3示出了根据本发明另一示范性实施例的IC 300。该IC 300与在前描述的IC 200公用共同的部件和材料。同样地，将突出显示不同之处，且不讨论共同的特征。IC 300说明性地包括分别具有两个LDMOS FET 302和303的n型衬底301。有效地，LDMOS FET 302为图1的SF 102，而LDMOS FET 303为CF 101。LDMOS FET 303与图2a中描述的基本相同。一个区别在于它的源极连接，其经由金属化与LDMOS FET 302的漏极触点304连接。当然，这对应于图1的输出端105。
用作SF 102的LDMOS FET 302具有经由源极触点308接地的源极306和主体307。栅极309连接到控制功能元件(未示出)，如同以上描述的栅极211的控制功能元件。漏极215设置在n阱220中，并经由305与输出端304连接。器件设置在n外延阱206中。有利地，IC 300具有低的接通电阻，对于20V，每个LDMOS晶体管都具有每单位面积约10mΩ*mm2数量级的接通电阻(Ron)。而且，现在与IC的所有功率都连接在芯片的共用侧上，消除了形成背面触点或深导电插塞或类似器件的需要。该说明性的实施例还在下面的方面是有利的，因为在处理期间不需削薄衬底以减小寄生电阻，或经由超掺杂具有很低的电阻率。然而该实施例对LDMOS器件的金属化有更高的要求，且需要另外的(第三)金属层和通孔图案。
图4示出了本发明的另一示范性实施例。该实施例共用图2a、2b和3中共同的部件和结构，且可用于如图1所示的电路中。图4的IC 400本质上是具有n+插塞401(扩散的、预蚀刻的或沟槽)的IC 300和具有在底侧经由金属化223的图1中电路的输出端105的n+衬底201。插塞401用于减少对两个LDMOS FET的金属化的需求且允许两层金属系统，其在制造期间是有利的。
图5是本发明的另一示范性实施例。而且，IC 500共用图2-4的示范性实施例共同的部件和结构。也就是说，IC 500本质上是IC 400，除了p外延层501设置在n+衬底201上之外，或可以是在具有覆层P阱注入和扩散的n+衬底202上的n外延层。在此将器件309设置在p阱501中。在该实施例中插塞401还用于阱隔离。这节省了至少一个掩模步骤。
如此描述本发明，显而易见的是，可由具有本公开优点的普通技术人员中任何一个以许多的方式改变相同的事物。这种改变不认为脱离了本发明的精神和范围，且对于本领域技术人员显而易见的是这种修改意于包括在下面的权利要求和它们的合法等效物的范围之内。

Claims (20)

1.一种下变频器，包括：
具有控制FET(CF)和同步整流器FET(SF)的集成电路，
其中控制FET是LDMOS FET，且LDMOS FET的导电类型和衬底的导电类型相同。
2.如权利要求1所述的下变频器，其中同步整流器FET是VDMOSFET。
3.如权利要求1所述的下变频器，其中同步整流器FET是垂直沟槽DMOS FET。
4.如权利要求1所述的下变频器，其中同步整流器FET是另一LDMOS FET。
5.如权利要求2所述的下变频器，进一步包括平行电连接的多个导电插塞，其提供了从控制FET的源极到衬底表面上的输出端的几毫欧的欧姆连接。
6.如权利要求3所述的下变频器，进一步包括平行电连接的多个导电插塞，其提供了从控制FET的源极到衬底表面上的输出端的几毫欧的欧姆连接。
7.如权利要求4所述的下变频器，进一步包括平行电连接的多个导电插塞，其提供了从控制FET的源极和同步整流器FET的漏极到衬底表面上的输出端的几毫欧的欧姆连接。
8.如权利要求2所述的下变频器，其中VDMOS FET和LDMOS FET设置在具有相反极性的各个阱中。
9.如权利要求3所述的下变频器，其中垂直沟槽DMOS FET和LDMOSFET设置在具有相反极性的各个阱中。
10.如权利要求1所述的下变频器，其中集成电路不包括在CF和SF之间的隔离区。
11.如权利要求1所述的下变频器，其中导电类型是n型。
12.一种下变频器，包括具有控制FET(CF)和同步整流器FET(SF)的集成电路，其中控制FET和同步整流器FET都是LDMOS FET，且LDMOS FET的导电类型和衬底的导电类型相同。
13.一种电力负载的开关方法，该方法包括：
提供包括具有高侧开关和低侧开关的集成电路的功率变换器，其中高侧开关是LDMOS FET，且LDMOS FET的导电类型和衬底的导电类型相同。
14.如权利要求13所述的方法，其中低侧开关是VDMOS FET。
15.如权利要求13所述的方法，其中低侧开关是垂直沟槽DMOSFET。
16.如权利要求13所述的方法，其中低侧开关是另一LDMOS FET。
17.如权利要求14所述的方法，其中功率变换器进一步包括多个导电插塞，其提供了与衬底表面上的输出端的几毫欧的欧姆连接。
18.如权利要求15所述的方法，其中功率变换器进一步包括多个导电插塞，其提供了与衬底表面上的输出端的几毫欧的欧姆连接。
19.如权利要求16所述的方法，其中功率变换器进一步包括多个导电插塞，其提供了与衬底表面上的输出端的几毫欧的欧姆连接。
20.如权利要求13所述的方法，其中高侧开关是CF，且低侧开关是SF。
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