CN102136472A - 半导体装置模块 - Google Patents
半导体装置模块 Download PDFInfo
- Publication number
- CN102136472A CN102136472A CN2010105713577A CN201010571357A CN102136472A CN 102136472 A CN102136472 A CN 102136472A CN 2010105713577 A CN2010105713577 A CN 2010105713577A CN 201010571357 A CN201010571357 A CN 201010571357A CN 102136472 A CN102136472 A CN 102136472A
- Authority
- CN
- China
- Prior art keywords
- main electrode
- electrode terminal
- heating panel
- semiconductor device
- device module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/40—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/40—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs
- H01L23/4006—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs with bolts or screws
- H01L2023/4037—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs with bolts or screws characterised by thermal path or place of attachment of heatsink
- H01L2023/4056—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs with bolts or screws characterised by thermal path or place of attachment of heatsink heatsink to additional heatsink
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/29111—Tin [Sn] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29199—Material of the matrix
- H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29299—Base material
- H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/29339—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/37001—Core members of the connector
- H01L2224/3701—Shape
- H01L2224/37011—Shape comprising apertures or cavities
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/37001—Core members of the connector
- H01L2224/37099—Material
- H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/37138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/37147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/3754—Coating
- H01L2224/37599—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
- H01L2224/40139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous strap daisy chain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73221—Strap and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8384—Sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
- H01L2224/848—Bonding techniques
- H01L2224/8485—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/852—Applying energy for connecting
- H01L2224/85201—Compression bonding
- H01L2224/85205—Ultrasonic bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1203—Rectifying Diode
- H01L2924/12032—Schottky diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
本发明提供可高温动作并且可实现小型化、轻量化的半导体装置模块。半导体元件具有用硅或环氧等树脂来树脂密封的P侧封装单元(21)及N侧封装单元(22),P侧封装单元(21)及N侧封装单元(22)在金属的散热板(4)的主表面上配置成使散热板(3)的主表面垂直。P侧封装单元(21)及N侧封装单元(22)构成为散热板(3)的端缘部被夹在配置于散热板(4)的主表面上的导轨状的单元安装部(50)而固定。
Description
技术领域
本发明涉及半导体装置模块,特别是涉及可高温动作的半导体装置模块。
背景技术
半导体装置中搭载有较多的电子部件,通过连接这些电子部件和布线构件,形成电气电路。这些电子部件的配置、布线构件的连接,以往是通过螺纹连接或锡焊等的钎焊来进行的。例如,在专利文献1中,公开了通过膏状钎焊料将半导体芯片的内部引线连接至外部导出导体板的结构。
最近随着高功能化,半导体装置需要更多的,且涉及多种的部件,另一方面,从使用于民生用电气制品、车载用电子设备的观点来看,还要求小型化及轻量化。
近年来,进行着作为取代硅基板的半导体基板而使用碳化硅(SiC)基板的半导体元件(碳化硅半导体元件)的开发。
碳化硅半导体元件可在比迄今为止的硅半导体元件更加高温度的环境下进行动作。在硅半导体元件中,难以得到保证175℃以上的结(junction)温度(Tj)的所谓的高Tj对应的半导体装置。
关于这一点,碳化硅半导体元件可以高Tj对应,但是,为此即使在半导体装置模块内的布线的连接部位中,也必须确保其耐久性。
此外,在提高散热性的需要方面上,硅半导体元件的配置受较大的制约,且半导体装置模块的小型化也有极限。例如,在专利文献2中,公开了将半导体芯片以平面方式配置,并通过将散热构件抵接到半导体芯片的两主表面来提高散热性的结构。
另一方面,在可高Tj对应的碳化硅半导体元件中,其制约较小,可更进一步地进行半导体装置模块的小型化,但迄今不能达到充分的小型化。
专利文献1:日本特开平5-145011号公报
专利文献2:日本特开2001-156225号公报
发明内容
本发明为了消除上述那样的问题而构思,其目的在于提供可高温动作并且能够实现小型化、轻量化的半导体装置模块。
本发明的半导体装置模块的方式,包括:具有搭载有半导体元件的电路基板、搭载所述电路基板的第一散热板、以及与所述半导体元件的主电极电连接的主电极端子的至少一个电路单元;搭载所述至少一个电路单元的第二散热板,其中所述第一散热板以使其主表面与所述第二散热板的主表面垂直的方式搭载于所述第二散热板上,所述主电极端子的一端与所述电路基板连接,沿着与所述第一散热板的所述主表面平行的方向延伸并且另一端从所述第一散热板上突出。
(发明效果)
依据本发明的半导体装置模块的方式,由于构成为第一散热板以使其主表面与第二散热板的主表面垂直的方式搭载于第二散热板上,主电极端子的一端与电路基板连接,另一端沿着与第一散热板的主表面平行的方向延伸而从第一散热板上突出,能够得到小型化且轻量化的半导体装置模块。
附图说明
图1是表示本发明的实施方式1的半导体装置模块的结构的斜视图。
图2是表示半导体装置模块的电路结构的图。
图3是表示P侧封装单元的结构的图。
图4是表示N侧封装单元的结构的图。
图5是表示焊接前的半导体装置模块的结构的剖视图。
图6是表示焊接后的半导体装置模块的结构的剖视图。
图7是说明焊接部的接合强度的图。
图8是表示本发明的实施方式1的半导体装置模块的制造工序的图。
图9是表示本发明的实施方式1的半导体装置模块的制造工序的图。
图10是表示本发明的实施方式1的半导体装置模块的制造工序的图。
图11是表示本发明的实施方式1的半导体装置模块的制造工序的图。
图12是表示本发明的实施方式1的半导体装置模块的制造工序的图。
图13是表示本发明的实施方式1的半导体装置模块的制造工序的图。
图14是表示本发明的实施方式1的半导体装置模块的制造工序的图。
图15是表示本发明的实施方式1的半导体装置模块的制造工序的图。
图16是表示本发明的实施方式1的半导体装置模块的制造工序的图。
图17是表示本发明的实施方式2的半导体装置模块的结构的剖视图。
图18是表示本发明的实施方式3的半导体装置模块的结构的剖视图。
图19是表示本发明的实施方式3的P侧电路单元的结构的图。
图20是表示本发明的变形例的半导体装置模块的结构的斜视图。
具体实施方式
<实施方式1>
<装置结构>
借助图1~图16,对本发明的实施方式1进行说明。图1是表示半导体装置模块100的结构的斜视图。
如图1所示,半导体装置模块100中,半导体元件(未图示)具有用硅或环氧等树脂来树脂密封的P侧封装单元21及N侧封装单元22,且P侧封装单元21及N侧封装单元22以在金属的散热板4的主表面上使金属的散热板3的主表面垂直的方式配置。
P侧封装单元21及N侧封装单元22构成为散热板3的端缘部被配置在散热板4的主表面上的导轨状的单元安装部50夹持而固定。
即,单元安装部50成为这样的结构:利用沿着散热板4的长边隔着间隔而并行地延伸的2条长条材料呈1对导轨状结构,在导轨的间隙夹持散热板3的长边侧端缘部。
在P侧封装单元21的、与被单元安装部50夹挟的一侧相反侧的长边中,第一主电极端子5、第二主电极端子6及信号端子13从成形为长方体状的树脂封装15的侧面突出,在N侧封装单元22的与被单元安装部50夹挟的一侧相反侧的长边中,第一主电极端子7、第二主电极端子8及信号端子13从树脂封装15的侧面突出。
P侧封装单元21及N侧封装单元22分别构成半导体装置模块中的一个电路单元,但主电极端子的配置有所不同,通过配置成使散热板3彼此对置,构成为各自的第一主电极端子与第二主电极端子相对。
并且,第二主电极端子6及第一主电极端子7构成为通过导电性的连接构件9彼此电性且机械连接。此外,第一主电极端子5、第二主电极端子8及信号端子13也分别对电源或电气设备、控制电路的所谓外部设备连接,但图示省略。
接着,借助图2,对半导体装置模块100的电路结构进行说明。图2是表示三相逆变器IV的电路图,三相逆变器IV由3个逆变器IV1~IV3构成。逆变器IV1具备:在提供电源电压VDD的电源线P和与接地电位连接的电源线N间串联连接的IGBT(绝缘栅双极型晶体管(insulated gate bipolar transistor):下面,有时简单称为晶体管)T1L及T1U;以及与晶体管T1L及T1U分别反并联连接的续流二极管D1L及D1U。再者,晶体管T1L及T1U的连接节点成为U相输出。
逆变器IV2也为同样的构成,具备:在电源线P-N间串联连接的晶体管T2L及T2U;以及与晶体管T2L及T2U分别反并联连接的续流二极管D2L及D2U,晶体管T2L及T2U的连接节点成为V相输出。
逆变器IV3具备:在电源线P-N间串联连接的晶体管T3L及T3U;以及与晶体管T3L及T3U分别反并联连接的续流二极管D3L及D3U,晶体管T3L及T3U的连接节点成为W相输出。
此外,图中逆变器IV1的晶体管T1L及T1U中,将发射极、集电极、栅极分别用E、C、G表示。
半导体装置模块100例如构成逆变器IV1,P侧封装单元21构成为包括晶体管T1U及续流二极管D1U,晶体管T1U的集电极C与第一主电极端子5连接,发射极E与第二主电极端子6连接,栅极G与信号端子13连接。同样地,N侧封装单元22构成为包括晶体管T1L及续流二极管D1L,晶体管T1L的集电极C与第一主电极端子7连接,发射极E与第二主电极端子8连接,栅极G与信号端子13连接。这时,通过连接构件9来互相连接的第二主电极端子6及第一主电极端子7成为U相输出。
如此,在设半导体装置模块100为一个逆变器电路的情况下,通过组合3个半导体装置模块100,构成图2所示的三相逆变器IV。
接着,借助图3~图5,对半导体装置模块100的内部结构进行说明。图3是在从树脂封装15侧观看P侧封装单元21时省略树脂封装15而显示的图。
在散热板3的主表面上搭载有电路基板2,在电路基板2的主表面上形成的细长形状的导体图案P1上,各形成两个一边的长度为2~5mm且厚度为0.06~0.25mm的半导体元件1a及1b,合计4个串联配置。
半导体元件1a及1b为形成在碳化硅基板的碳化硅半导体元件,半导体元件1a为IGBT或MOSFET(metal oxide semiconductor field effect transistor)等的开关元件,半导体元件1b为SBD(肖特基势垒二极管:schottky barrier diode)等。
通过使用碳化硅半导体元件,能够得到比使用硅半导体元件时更加小型且耐热性优越的半导体装置模块。
在图3所示的结构中,使用IGBT1a作为半导体元件1a,并且使用SBD1b作为半导体元件1b。此外,借助图2进行说明的、晶体管T1U及续流二极管D1U分别对应于IGBT1a及SBD1b,但在图3的例子中,成为各自两个并联连接的电路结构。
此外,上述为一例,半导体元件的种类并不局限于上述的半导体元件,此外关于个数,既可以各一个又可以多个,根据所求出的电流、电压等的制品规格,选择种类、个数、组合并加以搭载也可。此外,通过将部件通用化,能够削减成本。
对IGBT1a及SBD1b的导体图案P1的连接,是通过用高温焊锡等的焊料或导电性粘接材料等的接合材料11(未图示)使其背面侧的电极(如果是IGBT则为集电极,如果是二极管则为负极)与导体图案P1接合来连接的。
此外,IGBT1a及SBD1b的上表面侧的电极(如果是IGBT则为发射极,如果是二极管则为正极),配置成使由具有良导电性的金属例如铜或其合金材料形成的厚度0.3~1.5mm的布线构件10横跨IGBT1a及SBD1b的上表面,并通过高温焊锡等的焊料或导电性粘接剂等的接合材料11来与元件的上表面接合。
在此,作为接合材料11,在使用高温焊锡时,采用以Sn(锡)为主要成分的具有175℃以上的耐热性的焊锡材料。此外,作为接合材料11,在使用导电性粘接剂时,使用例如用有机分子膜覆盖直径2~30nm的银的颗粒(银纳米颗粒)的银纳米颗粒膏,将它涂敷到IGBT1a及SBD1b的上表面并在其上使布线构件10横跨,通过烧结,能够形成导热系数20~90W/mK且具有175℃以上的耐热性的接合部。
此外,在导体图案P1的端缘部还接合有第一主电极端子5,在导体图案P1的延伸方向且与第一主电极端子5所接合的一侧的相反侧,配置有独立的导体图案P2,在该导体图案P2接合有布线构件10,并且还接合有第二主电极端子6。
在此,第一主电极端子5及第二主电极端子6由具有良导电性的金属例如铜或其合金材料形成,其厚度为0.3~1.5mm,长边的长度为5~20mm。
此外,在第一主电极端子5、第二主电极端子6及布线构件10设有贯通孔TH,其中填满接合材料11。通过采用这种结构,第一主电极端子5、第二主电极端子6及布线构件10的表面通过接合材料11来与对置的面接合,并且通过接合材料11也与贯通孔TH的内壁面接合,因此能够得到可靠性较高的接合部。再者,设于第一主电极端子5及第二主电极端子6的贯通孔TH,在图3的例子中,分别有一处,但并不限于此。
此外,与导体图案P1的延伸方向并行地设有独立的导体图案P3,在该导体图案P3接合有信号端子13,并且与IGBT1a的栅极之间是用引线14来接合的。引线14用铝等的金属制的金属丝来构成,可以利用引线接合或超声波接合经压接而接合,也可以利用导体板并利用接合材料11来接合。
在此,将利用接合材料11的IGBT1a、SBD1b及第一主电极端子5对导体图案P1的接合、第二主电极端子6及布线构件10对导体图案P2的接合、以及布线构件10与IGBT1a及SBD1b的上表面侧的电极的接合,用接合材料11来进行接合时,或者用导电性粘接剂来进行接合时,能够经过共同的热处理工序而同时将它们全部接合,因此能够谋求提高生产性。
此外,采用将第二主电极端子6没有直接连接到IGBT1a及SBD1b的主电极,而暂且连接到导体图案P2之后,经由布线构件10与IGBT1a及SBD1b的主电极电连接的结构,因此在后述的主电极端子前端的焊接时或树脂密封时能够防止对半导体元件作用无用的力矩。
电路基板2是由AlN(氮化铝)、Al2O3(氧化铝)及Si2N3的任意种构成的具有绝缘性的绝缘基板,其厚度0.6~3mm、长边的长度为10~150mm。此外,根据所搭载的半导体元件的个数,任意变更长边的长度。
如图3所示,在电路基板2的一个主表面形成有导电图案P1~P3,在相反侧的另一主表面的大致整个面形成有导体图案(未图示),该导体图案与散热板3的主表面接合,起到将半导体元件产生的热向散热板3传递并散热的作用。
在此,散热板3由厚度0.8~4mm的铝、铝合金、铜或铜合金构成,为了确保热容量,具有比电路基板2的长边的长度长的长边尺寸。
再者,散热板3的长边侧端缘部被形成在散热板4的主表面上的导轨状结构的单元安装部50夹持,由此散热板3的主表面垂直置于散热板4的主表面。
单元安装部50在使散热板3的长边侧端缘部插入其间隙之后,用压力机来铆接,从而固定散热板3。通过采用这种结构,能够尽量减小半导体装置模块100的外形尺寸,并且能够增大热容量。因此能够提高半导体装置模块100驱动时发热的半导体元件的散热性。
在此,散热板4由厚度0.8~4mm的铝、铝合金、铜或铜合金构成,为了确保热容量,具有比电路基板2的长边的长度长的长边尺寸。
此外,如后所述,在焊接主电极端子前端时进行利用电弧放电的局部焊接、所谓的精密(micro)焊接,此时产生的热,能够通过散热板3及4而散热。因此,能够防止对各部分的接合所使用的接合材料11施加熔点以上的热的情形,并能防止接合材料11的软化、熔融导致的接合部的品质下降。
此外,也可以在散热板4的背面侧(与设有散热板3的一侧相反侧的主表面侧)设置散热片。由此能够进一步提高散热性,但是也可以根据半导体元件的发热量,此外,根据半导体装置模块100的使用方式或安装状态决定否使用它。
此外,取代散热片而设置冷却扇来强制气冷也可,也可以通过水冷来强制冷却。这些方法对保证半导体装置模块100在高温动作域的动作有效。
虽然在图3中未做图示,但是散热板3的接合有电路基板2的一侧的主表面上,形成有将接合IGBT1a、SBD1b、第一主电极端子5、第二主电极端子6及布线构件10的状态的电路基板2进行树脂密封的树脂封装15(图1)。此外,散热板3的背面(与接合有电路基板2的一侧相反侧的主表面)侧露出。
树脂封装15的树脂材料是以硅树脂或环氧树脂为主要成分的树脂,在接合半导体元件ゃ布线构件10之后,确保绝缘性,并且将第一主电极端子5、第二主电极端子6固定保持,确保与电路基板2的接合的耐久性。再者,树脂密封的方法采用例如用型箱的接合(bonding)法,通过80~150℃的加热来成形。
接着,对N侧封装单元22的结构进行说明。图4是在从树脂封装15侧观看N侧封装单元22时省略树脂封装15而显示的图。
与图3所示的P侧封装单元21相比,N侧封装单元22采用相对于在两封装间设定的假想线而言线对称的结构,成为彼此的散热板3的背面对置的结构。这是对提高半导体装置模块100的冷却能力并实现各封装所包含的半导体元件的稳定的动作有效的结构。
对于与图3所示的P侧封装单元21相同的结构,标注相同的附图标记,并省略重复的说明。但是,在N侧封装单元22中,第一主电极端子7与导体图案P1的端缘部接合,在与接合有第一主电极端子7的一侧相反侧的导体图案P2,接合有布线构件10,并且接合有第二主电极端子8。
在此,第一主电极端子7及第二主电极端子8由具有良导电性的金属例如铜或其合金材料形成,其厚度为0.3~1.5mm。
此外,在第一主电极端子7、第二主电极端子8及布线构件10设有贯通孔TH,其中填满接合材料11。通过采用这种结构,第一主电极端子7、第二主电极端子8及布线构件10的表面,通过接合材料11来与对置的面接合,并且通过接合材料11也与贯通孔TH的内壁面接合,因此能够得到可靠性高的接合部。此外,设于第一主电极端子7及第二主电极端子8的贯通孔TH,在图3的例子中,分别有一处,但并不限于此。
此外,与导体图案P1的延伸方向并行地设有独立的导体图案P3,在该导体图案P3接合有信号端子13,并且与IGBT1a的栅极之间是用引线14来接合的。
虽然在图4中未做图示,但在散热板3的接合有电路基板2的一侧的主表面上,形成有将接合IGBT1a、SBD1b、第一主电极端子7、第二主电极端子8及布线构件10的状态的电路基板2进行树脂密封的树脂封装15(图1)。此外,散热板3的背面(与接合有电路基板2的一侧相反侧的主表面)侧露出。
接着,在图5示出图3及图4中的A-A线的剖面向视图。如图5所示,在P侧封装单元21的第二主电极端子6与N侧封装单元22的第一主电极端子7之间,插入有导电性的连接构件9。
如此,电路基板2、IGBT1a、SBD1b及布线构件10树脂密封在树脂封装15内,但是第一主电极端子5、7及第二主电极端子6、8,其长边的长度中的2~15mm从树脂封装15突出。再者,突出的各主电极端子的前端并不平坦,而如图3及图4所示,成为短边的中央部凹下而具有凹凸的形状。
通过做成这样的形状,将第二主电极端子6和第一主电极端子7焊接至连接构件9时能够防止焊接部彼此接触。
在此,若将沿着各主电极端子的短边的方向称为宽度方向,则凹凸形状的凹部与凸部的尺寸,在将主电极端子的宽度设为A(mm)、凹部的宽度设为X(mm)时,设定成为满足X≥0.4A的关系。
如此,设定凹凸形状的尺寸的原因在于:在凹部的宽度较窄的情况下,将第二主电极端子6和第一主电极端子7焊接至连接构件9时,防止相邻的焊接部彼此接触或者有可能接合的情形。
若焊接部彼此接合,则焊接部的形状不会成为大致半球形状的稳定的形状而成为不稳定的形状,有可能降低可靠性。另一方面,对于半导体装置模块100要求小型化、轻量化,无法无限扩大主电极端子宽度,如果还考虑接合部的可靠性提高及制品质量的确保,则最好满足上述关系。
再者,若凹部的宽度过宽,则凸部的宽度变窄,不仅妨碍焊接作业而且降低接合强度,因此凹部的宽度的上限最好为凸部的宽度的0.5倍左右。
在此,图6中示出通过利用电弧放电的局部焊接来将第二主电极端子6和第一主电极端子7接合至连接构件9的状态的剖视图。将形成树脂封装15之后的P侧封装单元21及N侧封装单元22,安装到设于散热板4上的单元安装部50,用压力机等来铆接后,将连接构件9插入第二主电极端子6与第一主电极端子7之间,则成为图5所示的状态。
在此,连接构件9具有沿着长边的方向的两端部向相同方向大致弯曲90度的形状,弯曲的前端的前端部成为具有与主电极端子相同的凹凸的形状。此外,若将沿着连接构件9的短边的方向称为宽度方向,则连接构件9的宽度设定为与第二主电极端子6及第一主电极端子7的宽度相同的长度,且凹部及凸部的尺寸也与第二主电极端子6及第一主电极端子7相同。通过做成这样的结构,能够易于进行组装及焊接。
在将连接构件9插入第二主电极端子6与第一主电极端子7之间时,以使第二主电极端子6、第一主电极端子7的前端部与连接构件9的已弯曲的前端的前端部一致的方式插入。
然后,通过利用电弧放电的局部焊接,焊接第二主电极端子6及第一主电极端子7的前端部与连接构件9的前端部。通过电弧放电的热,彼此的前端熔化,形成大致半球状的焊接部BL。
在此,成为焊接部BL的最大宽度具有比接合前的第二主电极端子6及第一主电极端子7的前端部的凸部的宽度的1.1倍以上的大小的结构。由此能够提高接合部的可靠性,并能提高制品质量。
对于该理由,借助图7进行说明。图7中示出以横轴取接合宽度(焊接部BL的最大宽度)相对于主电极端子的凸部的宽度的比例、纵轴取断裂强度(N)时的接合强度试验结果。
由图7可以判断出通过使焊接部BL的最大宽度成为主电极端子的凸部的宽度的1.1倍以上,使断裂强度超过10N(牛顿),具有所需接合强度。断裂强度从横轴的比例超过1的附近起急速升高,但比例小于1.1时,难以得到充分的接合强度。
此外,该1.1倍的宽度是指能以最小能量确保电极的接合部的可靠性的宽度,将这种结构称为最小接合结构。然后,通过采用最小接合结构,能够削减生产成本,并能实现小型化、轻量化。
此外,由图7可知:如果焊接部BL的最大宽度为主电极端子的凸部的宽度的1.1倍以上,则能得到所需的接合强度,但是,从之前说明的与主电极端子的凹部的宽度的关系,认为上限为主电极端子的凸部的宽度的2倍左右。
在此,焊接方法可以使用电子束焊接或激光焊接来代替利用电弧放电的局部焊接,在这种情况下,也能形成大致半球状的焊接部BL。
此外,将在形成树脂封装15之后的P侧封装单元21及N侧封装单元22,安装于单元安装部50而铆接后,进行利用电弧放电的局部焊接,因此半导体元件被密封树脂覆盖,以裙状扩展的电弧放电不会对半导体元件造成损害。这在使用电子束焊接或激光焊接时也同样。
通过将第二主电极端子6和第一主电极端子7利用连接构件9进行接合,使P侧封装单元21和N侧封装单元22电连接,形成图2所示的1组逆变器电路。
<制造方法>
接着,借助顺序表示制造工序的图8~图16,对半导体装置模块100的制造方法进行说明。此外,在以下的说明中以图3所示的P侧封装单元21的制造方法为例子进行说明。
首先,在图8所示的工序中,准备在一个主表面上形成有导体图案P1~P3的电路基板2,在导体图案P1上的搭载有半导体元件的区域配置接合材料11。
接着,在图9所示的工序中,准备IGBT1a及SBD1b,并搭载于配置有接合材料11的区域。
接着,在图10所示的工序中,在IGBT1a及SBD1b的上表面、导体图案P1及P2上的,分别接合第一主电极端子5及第二主电极端子6的区域以及导体图案P2上的接合布线构件10的区域配置接合材料11。
接着,在图11所示的工序中,准备布线构件10及第一主电极端子5及第二主电极端子6,并搭载于配置接合材料11的区域。其后,在规定的温度条件下加热电路基板2,使接合材料11固化(或硬化),由此将各结构接合(固接)到电路基板2上。
接着,在图12所示的工序中,准备散热板3,在一个主表面上的接合电路基板2的区域配置接合材料11。
接着,在图13所示的工序中,将安装了半导体元件的电路基板2搭载于配置接合材料11的区域,在规定的温度条件下进行加热,使接合材料11固化(或硬化),由此将电路基板2接合(固接)到散热板3上。
接着,在图14所示的工序中,由于将IGBT1a的栅极电连接至导体图案P3,通过引线接合或超声波接合来进行引线14的接合。此外,信号端子13也通过引线接合或超声波接合来连接至导体图案P3。为了方便起见,将完成至该工序的结构称为电路单元。
接着,在图15所示的工序中,将安装有半导体元件的电路基板2在散热板3上进行树脂密封。具体的密封方法是完全覆盖电路基板2,并且在使第一主电极端子5及第二主电极端子6的端部突出的型箱嵌入散热板3,对该型箱内导入热固化性的密封树脂,在80~150℃进行加热而使树脂固化,成形树脂封装15。由此,完成P侧封装单元21及N侧封装单元22。
接着,在图16所示的工序中,准备散热板4,将P侧封装单元21及N侧封装单元22中的散热板3的长边(没有设置主电极端子的一侧的长边),插入各单元安装部50的导轨的间隙,利用压力机将构成导轨的长条材料铆接,由此进行固定。从而,固定成使散热板3的主表面垂直置于散热板4的主表面。
其后,在第二主电极端子6与第一主电极端子7之间插入连接构件9,通过利用电弧放电的局部焊接,将第二主电极端子6及第一主电极端子7的前端部和连接构件9的前端部焊接,由此形成图6所示的焊接部BL,完成半导体装置模块100。
<效果>
如以上说明的那样在半导体装置模块100中,在接合第二主电极端子6及第一主电极端子7和连接构件9时,不使用由与被接合材料(主电极端子)不同的金属构成的接合材料(例如焊锡材料),而使母材即第二主电极端子6、第一主电极端子7及连接构件9熔化并凝固,从而使金属原子彼此耦合并接合,因此不会产生母材和接合材料的线膨胀系数的失配(miss match)。
即,半导体装置模块要求在温度差(ΔT)225℃以上的温度变化较大的极为严厉的环境下使用,因此如果通过焊锡材料那样具有不同的线膨胀系数的材料来接合,则因与母材的线膨胀系数的失配而在接合部产生较大的热应变或热应力,有可能产生龟裂。再者,主电极端子的厚度薄至0.3~1.5mm,因此一旦产生龟裂,龟裂就有可能发展。
但是,本发明中通过使用利用了电弧放电的局部焊接,在数msec~数秒内结束焊接而能够抑制热应变的发生,并且不会产生线膨胀系数的失配,而能够抑制起因于线膨胀系数的差异的龟裂的发生。因此,能够得到可靠性高的接合部。
此外。作为接合材料11,使用具有175℃以上的耐热性的焊锡材料或银纳米颗粒膏,由此也能在树脂封装15内部的接合部中确保175℃以上的耐热性,并且作为半导体元件使用碳化硅半导体元件,与此同时能够提高半导体装置模块100本身的可靠性及制品质量。
此外,由于采用将散热板3的长边侧端缘部夹入形成在散热板4的主表面上的导轨状结构的单元安装部50,由此固定散热板4的结构,所以能够可靠且牢固地进行散热板4的固定。
此外,通过采用使散热板3的主表面垂直位于散热板4的主表面的结构,能够配合从树脂封装15的侧面使主电极端子突出的结构而谋求小型化、轻量化。
此外,通过组合散热板3及4,能够增大热容量,并且通过使散热板3的背面曝露于空气,在散热板3的背面中也能进行散热,能够提高半导体装置模块100在驱动时发热的半导体元件的散热性,即使在更高的温度下也能进行正常的动作。
<实施方式2>
接着,借助图17,对本发明的实施方式2的半导体装置模块200的结构进行说明。此外,对于与图3及图4所示的半导体装置模块100相同的结构标注相同的附图标记,省略其重复的说明。
图17是与图3及图4所示的半导体装置模块100同样的部分的剖面向视图,半导体元件1b接合到电路基板2之上,散热板3用接合材料12接合到散热板4的主表面上。
然后,P侧电路和N侧电路被壳体18包围,在由壳体18和散热板4构成的框体内填充绝缘性的密封材料16而树脂密封P侧电路及N侧电路。壳体18由PPS、PBT、SPS及环氧等的绝缘材料构成,其厚度为0.5~1.5mm。
如此在半导体装置模块200中,构成为P侧电路和N侧电路被共同树脂密封,由于树脂封装为一个,方便起见将P侧电路称为P侧电路单元210、将N侧电路称为N侧电路单元220。
P侧电路单元210的第二主电极端子6A及N侧电路单元220的第一主电极端子7A的形状为上端部被弯曲两道而剖面呈Z字状。即,具有暂且向与主电极端子的主表面垂直的方向弯曲而形成第一曲折部,再向与主电极端子的主表面并行的方向折回而形成第二曲折部的结构。再者,第一及第二曲折部弯曲成比直角稍微小的角度,由此成为Z字状的剖面形状。这在第一主电极端子7A中也相同,并且在P侧电路单元210的第一主电极端子(未图示)及N侧电路单元220的第二主电极端子(未图示)中也相同。
此外,在第二主电极端子6A与第一主电极端子7A之间的连接构件9A,沿着长边的方向的两端部向相同的方向弯曲成比90度稍微小的角度,并且具有中央部弯的剖面形状。
通过采用这种结构,能够在曲折部中吸收各主电极端子的接合部中产生的热应力、热应变,因此能够进一步提高可靠性及制品质量。
即,将半导体装置模块200在严厉的环境下使用时,例如在寒冷地使用、车载使用等情况下特别效果。
此外,通过将各主电极端子的形状做成弯曲形状,能够缩短电极长度,并能实现更进一步的小型化、轻量化。
即,这是因为主电极端子的材料即铜或铜合金的密度约为8933kg/m3,主电极端子的材料在半导体装置模块的全重量中所占的重量比是仅次于散热板较大的缘故。再者,各主电极端子的弯曲加工是利用压力机等,由依次传送金属模高生产效率地执行。
此外,在半导体装置模块200中,散热板3利用接合材料12接合到散热板4的主表面上,但接合材料12使用以Sn为主要成分的具有175℃以上的耐热性的高温焊锡等的焊料或银纳米颗粒膏等的导电性粘接剂。由此,半导体装置模块200在175℃以上的高温下也能确保耐久性,此外接合材料12的热传导率为20~90W/mK,因此通过散热板3而能够向在散热板4有效率地导热动作时半导体元件产生的热。
再者,与图3所示的半导体装置模块100同样地,也可以为利用单元安装部50进行铆接来固定散热板3的结构。相反,在半导体装置模块100中,与半导体装置模块200同样地,利用接合材料12接合散热板3的结构也可。
在半导体装置模块200的制造中,在散热板4的一个主表面上利用接合材料12接合P侧电路单元210及N侧电路单元220的散热板3的长边(没有设置主电极端子的一侧的长边)的侧面后,利用粘接剂(未图示)将无底无盖的壳体18固定在散热板4的主表面上,以包围P侧电路单元210及N侧电路单元220。
其后,在由壳体18和散热板4构成的框体内,作为密封材料16填充例如硅凝胶或环氧树脂。
如此,通过采用设置框体而填充密封材料16的结构,能够简化制造工序,此外,用密封材料16覆盖除主电极端子的前端部以外的P侧电路单元210及N侧电路单元220,由此能够防止在焊接时接合部以外的部分产生不良情况。
然后,在从密封材料16突出的第二主电极端子6与第一主电极端子7之间插入连接构件9,通过利用电弧放电的局部焊接,将第二主电极端子6及第一主电极端子7的前端部与连接构件9的前端部焊接,由此完成半导体装置模块200。
此外,也可以取代实施方式1的半导体装置模块100中第二主电极端子6、第一主电极端子7及连接构件9而使用第二主电极端子6A、第一主电极端子7A及连接构件9A。
<实施方式3>
接着,借助图18及图19,对本发明的实施方式3的半导体装置模块300的结构进行说明。此外,对于与图3及图4所示的半导体装置模块100相同的结构标注相同的附图标记,省略其重复的说明。
图18是与图3及图4所示的半导体装置模块100同样的部分的剖面向视图,半导体元件1b接合到电路基板2之上,散热板3利用接合材料12接合到散热板4的主表面上。
然后,构成为在P侧电路及N侧电路的上方,配置有包含生成对未图示的IGBT1a的栅极的控制信号的控制电路的控制基板19,包括该控制基板19在内,P侧电路及N侧电路全体收纳于树脂封装17内。
如此,在半导体装置模块300中,构成为P侧电路和N侧电路被共同树脂密封,由于树脂封装为一个,方便起见将P侧电路称为P侧电路单元210、将N侧电路称为N侧电路单元220。
如图19所示,P侧电路单元210及N侧电路单元220以使彼此的电路基板2相对的方式搭载于散热板4上,各散热板3的背面构成为在树脂封装17的一侧露出。
P侧电路单元210及N侧电路单元220的各散热板3,长边(没有设置主电极端子的一侧的长边)的侧面通过接合材料12接合到沿着散热板4的长边侧的端缘部而设的台阶差部。接合材料12使用以Sn为主要成分的具有175℃以上的耐热性的高温焊锡等的焊料或银纳米颗粒膏等的导电性粘接剂。
P侧电路单元210的第二主电极端子6及N侧电路单元220的第一主电极端子7,贯通配置在上方的控制基板19而延伸,通过利用电弧放电的局部焊接,第二主电极端子6及第一主电极端子7的前端部与之间插入的连接构件9的前端部焊接,形成焊接部BL。
此外,P侧电路单元210的第一主电极端子5(未图示)及N侧电路单元220的第二主电极端子8(未图示),贯通配置在上方的控制基板19而延伸,各自的前端部通过利用电弧放电的局部焊接来焊接至外部端子30及31。外部端子30及31的端部从树脂封装17的上表面突出,分别与电源或电气设备等连接。
图19是从电路基板2一侧观看P侧电路单元210时省略P侧电路单元210上的树脂封装17而显示的图。此外,图19中的B-B线的剖面向视图与图18对应。
如图19所示,与导体图案P3连接的信号端子13朝着上方的控制基板19而延伸,构成为通过与控制基板19的控制电路(未图示)连接而提供控制信号。
此外,P侧电路单元210的第二主电极端子6及N侧电路单元220的第一主电极端子7(未图示)与未图示的连接构件9连接,但连接构件9还与外部端子32连接,外部端子32的端部构成为从树脂封装17的上表面突出。此外,外部端子32也可以为与连接构件9一体地设置的结构。
如此,在半导体装置模块300中,P侧电路单元210及N侧电路单元220的各自的散热板3的背面,在树脂封装17的侧面中露出,散热板4的背面也露出,因此与散热相关的3个面(散热面)曝露于外部,从而能得到更高的散热性。由此,能够充分地发挥半导体元件所具有的特性。
再者,以自然冷却的方式冷却露出的散热面也可,但对各散热面安装气冷扇也可,此外安装水冷扇也可。
在半导体装置模块300的制造中,在沿着长边侧的端缘部而设有台阶差部的散热板4的主表面上用接合材料12接合P侧电路单元210及N侧电路单元220的散热板3的长边(没有设置主电极端子的一侧的长边)的侧面之后,配置控制基板19,以使各主电极端子贯通设于控制基板19的开口部,并且使P侧电路单元210及N侧电路单元220的各自的信号端子13连接到控制基板19上的规定的控制电路。这时,构成为例如通过锡焊将信号端子13连接至控制电路,由此支撑控制基板19也可。
接着,在第二主电极端子6与第一主电极端子7之间插入连接构件9,通过利用电弧放电的局部焊接,将第二主电极端子6及第一主电极端子7的前端部和连接构件9的前端部焊接。这时,在利用与外部端子32成为一体的连接构件9的情况下,可以省去将外部端子32焊接至连接构件9的工夫。
此外,外部端子30及32通过利用电弧放电的局部焊接来分别焊接至P侧电路单元210的第一主电极端子5及N侧电路单元220的第二主电极端子8(未图示)。此外,外部端子30及32的、分别与第一主电极端子5及第二主电极端子8连接的端部的形状,为与第一主电极端子5及第二主电极端子8的端部同样具有凹凸的形状既可。
然后,以使外部端子30~32的前端部以外的部分被完全树脂密封的方式形成树脂封装17。
具体的密封方法是在散热板4上,配置包围P侧电路单元210、N侧电路单元220及前端部以外的外部端子30~32的型箱,向该型箱内导入热固化性的密封树脂,在80~150℃中加热而使树脂固化,成形树脂封装17。
通过采用这种结构,各主电极端子与电路基板2的接合部位也被树脂封装17覆盖,能够提高可靠性及制品质量。
再者,由于通过利用金属模的成批成形来进行树脂密封作业,在大量制造等情况下,成为低价且生产性非常良好的结构。
此外,也可以取代实施方式3的半导体装置模块300中第二主电极端子6、第一主电极端子7及连接构件9而使用实施方式2的半导体装置模块200中使用的,第二主电极端子6A、第一主电极端子7A及连接构件9A。
<变形例1>
在图20中示出用树脂壳体30包围图1所示的半导体装置模块100周围的结构。此外,对于与图1所示的半导体装置模块100相同的结构标注相同的附图标记,省略其重复的说明。
如图20所示,在散热板4的主表面上以包围P侧封装单元21及N侧封装单元22的方式固定有无底无盖的树脂壳体40。
树脂壳体40在沿着长边的方向的两侧具有以分别向外侧延伸的方式设置的基座部41及42。
然后,构成为在基座部41上,从连接构件9延伸出外部端子ACT,并且在基座部41延伸出与P侧封装单元21的第一主电极端子5焊接的外部端子PT及与N侧封装单元22的第二主电极端子8焊接的外侧端子NT。
连接构件9和外部端子ACT形成为一体,通过将连接构件9焊接至第二主电极端子6及第一主电极端子7,使第二主电极端子6及第一主电极端子7电连接至外部端子ACT。
此外,P侧封装单元21的第一主电极端子5与外部端子PT的焊接、以及N侧封装单元22的第二主电极端子8与外部端子NT的焊接,也使用利用了电弧放电的局部焊接。
再者,外部端子PT及NT的,与各第一主电极端子5及第二主电极端子8连接的端部的形状,为与第一主电极端子5及第二主电极端子8的端部同样具有凹凸的形状既可。
如此,通过以包围P侧封装单元21及N侧封装单元22的方式配置树脂壳体40,半导体装置模块100作为一个单元成为更加牢固的结构。
此外,通过设置外部端子ACT、PT及NT,具有能够容易进行与电源或电气设备等的连接的效果。
<变形例2>
在以上说明的半导体装置模块100~300中,就图2所示的三相逆变器IV之中,具有构成逆变器IV1的两个电路单元的情形进行了说明。如此通过用多个电路单元构成一个模块,提高组装性。
但是,在1组的逆变器中,仅用一个电位侧的晶体管及续流二极管的电路单元构成模块也可。在此情况下,通过组合6个半导体装置模块,构成图2所示的三相逆变器IV。
此外,并不是1组逆变器而是3组逆变器,即,以包含构成图2所示的三相逆变器IV的所有的电路单元的方式构成模块也可。在此情况下,仅用1个半导体装置模块构成图2所示的三相逆变器IV。从组装性的观点来看,在1个散热板4上配置用于构成三相逆变器的所有的电路单元的一方较为有利。
附图标记说明
1a IGBT;1b SBD;2电路基板;3、4散热板;5、7、7A第一主电极端子;6、6A、8第二主电极端子;9、9A连接构件;10布线构件;11、12接合材料;15、17树脂封装;16密封材料;18壳体;P1~P3导体图案。
Claims (15)
1.一种半导体装置模块,包括:
具有搭载有半导体元件的电路基板、
搭载所述电路基板的第一散热板、
以及与所述半导体元件的主电极电连接的主电极端子的至少一个电路单元;
搭载所述至少一个电路单元的第二散热板,
其中所述第一散热板以使其主表面与所述第二散热板的主表面垂直的方式搭载于所述第二散热板上,
所述主电极端子的一端与所述电路基板连接,向与所述第一散热板的所述主表面平行的方向延伸并且另一端从所述第一散热板上突出。
2.如权利要求1所述的半导体装置模块,其中,
所述主电极端子由板状构件构成,所述另一端具有中央部成为凹部且其两侧成为凸部的凹凸形状。
3.如权利要求2所述的半导体装置模块,其中,
所述至少一个电路单元为多个电路单元,
所述多个电路单元以使各自的所述第一散热板平行的方式搭载于所述第二散热板上。
4.如权利要求3所述的半导体装置模块,其中,
在所述多个电路单元间具备连接各所述主电极端子彼此的连接构件,
所述连接构件与所述主电极端子通过焊接来接合。
5.如权利要求4所述的半导体装置模块,其中,
所述连接构件由板状构件构成,端部的形状具有与所述主电极端子的所述凹凸形状相同的形状、尺寸,所述连接构件的凸部配置成与所述主电极端子的凸部相对。
6.如权利要求4所述的半导体装置模块,其中,
所述连接构件和所述主电极端子的接合部形成半球状的焊接部,其最大宽度为所述主电极端子的凸部的宽度的1.1倍以上。
7.如权利要求4所述的半导体装置模块,其中,
所述主电极端子的凹部的宽度为端子宽度的0.4倍以上。
8.如权利要求1所述的半导体装置模块,其中,
所述电路基板在其主表面上具有导体图案,
所述主电极端子的所述一端与所述导体图案连接,
所述至少一个电路单元具备电连接所述半导体元件的所述主电极和所述导体图案的布线构件。
9.如权利要求1所述的半导体装置模块,其中,
所述至少一个电路单元具有配置在所述第一散热板上并且以完全覆盖所述电路基板的方式形成的树脂封装,
所述主电极端子的所述另一端从所述树脂封装的侧面突出。
10.如权利要求1所述的半导体装置模块,其中,
具备壳体,该壳体搭载于所述第二散热板上,并包围所述主电极端子的除所述另一端以外的所述至少一个电路单元的周围,
在由所述壳体和所述第二散热板构成的框体内,填充有绝缘性的密封材料。
11.如权利要求1所述的半导体装置模块,其中,
以使与搭载所述电路基板的一侧相反侧的背面成为外侧的方式,所述第一散热板通过接合材料使与所述主电极端子突出的一侧相反侧的端面与所述第二散热板的端缘部接合,
所述至少一个电路单元具备树脂封装,树脂密封除所述第一散热板的所述背面以外的,整个所述至少一个电路单元。
12.如权利要求1所述的半导体装置模块,其中,
所述主电极端子由板状构件构成,具有所述另一端侧暂且向与其主表面垂直的方向弯曲而形成第一曲折部,进而向与主表面并行的方向折回而形成第二曲折部的Z字状的剖面形状。
13.如权利要求1所述的半导体装置模块,其中,
通过使与所述主电极端子突出的一侧相反例的端缘部夹于设置在所述第二散热板上的导轨状的单元安装部,固定所述第一散热板。
14.如权利要求1所述的半导体装置模块,其中,
利用接合材料,使所述第一散热板的与所述主电极端子突出的一侧相反侧的端面接合至所述第二散热板上。
15.如权利要求1所述的半导体装置模块,其中,
所述半导体元件为碳化硅半导体元件。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010-014912 | 2010-01-27 | ||
JP2010014912A JP5213884B2 (ja) | 2010-01-27 | 2010-01-27 | 半導体装置モジュール |
Publications (2)
Publication Number | Publication Date |
---|---|
CN102136472A true CN102136472A (zh) | 2011-07-27 |
CN102136472B CN102136472B (zh) | 2014-02-26 |
Family
ID=44296204
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201010571357.7A Active CN102136472B (zh) | 2010-01-27 | 2010-11-22 | 半导体装置模块 |
Country Status (5)
Country | Link |
---|---|
US (1) | US8610263B2 (zh) |
JP (1) | JP5213884B2 (zh) |
KR (1) | KR101173927B1 (zh) |
CN (1) | CN102136472B (zh) |
DE (1) | DE102011003205B4 (zh) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108140631A (zh) * | 2015-09-28 | 2018-06-08 | 三菱电机株式会社 | 半导体装置 |
CN111108677A (zh) * | 2017-10-12 | 2020-05-05 | 矢崎总业株式会社 | 半导体模块单元 |
CN112534572A (zh) * | 2018-08-20 | 2021-03-19 | 三菱电机株式会社 | 半导体模块 |
CN113508461A (zh) * | 2019-03-11 | 2021-10-15 | 株式会社电装 | 半导体装置 |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012145489A (ja) * | 2011-01-13 | 2012-08-02 | Sankei Engineering:Kk | 検査用プローブの製造方法 |
JP2013258387A (ja) | 2012-05-15 | 2013-12-26 | Rohm Co Ltd | パワーモジュール半導体装置 |
US10308856B1 (en) | 2013-03-15 | 2019-06-04 | The Research Foundation For The State University Of New York | Pastes for thermal, electrical and mechanical bonding |
US9543227B2 (en) | 2013-12-27 | 2017-01-10 | Mitsubishi Electric Corporation | Semiconductor device |
WO2015116924A1 (en) * | 2014-01-30 | 2015-08-06 | Arkansas Power Electronics International, Inc. | Low profile, highly configurable, current sharing paralleled wide band gap power device power module |
TWM496091U (zh) * | 2014-03-26 | 2015-02-21 | Leadray Energy Co Ltd | 具矽基座的發光二極體及發光二極體燈具 |
JP5862702B2 (ja) * | 2014-05-07 | 2016-02-16 | トヨタ自動車株式会社 | 三相インバータモジュール |
US10334715B2 (en) * | 2015-12-18 | 2019-06-25 | Intel Corporation | Systems, methods and devices for a package securing system |
JP6759784B2 (ja) | 2016-07-12 | 2020-09-23 | 三菱電機株式会社 | 半導体モジュール |
JP7159609B2 (ja) * | 2018-05-15 | 2022-10-25 | 株式会社デンソー | 半導体装置 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070215897A1 (en) * | 2006-03-16 | 2007-09-20 | Hong Shen | GaAs integrated circuit device and method of attaching same |
US20080251909A1 (en) * | 2007-04-02 | 2008-10-16 | Hitachi, Ltd. | Power Semiconductor Module for Inverter Circuit System |
JP2009231672A (ja) * | 2008-03-25 | 2009-10-08 | Mitsubishi Electric Corp | 電力用半導体装置 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS53140369A (en) | 1977-05-14 | 1978-12-07 | Matsushita Electric Works Ltd | Production of metal plate covered with multi-layer synthetic resins |
JPS545569A (en) | 1977-06-15 | 1979-01-17 | Mitsubishi Electric Corp | Hybrid integrated circuit device |
JPS62130547A (ja) | 1985-12-02 | 1987-06-12 | Mitsubishi Electric Corp | 半導体装置 |
JPH03101156A (ja) | 1989-09-13 | 1991-04-25 | Fujitsu Ltd | 半導体装置 |
JPH03117846A (ja) | 1989-09-29 | 1991-05-20 | Toshiba Corp | 空気調和装置 |
JP3021896B2 (ja) | 1991-11-15 | 2000-03-15 | 日本インター株式会社 | 複合半導体装置の製造方法 |
JPH05315517A (ja) * | 1992-05-12 | 1993-11-26 | Nec Corp | 半導体装置 |
JPH0794669A (ja) * | 1993-09-20 | 1995-04-07 | Toshiba Corp | 半導体パッケ−ジモジュ−ル |
JP3525832B2 (ja) | 1999-11-24 | 2004-05-10 | 株式会社デンソー | 半導体装置 |
JP4019989B2 (ja) | 2003-03-26 | 2007-12-12 | 株式会社デンソー | 半導体装置 |
JP2005142520A (ja) | 2003-10-14 | 2005-06-02 | Sumitomo Electric Ind Ltd | パワーモジュール |
KR100586698B1 (ko) * | 2003-12-23 | 2006-06-08 | 삼성전자주식회사 | 수직 실장된 반도체 칩 패키지를 갖는 반도체 모듈 |
JP2006019465A (ja) * | 2004-07-01 | 2006-01-19 | Mitsui Chemicals Inc | 半導体パッケージおよびその製造方法 |
JP4567570B2 (ja) * | 2005-10-17 | 2010-10-20 | 三菱電機株式会社 | 電力変換装置 |
JP4878520B2 (ja) | 2006-08-09 | 2012-02-15 | 本田技研工業株式会社 | 半導体装置 |
JP4667476B2 (ja) * | 2008-02-18 | 2011-04-13 | 三菱電機株式会社 | 電気部品の接続方法及び接続構造、並びにその接続構造を用いた電力変換装置 |
-
2010
- 2010-01-27 JP JP2010014912A patent/JP5213884B2/ja active Active
- 2010-10-20 US US12/908,327 patent/US8610263B2/en active Active
- 2010-11-22 CN CN201010571357.7A patent/CN102136472B/zh active Active
-
2011
- 2011-01-24 KR KR1020110006628A patent/KR101173927B1/ko active IP Right Grant
- 2011-01-26 DE DE102011003205.3A patent/DE102011003205B4/de active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070215897A1 (en) * | 2006-03-16 | 2007-09-20 | Hong Shen | GaAs integrated circuit device and method of attaching same |
US20080251909A1 (en) * | 2007-04-02 | 2008-10-16 | Hitachi, Ltd. | Power Semiconductor Module for Inverter Circuit System |
JP2008259267A (ja) * | 2007-04-02 | 2008-10-23 | Hitachi Ltd | インバータ回路用の半導体モジュール |
JP2009231672A (ja) * | 2008-03-25 | 2009-10-08 | Mitsubishi Electric Corp | 電力用半導体装置 |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108140631A (zh) * | 2015-09-28 | 2018-06-08 | 三菱电机株式会社 | 半导体装置 |
CN108140631B (zh) * | 2015-09-28 | 2021-02-05 | 三菱电机株式会社 | 半导体装置 |
CN111108677A (zh) * | 2017-10-12 | 2020-05-05 | 矢崎总业株式会社 | 半导体模块单元 |
CN111108677B (zh) * | 2017-10-12 | 2023-09-26 | 矢崎总业株式会社 | 半导体模块单元 |
CN112534572A (zh) * | 2018-08-20 | 2021-03-19 | 三菱电机株式会社 | 半导体模块 |
CN113508461A (zh) * | 2019-03-11 | 2021-10-15 | 株式会社电装 | 半导体装置 |
CN113508461B (zh) * | 2019-03-11 | 2023-08-11 | 株式会社电装 | 半导体装置 |
Also Published As
Publication number | Publication date |
---|---|
DE102011003205B4 (de) | 2014-01-16 |
KR101173927B1 (ko) | 2012-08-16 |
JP5213884B2 (ja) | 2013-06-19 |
US8610263B2 (en) | 2013-12-17 |
KR20110088404A (ko) | 2011-08-03 |
CN102136472B (zh) | 2014-02-26 |
DE102011003205A1 (de) | 2011-07-28 |
JP2011155088A (ja) | 2011-08-11 |
US20110180809A1 (en) | 2011-07-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN102136472B (zh) | 半导体装置模块 | |
CN107210238B (zh) | 功率模块 | |
US9379083B2 (en) | Semiconductor device and method for manufacturing semiconductor device | |
JP7204770B2 (ja) | 両面冷却型パワーモジュールおよびその製造方法 | |
JP4455488B2 (ja) | 半導体装置 | |
CN105190874B (zh) | 半导体模块及半导体装置 | |
JP5863602B2 (ja) | 電力用半導体装置 | |
CN104170085A (zh) | 半导体装置 | |
JP5659938B2 (ja) | 半導体ユニットおよびそれを用いた半導体装置 | |
JP5895220B2 (ja) | 半導体装置の製造方法 | |
CN102446864A (zh) | 功率模块及其制造方法 | |
US10615131B2 (en) | Semiconductor device with high quality and reliability wiring connection, and method for manufacturing the same | |
JP5213919B2 (ja) | 半導体装置 | |
WO2018151010A1 (ja) | 半導体装置 | |
JP2015176871A (ja) | 半導体装置及びその製造方法 | |
CN112331632B (zh) | 半导体装置 | |
JP4620566B2 (ja) | 半導体装置およびその製造方法 | |
CN103296019A (zh) | 半导体装置以及用于制造半导体装置的方法 | |
JP4336205B2 (ja) | パワー半導体モジュール | |
US8215008B2 (en) | Method for producing a housing part for a semiconductor module | |
JP7278077B2 (ja) | 半導体装置およびその製造方法 | |
JP2012227455A (ja) | 半導体モジュール | |
CN114556548A (zh) | 功率模块 | |
CN117913059A (zh) | 引脚件、连接件及其制作方法以及功率模块的制作方法 | |
JP2013058809A (ja) | 半導体装置モジュール |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant |