CN101836518A - 陶瓷多层基板 - Google Patents

陶瓷多层基板 Download PDF

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Publication number
CN101836518A
CN101836518A CN200880109134.XA CN200880109134A CN101836518A CN 101836518 A CN101836518 A CN 101836518A CN 200880109134 A CN200880109134 A CN 200880109134A CN 101836518 A CN101836518 A CN 101836518A
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China
Prior art keywords
dielectric constant
layer
weight portions
ceramic
low
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CN200880109134.XA
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CN101836518B (zh
Inventor
长谷川朋之
长友贵志
井出良律
小田切正
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NGK Insulators Ltd
Soshin Electric Co Ltd
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NGK Insulators Ltd
Soshin Electric Co Ltd
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    • H05K1/162—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed capacitors
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
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Abstract

本发明提供一种陶瓷多层基板，其通过将由低介电常数的绝缘体组成的低介电常数层和由高介电常数的电介质组成的高介电常数层进行共烧结而得到。低介电常数层包括具有xBaO-yTiO2-zZnO(x，y，z分别表示摩尔比，x+y+z＝1，0.09≤x≤0.20，0.49≤y≤0.61，0.19≤z≤0.42)组成的低介电常数陶瓷成分，和相对于100重量份的该低介电常数陶瓷成分添加量为1.0重量份以上、5.0重量份以下的含氧化硼的玻璃成分。高介电常数层是由添加有CuO和Bi2O3的钛酸钡系电介质组成。

Description

陶瓷多层基板
技术领域
本发明为涉及陶瓷多层基板的发明。
背景技术
近年来，试图通过在陶瓷多层基板中内藏原本安装在陶瓷基板表面的电容器或感应器等被动元件，使电子器械小型化和高密度化。为了制作这样的陶瓷多层基板，通过刮板法将电介质瓷组合物和有机溶剂的混合浆料来制作生片，使其干燥后，在该生片上面印刷布线导体。然后，层叠与上述同样的电介质瓷组合物的生片来作为层叠物，同时进行烧成。
像这样的陶瓷多层基板由于要在高速下进行高效能的信号处理，因此，使用比电阻小的Ag或Cu作为布线导体。由此，正在开发在比Ag的熔点962℃和Cu的溶点1084℃低的温度下，与这些能够同时烧成的各种陶瓷材料。
可是，上述陶瓷多层基板为了抑制杂散电容或布线间的耦合电容等，一般适宜地使用介电常数为10以下的基板，而另一方面，在陶瓷多层基板内部形成电容器时，优选构成电容器的陶瓷的介电常数高。
钛酸钡系电介质瓷组合物一般介电常数高，在陶瓷多层基板内部可以形成高容量的电容器。但是，烧结温度高，需要为1150～1200℃以上，因此，不能使用Ag或Cu作为同时被烧成的布线导体。因此，需要在1000℃以下的温度下可以烧结的、具有实用性的介电常数的钛酸钡系的电介质瓷组合物。
有关钛酸钡系电介质瓷组合物已知有各种各样的现有技术。在特开昭54-53300中记载有，在铅添加系中添加有氧化铜和氧化铋。
另外，在日本特开2006-93484、日本特开平5-325641中记载有无铅系的可低温烧成的钛酸钡系电介质。
进而，在“应用物理日本学报”(Japanese Journal of Applied physics)，Vol.45.No.9B，2006，pp7360-7364“Dielectric Properties and Microstructures ofLow-Temperature-Sintered BaTiO3-Based Ceramics with CuBi2O4 sintering Aid”中，公开有相对于钛酸钡电介质不添加玻璃，而添加作为烧结助剂的CuBi2O4。由此，确认出钛酸钡电介质在920℃下可以烧结，并且得到良好比介电常数的温度特性。特别是公开了可以得到大约1900的比介电常数和大约0.6％的介电损耗。
另外，在陶瓷多层基板用途中，已知有多种低介电常数的陶瓷(日本特开平9-301768、日本特开2000-264722、日本特开2000-264723)。
发明内容
在新的有用的陶瓷多层基板的开发时，需要将构成电容器乃至感应器等高介电常数的陶瓷层和低介电常数的陶瓷层层叠，使其一体化。另外，由上述的理由可知，需要在1000℃以下的低温区域内、可致密地烧成高介电常数的陶瓷层和低介电常数的陶瓷层，并且需要在不分层或无开裂下接合两者。而且，在高介电常数的陶瓷层和低介电常数的陶瓷层之间，在共烧结时产生成分扩散，作为其结果有恶化介电特性的倾向。目前还没有已解决这些问题点的陶瓷层叠体。
本发明人在特愿2006-235529中公开了一种可低温烧成、且介电损耗小的高介电常数钛酸钡系电介质。但是，其与低介电常数陶瓷层共烧结时，虽然需要两者牢固地接合且在不分层或无开裂下进行接合，但却没有提供这样的技术。
本发明的课题在于提供钛酸钡系的高介电常数层和低介电常数层的层叠体，通过低温烧成来接合，且能抑制分层或开裂。
本发明提供一种通过低介电常数层和高介电常数层的共烧结而得到的陶瓷多层基板。低介电常数层包括低介电常数陶瓷成分和含氧化硼的玻璃成分。该低介电常数陶瓷成分具有xBaO-yTiO2-zZnO(x，y，z分别表示摩尔比，x+y+z＝1，0.09≤x≤0.20，0.49≤y≤0.61，0.19≤z≤0.42)的组成，该含氧化硼的玻璃成分的添加量相对于100重量份的该低介电常数陶瓷成分为1.0重量份以上、5.0重量份以下。高介电常数层是添加有CuO和Bi2O3的钛酸钡系电介质。
根据本发明，通过向钛酸钡系电介质中添加CuO和Bi2O3，可以降低钛酸钡系电介质的最适烧成温度。特别是可以为1000℃以下。而且，发现如果将上述的特定组成的BaO-TiO2-ZnO系低介电常数陶瓷与上述的可低温烧成的钛酸钡系电介质进行共烧结，发现可以提高接合强度，并可抑制在接合面的分层或开裂，另外，接合界面的成分扩散也被抑制，从而完成本发明。
附图说明
图1是示意性地显示本发明陶瓷多层基板一例子的截面图。
具体实施方式
本发明的钛酸钡系电介质的介电常数没有特别地限定。但是，在以如电介质电容器这样的高介电常数为必须的用途中，优选介电常数例如为1000以上。
钛酸钡系电介质是指以钛酸钡为主成分的电介质。具体的是，在原料阶段可以是钛酸钡的临时烧成物，或者还可以是烧结后生成钛酸钡的氧化钛和氧化钡的混合物。另外，钛酸钡系电介质全体如果为100摩尔％，100摩尔％的全体可以由钛酸钡组成。或者，电介质的钡部位中30摩尔％以下可以由锶、钙和镁来置换。另外，电介质的钛部位中30摩尔％以下可以由锆来置换。
在本发明中，向钛酸钡系电介质中添加CuO和Bi2O3。由此，可以减低钛酸钡系电介质的烧成温度。
添加的方法可以如下所示。
(1)以各自的氧化物的形式添加CuO和Bi2O3。
(2)添加CuO和Bi2O3的复合氧化物。
(3)同时添加(1)的多种氧化物和(2)的复合氧化物。
(2)、(3)的复合氧化物可以通过临时烧成而生成。另外，作为复合氧化物可以列举CuBi2O4。
由本发明的观点出发，相对于100重量份的钛酸钡系电介质，优选添加0.5重量份以上、4.0重量份以下的CuO和4.0重量份以上、9.0重量份以下的Bi2O3。
通过向100重量份的钛酸钡系电介质中添加0.5重量份以上的CuO和4.0重量份以上的Bi2O3，可以提高在1000℃以下烧成时的瓷器的致密性和介电常数，使接合性也提高成为可能。由这个观点，更优选CuO的添加量为0.85重量份以上，另外，Bi2O3的添加量更优选为5.0重量份以上。
另外，通过相对于100重量份的钛酸钡系电介质，CuO的添加量为5.0重量份以下和Bi2O3的添加量为9.0重量份以下，可以提高在1000℃以下烧成时的瓷的致密性和介电常数，使接合性也提高成为可能。由这个观点，更优选CuO的添加量为3.0重量份以下，另外，Bi2O3的添加量更优选为8.0重量份以下。
本发明的陶瓷多层基板的共烧结优选在900～1000℃下进行。共烧结温度不到900℃，烧结困难。另外，通过使烧结温度为1000℃以下，可以开展广范的用途，产业上的优点多。烧结温度更优选为980℃以下。另外，使用作为导体的Ag等时，优选烧结温度为950℃以下。
在本发明的钛酸钡系电介质中实质上不含有Pb的氧化物，因此优选。但不能排除微量的不可避免的杂质。
在本发明的钛酸钡系电介质中实质上不含有玻璃成分。另外，作为各金属成分的原料可以例示各金属的氧化物、硝酸盐、碳酸盐和磷酸盐。
本发明的低介电常数是由低介电常数陶瓷成分和在该低介电常数陶瓷成分中添加的含氧化硼的玻璃成分组成。在这里，低介电常数层意味着比介电常数为30以下的层。
上述低介电常数陶瓷成分是具有xBaO-yTiO2-zZnO(x，y，z分别表示摩尔比，x+y+z＝1，0.09≤x≤0.20，0.49≤y≤0.61，0.19≤z≤0.42)组成的瓷器。通过该范围的组成，在共烧结时与高介电常数陶瓷层的接合性好，另外降低比介电常数，可以得到低温下的致密的瓷器。
由本发明的观点，上述低介电常数陶瓷成分中的BaO的比率x更优选为0.11以上，且更优选为0.15以下。另外，上述低介电常数陶瓷成分中的TiO2的比率y更优选为0.5以上，且更优选为0.6以下。上述低介电常数陶瓷成分中的ZnO的比率z更优选为0.3以上，且更优选为0.4以下。
通过在100重量份的上述低介电常数陶瓷成分中添加1.0重量份以上、且5.0重量份以下的含氧化硼的玻璃成分，可以有效地降低低介电常数层的烧结温度。
该含氧化硼的玻璃成分意味着至少含有氧化硼的玻璃成分。该玻璃成分可以只是氧化硼，但是优选含有氧化硼以外的金属氧化物。作为氧化硼以外的金属氧化物成分，可以例示BaO、Al2O3、ZnO、SiO2和碱金属氧化物。
在优选的实施方式中，上述陶瓷多层基板含有BaO-Al2O3-SiO2系陶瓷，通过与该BaO-Al2O3-SiO2系陶瓷共烧结来接合低介电常数陶瓷层。
BaO-Al2O3-SiO2系陶瓷可以在陶瓷多层基板内将比电阻小的Ag、Cu、Ag-Pd等低熔点金属作为布线导体，同时进行烧结，从而可以形成高频率特性优异的陶瓷多层基板。另外，由于几乎与上述低电介常数层的玻璃成分为相同组成，因此，接合强度大，由共烧结而成的基板特性的变动也少。
BaO-Al2O3-SiO2系陶瓷优选具有以下的组成。
必须成分：
BaO：40～65重量份
Al2O3：0.1～20重量份
SiO2：25～46重量份
任意成分：
ZnO：0.5～20重量份
还可以根据需要添加0.3～5.0重量份的上述含氧化硼的玻璃成分的任何一种。
本发明中，上述的各金属氧化物成分的比率为换算成原料混合物中各金属氧化物的值。换算成原料混合物中各金属氧化物的值由各金属原料的混合比率来决定。本发明中，由精密天平来称量各金属原料的混合比率，根据该称量值来算出上述换算值。
本发明的陶瓷多层基板优选具有由Ag、Cu和Ag-Pd合金组成的群中选出的材质组成的导电膜。
另外，本发明的陶瓷多层基板优选具有一对电极层，在该一对电极层之间配置上述高介电常数陶瓷层，由该一对电极层产生规定的静电容量。
在制造本发明的陶瓷多层基板时，优选称量各氧化物粉末为希望的组成，进行湿式混合，得到关于钛酸钡系电介质和低介电常数电介质双方的各混合粉末。其后，低介电常数材料在900℃～1300℃的范围(优选为1050℃以上)和高介电常数材料在900～1200℃的范围(优选为1000～1100℃)进行临时烧成。粉碎临时烧成体，得到各陶瓷粉末。然后，优选混合各陶瓷粉末和有机粘合剂、可塑剂、分散剂和有机溶剂，由刮板法进行板成型，将其层叠而得到层叠体。在900～1000℃下，烧成该层叠体，得到陶瓷多层基板。
图1表示适用本发明的陶瓷多层基板的一个例子。本图为示意性地显示内藏LC的多层布线基板的截面图。在多层布线基板10上隔着外装电极3和焊料凸点2搭载集成电路1。多层布线基板10例如由上述这样的低介电常数层4和高介电常数层5、6组成。根据适宜地设计，水平或垂直地形成内层电极7和贯通导体8，从而构成多层布线。在多层基板10中，C1、C2和C3都形成电容器，L1形成感应器，可以用于各种各样规定的用途中，另外，可以在低介电常数层4中，例如由BaO-Al2O3-SiO2系陶瓷来形成L1的层。
实施例
实验A
电介质原料的制作
称量各氧化物粉末为希望的组成，进行湿式混合，得到关于钛酸钡系电介质和低介电常数电介质双方的各混合粉末。其后，低介电常数材料在1050～1300℃下进行临时烧成，高介电常数材料在1000～1100℃下进行临时烧成。然后，粉碎，得到各陶瓷原料粉末。
制作玻璃
制作表1所示的各种玻璃A、B、C。称量构成各玻璃成分的各氧化物，通过干式混合得到混合物。其后，使其在铂坩埚中熔融，在水中急速地冷却熔融物，得到块状的玻璃。湿式粉碎该玻璃，得到各低熔点玻璃粉末。
表1
Figure GPA00001070272100061
低介电常数材料的调制
添加所得到的临时烧成物和玻璃，以及根据需要添加规定量的CuO，进行粉碎得到低介电常数陶瓷原料粉末。表2～5所记载的低介电常数组成的介电常数全部为20～30，Q值(3GHz)为3000以上。
高介电常数材料的调制
向钛酸钡系电介质临时烧成物中添加规定量的CuO和B2O3，进行粉碎得到表2～5所记载的各高介电常数陶瓷原料。
薄片成形(tape casting)
在调制的各原料粉末中添加有机粘合剂、可塑剂、分散剂和有机溶剂，用球磨机进行混合，得到浆料。使用该浆料由刮板法装置成型厚度为0.02～0.1mm的生片。
接合性、弯曲强度试验
将低介电常数陶瓷生片层叠使之烧成后厚度为2mm左右，在其中间插入高介电常数陶瓷生片后进行烧成，取出大约3mm×30mm×2mm的试验片，进行3点弯曲试验。接合性是对同样的结构物进行镜面抛光，用电子显微镜观察接合界面部的开裂、空隙和相互扩散。表2、3、4、5表示该结果。
介电常数测定
相对于在低介电常数陶瓷生片的中间插入有高介电常数陶瓷生片的结构物，预先以高介电常数层的一部分为容量层的方式，由网板印刷形成电极图案(电极的叠加面积烧成后为2mm2)，由贯通电极引出电极。其后，切割成适当大小，测定容量，算出介电常数。表2、3、4、5表示其结果。
表2
Figure GPA00001070272100071
这里，“接合性”的项目没有扩散、微小开裂、分层，弯曲强度为200MPa以上时为“○”。观察到扩散或微小开裂时为“△”，扩散成分多或者观察到分层或开裂时为“×”。
如表2所示，试料1中BaO的比率x为本发明以外，观察到扩散、微小开裂。试料2、3得到良好的接合性。试料4中，向低介电常数层的玻璃添加量为0.5重量部，为本发明以外，与高介电常数层的接合性低。试料5、6、7、8得到良好的接合性。试料9中向低介电常数层的玻璃添加量为6.0重量部，为本发明以外，观察到扩散、微小开裂。
表3
Figure GPA00001070272100081
如表3所示，试料10、11得到良好的接合性。试料12、13中BaO的比率x为0.22、0.25，为本发明以外，降低接合性。试料14、15中TiO2的比率y为本发明以外，降低接合性。试料16、17中TiO2的比率y和ZnO的比率z为本发明以外，降低接合性。试料18、19得到良好的接合性。
表4
Figure GPA00001070272100091
如表4所示，通过在低介电常数层中添加CuO，可以得到进一步提高被共烧结的高介电常数层的介电常数这样的作用效果。相对于100重量份的低介电常数陶瓷成分，该比率特别优选为20重量份以下，进一步优选为2～20重量份。
表5
如表5所示，试料27～37得到良好的弯曲强度和介电常数。
以上说明了本发明的特定实施方式，但是本发明不限定于这些特定的实施方式，在不脱离权利要求保护的范围，可进行各种各样的变更或改变来实施。

Claims (7)

1.一种陶瓷多层基板，其为通过低介电常数层和高介电常数层的共烧结而得到的陶瓷多层基板，其特征在于，
所述低介电常数层包括具有xBaO-yTiO2-zZnO(x，y，z分别表示摩尔比，x+y+z＝1，0.09≤x≤0.20，0.49≤y≤0.61，0.19≤z≤0.42)组成的陶瓷成分，和相对于100重量份的该陶瓷成分添加量为1.0重量份以上、5.0重量份以下的含氧化硼的玻璃成分，
所述高介电常数层是添加有CuO和Bi2O3的钛酸钡系电介质。
2.根据权利要求1所述的陶瓷多层基板，其中，在所述高介电常数层中，相对于100重量份的所述钛酸钡系电介质，添加0.5重量份以上且4.0重量份以下的CuO，和4.0重量份以上且9.0重量份以下的Bi2O3。
3.根据权利要求1或2所述的陶瓷多层基板，其中，在所述低介电常数层中，相对于100重量份的所述陶瓷成分，添加20重量份以下的CuO。
4.根据权利要求1～3中任一项所述的陶瓷多层基板，其中，所述陶瓷多层基板含有BaO-Al2O3-SiO2系陶瓷，所述低介电常数层通过共烧结来与该BaO-Al2O3-SiO2系陶瓷接合。
5.根据权利要求1～4中任一项所述的陶瓷多层基板，其中，所述共烧结的温度为1000℃以下。
6.根据权利要求1～5中任一项所述的陶瓷多层基板，其中，具有由Ag、Cu和Ag-Pd合金组成的群中选出的材质组成的导电膜。
7.根据权利要求1～6中任一项所述的陶瓷多层基板，其中，具有一对电极层，在该一对电极层之间配置所述高介电常数层，由该一对电极层产生规定的静电容量。
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