CN101683006A - 电子部件内置线路板及其制造方法 - Google Patents
电子部件内置线路板及其制造方法 Download PDFInfo
- Publication number
- CN101683006A CN101683006A CN200880015470A CN200880015470A CN101683006A CN 101683006 A CN101683006 A CN 101683006A CN 200880015470 A CN200880015470 A CN 200880015470A CN 200880015470 A CN200880015470 A CN 200880015470A CN 101683006 A CN101683006 A CN 101683006A
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- Prior art keywords
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- circuit board
- built
- splicing ear
- electronic parts
- Prior art date
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49147—Assembling terminal to base
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
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- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
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Abstract
在以能够分离的状态将铜箔配置在载体上而得到的第一基材上形成用于安装电子部件(2)的连接端子(80)。并且,将连接端子(80)与电子部件(2)的凸块(20)电连接,在电子部件(2)与第一基材之间填充填底材料(4)。然后,由绝缘构件(3)覆盖电子部件(2)。然后,分离载体和铜箔,进行蚀刻来去除露出的不需要的铜箔,则得到电子部件内置线路板(1)。
Description
技术领域
本发明涉及一种在内部容纳有半导体元件等电子部件的电子部件内置线路板。
背景技术
近年来,随着电子设备的高性能化、小型化的发展,被安装在电子设备内部的线路板的高功能化、高集成化的要求日益变高。
对此,提出了各种将IC芯片等电子部件容纳(内置)于线路板内的技术(例如,专利文献1)。
如专利文献1所公开的那样,通过将电子部件内置于线路板,能够实现多层线路板的高功能化和高密度化。也就是说,通过将电子部件容纳在内部,能够在表层的安装区域安装其它电子部件等,能够实现高功能化。
另外,通过内置电子部件,还能够使多层线路板本身变小,与以往的多层线路板相比,能够使电路高密度化。
并且,由于能够减少布线长,因此还能够期待性能提高。
专利文献1:日本特表2005-517287号公报
发明内容
发明要解决的问题
另外,为了以细间距形成与内置的电子部件进行连接的连接端子,要求形成该连接端子的金属层(也可以由多个层构成)的表面平坦。并且,为了确保表面的平坦性,一般希望该金属层具有一定以上的厚度。另一方面,如果将金属层的厚度设得较大,则还担心在安装电子部件后的工序中连接端子由于该金属层的蚀刻而受到损伤。
关于这一点,上述专利文献1以及其它现有技术都没有示出任何解决方法。
另外,在上述专利文献1以及其它现有技术中,构成内置了电子部件的线路板(相当于多层线路板中的芯基板)的绝缘层以该芯基板的厚度方向的中心线为基准,以偏向一侧、即电子部件与构成该芯基板的导体层的接合面的相反面一侧的方式被形成。
这种非对称结构难以缓冲由于应力(热、振动冲击、落下冲击等)而产生的应力,其结果,有可能导致多层线路板产生翘曲。因此,在现有技术中,存在难以确保电子部件的连接可靠性的问题。
本发明是鉴于上述情形而完成的,其第一目的在于提供一种能够以细间距形成与电子部件进行连接的连接端子的电子部件内置型的线路板的制造方法。
另外,其第二目的在于提供一种能够确保所安装的电子部件的连接可靠性的电子部件内置型的线路板的制造方法。
用于解决问题的方案
本发明所涉及的电子部件内置线路板的制造方法的特征在于,具有以下工序:连接端子形成工序,在以能够分离的状态将第一金属箔配置在支承体上而得到的第一层叠基材的上述第一金属箔上,通过添加法形成用于安装电子部件的连接端子;安装工序,在上述第一层叠基材上使上述电子部件的电路形成面与上述连接端子的形成面相面对地配置该电子部件,将上述电子部件与上述连接端子电连接;覆盖工序,用绝缘构件覆盖该安装工序后的上述电子部件;分离工序,将上述支承体与上述第一金属箔分离;以及去除工序,去除露出的上述第一金属箔。
优选在上述安装工序后,还具有对上述连接端子的周围填充绝缘性树脂的工序。
另外,也可以还具有以下工序:在以能够分离的状态将第二金属箔配置在上述支承体上而得到的第二层叠基材的上述第二金属箔上形成导体图案;以及在上述覆盖工序后,使上述导体图案的形成面与上述绝缘构件的表面密合地层叠上述第二层叠基材。
另外,优选上述覆盖工序包括以覆盖上述电子部件的方式载置上述绝缘构件的工序。在这种情况下,更优选设上述绝缘构件由预浸料构成,该绝缘构件至少组合配合上述电子部件的形状进行了开孔加工的预浸料与没有进行开孔加工的薄片状的预浸料而形成。
另外,优选在上述电子部件上形成用于与上述连接端子接合的凸块。
另外,优选上述连接端子的至少一部分利用由包含锡、银以及铜的合金构成的焊锡构成。
另外,优选填充于上述连接端子的周围的上述绝缘性树脂包含无机填料。
另外,优选第一金属箔是铜箔。
另外,也可以还具有以下工序:对上述覆盖工序后的基板设置贯通孔,形成通孔导体以及与该通孔导体相连接的通孔连接盘的工序。
另外,也可以还具有以下工序:在上述绝缘构件上隔着层间绝缘构件形成上层导体图案的工序;形成将上述连接端子与上述上层导体图案电连接的电路连接用通路孔的工序;以及形成将上述通孔连接盘与上述上层导体图案电连接的通孔连接盘连接用通路孔的工序.
本发明所涉及的电子部件内置线路板的特征在于,具备:连接端子,其通过添加法形成;电子部件,其与该连接端子电连接;绝缘构件,其覆盖该电子部件;导体图案,其埋设于该绝缘构件;通孔导体,其设置于上述绝缘构件;以及通孔连接盘,其与该通孔导体相连接,其中,该通孔连接盘从上述绝缘构件的表面突出。
优选上述通孔连接盘的厚度比埋设于上述绝缘构件的上述导体图案的厚度厚。
也可以设为如下结构,即,具备:上层导体图案,其隔着层间绝缘构件形成在上述绝缘构件上;电路连接用通路孔,其将上述连接端子与上述上层导体图案电连接,或将上述导体图案与上述上层导体图案电连接;以及通孔连接盘连接用通路孔,其将上述通孔连接盘与上述上层导体图案电连接,其中,该通孔连接盘连接用通路孔与上述通孔连接盘之间的连接面的面积大于上述电路连接用通路孔与上述连接端子之间或上述电路连接用通路孔与上述导体图案之间的连接面的面积。
发明的效果
根据本发明,能够提供一种实现与电子部件相连接的连接端子的细间距化并且还能够确保与所安装的电子部件的连接可靠性的电子部件内置线路板。
附图说明
图1A是表示第一基材的结构的截面图。
图1B是表示在第一基材的铜箔上形成了第一基底层和第二基底层的情形的截面图。
图1C是表示在图1B的基板的第二基底层上层压了感光性抗蚀剂的情形的截面图。
图1D是表示在图1B的基板的第二基底层上形成了抗镀层的情形的截面图。
图1E是表示对图1D的基板形成了镀铜层的情形的截面图。
图1F是表示剥离抗镀层后、图1E的基板表面被粗糙化的情形的截面图。
图1G是表示在图1F的基板表面形成了阻焊层的情形的截面图。
图1H是表示在图1G的基板的焊盘上形成了接合层的情形的截面图。
图2A是表示电子部件的安装工序的截面图。
图2B是表示电子部件的安装工序的截面图。
图3A是表示层叠工序的截面图。
图3B是表示层叠工序的截面图。
图3C是表示层叠工序的截面图。
图4A是表示后工序的截面图。
图4B是表示后工序的截面图。
图4C是表示后工序的截面图。
图4D是表示后工序的截面图。
图4E是表示后工序的截面图。
图4F是表示本发明的一个实施方式所涉及的电子部件内置线路板的结构的截面图。
图5A是表示用图4F的电子部件内置线路板制造多层线路板的工序的截面图。
图5B是表示用图4F的电子部件内置线路板制造多层线路板的工序的截面图。
图5C是表示用图4F的电子部件内置线路板制造多层线路板的工序的截面图。
图5D是表示用图4F的电子部件内置线路板制造多层线路板的工序的截面图。
图5E是表示用图4F的电子部件内置线路板制造多层线路板的工序的截面图。
图5F是表示使用了图4F的电子部件内置线路板的多层线路板的结构的截面图。
图6是用于说明图5F的多层线路板的特征的要部截面图。
图7是表示本发明的另一实施方式所涉及的电子部件内置线路板的结构的截面图。
图8是从连接端子形成侧观察图6的电子部件内置线路板的俯视图。
图9是表示本发明的另一实施方式所涉及的多层线路板的结构的截面图。
附图标记说明
1:电子部件内置线路板;2:电子部件;3:绝缘构件;4:填底材料;5:填充树脂;20:凸块;40、50、60、70:导体图案;80:连接端子;81:焊盘;82:接合层;90:通孔导体;91、92、93、94:通孔连接盘;112:阻焊层。
具体实施方式
下面,参照附图说明本发明的一个实施方式所涉及的电子部件内置线路板。
图4F是本实施方式所涉及的电子部件内置线路板1的概要截面图。该电子部件内置线路板1例如用作多层印刷线路板的芯基板等。
电子部件内置线路板1由电子部件2、绝缘构件3、填底材料4、填充树脂5、内层的导体图案40、50、阻焊层112、外层的导体图案60、70、连接端子80以及通孔导体90构成。
绝缘构件3是使环氧树脂、聚酯树脂、聚酰亚胺树脂、双马来酰亚胺-三嗪树脂(BT树脂)、酚醛树脂等树脂浸渗在玻璃纤维、芳香族聚酰胺纤维等加强材料中而形成的板材,在本实施方式中由预浸料构成。
填底材料4例如是包含二氧化硅、氧化铝等无机填料的绝缘性树脂,起到如下作用:确保电子部件2的固定强度,并且吸收由于电子部件2与绝缘构件(例如,绝缘构件3、填充树脂5)之间的热膨胀率的差别而产生的应变。填底材料4优选为由热固化性树脂和40~90wt%的无机填料构成。另外,填料的尺寸(平均粒径)优选为0.1~3.0μm。
填充树脂5优选为由热固化性树脂和无机填料构成。无机填料例如能够使用Al2O3、MgO、BN、AlN或SiO2等。热固化性树脂例如优选耐热性高的环氧树脂、酚醛树脂或氰酸酯树脂,其中特别优选耐热性好的环氧树脂。
由铜等构成的导体图案40被形成在电子部件内置线路板1的第一表面侧(与电子部件2的电路形成面相对的一侧)的内部(以下称为第一内层)。导体图案40的厚度大约是15μm,其一部分成为构成连接端子80的焊盘81、与通孔导体90连接的第一内层的通孔连接盘91。
由铜等构成的导体图案50被形成在电子部件内置线路板1的第二表面(与第一面相反侧的主表面)的内侧(以下称为第二内层),其一部分成为与通孔导体90连接的第二内层的通孔连接盘92。其厚度大约是15μm。第一内层的通孔连接盘91和第二内层的通孔连接盘92通过通孔导体90而电连接。
由铜等构成的导体图案60被形成在电子部件内置线路板1的第一表面上(以下称为第一外层),其一部分成为与通孔导体90连接的第一外层的通孔连接盘93。导体图案60的厚度大约是20μm。
由铜等构成的导体图案70被形成在电子部件内置线路板1的第二表面上(以下称为第二外层),其一部分成为与通孔导体90连接的第二外层的通孔连接盘94。导体图案70的厚度大约是20μm。
连接端子80是用于与电子部件2电连接的端子,由焊盘81和接合层82构成。焊盘81的厚度大约是15μm。
接合层82例如通过镀锡、镀焊锡或镀锡-银-铜等镀合金、或者由包含锡、银以及铜的合金构成的焊锡构成,其厚度大约是15μm。
在电子部件2上设置有凸块20(例如厚度大约为30μm的柱形金凸块(Au Stud Bump)),凸块20与连接端子80电连接。
接着,参照图1A~图4E说明电子部件内置线路板1的制造方法。
(1)连接端子80的形成工序(图1A~图1H)
首先,准备图1A所示的第一基材100。第一基材100是使用粘结剂(剥离层)可剥离(分离)地粘结铜箔101和由铜构成的载体102而得到的所谓的带载体的铜箔。在此,铜箔101的厚度大约是5μm,载体102的厚度大约是70μm。此外,作为载体102,并不限于铜,还能够采用绝缘构件等。
接着,在第一基材100的铜箔101上使用添加法来形成用于安装电子部件2的连接端子80。
此外,在通过添加法形成连接端子80之前,如图1B所示,作为第一基底层110,通过无电解镀、电解镀、溅射等方法在第一基材100的铜箔101的整个表面上将镍等金属形成为厚度大约1μm。由此,能够防止由于蚀刻引起的腐蚀,能够形成精细图案。
另外,如本实施方式那样,在形成阻焊层112的情况下,如图1B所示,作为第二基底层111,通过无电解镀、溅射等方法在第一基底层的整个表面上将钛等金属形成为厚度大约0.1μm。由此,能够得到提高与阻焊层112之间的密合性的效果。
在此,添加法是指在使镀膜在抗镀层图案的非形成部分生长之后通过去除抗镀层来形成导体图案的方法。以下具体说明。
在图1B的基板的第二基底层111上层压干膜状的感光性抗蚀剂103(参照图1C)。然后,使掩模与层压后的感光性抗蚀剂103密合,利用紫外线进行曝光,利用碱性水溶液进行显影。其结果,形成仅相当于导体图案10的部分开口的抗镀层104(参照图1D)。
接着,对图1D的基板进行水洗,在使其干燥之后进行电解镀铜,形成厚度大约为15μm的镀铜层105(参照图1E)。
接着,在剥离抗镀层104之后,通过黑化处理、化学蚀刻处理(CZ处理)等表面粗糙化方法对所形成的导体图案10以及焊盘81的表面进行粗糙化(参照图1F)。
然后,在图1F的基板表面形成相当于焊盘81的部分开口的阻焊层112(参照图1G),然后形成接合层82(参照图1H)。在此,接合层82例如通过镀锡、镀焊锡或镀锡-银-铜等镀合金来形成。或者,也可以通过印刷由包含锡、银以及铜的合金构成的焊锡膏并进行回流焊来形成。
通过以上处理,能够得到用于与电子部件2的凸块20接合的连接端子80。
这样,在添加法中不需要蚀刻,因此能够以细间距形成导体图案10以及连接端子80。
(2)电子部件2的安装工序(图2A、图2B)
接着,以倒装方式将电子部件2的凸块20与设置于第一基材100的连接端子80接合,来将电子部件2安装到第一基材100(参照图2A)。在安装电子部件2之后,对电子部件2与第一基材100之间所产生的空隙填充填底材料4(参照图2B)。
如上所述,填底材料4例如是包含二氧化硅、氧化铝等无机填料的绝缘性树脂。
(3)层叠工序(图3A~图3C)
接着,将绝缘构件30a与绝缘构件30b载置在第一基材100的电子部件2的安装面上(参照图3A)。绝缘构件30a、30b是使树脂浸渗在玻璃布等加强材料中而形成的板材(在本实施方式中是预浸料)。配合电子部件2的形状对绝缘构件30a实施开孔加工,在相对于电子部件2的安装面平行的方向包围电子部件2地载置绝缘构件30a。在开孔加工中冲孔加工法(穿孔)较佳。此外,也可以使用机械钻孔机、激光等。
另一方面,绝缘构件30b没有被实施开孔加工,是薄片状,被载置在绝缘构件30a上以及与电子部件2的凸块20形成面相反的面上。
在载置绝缘构件30a、30b之后,在绝缘构件30b上使导体图案50的形成面与绝缘构件30b的上表面密合地层叠形成有导体图案50的第二基材500(参照图3B、图3C)。
第二基材500是与第一基材100同样的带载体的铜箔,具备厚度大约为5μm的铜箔501和厚度大约为70μm的载体502。与导体图案10的形成同样地,通过添加法形成导体图案50。即,首先,在第二基材500的铜箔501上层压干膜状的感光性抗蚀剂,使掩模与该感光性抗蚀剂密合,进行曝光/显影,由此形成仅相当于导体图案50的部分开口的抗镀层。然后,对形成了抗镀层的第二基材500进行水洗,在使其干燥之后进行电解镀铜,由此形成导体图案50。
在第二基材500的上述层叠之前,通过黑化处理、化学蚀刻处理(CZ处理)等表面粗糙化方法来在导体图案50的表面形成粗糙化层。另外,要进行第二基材500的上述层叠,例如能够使用高压釜方式、液压方式等。另外,通过上述方式等进行加压,绝缘构件30a与绝缘构件30b熔合,形成绝缘构件3(参照图3C)。并且,此时,树脂成分从绝缘构件30a、30b流出,由填充树脂5填充电子部件2与绝缘构件30a、30b之间所产生的空隙部分。
(4)后工序(图4A~图4E)
接着,从图3C的基板剥离(分离)载体102和载体502,得到图4A的基板。然后,通过使用了机械钻孔机等已知的开孔加工法,对图4A的基板开贯通孔106(参照图4B)。在形成贯通孔106之后,对图4B的基板实施无电解镀铜,在两个主表面上以及贯通孔106的内壁形成镀铜层113(参照图4C)。
然后,在图4C的基板的两个主表面上层压干膜状的感光性抗蚀剂,使掩模与该感光性抗蚀剂密合,进行曝光/显影。这样,形成仅相当于导体图案60的部分开口的抗镀层107以及仅相当于导体图案70的部分开口的抗镀层108(参照图4D)。
接着,对图4D的基板进行水洗,在使其干燥之后进行电解镀铜,除去抗镀层108。于是,如图4E所示,形成铜镀膜109和通孔导体90。然后,进行蚀刻来去除图4E的基板的两个主表面上的不需要的镀铜层113、铜箔101、第一基底层110、第二基底层111以及铜箔501,则能够得到形成了导体图案60(第一外层的通孔连接盘93)和导体图案70(第二外层的通孔连接盘94)的图4F所示的电子部件内置基板1。
在此的蚀刻能够采用不使用抗蚀金属的(或者将锡等作为抗蚀金属稍进行电镀的)所谓的快速蚀刻法。
如上这样制造出的电子部件内置基板1具有如下优异特征。
(1)由于容纳(内置)有电子部件2,因此能够在表层的安装区域安装其它电子部件等,能够实现高功能化。另外,通过倒装法安装要内置的电子部件,能够实现薄型化(小型化)。
(2)另外,通过(a)预先在第一基材100上形成用于安装电子部件的连接端子80、(b)第一基材100的厚度较大(大约75μm)、(c)通过添加法形成导体图案40和连接端子80等,能够以细间距(例如,50μm)形成导体图案40和连接端子80。另外,通过剥离而容易地去除第一基材100的载体102,因此在去除不需要的金属层时,能够极力减少有可能施加到连接端子80的损伤。并且,所形成的连接端子80和导体图案40在后工序中没有被蚀刻等,因此保持形成时的图案形状。因而,能够实现图案精确度的提高。
(3)另外,所容纳的电子部件2被填底材料4、绝缘构件3覆盖、密封,因此固定强度较高。因此,在将电子部件内置基板1作为芯基板的积层等多层化工序中,容易进行处理,另外,即使进行蚀刻等也能够极力防止对电子部件2产生的影响。
(4)另外,电子部件内置基板1具有绝缘构件(填底材料4和绝缘构件3)在电子部件2的安装面的下方向和上方向夹持电子部件2的方式的结构(对称结构)。当设为上述对称结构时,能够缓和由于应力(热、振动冲击、落下冲击等)所产生的应力,能够确保对于翘曲的耐性。因而,提高电子部件的连接可靠性。
(5)并且,电子部件内置基板1为内层的导体图案40、50埋设于绝缘构件3,第一外层通孔连接盘93、第二外层通孔连接盘94突出于绝缘构件3的结构。并且,由第一内层通孔连接盘91以及第一外层通孔连接盘93构成的第一表面侧的通孔连接盘的厚度(大约35μm)比导体图案40的厚度(大约15μm)厚,同样地,由第二内层通孔连接盘92以及第二外层通孔连接盘94构成的第二面侧的通孔连接盘的厚度(大约35μm)比导体图案50的厚度(大约15μm)厚。
由此,形成坚固的金属柱,能够抑制电子部件2周围的绝缘构件(填底材料4以及绝缘构件3)的变形。
图5F是将图4F的电子部件内置基板1用作芯基板的多层线路板600的概要截面图。
在该多层线路板600中,当比较连接第一外层通孔连接盘93与导体图案607的通路孔603和连接连接端子80与导体图案607的通路孔604时,如图6所示那样,通路孔603的纵横比较小,接触面积较大。同样地,当比较通路孔605和通路孔606时,通路孔605的纵横比较小,接触面积较大。
因而,一般即使在热应力容易集中的通孔周围也能够减轻通路孔603(通路孔605)底部的热应力,保持连接强度。
在此,参照图5A~图5E简单说明该多层线路板600的制造方法。
首先,在图4F的电子部件内置基板1的两个主表面上(第一表面和第二表面上)载置使树脂浸渗在玻璃布等加强材料中而形成的薄片状的板材(本实施方式中是预浸料),并且,在其上载置压延铜箔或电解铜箔,进行加热压接。其结果,形成厚度大约为40μm的绝缘层601、602以及厚度大约为12μm的铜箔610、611(参照图5A)。
此时,由第一外层通孔连接盘93以及第二外层通孔连接盘94排挤出的树脂量与进入通孔导体90的内部(空心)的树脂量相抵消。因而,绝缘层601和602的表面被平坦化。
接着,利用二氧化碳(C02)激光、UV-YAG激光等在图5A的基板的两个主表面的规定位置形成激光通路孔(盲孔)612、613(参照图5B)。
然后,在图5B的基板上,对整个表面进行无电解镀铜,在两个主表面上以及激光通路孔612和613的内表面形成镀铜层620(参照图5C)。
然后,在形成抗镀层621、622之后(参照图5D)进行电解镀铜,形成通路孔603~606以及镀铜层614、615(参照图5E)。
然后,在图5E的基板中去除抗镀层621、622,并进行蚀刻去除两个主表面上的不需要的铜箔610、611以及镀铜层620,则能够得到形成了导体图案607、608的图5F的多层线路板600。
此外,本发明并不限定于上述实施方式,在不脱离本发明的要旨的范围内能够进行各种变更。
例如,在内置的电子部件2的端子排列的方式是圆周型等的情况下,也可以如图7、图8所示那样使所有的连接端子80与各自对应的通孔导体90相连接地形成导体图案40。这样,不需要增加用于将电子部件2的电路部分与其它电路部分电连接的层数,能够实现薄型化。
或者,在多层线路板600中,也可以如图9所示那样设为一部分连接端子80与通孔导体90相连接的结构。
另外,上述实施方式的多层线路板600在电子部件内置基板1的两个主表面上各自层叠一层由绝缘层601、602以及导体图案607、608构成的层,但是并不限定于上述结构。即,也可以层叠两层以上,在两个主表面上层叠数也可以不同。并且,也可以仅在一侧的主表面上层叠。
本申请基于2008年3月27日申请的美国临时专利申请61/040000。在本说明书中参照并引用了其说明书、权利要求书、附图的全部内容。
产业上的可利用性
本发明所涉及的电子部件内置型线路板实现了小型化、高功能化,并且能够确保电子部件的连接可靠性。因而,能够期待应用于以手机为代表的移动设备。
Claims (14)
1.一种电子部件内置线路板的制造方法,其特征在于,具有以下工序:
连接端子形成工序,在以能够分离的状态将第一金属箔配置在支承体上而得到的第一层叠基材的上述第一金属箔上,通过添加法形成用于安装电子部件的连接端子;
安装工序,在上述第一层叠基材上使上述电子部件的电路形成面与上述连接端子的形成面相面对地配置该电子部件,将上述电子部件与上述连接端子电连接;
覆盖工序,用绝缘构件覆盖该安装工序后的上述电子部件;
分离工序,将上述支承体与上述第一金属箔分离;以及
去除工序,去除露出的上述第一金属箔。
2.根据权利要求1所述的电子部件内置线路板的制造方法,其特征在于,
在上述安装工序后,还具有对上述连接端子的周围填充绝缘性树脂的工序。
3.根据权利要求1所述的电子部件内置线路板的制造方法,其特征在于,还具有以下工序:
在以能够分离的状态将第二金属箔配置在上述支承体上而得到的第二层叠基材的上述第二金属箔上形成导体图案;以及
在上述覆盖工序后,使上述导体图案的形成面与上述绝缘构件的表面密合地层叠上述第二层叠基材。
4.根据权利要求1所述的电子部件内置线路板的制造方法,其特征在于,
上述覆盖工序包括以覆盖上述电子部件的方式载置上述绝缘构件的工序。
5.根据权利要求4所述的电子部件内置线路板的制造方法,其特征在于,
上述绝缘构件由预浸料构成,该绝缘构件至少组合配合上述电子部件的形状进行了开孔加工的预浸料与没有进行开孔加工的薄片状的预浸料而形成。
6.根据权利要求1所述的电子部件内置线路板的制造方法,其特征在于,
在上述电子部件上形成用于与上述连接端子接合的凸块。
7.根据权利要求1所述的电子部件内置线路板的制造方法,其特征在于,
上述连接端子的至少一部分利用由包含锡、银以及铜的合金构成的焊锡构成。
8.根据权利要求2所述的电子部件内置线路板的制造方法,其特征在于,
填充于上述连接端子的周围的上述绝缘性树脂包含无机填料。
9.根据权利要求1所述的电子部件内置线路板的制造方法,其特征在于,
上述第一金属箔是铜箔。
10.根据权利要求1所述的电子部件内置线路板的制造方法,其特征在于,
还具有以下工序:对上述覆盖工序后的基板设置贯通孔,形成通孔导体以及与该通孔导体相连接的通孔连接盘的工序。
11.根据权利要求10所述的电子部件内置线路板的制造方法,其特征在于,还具有以下工序:
在上述绝缘构件上隔着层间绝缘构件形成上层导体图案的工序;
形成将上述连接端子与上述上层导体图案电连接的电路连接用通路孔的工序;以及
形成将上述通孔连接盘与上述上层导体图案电连接的通孔连接盘连接用通路孔的工序。
12.一种电子部件内置线路板,其特征在于,具备:
连接端子,其通过添加法形成;
电子部件,其与该连接端子电连接;
绝缘构件,其覆盖该电子部件;
导体图案,其埋设于该绝缘构件;
通孔导体,其设置于上述绝缘构件;以及
通孔连接盘,其与该通孔导体相连接,
其中,该通孔连接盘从上述绝缘构件的表面突出。
13.根据权利要求12所述的电子部件内置线路板,其特征在于,
上述通孔连接盘的厚度比埋设于上述绝缘构件的上述导体图案的厚度厚。
14.根据权利要求12所述的电子部件内置线路板,其特征在于,具备:
上层导体图案,其隔着层间绝缘构件形成于上述绝缘构件上;
电路连接用通路孔,其将上述连接端子与上述上层导体图案电连接,或将上述导体图案与上述上层导体图案电连接;以及
通孔连接盘连接用通路孔,其将上述通孔连接盘与上述上层导体图案电连接,
其中,该通孔连接盘连接用通路孔与上述通孔连接盘之间的连接面的面积大于上述电路连接用通路孔与上述连接端子之间或上述电路连接用通路孔与上述导体图案之间的连接面的面积。
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2008
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- 2008-08-26 WO PCT/JP2008/065219 patent/WO2009118925A1/ja active Application Filing
- 2008-08-26 CN CN201210039282.7A patent/CN102625579B/zh active Active
- 2008-08-26 EP EP08873563A patent/EP2259666A4/en not_active Withdrawn
- 2008-08-26 JP JP2009539957A patent/JPWO2009118925A1/ja active Pending
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Cited By (4)
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CN105704948A (zh) * | 2016-03-28 | 2016-06-22 | 上海美维电子有限公司 | 超薄印制电路板的制作方法及超薄印制电路板 |
CN105704948B (zh) * | 2016-03-28 | 2018-05-29 | 上海美维电子有限公司 | 超薄印制电路板的制作方法及超薄印制电路板 |
CN108235597A (zh) * | 2018-02-08 | 2018-06-29 | 惠州奔达电子有限公司 | 一种pcb的制作方法及pcb |
CN108235597B (zh) * | 2018-02-08 | 2024-02-23 | 惠州奔达电子有限公司 | 一种pcb的制作方法及pcb |
Also Published As
Publication number | Publication date |
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EP2259666A1 (en) | 2010-12-08 |
CN101683006B (zh) | 2012-04-18 |
US20090242255A1 (en) | 2009-10-01 |
EP2259666A4 (en) | 2011-09-07 |
CN102625579A (zh) | 2012-08-01 |
CN102625579B (zh) | 2014-10-29 |
JPWO2009118925A1 (ja) | 2011-07-21 |
US8347493B2 (en) | 2013-01-08 |
WO2009118925A1 (ja) | 2009-10-01 |
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