CN101556945B - 用于为互连焊盘提供结构支撑同时允许信号传导的方法和装置 - Google Patents

用于为互连焊盘提供结构支撑同时允许信号传导的方法和装置 Download PDF

Info

Publication number
CN101556945B
CN101556945B CN2009101321085A CN200910132108A CN101556945B CN 101556945 B CN101556945 B CN 101556945B CN 2009101321085 A CN2009101321085 A CN 2009101321085A CN 200910132108 A CN200910132108 A CN 200910132108A CN 101556945 B CN101556945 B CN 101556945B
Authority
CN
China
Prior art keywords
metal
interconnect
metal layer
layer
openings
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CN2009101321085A
Other languages
English (en)
Chinese (zh)
Other versions
CN101556945A (zh
Inventor
凯文·J·埃斯
苏珊·H·唐尼
詹姆斯·W·米勒
杨俊才
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Freescale Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=36653824&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=CN101556945(B) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Publication of CN101556945A publication Critical patent/CN101556945A/zh
Application granted granted Critical
Publication of CN101556945B publication Critical patent/CN101556945B/zh
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
    • H10W20/4403—Conductive materials thereof based on metals, e.g. alloys, metal silicides
    • H10W20/4405—Conductive materials thereof based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
    • H10W20/4403—Conductive materials thereof based on metals, e.g. alloys, metal silicides
    • H10W20/4421—Conductive materials thereof based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Wire Bonding (AREA)
CN2009101321085A 2005-01-11 2005-11-30 用于为互连焊盘提供结构支撑同时允许信号传导的方法和装置 Expired - Lifetime CN101556945B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/033,008 2005-01-11
US11/033,008 US7241636B2 (en) 2005-01-11 2005-01-11 Method and apparatus for providing structural support for interconnect pad while allowing signal conductance

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
CNB2005800409510A Division CN100561693C (zh) 2005-01-11 2005-11-30 用于为互连焊盘提供结构支撑同时允许信号传导的方法

Publications (2)

Publication Number Publication Date
CN101556945A CN101556945A (zh) 2009-10-14
CN101556945B true CN101556945B (zh) 2012-05-23

Family

ID=36653824

Family Applications (2)

Application Number Title Priority Date Filing Date
CN2009101321085A Expired - Lifetime CN101556945B (zh) 2005-01-11 2005-11-30 用于为互连焊盘提供结构支撑同时允许信号传导的方法和装置
CNB2005800409510A Expired - Lifetime CN100561693C (zh) 2005-01-11 2005-11-30 用于为互连焊盘提供结构支撑同时允许信号传导的方法

Family Applications After (1)

Application Number Title Priority Date Filing Date
CNB2005800409510A Expired - Lifetime CN100561693C (zh) 2005-01-11 2005-11-30 用于为互连焊盘提供结构支撑同时允许信号传导的方法

Country Status (6)

Country Link
US (2) US7241636B2 (https=)
JP (1) JP2008527710A (https=)
KR (1) KR101203220B1 (https=)
CN (2) CN101556945B (https=)
TW (1) TWI389226B (https=)
WO (1) WO2006076082A2 (https=)

Families Citing this family (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005236107A (ja) * 2004-02-20 2005-09-02 Toshiba Corp 上層メタル電源スタンダードセル、面積圧縮装置および回路最適化装置
US7443020B2 (en) * 2005-02-28 2008-10-28 Texas Instruments Incorporated Minimizing number of masks to be changed when changing existing connectivity in an integrated circuit
JP4708148B2 (ja) 2005-10-07 2011-06-22 ルネサスエレクトロニクス株式会社 半導体装置
US7645675B2 (en) * 2006-01-13 2010-01-12 International Business Machines Corporation Integrated parallel plate capacitors
US7592710B2 (en) * 2006-03-03 2009-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Bond pad structure for wire bonding
JP2007299968A (ja) * 2006-05-01 2007-11-15 Matsushita Electric Ind Co Ltd 半導体装置
US7253531B1 (en) * 2006-05-12 2007-08-07 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor bonding pad structure
US7589945B2 (en) * 2006-08-31 2009-09-15 Freescale Semiconductor, Inc. Distributed electrostatic discharge protection circuit with varying clamp size
JP2008205165A (ja) * 2007-02-20 2008-09-04 Toshiba Corp 半導体集積回路装置
US7586132B2 (en) * 2007-06-06 2009-09-08 Micrel, Inc. Power FET with low on-resistance using merged metal layers
US20090020856A1 (en) * 2007-07-17 2009-01-22 International Business Machines Corporation Semiconductor device structures and methods for shielding a bond pad from electrical noise
US7777998B2 (en) 2007-09-10 2010-08-17 Freescale Semiconductor, Inc. Electrostatic discharge circuit and method therefor
JP5027605B2 (ja) * 2007-09-25 2012-09-19 パナソニック株式会社 半導体装置
US7739636B2 (en) * 2007-10-23 2010-06-15 International Business Machines Corporation Design structure incorporating semiconductor device structures that shield a bond pad from electrical noise
US8183698B2 (en) * 2007-10-31 2012-05-22 Agere Systems Inc. Bond pad support structure for semiconductor device
KR20090046627A (ko) * 2007-11-06 2009-05-11 주식회사 동부하이텍 반도체 소자 및 그 제조 방법
JP5291917B2 (ja) 2007-11-09 2013-09-18 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
KR20100112148A (ko) * 2007-12-28 2010-10-18 이 아이 듀폰 디 네모아 앤드 캄파니 화학선 경화성 접착제 조성물
US8258629B2 (en) * 2008-04-02 2012-09-04 Taiwan Semiconductor Manufacturing Company, Ltd. Curing low-k dielectrics for improving mechanical strength
US8274146B2 (en) * 2008-05-30 2012-09-25 Freescale Semiconductor, Inc. High frequency interconnect pad structure
US8581423B2 (en) 2008-11-17 2013-11-12 Taiwan Semiconductor Manufacturing Company, Ltd. Double solid metal pad with reduced area
US20100148218A1 (en) * 2008-12-10 2010-06-17 Panasonic Corporation Semiconductor integrated circuit device and method for designing the same
CN102034823B (zh) * 2009-09-30 2013-01-02 意法半导体研发(深圳)有限公司 用于spu和stog良好性能的功率晶体管的布局和焊盘布图规划
US8030776B2 (en) * 2009-10-07 2011-10-04 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit with protective structure
US8261229B2 (en) * 2010-01-29 2012-09-04 Xilinx, Inc. Method and apparatus for interconnect layout in an integrated circuit
US8242613B2 (en) 2010-09-01 2012-08-14 Freescale Semiconductor, Inc. Bond pad for semiconductor die
TWI453425B (zh) 2012-09-07 2014-09-21 Mjc Probe Inc 晶片電性偵測裝置及其形成方法
US20130154099A1 (en) 2011-12-16 2013-06-20 Semiconductor Components Industries, Llc Pad over interconnect pad structure design
CN103579192A (zh) * 2012-07-26 2014-02-12 中芯国际集成电路制造(上海)有限公司 一种新型的通孔链测试结构及其测试方法
JP5772926B2 (ja) * 2013-01-07 2015-09-02 株式会社デンソー 半導体装置
US9105485B2 (en) * 2013-03-08 2015-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Bonding structures and methods of forming the same
US9659882B2 (en) * 2015-01-20 2017-05-23 Sandisk Technologies Llc System, method and apparatus to relieve stresses in a semiconductor die caused by uneven internal metallization layers
US9564404B2 (en) * 2015-01-20 2017-02-07 Sandisk Technologies Llc System, method and apparatus to relieve stresses in a semiconductor wafer caused by uneven internal metallization layers
US9859891B1 (en) * 2016-06-24 2018-01-02 Qualcomm Incorporated Standard cell architecture for reduced parasitic resistance and improved datapath speed
KR102508527B1 (ko) * 2016-07-01 2023-03-09 삼성전자주식회사 필름형 반도체 패키지
US10192832B2 (en) * 2016-08-16 2019-01-29 United Microelectronics Corp. Alignment mark structure with dummy pattern
US9929114B1 (en) 2016-11-02 2018-03-27 Vanguard International Semiconductor Corporation Bonding pad structure having island portions and method for manufacturing the same
JP6836418B2 (ja) * 2017-02-27 2021-03-03 ルネサスエレクトロニクス株式会社 半導体装置
US10910330B2 (en) * 2017-03-13 2021-02-02 Mediatek Inc. Pad structure and integrated circuit die using the same
US10566300B2 (en) * 2018-01-22 2020-02-18 Globalfoundries Inc. Bond pads with surrounding fill lines
CN110544683B (zh) * 2018-05-29 2021-03-19 澜起科技股份有限公司 用于检测金属间介质层缺陷的叠层结构及测试方法
US10861807B2 (en) * 2018-11-21 2020-12-08 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit features with obtuse angles and method forming same
DE102019107500A1 (de) 2018-11-21 2020-05-28 Taiwan Semiconductor Manufacturing Company, Ltd. Integrierte Schaltkreiselemente mit stumpfen Winkeln und Verfahren zu deren Herstellung
CN110491849B (zh) * 2019-07-18 2024-11-08 珠海零边界集成电路有限公司 芯片、输入输出结构和垫层
US20210104477A1 (en) * 2019-10-04 2021-04-08 Macronix International Co., Ltd. Pad structure
KR20220140129A (ko) 2021-04-09 2022-10-18 삼성전자주식회사 반도체 소자의 검출용 패드 구조물
CN113571479B (zh) * 2021-06-30 2024-08-27 华为数字能源技术有限公司 芯片封装组件的测试方法

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5149674A (en) * 1991-06-17 1992-09-22 Motorola, Inc. Method for making a planar multi-layer metal bonding pad
EP0637840A1 (en) * 1993-08-05 1995-02-08 AT&T Corp. Integrated circuit with active devices under bond pads
US5514892A (en) * 1994-09-30 1996-05-07 Motorola, Inc. Electrostatic discharge protection device
JP3482779B2 (ja) * 1996-08-20 2004-01-06 セイコーエプソン株式会社 半導体装置およびその製造方法
US5700735A (en) * 1996-08-22 1997-12-23 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming bond pad structure for the via plug process
US6144100A (en) * 1997-06-05 2000-11-07 Texas Instruments Incorporated Integrated circuit with bonding layer over active circuitry
US6365958B1 (en) * 1998-02-06 2002-04-02 Texas Instruments Incorporated Sacrificial structures for arresting insulator cracks in semiconductor devices
US6232662B1 (en) * 1998-07-14 2001-05-15 Texas Instruments Incorporated System and method for bonding over active integrated circuits
US6087732A (en) * 1998-09-28 2000-07-11 Lucent Technologies, Inc. Bond pad for a flip-chip package
US6037668A (en) * 1998-11-13 2000-03-14 Motorola, Inc. Integrated circuit having a support structure
JP2000183104A (ja) * 1998-12-15 2000-06-30 Texas Instr Inc <Ti> 集積回路上でボンディングするためのシステム及び方法
JP3727818B2 (ja) * 1999-03-19 2005-12-21 株式会社東芝 半導体装置の配線構造及びその形成方法
US6198170B1 (en) * 1999-12-16 2001-03-06 Conexant Systems, Inc. Bonding pad and support structure and method for their fabrication
US6484060B1 (en) * 2000-03-24 2002-11-19 Micron Technology, Inc. Layout for measurement of overlay error
US6586839B2 (en) * 2000-08-31 2003-07-01 Texas Instruments Incorporated Approach to structurally reinforcing the mechanical performance of silicon level interconnect layers
US20030020163A1 (en) * 2001-07-25 2003-01-30 Cheng-Yu Hung Bonding pad structure for copper/low-k dielectric material BEOL process
DE10142318C1 (de) * 2001-08-30 2003-01-30 Advanced Micro Devices Inc Halbleiterstruktur und Verfahren zur Bestimmung kritischer Dimensionen und Überlagerungsfehler
KR100437460B1 (ko) * 2001-12-03 2004-06-23 삼성전자주식회사 본딩패드들을 갖는 반도체소자 및 그 제조방법
US6614091B1 (en) 2002-03-13 2003-09-02 Motorola, Inc. Semiconductor device having a wire bond pad and method therefor
JP3967199B2 (ja) * 2002-06-04 2007-08-29 シャープ株式会社 半導体装置及びその製造方法
US6804808B2 (en) * 2002-09-30 2004-10-12 Sun Microsystems, Inc. Redundant via rule check in a multi-wide object class design layout
JP3811473B2 (ja) * 2003-02-25 2006-08-23 富士通株式会社 半導体装置
EP1519411A3 (en) * 2003-09-26 2010-01-13 Panasonic Corporation Semiconductor device and method for fabricating the same
US7049701B2 (en) * 2003-10-15 2006-05-23 Kabushiki Kaisha Toshiba Semiconductor device using insulating film of low dielectric constant as interlayer insulating film
US7081679B2 (en) * 2003-12-10 2006-07-25 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and method for reinforcing a bond pad on a chip
US7555736B2 (en) * 2005-06-14 2009-06-30 Cadence Design Systems, Inc. Method and system for using pattern matching to process an integrated circuit design

Also Published As

Publication number Publication date
CN100561693C (zh) 2009-11-18
KR101203220B1 (ko) 2012-11-20
CN101556945A (zh) 2009-10-14
US7241636B2 (en) 2007-07-10
KR20070099599A (ko) 2007-10-09
CN101167170A (zh) 2008-04-23
WO2006076082A2 (en) 2006-07-20
US7626276B2 (en) 2009-12-01
US20060154469A1 (en) 2006-07-13
TWI389226B (zh) 2013-03-11
US20070210442A1 (en) 2007-09-13
JP2008527710A (ja) 2008-07-24
TW200634957A (en) 2006-10-01
WO2006076082A3 (en) 2007-12-21

Similar Documents

Publication Publication Date Title
CN101556945B (zh) 用于为互连焊盘提供结构支撑同时允许信号传导的方法和装置
US6384486B2 (en) Bonding over integrated circuits
JP4308671B2 (ja) ワイヤボンドパッドを有する半導体装置とその製作方法
US8064224B2 (en) Microelectronic package containing silicon patches for high density interconnects, and method of manufacturing same
US6232662B1 (en) System and method for bonding over active integrated circuits
CN101728371B (zh) 集成电路结构
CN101150094B (zh) 半导体晶圆结构
KR20220136408A (ko) 직접 결합을 위한 상호연결 패드의 선택적인 변경
US6908841B2 (en) Support structures for wirebond regions of contact pads over low modulus materials
US11380639B2 (en) Shielding structures
CN102130094B (zh) 集成电路芯片
US20080169569A1 (en) Bonding pad of semiconductor integrated circuit, method for manufacturing the bonding pad, semiconductor integrated circuit, and electronic device
KR20110057196A (ko) 칩 패키지 상호작용 안정도를 증진시키기 위한 스트레스 완화 갭들을 포함하는 반도체 디바이스
US7247552B2 (en) Integrated circuit having structural support for a flip-chip interconnect pad and method therefor
US20080128826A1 (en) Semiconductor integrated circuit and fabrication method for the same
US20110101531A1 (en) Thermo-mechanical stress in semiconductor wafers
US7741716B1 (en) Integrated circuit bond pad structures
US6020647A (en) Composite metallization structures for improved post bonding reliability
KR20060087516A (ko) 능동 영역에 연결 가능한 고전류 구조
US7323779B2 (en) Semiconductor device
US20090014717A1 (en) Test ic structure
CN114975400A (zh) 芯片封装结构及用以形成芯片封装结构的方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CP01 Change in the name or title of a patent holder

Address after: Texas in the United States

Patentee after: NXP USA, Inc.

Address before: Texas in the United States

Patentee before: FREESCALE SEMICONDUCTOR, Inc.

CP01 Change in the name or title of a patent holder
CX01 Expiry of patent term

Granted publication date: 20120523

CX01 Expiry of patent term