JP6836418B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP6836418B2 JP6836418B2 JP2017035049A JP2017035049A JP6836418B2 JP 6836418 B2 JP6836418 B2 JP 6836418B2 JP 2017035049 A JP2017035049 A JP 2017035049A JP 2017035049 A JP2017035049 A JP 2017035049A JP 6836418 B2 JP6836418 B2 JP 6836418B2
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- wiring
- opening
- insulating film
- pad
- film
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Description
<半導体装置の構造について>
図1および図2は、本実施の形態の半導体装置の断面構造を示す要部断面図である。図1と図2とは、本実施の形態の半導体装置における互いに異なる位置での断面図に対応しており、図1には、パッドPD1を横切る断面が示され、図2には、パッドPD2を横切る断面が示されている。なお、図2では、図面の簡略化のために、層間絶縁膜IL2とそれよりも下の構造については図示を省略してあるが、実際には、図2の断面構造の下にも、図1に示される層間絶縁膜IL2とそれよりも下の構造に類似した構造が存在している。
次に、本実施の形態の半導体装置の製造工程について説明する。以下の製造工程により、上記図1〜図4の半導体装置が製造される。
次に、本実施の形態の半導体装置(半導体チップ)を用いた半導体パッケージ(半導体装置)PKGの一例について、図22を参照して説明する。図22は、本実施の形態の半導体パッケージPKGの断面図である。
図23は、本実施の形態の半導体装置の要部断面図であり、上記図1と同じ断面が示されている。但し、図23では、図面の簡略化のために、層間絶縁膜IL2とそれよりも下の構造については図示を省略してあるが、実際には、図23の断面構造の下にも、図1に示される層間絶縁膜IL2とそれよりも下の構造とが存在している。また、図24および図25は、本実施の形態の半導体装置の要部平面図である。図24および図25には、同じ平面領域が示されているが、示される層が相違しており、図24には、パッドPD1が示され、図25には、パッドPD1よりも下層の配線M2が示されている。図24は、平面図であるが、図面を見やすくするために、パッドPD1および配線M3にハッチングを付し、また、図25は、平面図であるが、図面を見やすくするために、配線M2にハッチングを付してある。図24および図25のA−A線の位置での断面図が、上記図1および図23にほぼ対応している。図26および図27も、本実施の形態の半導体装置の要部平面図であり、図25と同じ平面領域で、かつ、図25と同じ層が示されている。なお、図26は、開口部OP1,OP2と、図25に示される配線M2との位置関係が分かるように用意した図面であり、図25において、ハッチングを省略し、かつ、開口部OP1,OP2の位置を追加したものが、図26に対応している。また、図27は、後述の開口部形成領域RG1,RG2が分かるように用意した図面であり、図25において、開口部形成領域RG1を示す点線と、開口部形成領域RG2を示す点線とを追加したものが、図27に対応している。図24および図26では、上記絶縁膜LFの開口部OP1の位置(平面位置)を二点鎖線で示し、上記樹脂膜PL1の開口部OP2の位置(平面位置)を一点鎖線で示している。
本発明者は、パッド形成後に再配線を形成した半導体装置について検討している。そのような半導体装置においては、再配線(RW)を通じてパッド(PD1)に印加される圧力(応力)に起因して、パッド(PD1)の下の層間絶縁膜(IL3)にクラックが発生する虞があることが、本発明者の検討により分かった。以下に、図28〜図30を参照して具体的に説明する。
本実施の形態の半導体装置は、半導体基板SBと、半導体基板SB上に層間絶縁膜IL2(第1層間絶縁膜)を介して形成された配線M2a(第1配線)と、層間絶縁膜IL2上に、配線M2aを覆うように形成された層間絶縁膜IL3(第2層間絶縁膜)と、層間絶縁膜IL3上に形成されたパッドPD1(第1パッド)と、を有している。本実施の形態の半導体装置は、層間絶縁膜IL3上に形成され、パッドPD1を露出する開口部OP3(第1開口部)を有する積層膜LM(第1絶縁膜)、を更に有している。本実施の形態の半導体装置は、開口部OP3から露出されたパッドPD1上を含む積層膜LM上に形成され、パッドPD1と電気的に接続された再配線RW(第2配線)と、積層膜LM上に形成され、再配線RWと一体的に接続されたパッドPD2(第2パッド)と、を更に有している。
本実施の形態の各変形例について、図面を参照して説明する。
IL1,IL2,IL3 層間絶縁膜
LF 絶縁膜
LM 積層膜
M1,M2,M2a,M2b,M2c,M3,M102a,M102b,M102c 配線
OP1,OP2,OP3,OP4,SL 開口部
PD1,PD2 パッド
PA 保護膜
PL1 樹脂膜
RG1,RG2 開口部形成領域
RW 再配線
SB 半導体基板
Claims (19)
- 半導体基板と、
前記半導体基板上に第1層間絶縁膜を介して形成された第1配線と、
前記第1層間絶縁膜上に、前記第1配線を覆うように形成された第2層間絶縁膜と、
前記第2層間絶縁膜上に形成された第1パッドと、
前記第2層間絶縁膜上に形成され、前記第1パッドを露出する第1開口部を有する第1絶縁膜と、
前記第1開口部から露出された前記第1パッド上を含む前記第1絶縁膜上に形成され、前記第1パッドと電気的に接続された第2配線と、
前記第1絶縁膜上に形成され、前記第2配線と一体的に接続された第2パッドと、
を有し、
前記第1配線の少なくとも一部は、前記第1パッドと平面視において重なっており、
前記第1パッドと前記第2配線との接続領域の下方に、前記第1配線の端部が位置し、
前記第1配線における第1領域に複数の第2開口部が形成されており、
前記第1領域の少なくとも一部は、前記接続領域と平面視において重なっており、
前記第1配線は、第1方向に延在する第1配線部と、前記第1方向と交差する第2方向に延在する第2配線部と、を一体的に有し、
前記第1配線部と前記第2配線部との連結部は、前記第1領域に含まれており、
前記第1配線部における前記第1領域において、前記複数の第2開口部は、前記連結部の近傍ではメッシュ状に形成され、前記連結部の近傍以外では、前記第1方向に延在するスリット状に形成されている、半導体装置。 - 請求項1記載の半導体装置において、
平面視において、前記第1配線と前記接続領域との重なり領域は、前記第1領域に含まれている、半導体装置。 - 請求項1記載の半導体装置において、
前記複数の第2開口部は、前記第1配線の前記第1領域に、スリット状に形成されている、半導体装置。 - 請求項1記載の半導体装置において、
前記複数の第2開口部は、前記第1配線の前記第1領域に、メッシュ状に形成されている、半導体装置。 - 請求項1記載の半導体装置において、
前記第1配線において前記複数の第2開口部が形成されていないと仮定した場合の前記第1配線の第1の幅は、0.6μm以上であり、
前記接続領域の下方において、前記第1配線に幅が0.6μm以上となる箇所が生じないように、前記第1配線の前記第1領域に前記複数の第2開口部が形成されている、半導体装置。 - 請求項1記載の半導体装置において、
前記第1絶縁膜は、第2絶縁膜と前記第2絶縁膜上の第3絶縁膜との積層膜からなり、
前記第3絶縁膜は、樹脂膜からなり、
前記第1開口部は、前記第2絶縁膜の第3開口部と、前記第3絶縁膜の第4開口部とにより形成されており、
前記第3開口部は、平面視において前記第4開口部に内包され、
前記第2絶縁膜の前記第3開口部から露出された前記第1パッドに、前記第2配線が接続されている、半導体装置。 - 請求項6記載の半導体装置において、
平面視において、前記第1配線と前記第3開口部との重なり領域は、前記第1領域に含まれている、半導体装置。 - 請求項7記載の半導体装置において、
平面視において、前記第1配線と前記第4開口部との重なり領域は、前記第1領域に含まれている、半導体装置。 - 請求項8記載の半導体装置において、
前記第1配線において前記複数の第2開口部が形成されていないと仮定した場合の前記第1配線の第1の幅は、0.6μm以上であり、
前記第4開口部の下方において、前記第1配線に幅が0.6μm以上となる箇所が生じないように、前記第1配線の前記第1領域に前記複数の第2開口部が形成されている、半導体装置。 - 請求項8記載の半導体装置において、
平面視において、前記第4開口部から5μm以上離れた領域には、前記複数の第2開口部は形成されていない、半導体装置。 - 請求項8記載の半導体装置において、
前記複数の第2開口部は、前記第1配線の前記第1領域に、スリット状に形成されている、半導体装置。 - 請求項8記載の半導体装置において、
前記複数の第2開口部は、前記第1配線の前記第1領域に、メッシュ状に形成されている、半導体装置。 - 請求項8記載の半導体装置において、
前記第2絶縁膜は、酸化シリコン膜からなる第4絶縁膜と、前記第4絶縁膜上に形成された酸窒化シリコン膜または窒化シリコン膜からなる第5絶縁膜と、の積層膜からなる、半導体装置。 - 請求項1記載の半導体装置において、
前記第1パッドは、アルミニウムパッドであり、
前記第2配線は、銅配線である、半導体装置。 - 請求項1記載の半導体装置において、
前記第1配線は、電源配線またはグランド配線である、半導体装置。 - 請求項1記載の半導体装置において、
前記第1絶縁膜上に、前記第2配線を覆うように形成された保護絶縁膜を更に有し、
前記保護絶縁膜は、前記第2パッドを露出する第5開口部を有する、半導体装置。 - 請求項1記載の半導体装置において、
前記第1パッドの下方に延在する、前記第1配線と同層の第3配線を更に有し、
前記第3配線の少なくとも一部は、前記第1パッドと平面視において重なっており、
前記接続領域の下方に、前記第3配線の端部が位置し、
前記第3配線には、開口部は形成されておらず、
前記第3配線の第2の幅は、前記第1配線において前記複数の第2開口部が形成されていないと仮定した場合の前記第1配線の第1の幅よりも小さい、半導体装置。 - 請求項17記載の半導体装置において、
前記第1配線は、電源配線またはグランド配線であり、
前記第3配線は信号配線である、半導体装置。 - 半導体基板と、
前記半導体基板上に第1層間絶縁膜を介して形成された第1配線と、
前記第1層間絶縁膜上に、前記第1配線を覆うように形成された第2層間絶縁膜と、
前記第2層間絶縁膜上に形成された第1パッドと、
前記第2層間絶縁膜上に形成され、前記第1パッドを露出する第1開口部を有する第1絶縁膜と、
前記第1開口部から露出された前記第1パッド上を含む前記第1絶縁膜上に形成され、前記第1パッドと電気的に接続された第2配線と、
前記第1絶縁膜上に形成され、前記第2配線と一体的に接続された第2パッドと、
を有し、
前記第1絶縁膜は、第2絶縁膜と前記第2絶縁膜上の第3絶縁膜との積層膜からなり、
前記第3絶縁膜は、樹脂膜からなり、
前記第1開口部は、前記第2絶縁膜の第3開口部と、前記第3絶縁膜の第4開口部とにより形成されており、
前記第3開口部は、平面視において前記第4開口部に内包され、
前記第2絶縁膜の前記第3開口部から露出された前記第1パッドに、前記第2配線が接続されており、
前記第1配線の少なくとも一部は、前記第1パッドと平面視において重なっており、
前記第4開口部の下方に、前記第1配線の端部が位置し、
前記第1配線における第1領域に複数の第2開口部が形成されており、
前記第1領域の少なくとも一部は、前記第4開口部と平面視において重なっており、
前記第1配線は、第1方向に延在する第1配線部と、前記第1方向と交差する第2方向に延在する第2配線部と、を一体的に有し、
前記第1配線部と前記第2配線部との連結部は、前記第1領域に含まれており、
前記第1配線部における前記第1領域において、前記複数の第2開口部は、前記連結部の近傍ではメッシュ状に形成され、前記連結部の近傍以外では、前記第1方向に延在するスリット状に形成されている、半導体装置。
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