CN101536189B - 具有电磁干扰滤波器的垂直瞬态电压抑制器（tvs） - Google Patents

具有电磁干扰滤波器的垂直瞬态电压抑制器（tvs） Download PDF

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CN101536189B
CN101536189B CN2007800405773A CN200780040577A CN101536189B CN 101536189 B CN101536189 B CN 101536189B CN 2007800405773 A CN2007800405773 A CN 2007800405773A CN 200780040577 A CN200780040577 A CN 200780040577A CN 101536189 B CN101536189 B CN 101536189B
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tvs
epitaxial loayer
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CN101536189A (zh
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雪克·玛力卡勒强斯瓦密
马督儿·博德
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Alpha and Omega Semiconductor Ltd
Alpha and Omega Semiconductor Inc
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Abstract

一垂直TVS电路包括一半导体衬底以支撑垂直TVS器件，在半导体衬底上有一延伸到衬底底部的重掺杂层。深沟槽提供了多通道垂直TVS间的隔离。沟槽栅极也用于增加整合有EMI滤波器的垂直TVS的电容。

Description

具有电磁干扰滤波器的垂直瞬态电压抑制器(TVS)
技术领域
本发明一般涉及一种瞬态电压抑制器(TVS)的电路结构及其制造方法，更特别的是，本发明涉及一种具有电磁干扰滤波器的垂直瞬态电压抑制器(VTVS)的电路结构及制造方法。 
背景技术
瞬态电压抑制器(TVS)一般用来保护集成电路不被意外产生的过量电压所损坏。集成电路被设计为可以在超出电压的一个正常范围内运行。然而，在诸如静电放电(ESD)、电快速瞬变及闪电等情况下、非预期且无法控制的高电压等皆可能瞬间施加到电路上。TVS器件即被要求用于提供电路保护的功能，以在这样的过电压情况发生时，使集成电路避免受到类似的损害。随着集成电路上易受过电压破坏的器件数量的增加，对于TVS的保护需求也随之增加。TVS的具体应用范例可见于USB电源供应器及数据线防护、数字视频接口、高速以太网、笔记本电脑、显示器及平板显示器。 
图1A-1所示为典型商用多通道TVS阵列10。具有两组控向二极管，即二极管15-H、15-L和20-H、20-L分别作为两输入/输出(I/O)端I/O-1及I/O-2。另外，具有稳压二极管，即二极管30，其具有较大尺寸功能，用以作为从高电压端，即Vcc端，到接地端，即Gnd端之间的雪崩二极管。当正电压施加到I/O衬垫时，高电压侧二极管15-H和20-H提供一正向偏压，并被较大的Vcc-Gnd二极管，即稳压二极管30压制。控向二极管15-H、15-L、20-H和20-L被设计为小尺寸，用以减少I/O电容，并由此减少如以太网应用这样的高速线路中的插入损耗。图1A-2所示为反向电流IR相对于图1A-1中的TVS10上的电压源Vcc与接地电压之间的稳压二极管的反向阻断电压BV特征的示意图。在图1A-2中所示的反向电流IR表示通过稳压二极管，即在Vcc及Gnd之间，传导的一反向电流。假设每个控向二极管的反向BV都高于稳压二极管的反向BV。但需要注意到高电流时，当Vcc至Gnd的衬垫电压等于或大于控向二极管的反向阻断电压的总和时，电流会通过所有两列路径上的控向二极管。由于稳压二极管与双极结晶体管BJT或硅控整流器SCR加上双极结晶体管相较之下，稳压二极管每一单位区域具有较高的阻抗，在高电流情况下这确实是一个缺点，因为控向二极管也需要在反向传导时坚固耐用。在SCR+BJT的例子中，稳压二极管压制电压在高电流时较低，因此控向二极管的路径不会被导通。Vcc-Gnd二极管30以及控向二极管15和20的击穿电压应大于其运行电压(Vrwm)，使这些二极管只在电压瞬变期间导通。Vcc-Gnd压制二极管的问题在于，在反向阻断模式下，这些二极管的阻抗通常较大，且需要大面积以减少阻抗。如图1A-2所示，高阻抗使阻断电压BV在高电流时增加。所不期望的高BV不但造成上述的控向二极管的击穿，还会损坏TVS器件所要保护的电路。在这样的TVS电路的实现中，对大尺寸二极管的需求限制了器件的进一步最小化。 
为了缩小瞬态电压抑制器(TVS)电路的尺寸及所占的表面积，垂直TVS二极管可以以图1B-1的形式实现。TVS以标准P型衬底连接至N+型稳压雪崩二极管来实现，TVS在P-衬底掺杂的顶部表面上形成一阴极端，并在阴极下方具有一N+区域。一金属层形成于衬底底部作为阳极。P型衬底通常具有10-20欧姆-厘米的电阻率，由此造成二极管具有高电阻值。图1B-2所示为一双通道垂直TVS二极管的等效电路。如图1C-1及图1C-2所示，TVS二极管也可以与一EMI滤波器整合。垂直整合结构类似于在两个垂直TVS二极管间额外内连接一电阻的垂直TVS二极管。如图1B-1至图1C-2中所示的这样的垂直二极管及EMI滤波器结构需要承受巨大的结电容和低箝制效果这样的缺点，这是由于高电阻率的衬底导致的高二极管串联电阻所形成的。 
因此，在本领域中仍然对电路设计和器件的制造存在一种需求，即提供一种新的优化的电路结构和制作方法以解决上述的问题。特别是存在提供一种新的优化的TVS电路的需求以能够提供一种用于便携式电子器件的低成本高密度的TVS和EMI滤波器。 
发明内容
因此，本发明的一个方面是提供一种应用DMOS技术的优化的具有EMI 滤波器的垂直TVS电路，以实现利用主流DMOS工艺生产低成本的具有EMI滤波器的TVS电路，其具有小的硅芯片足迹面积以此来克服上述的限制及困难。 
此外，本发明的另一个方面提供了一种具有EMI滤波器的垂直TVS电路的优化的器件结构及制造方法，其使用主流垂直沟槽DMOS技术，其中沟槽栅极做为TVS结构的一部分，作用是隔离通道和滤波器电容。 
本发明的另一个方面提供了一种应用DMOS技术的优化的具有EMI滤波器的垂直TVS电路结构，以实现利用主流沟槽DMOS工艺，其中具有EMI滤波器的TVS的垂直结构能够形成小的硅芯片足迹面积并增加集成电路单元密度，从而进一步减少制作成本。 
本发明的一个优选实施例大致公开了一种整合有EMI滤波器的瞬态电压抑制器(TVS)的电路结构，用以抑制瞬态电压，其包括第一及第二VTVS，其中每个VTVS包括一设置于井中，即本体区域中的具有第一导电类型的阴极连接掺杂区域，该井具有第二导电类型，其被第一导电类型的外延层所包围的，该外延层设置于具有第一导电类型的半导体衬底上，并连接设置在半导体衬底底部表面的阳极，并具有设置于半导体器件顶部表面的阴极且与阴极连接掺杂区相连接，从而形成第一和第二垂直TVS。整合有EMI滤波器的VTVS还包括一独立导电区，其与第一和第二VTVS的阴极电连接，从而与第一和第二VTVS共同作用，以作为EMI滤波器。在另一实施例中，导电区域是设置在半导体衬底顶部的多晶硅层，用以与第一和第二VTVS的阴极电连接。在另一实施例中，半导体衬底为一N型衬底，而第一及第二VTVS的井为P型井。在另一实施例中，半导体衬底为一P型衬底，而第一及第二VTVS的井为N型井。在另一实施例中，第一及第二VTVS还各自包括一第二导电类型的掺杂区域，其设置在阴极掺杂区域下，用以调节二极管的击穿电压。 
在另一优选实施例中，本发明还公开了一种形成为集成电路(IC)的电子器件，其中该电子器件还包括一瞬态电压抑制(TVS)器件。TVS器件包括一半导体衬底用以支撑该VTVS器件，该半导体衬底的前侧做为VTVS的阳极而后侧则做为VTVS的阴极。该VTVS还包括一固有二极管及一寄生晶体管，其结构为一沟槽DMOS，其中源极区域及本体区域即做为固有二极管， 而源极区域、本体区域及外延层则作为具有一沟槽栅极的寄生晶体管，该沟槽栅极作为一隔离沟槽。DMOS还具有一沟槽栅极引道，其与设置在后侧作为阴极的漏极短接。在另一优选实施例中，半导体衬底还包括一N型衬底，其支撑N型外延层，该外延层具有形成于N-源极与P-本体区域之间的固有二极管以及形成于N-源极、P-本体区域和N-外延层之间的NPN晶体管。在另一实施例中，沟槽栅极引道设置于半导体衬底的边缘，其宽度大于隔离沟槽，以将沟槽栅极引道通过外延层短接到阴极。在另一实施例中，本体区域的掺杂浓度使MOSFET栅极阈值电压约为6伏，并且沟槽栅极的栅极氧化层提供所能承受的击穿电压约为15伏，由此，当加载在VTVS上的电压超过6伏时，VTVS导通，并且提供寄生晶体管用以传送瞬时电流，从而将电压维持在箝制电压之下。 
本发明进一步公开了一种具有整合了瞬态电压抑制器(TVS)电路的电子器件的制造方法。该方法包括应用标准DMOS制程制造一垂直DMOS器件的步骤，该器件具有一固有PN结二极管及一寄生NPN型或PNP型晶体管，以作为一垂直TVS。 
本领域的普通技术人员在结合多幅附图阅读了后续的对于优选实施例的详细叙述后，上述及其它本发明的内容及优点将变得显而易见。 
附图说明
图1A-1所示为现有TVS器件的电路图；图1A-2为I-V图，即电流电压对比图，用以描述TVS器件的反向特征。 
图1B-1为垂直TVS二极管的剖视图；图1B-2为现有的垂直TVS二极管的等效电路图。 
图1C-1为整合了EMI滤波器的垂直TVS二极管的剖视图，图1C-2为现有的整合了EMI滤波器的垂直TVS二极管的等效电路图。 
图2A和图2B分别是以垂直沟槽DMOS技术制成的垂直沟槽DMOS结构的垂直TVS的剖视图和等效电路图。 
图3A至图3D分别是以垂直沟槽DMOS技术制成的垂直TVS的两个实施例的剖视图和等效电路图。 
图4为利用DMOS技术制成的垂直二极管结构的TVS电路的剖视图。 
图5A至5E为利用DMOS技术制成的双极晶体管结构的垂直TVS的实施例的剖视图。 
图6为利用DMOS技术制成的整合了EMI滤波器的垂直TVS的剖视图，其结构为以一电阻元件连接的二极管。 
图7A至7B为利用DMOS技术制成的整合了EMI滤波器的垂直TVS的剖视图，其结构为以一电阻元件连接的双极晶体管。 
图8为利用DMOS技术制成的整合了EMI滤波器的垂直TVS的剖视图，其结构为通过沟槽隔离的二极管并与电阻元件连接。 
图9A至9D为利用DMOS技术制成的整合了EMI滤波器的垂直TVS的剖视图，其结构为通过沟槽隔离的双极晶体管以并与电阻元件连接。 
图10A至10B为利用DMOS技术制成的垂直TVS的剖视图，其结构为控向二极管并且TVS具有位于二极管间的沟槽隔离。 
图11、12A及12B为利用DMOS技术制成的整合有EMI滤波器的垂直TVS的剖视图，其结构为在输入输出通道之间设置沟槽间隔，其中多晶硅填充沟槽进一步作为多晶硅电容。 
图13A及13B分别为利用DMOS技术制成的整合了EMI滤波器的垂直TVS的侧面剖视图和俯视图，其结构为通过隔离沟槽间隔的垂直二极管，并且通过沟槽电感内部连接。 
图14A至14G为本发明中使用主流沟槽DMOS制程来制造的整合了EMI滤波器的多通道VTVS的一系列制程步骤的侧面剖视图。 
具体实施方式
参考图2A和图2B所示的以标准DMOS工艺制成的垂直瞬态电压抑制器(VTVS)100的侧面剖示图和电路图。设置于一重掺杂半导体衬底105上的VTVS 100包含一作为阳极端110的前侧以及作为阴极端120的背侧，以形成包含一固有二极管与一NPN型晶体管的垂直TVS。由于产品是通过应用标准沟槽DMOS制程制造的，故剖视图图2A所示为一沟槽NMOS结构，其包含形成于本体区域130上的源极区125，本体区域130位于作为漏极的N+衬底105上的N外延层115的顶部。隔离沟槽栅极135与栅极引道135-GR内部连接于边缘区域，并在三维空间穿过其它沟槽栅极。如图2A所示，本 VTVS器件与其它一般沟槽DMOS的不同之处在于栅极引道135-GR通过与N外延层115相连接的、位于栅极沟槽接触(或栅极衬垫)区域中的栅极金属140短接到漏极105。这是通过在DMOS接触开口制程时不使用额外的掩模，并蚀刻宽度大于栅极引道沟槽135-GR的栅极接触开口140来实现的。因此，图2B所示的等效电路图中，栅极短接至漏极。在制作一使用于5V器件的VTVS时，P-本体区域130的掺杂浓度可能会通过多次注入来增加，以符合MOSFET的栅极阈值电压约为6V的等级，并且栅极氧化层145的厚度会增加以能够承受15V的击穿电压。因此，当接入一般为5V的运行电压时，VTVS不会导通。然而，在本例中会产生超过5V的瞬态电压，该电压加载于栅极并导通MOS。寄生NPN也会被导通，因此大量的电流将会流过该不具有太多阻抗的器件，以此提供对二极管的优化的箝制。图2A也显示出DMOS本体区域130与一般DMOS器件一样被短接至源极125。 
图3A为另一与图2所示相似的器件结构的可选实施例的剖视图，区别是本体区域130′是浮动的。如等效电路图图3B所示，栅极135与漏极105连接结合，器件作为MOS+NPN。栅极135也可以与源极125连接结合，在这个情形下MOS晶体管不会被导通，且此器件作为NPN。栅极135的深度可以延伸穿过N-外延层115并进入到N+衬底105中的一定深度，以此来改善通道间以及输出与输入端间的间隔。更进一步，沟槽栅极135可以由氧化物145′或其它绝缘材料填充，以代替图3C中所示的导体材料。N+区域125、P本体区域130和N-外延层115构成一如图3D所示的开放基极NPN。可以通过改变P本体区域130的掺杂浓度来调整本体区域130到N+区域125或N-外延结115之间具有6V的击穿电压，从而当更高的瞬时电压冲击结合处，会发生电压击穿，该击穿会触发NPN导通，从而来保护其它电路。除了在图2和图3所显示的器件结构外，一个P-沟道DMOS和VTVS的PNP可以使用类似通过改变半导体极性的方式来制成。 
参考图4为一个应用于VTVS的优化二极管。该二极管200基于重掺杂P+衬底205以减低阻抗。相较于现有技术中使用标准IC制程所制造的二极管中所使用的P衬底所具有的10-20欧姆厘米的电阻率，使用于DMOS里的P+重掺杂衬底在仅提供只有几微欧姆厘米的电阻率。此外，也可以使用一个具有重掺杂底层的轻掺杂衬底来降低电阻率。通过向P-外延层210注入砷或 磷离子来形成一N-本体区域215，借此，通过控制掺杂浓度，以调整N-本体区域215和P-外延层210间的击穿电压至6V或是任何需要的电压值。P-外延层210的厚度只有几微米以将电阻降到最小。更进一步的，N+区域220被形成于N-本体区域215的顶部，以改善阴极225与形成于衬底205底部的阳极电极230的欧姆连接。 
图5A至图5C为应用于VTVS的双极晶体管。如图5A中所示的NPN，一N+区域220′被注入到N+衬底205′上的N-外延层210′顶部的P-井中，用来形成一连接到阴极电极225′的阴极区域。也可以在N+阴极区220′下设置一可选择的P区域235，用以通过改变P掺杂浓度来调整击穿电压。P-井215′通过连接金属240和N-外延层210′短接到阳极230。当一超过预设器件工作电压的瞬间高电压加载在位于N+阴极区220′与其下方的P区域235之间的结点时，会发生电压击穿，导致电子流经短接金属240到N-外延层210以及到达阳极230。当电流增加，在区域220′、235、215′和210′间形成的NPN会被导通，以更低的电阻值来传导更高的电流，从而改善箝制性能。在图5B中，击穿调整P区域235′被设置于N+型阴极区域220′的侧面。此举提供一项优势，即使得在发生电压击穿的金属电极240、225′和N+/P区域结点间的空间间隔可以弹性地调整来避免过热。 
图5C是另一基于PNP双极晶体管的改良VTVS。相较于图4中的二极管200，图5C中的器件更进一步包含了一个在连接到阴极的N-本体区域215内的P+注入区域220″。P+区域220″、N-井215和P-外延层210或P+衬底205的结构为一PNP晶体管，由N-本体区域215与P-外延层210之间的结点击穿来提供触发。VTVS器件的箝制也由此得到改善。 
图5D为另一具有类似工作原理的可替代实施例的剖视图，其结构为一对称TVS。当半导体衬底的底部为浮动时，P-井215′被短接到N+220′，且直接连接到分别被设计为输入、接地(GND)和输出的电极端226、227和228。输入、接地和输出通道进一步被多个栅极沟槽135′所隔离。在高电压瞬变时，P-井215′与N-外延层210′之间的结会产生电压击穿，并触发导通由N+220′、P-井215′和N-外延层210′构成的NPN。一正的高电压瞬间加载于输出或输入端时，将会触发TVS的接地通道，同样的一个负的高电压瞬间加载于输出或输入端时，将会触发TVS的输出或输入通道。由于所有的通道都是同时制作 的，所以触发TVS沟道的正负瞬间电压本质上是大小相等的，因此该TVS装置是对称的。图5E为一个与图5D所示器件结构相似的可替代实施例的剖视图，不同点在于去除了N+220′，使得箝制功能是由P-井215′和N-外延层210′间的结面二极管所提供的，但仍保持对称运作。 
图6为一多通道TVS和一EMI滤波器的剖视图，其器件结构是基于图4所示的TVS器件结构实现的。第一和第二垂直TVS(VTVS)被形成作为基于P+衬底205的第一二极管和第二二极管，以降低阻抗。每一个第一二极管和第二二极管都包含一由在P-外延层210中注入砷或磷离子形成的N-本体区域215。通过控制P-外延层210的掺杂浓度，这些二极管的N-本体区域215和P-外延层210间的击穿电压被调整到6V左右或任何需要的电压，P-外延层210只有几微米的厚度，以此来降低阻抗。对于每一个二极管，在N-本体区域215的顶部形成N+区域220，以此来优化第一和第二阴极电极225-1和225-2与形成于衬底205底部的阳极端230之间的欧姆连接。此器件更进一步作为一个EMI滤波器，其中，阴极电极225-1作为输入端，第二阴极电极225-2作为输出端，并有一形成于隔离层255之上的多晶硅层250，其电连接第一电极225-1和第二电极225-2。多晶硅层250作用为一电阻内连接分别作为输入和输出端的第一和第二阴极电极225-1和225-2。 
图7A为一整合有EMI滤波器的多通道TVS的器件结构剖视图，其包含基于如图5A所示的器件结构的第一和第二垂直TVS。第一和第二VTVS的阴极电极225′-1以及225′-2通过多晶硅层250′内部连接，该多晶硅层250′周围填补有隔离层255′。该多晶硅层250′作为一个介于EMI滤波器输入和输出端之间的电阻，这些端点分别为第一和第二阴极电极225′-1以及225′-2。图7B是图7A中所示的整合有EMI滤波器的多通道TVS的器件结构的PNP互补结构，其包含基于图5C所示的器件结构的第一和第二垂直TVS。一可选的P注入区域214可以被形成于N-本体区域215之下，目的是调整击穿电压。 
图8所示为一整合有EMI滤波器的多通道TVS，该器件结构类似于图6所示的多通道TVS和EMI滤波器的器件结构，不同点在于数个隔离沟槽270形成于多晶硅层250的下方，该多晶硅层250的周围填补有隔离层255。图9A所示为另一个整合有EMI滤波器的多通道TVS，该器件结构类似于图7A所示的多通道TVS和EMI滤波器的器件结构，不同点在于数个隔离沟槽270 形成于多晶硅层250′下方，该多晶硅层250′的周围填补有一隔离层255′。图9B所示为另一个整合有EMI滤波器的多通道TVS，该器件结构类似于图7B所示的TVS和EMI滤波器的器件结构，不同点在于数个隔离沟槽270形成于多晶硅层250′下方，该多晶硅层250′的周围填补有一隔离层255′。如图9C所示，可以使用更多个沟槽来改善输出和输入之间的隔离。更进一步来说，图9D所示为一整合有EMI滤波器的多通道对称TVS，其建构于图5D中的对称TVS的器件结构之上，且通过一电阻或电感连接输入端226和输出端228。也可以通过切换掺杂极性来制造PNP互补结构。 
图10A和10B所示为多通道TVS的剖视图，其具有类似于图1A-1所示的电路，但通过一新的器件结构来实现。图10A中的TVS 300形成于支撑P-型外延层310的P+衬底305上。多个N-本体区域320形成于隔离沟槽315之间。在N-本体区域320中形成一个P+欧姆连接掺杂区域330，用来连接输入输出(I/O)端325。一可选的N+埋入层322可以借由高能量N+注入形成于P+结点之下，以此降低PNP增益。一P-本体区域335设置于N-本体区域320和一可选的N+埋入层322之下，作为稳压二极管。P+欧姆连接掺杂区域330和N-本体区域320提供功能为连接IO端325和Vcc 340的上层二极管。形成于外延层310和N-本体区域320间的二极管被连接于IO端325和接地电位的阳极端350间。同时，稳压二极管连接于Vcc 340和阳极350的接地电压之间，且并联上层和下层二极管，其连接位于上层和下层二极管中点的IO端325。每个二极管都被隔离沟槽315隔离。图10B为进一步改良的结构，其使用PNP来代替稳压二极管。在可选的注入N+区域322期间，使用一掩模来阻挡P+区域334所在的N-井320。由P+区域334、N-井320和P本体区域335组成的PNP晶体管可以被N-井320和P本体区域335间的结点击穿电压所触发。 
图11为一多通道TVS的剖视图，其整合有图8所示的内部连接于输出和输入端点225′-1和225′-2之间的EMI滤波器，且具有额外的沟槽275来增加形成于沟槽栅极275和外延层210′之间的寄生电容的电容值。这些电容如图11所示那样并联。EMI滤波器的截止频率可以通过改变电容值来调整。可以注入P-扩散区域276以封闭沟槽电容，并通过制造良好的与衬底间的低阻抗连接来降低电容的等效串连电阻(ESR)。图12A与其具有类似的器件 结构，并具有分离沟槽栅极275′以进一步增加电容值。图12B是另一个沿着B-B′方向的器件剖视图，用以显示分离沟槽电容间的并联关系。 
图13A和13B所示分别为在器件内使用沟槽电感布局设计的侧面剖视图和俯视图，其包含如图4所示的形成为第一和第二二极管的一多通道TVS，其具有作为输入端的第一阴极电极225″-1和作为输出端的第二阴极电极225″-2。第一和第二二极管通过隔离沟槽280隔离，并由一沟槽电感285连接。输入和输出端的连接开口分别为所示的225″-1-C和225″-2-C。连接开口到沟槽电感的连接分别为所示的285-C1和285-C2，其分别连接到到输入和输出电极。 
参考图14A至图14G，为根据本发明通过使用主流沟槽DMOS制程制造整合有EMI滤波器的多通道VTVS的制造过程。在图14A中，通过蚀刻贯穿一氧化物硬掩模(图中未表示)在一个N+衬底405顶部上的N外延层410之中形成多个沟槽470。衬底405是一个典型用于垂直DMOS器件的重掺杂衬底，所具有的掺杂浓度高于1E18/cm3，相当于电阻率小于N型的20微-欧姆-厘米或P型40微-欧姆-厘米，相较于典型的集成电路制程衬底，其拥有小于1E16的掺杂浓度和数欧姆-厘米的电阻率。也可选择，使用一具有重掺杂底层的轻掺杂衬底来降低电阻率。沟槽最好蚀刻贯穿外延层410到达衬底405，以提供最好的隔离。也可以实施一些可选的流程以移除氧化物硬掩模，如在沟槽DMOS制程中生长牺牲氧化物和圆滑化沟槽底部。在图14B中，一栅极氧化物层455被热生长，接着沉积多晶硅以填充沟槽，然后使用毯式回蚀制程来去除沟槽上超出的多晶硅。氧化物层455的厚度可以透过热增长或沉积来增加到希望的厚度。在图14C中，实施精密控制厚度和掺杂物密度的第二多晶硅沉积，之后使用掩模来图案化以形成第二多晶硅450从而形成EMI滤波器电阻。氧化物层455也被清除以进行后续的注入步骤。在图14D中，P本体区域415和初始击穿电压调整区域435被P型掺杂物注入并扩散。为了获得一深的P本体区域415可以实施高能量注入。在一个实施例中，实施硼离子注入的能量等级介于700KeV到1000KeV之间，且剂量范围从5E13到1E14，以形成一2-3um深度的P本体。在图14E中，实施N型注入以形成N+区域420和423。在图14F中，氧化物层460被形成于顶部表面，接下来进行可选的沉积并回流硼磷硅玻璃以使表面平面化。在连接开口被蚀刻贯穿氧化层460后，实施一P+连接注入以形成P-本体连接区域424。不需要反掺杂N+区域423，由此提供外延层欧姆连接用以将P-本体区域短接到外延层和衬底。在一实施例中，连接注入使用B/BF2离子，剂量为2E15/cm2，能量60KeV，同时N+区域由双注入形成，先进行剂量为4E15、注入能量为80KeV的砷离子注入，随后进行剂量为4E15、能量为80KeV的磷注入。N+区域420反掺杂至击穿电压控制P区域435的中央部分，该P区域435已经被进行了低浓度注入，其剂量为1E13到4E13，并具有较低的能量50KeV，剩下的未受影响的435区域的边缘用以形成一具有N+区域420的侧边二极管以提供初始崩溃电压。在图14G中，金属层被沉积并图案化来形成输入电极425-1和输出电极425-2，并且P-本体外延层也短接到电极440。金属层430也被沉积在底部表面以形成阳极。
上述制程提供一个整合有EMI滤波器的垂直TVS，其结构为被沟槽隔离并通过一电阻元件连接的NPN晶体管，其通过使用类似于图9所示的实施例中的DMOS技术制造而成，其具有设置于侧面的一初始击穿电压二极管。其它实施例可以开始于适当的衬底并通过增加或跳过某些步骤的类似程序制造。特别是没有隔离沟槽的实施例，它可能跳过形成沟槽的制程；不整合有EMI滤波器的TVS的实施例可以跳过第二多晶硅沉积制程。此外，如图13A和13B所示的，为了增加电容而具有分隔栅极的实施例可能还包含多个多晶硅沉积和回蚀制程的步骤。 
尽管本发明已经通过现有的优选实施例进行了叙述，但应当认识到这样的公开不应被视为对本发明的限制。在阅读了上述公开内容后，对本领域的技术人员而言，多种变化和修改都会变得显而易见。相应的，附后的权利要求应当被视为覆盖了所有落入本发明真正精神和范围内的变化和修改。 

Claims (5)

1.一种垂直瞬态电压抑制器，其特征在于，包括：
一衬底，其包含延伸至所述衬底的底部表面的一重掺杂层，其中所述重掺杂层具有第一导电类型；
一被支撑在所述的重掺杂层顶部的具有第一导电类型的外延层，所述的外延层具有一顶部表面，而所述的重掺杂层具有一底部表面；
设置于所述外延层的顶部区域的具有与所述第一导电类型相反的第二导电类型的本体区域，该本体区域与所述的外延层形成一PN结；
一具有第一导电类型的一顶部半导体区域，其掺杂浓度大于所述的本体区域的掺杂浓度，该顶部半导体区域位于所述的本体区域的顶部，并具有与所述外延层的顶部表面同一平面的顶部表面；
一沟槽，其开设于所述的外延层中，贯穿所述的顶部半导体区域及所述的本体区域；所述沟槽具有利用一绝缘层确定的一侧壁及一底部；该沟槽还填充有导电材料形成栅极；所述栅极与一栅极引道连接，所述栅极引道通过与所述外延层连接的一栅极金属短接到所述重掺杂层。
2.如权利要求1所述的垂直瞬态电压抑制器，其特征在于，其中，所述的本体区域包括一与所述的外延层顶部表面位于同一平面的顶部表面。
3.如权利要求1所述的垂直瞬态电压抑制器，其特征在于，其中，所述的沟槽开设贯穿所述的外延层并进入所述的重掺杂衬底。
4.如权利要求1所述的垂直瞬态电压抑制器，其特征在于，其中，所述的第一导电类型是N型，所述的第二导电类型是P型。
5.如权利要求1所述的垂直瞬态电压抑制器，其特征在于，其中，所述的第一导电类型是P型，所述的第二导电类型是N型，而所述的本体区域通过一金属电极短接到所述的顶部半导体区域。
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