CN101399248B - 配线基板及其制造的方法 - Google Patents

配线基板及其制造的方法 Download PDF

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Publication number
CN101399248B
CN101399248B CN2008101488407A CN200810148840A CN101399248B CN 101399248 B CN101399248 B CN 101399248B CN 2008101488407 A CN2008101488407 A CN 2008101488407A CN 200810148840 A CN200810148840 A CN 200810148840A CN 101399248 B CN101399248 B CN 101399248B
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CN
China
Prior art keywords
wiring
wiring substrate
reinforcing member
opening
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN2008101488407A
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English (en)
Chinese (zh)
Other versions
CN101399248A (zh
Inventor
松元俊一郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Publication of CN101399248A publication Critical patent/CN101399248A/zh
Application granted granted Critical
Publication of CN101399248B publication Critical patent/CN101399248B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/401—Package configurations characterised by multiple insulating or insulated package substrates, interposers or RDLs
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09136—Means for correcting warpage
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/20—Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
    • H05K2201/2018—Presence of a frame in a printed circuit or printed circuit assembly
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Structure Of Printed Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
CN2008101488407A 2007-09-27 2008-09-27 配线基板及其制造的方法 Expired - Fee Related CN101399248B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2007250807 2007-09-27
JP2007-250807 2007-09-27
JP2007250807A JP5025399B2 (ja) 2007-09-27 2007-09-27 配線基板及びその製造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
CN2011102042880A Division CN102280435A (zh) 2007-09-27 2008-09-27 配线基板及其制造的方法

Publications (2)

Publication Number Publication Date
CN101399248A CN101399248A (zh) 2009-04-01
CN101399248B true CN101399248B (zh) 2011-12-28

Family

ID=40506896

Family Applications (2)

Application Number Title Priority Date Filing Date
CN2008101488407A Expired - Fee Related CN101399248B (zh) 2007-09-27 2008-09-27 配线基板及其制造的方法
CN2011102042880A Pending CN102280435A (zh) 2007-09-27 2008-09-27 配线基板及其制造的方法

Family Applications After (1)

Application Number Title Priority Date Filing Date
CN2011102042880A Pending CN102280435A (zh) 2007-09-27 2008-09-27 配线基板及其制造的方法

Country Status (5)

Country Link
US (1) US20090084585A1 (https=)
JP (1) JP5025399B2 (https=)
KR (1) KR20090033004A (https=)
CN (2) CN101399248B (https=)
TW (1) TW200921874A (https=)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI557855B (zh) * 2011-12-30 2016-11-11 旭德科技股份有限公司 封裝載板及其製作方法
CN103379726A (zh) * 2012-04-17 2013-10-30 景硕科技股份有限公司 线路积层板的复层线路结构
KR101369150B1 (ko) * 2013-10-15 2014-03-04 주식회사 에스아이 플렉스 단차 지그를 이용한 인쇄공법
CN105960708B (zh) * 2014-09-27 2019-11-05 英特尔公司 采用单向加热的使用钢化玻璃的基板翘曲控制
US11081371B2 (en) * 2016-08-29 2021-08-03 Via Alliance Semiconductor Co., Ltd. Chip package process
JP6693850B2 (ja) * 2016-09-30 2020-05-13 新光電気工業株式会社 キャリア基材付き配線基板、キャリア基材付き配線基板の製造方法
US11778293B2 (en) 2019-09-02 2023-10-03 Canon Kabushiki Kaisha Mounting substrate to which image sensor is mounted, sensor package and manufacturing method thereof
CN113131291B (zh) * 2021-03-11 2023-05-12 东莞市晟合科技有限公司 一种搭载电子元器件的连接线及其制作方法
KR20230013677A (ko) 2021-07-16 2023-01-27 삼성전자주식회사 더미 패턴을 포함하는 반도체 패키지
JP7307360B2 (ja) * 2021-09-30 2023-07-12 ダイキン工業株式会社 基板構造

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000323613A (ja) * 1999-03-11 2000-11-24 Shinko Electric Ind Co Ltd 半導体装置用多層基板及びその製造方法
CN1805657A (zh) * 2004-12-21 2006-07-19 日东电工株式会社 配线电路基板
CN1893054A (zh) * 2005-07-04 2007-01-10 日东电工株式会社 配线电路基板
CN1929123A (zh) * 2005-09-07 2007-03-14 新光电气工业株式会社 多层配线基板及其制造方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6876554B1 (en) * 1999-09-02 2005-04-05 Ibiden Co., Ltd. Printing wiring board and method of producing the same and capacitor to be contained in printed wiring board
JP3492348B2 (ja) * 2001-12-26 2004-02-03 新光電気工業株式会社 半導体装置用パッケージの製造方法
US7795714B2 (en) * 2004-08-06 2010-09-14 Supertalent Electronics, Inc. Two step molding process secured digital card manufacturing method and apparatus
JP4526983B2 (ja) * 2005-03-15 2010-08-18 新光電気工業株式会社 配線基板の製造方法
JP3914239B2 (ja) * 2005-03-15 2007-05-16 新光電気工業株式会社 配線基板および配線基板の製造方法
CN1925148A (zh) * 2005-08-29 2007-03-07 新光电气工业株式会社 多层配线基板及其制造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000323613A (ja) * 1999-03-11 2000-11-24 Shinko Electric Ind Co Ltd 半導体装置用多層基板及びその製造方法
CN1805657A (zh) * 2004-12-21 2006-07-19 日东电工株式会社 配线电路基板
CN1893054A (zh) * 2005-07-04 2007-01-10 日东电工株式会社 配线电路基板
CN1929123A (zh) * 2005-09-07 2007-03-14 新光电气工业株式会社 多层配线基板及其制造方法

Also Published As

Publication number Publication date
JP5025399B2 (ja) 2012-09-12
CN101399248A (zh) 2009-04-01
KR20090033004A (ko) 2009-04-01
TW200921874A (en) 2009-05-16
CN102280435A (zh) 2011-12-14
JP2009081358A (ja) 2009-04-16
US20090084585A1 (en) 2009-04-02

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CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20111228

Termination date: 20200927

CF01 Termination of patent right due to non-payment of annual fee