CN101252115B - 半导体封装及其制造方法和电子系统及其制造方法 - Google Patents
半导体封装及其制造方法和电子系统及其制造方法 Download PDFInfo
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- CN101252115B CN101252115B CN2008100808376A CN200810080837A CN101252115B CN 101252115 B CN101252115 B CN 101252115B CN 2008100808376 A CN2008100808376 A CN 2008100808376A CN 200810080837 A CN200810080837 A CN 200810080837A CN 101252115 B CN101252115 B CN 101252115B
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- conductive pattern
- semiconductor chip
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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Abstract
本发明公开了一种半导体封装及其制造方法和电子系统及其制造方法。这里描述的半导体封装的一个实施例包括:基底,具有穿过基底延伸的第一通孔;导电图案,在基底上并且在第一通孔上方延伸;第一半导体芯片,面向导电图案,使得第一半导体芯片的至少一部分设置在第一通孔内;第一外部接触端,在第一通孔内,并且将导电图案电连接到第一半导体芯片。
Description
本申请要求于2007年2月21日在韩国知识产权局提交的第10-2007-0017537号韩国专利申请和于2007年12月18日提交的第11/959,276号美国专利中请的优先权,所述申请的公开通过引用被完全包含于此。
技术领域
本发明的实施例总体上涉及半导体封装、包括所述半导体封装的电子系统(例如,集成电路(IC)卡)和制造所述半导体封装和电子系统的方法。更具体地讲,本发明的实施例涉及增加了半导体封装的表面和卡主体的相对表面之间的接触面积的半导体封装及其制造方法。本发明的其它实施例涉及减小了厚度的半导体封装及其制造方法。
背景技术
板上芯片(COB)型半导体封装通常用于制造IC卡,例如智能卡。现在,IC卡代替磁卡通常用在各种应用中。
参照图1,COB型半导体封装包括附于半导体封装基底4的顶部表面的半导体芯片3。半导体芯片3的有源表面3a利用键合线6电连接到金属层5,金属层5设置在半导体封装基底4的与顶部表面相对的另一表面上,键合线6延伸穿过限定在半导体封装基底4中的布线孔4a。当有源表面3a设置在半导体封装基底4的与设置有金属层5的表面相对的顶部表面上方时,通常需要键合线6。COB型半导体封装利用COB型半导体封装的表面1a和卡主体2的相对表面之间的粘合剂(未示出)结合到卡主体2。具体地讲,COB型半导体封装设置在空穴2a内,空穴2a限定在卡主体2中。
键合线6不可避免地从半导体芯片3的有源表面3a突出一定高度,从而形成键合线6远离有源表面3a延伸然后向金属层5弯曲的回路。还提供包封剂9,从而包封键合线6。因此,必须提供足够量的包封剂9来保护键合线6免受外部环境的影响。因此,包封剂9产生相对大的成型区域“B”,余下相对小的结合区域“A”,在结合区域“A”中,半导体封装的表面1a和卡主体2的相对表面可以彼此结合。另外,因为键合线6需要形成在半导体芯片3的两侧,所以又增加了成型区域“B”的长度,在可用封装系统的总长度受到限制的同时,进一步减小了结合区域“A”的长度。
另外,已经发现了在COB型半导体封装的制造过程中基底4的边缘趋于变形的问题。因此,因为传统系统的结合区域“A”相对小,所以基底4趋向于与卡主体2分离,并且所得IC卡会容易损坏或者破损。
随着半导体芯片3的尺寸增加并且封装系统或者IC卡经受更加苛刻的环境,这些问题会变得越来越严重。
图2是用来解决上述问题的另一传统的封装系统的剖视图。
参照图2,传统的封装系统可以被设置为倒装芯片型COB封装系统。如图2中所示,IC卡包括卡主体12,卡主体12具有在其中限定的空穴12a。半导体芯片13附于半导体封装基底14,形成倒装芯片型COB半导体封装。在倒装芯片型COB半导体封装中,半导体芯片13的有源表面13a利用结合到中间金属层17的导电凸块18电连接到金属层15。依次地,中间金属层17通过延伸穿过封装基底14的导电孔16电连接到金属层15。半导体封装利用倒装芯片型COB半导体封装的表面11a和卡主体2的相对表面之间的粘合剂(未示出)结合到卡主体2。
导电凸块18从半导体芯片13的表面远离空穴12a的底表面突出,提供包封剂19,从而包封导电凸块18。然而,也必须提供足够量的包封剂19,以将半导体芯片13充分地固定到中间金属层17和基底14。
因此,包封剂19保持相对大的成型区域“B”,余下相对小的结合区域“A”,在结合区域“A”中,可将粘合剂涂覆在半导体封装的表面11a和卡主体12的相对表面之间。如在图1中讨论的IC卡中,基底14或者半导体封装也趋向于与卡主体12分开。另外,中间金属层17的存在趋向于增加倒装芯片型COB半导体封装系统的总厚度“T”,并且增加制造倒装芯片型COB封装系统的成本和复杂程度。因此,即使采用针对图2所讨论的封装系统,也不能有效地解决上述问题。
本发明解决了传统技术的这些问题和其它缺点。
发明内容
本发明的一个实施例的特征可以示例性地在于这样一种半导体封装,所述半导体封装包括:基底,包括上表面和与上表面相对的下表面以及从上表面延伸到下表面的第一通孔;导电图案,在基底的上表面上并且在第一通孔上方延伸;第一半导体芯片,面向导电图案,第一半导体芯片的至少一部分设置在第一通孔内;第一外部接触端,在第一通孔内,并且将导电图案电连接到第一半导体芯片。
本发明的另一实施例的特征可以示例性地在于一种形成半导体封装的方法,所述方法包括以下步骤:提供包括上表面和与上表面相对的下表面的基底;在基底内形成第一通孔,第一通孔从上表面延伸到下表面;在基底的上表面上形成导电图案,其中,导电图案在第一通孔上方延伸;将第一半导体芯片的至少一部分设置在第一通孔内;利用位于第一通孔内的第一外部接触端将导电图案电连接到第一半导体芯片。
本发明的又一实施例的特征可以示例性地在于一种形成电子系统的方法,所述方法包括以下步骤:提供包括上表面和与上表面相对的下表面的基底;在基底内形成第一通孔,第一通孔从上表面延伸到下表面;在基底的上表面上形成导电图案,其中,导电图案在第一通孔上方延伸;将第一半导体芯片的至少一部分设置在第一通孔内;利用位于第一通孔内的第一外部接触端将导电图案电连接到第一半导体芯片;在导电图案和第一半导体芯片之间提供绝缘材料;将基底结合到封装主体,形成电子系统,其中,基底的至少一部分设置在限定在封装主体中的凹槽内。
本发明的再一实施例的特征可以示例性地在于一种电子系统,所述电子系统包括半导体封装和容纳该半导体封装的封装主体。所述半导体封装可以包括:基底,包括上表面和与上表面相对的下表面以及从上表面延伸到下表面的第一通孔;导电图案,在基底的上表面上并且在第一通孔上方延伸;第一半导体芯片,面向导电图案,第一半导体芯片的至少一部分设置在第一通孔内;第一外部接触端,在第一通孔内并且将导电图案电连接到第一半导体芯片。
附图说明
在下文中,将参照附图来描述本发明的实施例,在附图中:
图1是与卡主体结合形成集成电路(IC)卡的传统封装系统的剖视图;
图2是另一传统封装系统的剖视图;
图3A是根据一个实施例的封装系统的剖视图;
图3B是根据另一实施例的封装系统的剖视图;
图4是包含在图3A中示出的封装系统中的半导体封装的一个实施例的分解透视图;
图5是在图3A中示出的封装系统的一个实施例的分解透视图;
图6是描述制造在图3A中示出的封装系统的示例性方法的流程图;
图7是包含在图3A中示出的封装系统中的半导体封装的另一实施例的分解透视图;
图8是包含在图3A中示出的封装系统中的半导体封装的又一实施例的分解透视图;
图9A是包含在图3A中示出的封装系统中的半导体封装的再一实施例的分解透视图;
图9B是在图9A中示出的半导体封装的一部分的剖视图;
图10A-10E是半导体封装的一些实施例的剖视图;
图11是异类多芯片半导体封装的一个实施例的剖视图;
图12是同类多芯片半导体封装的一个实施例的剖视图;
图13A-13E是多芯片半导体封装的其它实施例的剖视图。
具体实施方式
现在,在下文中将参照附图来更充分地描述本发明的示例性实施例。然而,可以以许多不同的形式来实现这些实施例,而不应该被理解为限于这里阐述的实施例。相反,提供这些实施例,使得本公开将是彻底和完全的,并且将本发明的范围充分传达给本领域技术人员。在附图中,为了清晰起见,夸大了层和区域的厚度。在整个说明书中,相同的标号表示相同的元件。
图3A是根据一个实施例的封装系统的剖视图。图4是包含在图3A中示出的封装系统内的半导体封装的一个实施例的分解透视图。图5是在图3A中示出的封装系统的一个实施例的分解透视图。
参照图3A,根据一个实施例的IC卡或者封装系统200可以包括例如半导体封装20和卡主体26。
卡主体26可以包括限定在其中的凹槽26a。凹槽26a通常被构造为容纳半导体封装20。在一个实施例中,例如,凹槽26a可以包括:芯片容纳部分223,被构造为容纳第一半导体芯片22;基底容纳部分222,被构造为容纳基底23。
例如,半导体封装20可以包括第一半导体芯片22、位于第一半导体芯片22上的多个第一外部接触端21、封装基底23和设置在封装基底23上的多个导电图案24。半导体封装20具有利用公知技术(例如,采用粘合剂)结合到卡主体26的相对表面的粘合剂表面20a。可以利用传统技术例如,在基底23上形成导电层并且执行光刻来形成导电图案的技术来形成导电图案24。
在一个实施例中,例如,封装基底23可以包括上表面23b、下表面23c和从上表面23b延伸到下表面23c的第一通孔23a。例如,多个导电图案24可以设置在基底23的上表面23b上并且在第一通孔23a上方延伸。另外,第一半导体芯片22可以面向多个导电图案24,第一半导体芯片22的至少部分可以设置在第一通孔23a中(例如,如图4中示例性示出)。
另外,多个第一外部接触端21可以将多个导电图案24电连接到第一半导体芯片22。第一外部接触端21可以在第一通孔23a内接触多个导电图案24。因为第一外部接触端21可以直接接触多个导电图案24,所以在本实施例中,图2中示出的中间金属层17不是必须的,从而可以去除金属层17,如将在下面进一步解释。
因为第一半导体芯片22的至少部分设置在第一通孔23a中,所以与传统半导体封装相比,可以将半导体封装的总厚度“t”减小到第一半导体芯片22插入或者包含在第一通孔23a中的程度。例如,因为在半导体芯片和导电图案24之间没有如传统半导体封装中的额外的金属层,所以可以减小封装厚度“t”。
在一个实施例中,形成半导体封装20的方法可以以这样的方法为特征,该方法包括:提供包括上表面和与上表面相对的下表面的基底23;在基底23中形成第一通孔23a,并且第一通孔23a从上表面延伸到下表面;在基底23的上表面上形成导电图案24,从而导电图案24在第一通孔23a上方延伸;将第一半导体芯片22提供到第一通孔23a的至少部分中;采用位于第一通孔23a内的第一导电互连部分21将导电图案24电连接到半导体芯片22。还是如以上示例性所述,形成半导体封装20的方法可以以这样一种方法为特征,该方法包括:形成多个第一导电互连部分21和多个导电图案24,使得多个第一导电互连部分21将第一半导体芯片22电连接到多个导电图案24。
如图3A中示例性示出,多个第一外部接触端21的底表面可以位于基底23的上表面23b和下表面23c之间。
在一方面,在本实施例中,例如,如图3A中所示,第一半导体芯片22可以包括面向导电图案24的有源表面22a。可选地,有源表面22a可以背离导电图案24。在这种情况下,可以穿过半导体芯片22形成导电通孔,以连接到导电图案24,例如,如图12中所示。
在一个实施例中,多个第一外部接触端21可以为设置在第一半导体芯片22上的导电凸块(例如,焊料凸块)、导电球(例如,焊料球)等。例如,导电凸块或者导电球可以通过以下工艺形成:在第一半导体芯片22的有源表面22a上形成多个焊盘,在第一半导体芯片22的有源表面22a上方形成钝化层图案,以暴露多个焊盘中的每个的至少部分并在多个焊盘中的每个的暴露部分上设置导电材料(例如,铅、锡等或者它们的组合)。也可以通过将布线键合到多个焊盘中的每个的暴露部分并且在焊盘上方的一定高度处切断布线来形成导电凸块。多个第一外部接触端21可以通过以下工艺来示例性地形成:在第一半导体芯片22的有源表面22a上方提供种子层(seed layer),在种子层上方形成光致抗蚀剂图案,将种子层图案化,去除光致抗蚀剂图案并且在图案化的种子层上电镀导电材料。在一个实施例中,种子层可以包含铜,且种子层的厚度可以为大约0.5μm,而导电材料可以包含金。在另一个实施例中,尽管未示出,但是多个第一外部接触端21和多个导电图案24中的对应的导电图案可以设置为一体的结构。在这种实施例中,多个外部接触端从多个导电图案中的对应的导电图案突出,从而接触第一半导体芯片22,如在图3B中示例性示出。例如,如图3B中所示,导电图案24a可以包括远离导电图案24a的底表面突出的突出部分21a,以接触第一半导体芯片22。在一个实施例中,例如可以通过在将导电图案24附于基底23之前将导电图案24弯曲来形成导电图案24a。然而,应该理解,导电图案24a可以按照任何期望的方式构造,从而接触第一半导体芯片22。例如,可以通过压制来形成导电图案24a。
另外,绝缘材料25可以设置在第一半导体芯片22和多个导电图案24之间。结果,可以用绝缘材料25来覆盖形成有集成电路的有源表面22a和第一外部接触端21,从而可以保护有源表面22a和第一外部接触端21免受外部环境的损坏。采用可以形成在基底23上的绝缘材料25,第一半导体芯片22可以稳固地固定到基底23。例如,绝缘材料25可以包括绝缘材料,比如粘合剂、环氧树脂、环氧成型化合物(EMC)、聚酰胺树脂等或者它们的组合。
在一个实施例中,可以通过将绝缘材料注入到限定在第一半导体芯片22、基底23和导电图案24之间的空间中来提供绝缘材料25。
采用本发明上述的一些实施例,在可以增加粘合剂表面20a的面积的同时,可以减少基底23上的绝缘材料25的量。具体地讲,在可以减小成型区域“B1”的同时,可以增大结合区域“A1”。具体地,不需要充足地提供绝缘材料25来覆盖如图2中示出的传统的封装系统中的中间金属层是事实。
结果,半导体封装20可以稳固地结合到卡主体26,因此,可以显著地减少或者抑制半导体封装20与卡主体26分离或者损坏半导体封装20。
如在图4中更清楚地示出,多个半导体图案24中的每个可以基本上相同地构造。例如,半导体图案24中的每个可以基本上为矩形。在一个实施例中,导电图案24可以包含导电材料(例如,金属),并且可以具有大于大约18μm的厚度。在另一实施例中,当在平面图上观察时,第一通孔23a可以具有基本为矩形的形状。
另外,如图4中所示,通过基底23的限定第一通孔23a的两个相邻边缘的区域来支撑在第一通孔23a的拐角区域上方延伸的一些导电图案24。通过基底23的限定第一通孔23a的一个边缘的区域来支撑在第一通孔23a的侧面区域上方延伸的一些导电图案24。因此,可以由基底23来支撑每个导电图案24的仅一个区域。换而言之,每个导电图案24在一个区域由基底23支撑。因此,多个导电图案24中的第一部分可以在第一通孔23a的拐角区域上方延伸,多个导电图案24中的第二部分可以在第一通孔23a的侧面区域上方延伸,其中,侧面区域位于拐角区域之间。
另外,如图4中所示,半导体芯片22可以设置或者插入在第一通孔23a中。半导体芯片22结合到导电图案24,绝缘体(未示出)可以填充半导体芯片和包括导电图案24的基底23之间的空间。绝缘体可以为包封剂,例如,粘合剂、环氧树脂、包括聚酰胺的树脂等。
考虑到上述内容,总而言之,形成封装系统200(这里也被称作电子系统或者IC卡)的方法可以示例性地以这样一种方法为特征,该方法包括:提供包括上表面和与上表面相对的下表面的基底23;在基底23内形成第一通孔23a,使得第一通孔23a从上表面延伸到下表面;在基底23的上表面上形成导电图案24,使得导电图案24在第一通孔23a上方延伸;将第一半导体芯片22的至少部分提供到第一通孔23a中;利用位于第一通孔23a中的第一导电互连部分21将导电图案24电连接到半导体芯片22;在导电图案24和第一半导体芯片22之间提供绝缘材料25并将基底23结合到卡主体26来形成电子系统200,其中,基底23的至少部分设置在凹槽26a中,凹槽26a限定在卡主体26内。
另外根据如上所述,封装系统200(这里也被称作电子系统或者IC卡)的特征可以示例性地在于包括半导体封装20和容纳半导体封装20的卡主体26。半导体封装20的特征可以示例性地在于包括:基底23,具有上表面、与上表面相对的下表面和从上表面延伸到下表面的第一通孔23a;导电图案24,位于基底的上表面上并且在第一通孔23a上方延伸;第一半导体芯片22,面对导电图案24,使得第一半导体芯片22的至少部分设置在第一通孔23a内;第一外部接触端21,位于第一通孔23a内并且将导电图案24电连接到第一半导体芯片22。
另外,总而言之,如针对图3A至图5以上示例性示出的,与例如以上针对图2所述的第一半导体芯片22固定到中间金属层17相比,因为将第一半导体芯片22充分地固定到基底23所需的绝缘材料25的量较少,所以绝缘材料25产生相对于结合区域“A1”相对小的成型区域“B1”。因此,在半导体封装20的表面20a和卡主体26的相对表面之间可以涂覆粘合剂的位置,可以提供相对大的结合区域(粘合剂表面)“A1”。结果,可以防止半导体封装20与卡主体26分离。另外,与图2中示出的倒装芯片COB型封装系统的厚度相比,由于没有中间金属层17和基底14的设置在导电孔16之间的部分,所以可以减小系统封装200的厚度“t”。另外,可以以相对降低的成本和相对小的复杂程度来制造图3A至图5中示出的封装系统200。
图6是描述制造在图3A-5中示出的封装系统的示例性方法的流程图。
参照图6,制造图3A-5中示出的封装系统200的示例性方法的特征大体可以在于包括形成半导体封装20的第一工艺610、形成卡主体26的第二工艺620和将半导体封装20插入到卡主体26的凹槽26a中的第三工艺630。
在一个实施例中,形成半导体封装20的第一工艺610可以如下执行。在工艺611中,在第一半导体芯片22上形成多个第一外部接触端21。在工艺613中,在基底23中形成第一通孔23a。在工艺615中,在基底23上形成导电图案24。在一个实施例中,通过第一通孔23暴露导电图案24的一部分。在工艺617中,将第一半导体芯片22插入到第一通孔23a中。此时,半导体芯片22的有源表面面对导电图案24并且通过多个第一外部接触端21电连接到导电图案24。在工艺619中,将绝缘材料25形成或者注入在导电图案24和第一半导体芯片22之间,来包封第一半导体芯片22和导电图案24。在一个实施例中,可以在将半导体封装20插入到卡主体26的凹槽26a中的过程中形成绝缘材料25。即,可以在将半导体封装20结合到卡主体26的同时提供绝缘材料25。
在工艺620中,独立于上述工艺,在卡主体26中形成凹槽26a。在一个实施例中,可以在形成卡主体26时(例如,在成型工艺期间)形成凹槽26a。在工艺630中,将通过上述工艺形成的半导体封装20插入到凹槽26a中,形成封装系统200。
在一些实施例中,可以在执行底部充胶(underfill)工艺的同时执行工艺619和工艺630。
图7是包含在图3A中示出的系统内的半导体封装的另一实施例的分解透视图。
参照图7,可以与如上针对图3A和图4所述类似地提供半导体封装20。然而,根据在图7中示出的实施例,可以根据导电图案24在基底23的上表面上的位置来不同地构造多个导电图案24。例如,在第一通孔23a的侧面区域上方延伸的多个导电图案24中的至少一个可以包括接触部分34和延伸部分35。通过基底23的限定第一通孔23a的边缘(例如,第一边缘)的区域(例如,第一区域)来支撑接触部分34。通过基底23的限定第一通孔23a的另一边缘(例如,与第一边缘相对的第二边缘)的另一区域(例如,第二区域)来支撑延伸部分35。接触部分34被构造为便于与外部接触端21接触,并且延伸部分35被构造为支撑接触部分34的末端。因此,可以通过基底23仅支撑每个导电图案24的在第一通孔23a的侧面区域上方延伸的两个区域。换而言之,在第一区域和第二区域,通过基底23支撑在第一通孔23a的侧面区域上方延伸的每个导电图案24。第一区域和第二区域彼此分开。例如,对于每个导电图案24,在第一通孔23a的第一侧,通过基底23支撑接触部分34的区域;在第一通孔23a的与第一侧相对的第二侧,通过基底23支撑延伸部分35的区域。
在一个实施例中,一个导电图案24的接触部分34沿着第一通孔23a的第一侧(或者第二侧)与另一导电图案24的延伸部分35相邻。
在另一实施例中,在第一通孔23a的第一侧由基底23支撑的接触部分34的形状可以与在第一通孔23a的第二侧由基底23支撑的接触部分34的形状相同。类似地,在第一通孔23a的第二侧由基底23支撑的延伸部分35的形状可以与在第一通孔23a的第一侧由基底23支撑的延伸部分35的形状相同。
在又一实施例中,在第一通孔23a的侧面区域上方延伸的导电图案24的接触部分34的特征可以在于具有矩形形状。类似地,在第一通孔23a的侧面区域上方延伸的导电图案24的延伸部分35的特征可以在于具有窄条形形状。
当如上针对图7所述进行设置时,因为可以支撑导电图案24的两端,所以在第一通孔23a的侧面区域上方延伸的导电图案24可以比如上针对图4所述的导电图案24经历较小的变形(例如,弯曲、破裂、断开等)。
图8是包含在图3A中示出的封装系统内的半导体封装的又一实施例的分解透视图。
参照图8,可以与以上针对图3A和图4所述类似地提供半导体封装20。然而,根据在图8中示出的实施例,可以提供绝缘材料25作为在将第一半导体芯片22插入到第一通孔23a中之前形成的绝缘体框架主体252。在一个实施例中,绝缘体框架主体252可以包括上部252a和下部252b。绝缘体框架主体252的上部252a可以被构造为插入到第一通孔23a中。绝缘体框架主体252的下部252b可以被构造为结合到基底23的下表面(例如,通过粘合剂材料)。在一个实施例中,上部252a和下部252b可以利用粘合剂材料分别附于半导体芯片22和基底23,从而将半导体芯片22稳固地结合到基底23。
可以在绝缘体框架主体252中限定多个绝缘体框架主体通孔254,并且多个绝缘体框架主体通孔254从绝缘体框架主体252的上表面延伸到绝缘体框架主体252的下表面。在一个实施例中,多个第一外部接触端21可以插入到多个绝缘体框架主体通孔254中。在另一实施例中,多个第一外部接触端21可以延伸完全穿过多个绝缘体框架主体通孔254,以结合到导电图案24。
因此,如上示例性所述,根据一个实施例的绝缘材料25的特征可以在于包括穿过其限定的绝缘体框架主体通孔254的绝缘体框架主体252,使得第一外部接触端21可以延伸穿过绝缘体框架主体通孔254。
在一个实施例中,例如,提供绝缘材料25的方法可以包括:形成绝缘体框架主体252,其中,绝缘体框架主体252包括穿过其限定的绝缘体框架主体通孔254;将绝缘体框架主体252设置在第一通孔23a内,邻近导电图案24。例如,将导电图案24电连接到第一半导体芯片22的方法可以包括穿过绝缘体框架主体通孔254插入第一外部接触端21。
当多个第一外部接触端21延伸完全穿过多个绝缘体框架主体通孔254时,在一个实施例中,第一半导体芯片22可以接触绝缘体框架主体252的下部252b。在该实施例中,第一半导体芯片22可以通过例如粘合剂结合到绝缘体框架主体252的下部252b。
如上所述地构造,绝缘体框架主体252可以有助于多个第一外部接触端21相对于多个导电图案24中的对应的导电图案排列在第一通孔23a内。
绝缘体框架主体252可以由绝缘材料例如聚酰亚胺、环氧树脂、树脂等形成。图9A是包含在图3A中示出的封装系统内的半导体封装的再一实施例的分解透视图。图9B是在图9A中示出的半导体封装的一部分的剖视图。
参照图9A,可以与以上针对图3A和图4所述类似地提供半导体封装20。然而,根据在图9A中示出的实施例,可以在将第一半导体芯片22插入到第一通孔23a中之前提供并形成可以被设置成图3A、图3B和图4中的绝缘材料25的各向异性导电膜(ACF)253。ACF 253可以包括设置(例如,悬浮)在其中的多个导电颗粒253a。在该实施例中,ACF 253可被设置成可压缩材料。当不被压缩时,ACF 253显示出电绝缘特性。然而,当被压缩足够的量时,导电颗粒253a导致接触,从而可以通过导电颗粒253a传输电信号。
参照图9B,当将第一半导体芯片22插入到第一通孔23a中时,多个第一外部接触端21局部地压缩各向异性导电膜253的区域,从而可以在多个第一外部接触端21和导电图案24之间通过多个导电颗粒253a传输电信号。在一个实施例中,多个第一外部接触端21的高度可以为大约8-16μm,各向异性导电膜253的厚度可以比多个第一外部接触端21的高度大大约5-20μm。
图10A-10E是半导体封装的一些实施例的剖视图。
如上所述,可以通过将绝缘材料注入到在第一半导体芯片22、基底23和导电图案24之间限定的空间中来提供绝缘材料25。在注入工艺期间,绝缘材料25可能会流入在相邻的导电图案24之间限定的空间中,甚至流到导电图案24的上表面上。因此,可以提供阻挡构件(例如在图10A-10E中描述的40、41、42或43)来防止绝缘材料25流到导电图案24之间和流到导电图案24上,这些将在后面进行更详细地解释。
在一个实施例中,可以在形成绝缘材料25之前设置阻挡构件。
在一些实施例中,可以提供阻挡构件,使之跨过在多个导电图案24中的相邻的导电图案24之间限定的空间的至少一部分并且在多个导电图案24中的成对的相邻的导电图案24之间延伸,例如,如图10A中所示。另外,在图10A中,可以在相邻的导电图案24的下表面上提供阻挡构件40(例如,绝缘膜),使之跨过在相邻的导电图案24之间限定的空间。
在一些实施例中,可以在多个导电图案24中的相邻的导电图案24之间限定的空间的至少一部分内设置阻挡构件,例如,如图10B中所示。例如,在图10B中,阻挡构件41可以设置在相邻的导电图案24之间限定的空间内。如图10B中示例性示出的,阻挡构件41可以基本上完全设置在导电图案24的上表面和下表面之间。
在一些实施例中,阻挡构件可以位于多个导电图案24中的相邻的导电图案24和第一半导体芯片22之间,例如,如图10C和图10D中所示,将对这些进行详细的解释。
参照图10C,阻挡构件42可以设置在限定在相邻的导电图案24之间的空间中并且可以部分地延伸到在导电图案24和第一半导体芯片22之间限定的空间中。即,阻挡构件42可以部分地延伸到第一通孔23a中。采用图10C中示出的阻挡构件42,可以减小漏电流。
另外,参照图10D,阻挡构件43可以设置在限定在相邻的导电图案24之间的空间中,并且可接触第一半导体芯片22。采用完全延伸到第一半导体芯片22的阻挡构件43,可以进一步减小漏电流。
在一方面,可以在将绝缘材料25设置在第一半导体芯片22、基底23和导电图案24之间之前,利用丝网印刷方法来形成图10A-10D中示出的阻挡构件。
参照图10E,可以在相邻的导电图案24的上表面上提供阻挡构件44,使之跨过在导电图案24之间限定的空间。
在一些实施例中,阻挡构件40至43可以包含树脂型材料。在另一实施例中,阻挡构件44可以为带型材料。因此,例如,根据一个实施例的形成半导体封装的方法可以包括在形成绝缘材料25之后去除阻挡构件44。
在一个实施例中,带型材料可以包括选择性地可附于导电图案24/可与导电图案24分离的材料。在一个实施例中,树脂型材料可以包括可以硬化(例如,注入绝缘材料之后)的材料。
图11是异类多芯片半导体封装的一个实施例的剖视图。图12是同类多芯片半导体封装的一个实施例的剖视图。应该理解,以上针对图3A-10E描述的实施例不限于单一芯片半导体封装,而是可以容易地应用于或者延伸到各种类型的多芯片封装。例如,参照图11,多芯片半导体封装50a可以包括通过多个第一外部接触端21连接到导电图案24的第一半导体芯片22以及通过键合线561和562(共同标为560)连接到导电图案24的多个第二芯片571和572(共同标为570)。第二芯片571可以通过任何合适的方式(例如,通过粘合剂材料)结合到第一半导体芯片22。第二芯片572可以通过任何合适的方式结合到另一第二芯片571。在示出的实施例中,多个第一外部接触端21延伸穿过第一通孔23a,从而将第一半导体芯片22与导电图案24电连接;布线561延伸穿过通孔23d,从而将第二芯片570与导电图案24电连接。在一个实施例中,第二芯片570可以与第一半导体芯片22不同。因此,多芯片半导体封装50a可以为异类多芯片半导体封装。
参照图12,多芯片半导体封装50b可以包括通过多个第一外部接触端21连接到导电图案24的第一半导体芯片22以及通过穿过第一半导体芯片22延伸的导电通孔59连接到导电图案24的第二芯片57。在示出的实施例中,外部接触端58将导电通孔59与第二半导体芯片57电连接。如上所述,形成半导体封装50b的方法可以以这样一种方法为特征,该方法包括:将第二半导体芯片57结合到第一半导体芯片22;穿过第一半导体芯片22形成导电通孔59,其中,导电通孔59将第一半导体芯片22和第二半导体芯片57电连接。
在一个实施例中,第一半导体芯片22和第二半导体芯片57可以相同,可以基本相同或者可以相似(例如,基于功能)。因此,多芯片半导体封装50b可以是同类多芯片半导体封装。
图13A-13E是多芯片半导体封装的其它实施例的剖视图。
参照图13A,例如,多芯片半导体封装60a可以包括:第一半导体芯片22,通过多个第一外部接触端21电连接到导电图案24;第二半导体芯片575,通过布线563电连接到导电图案24;第三半导体芯片576,结合到第二半导体芯片575并且通过外部接触端58电连接到第二半导体芯片575的有源表面575a。
参照图13B,例如,可以与针对图13A所述类似地提供多芯片半导体封装60b,但是多芯片半导体封装60b还可以包括通过延伸穿过第三半导体芯片576的导电通孔59电连接到第二半导体芯片575的有源表面575a的另外的半导体芯片577。在示出的实施例中,外部接触端582将另外的半导体芯片577与导电通孔59电连接。
参照图13C,例如,多芯片半导体封装60c可以包括:第一半导体芯片22,通过多个第一外部接触端21电连接到导电图案24;第二半导体芯片578,结合到第一半导体芯片22;第三半导体芯片579,通过布线564电连接到导电图案24。第二半导体芯片578可以通过延伸穿过第三半导体芯片579的导电通孔59电连接到导电图案24。在示出的实施例中,外部接触端58将第二半导体芯片578与导电通孔59电连接。
参照图13D,例如,可以与针对图13C的描述类似地提供多芯片半导体封装60d,但是多芯片半导体封装60d还可以包括通过布线565电连接导电图案24的另外的半导体芯片580。在示出的实施例中,第三半导体芯片579可以通过延伸穿过另外的半导体芯片580的导电通孔592电连接到导电图案24,其中,外部接触端582将第三半导体芯片579与导电通孔592电连接。另外,在示出的实施例中,第二半导体芯片578可以通过延伸穿过第三半导体芯片579的导电通孔591电连接到导电图案24,其中,外部接触端581将第二半导体芯片578与导电通孔591电连接。
参照图13E,例如,多芯片半导体封装60e可以包括:第一半导体芯片22,通过多个第一外部接触端21电连接到导电图案24;第二半导体芯片573,通过延伸穿过第一半导体芯片22的导电通孔511电连接到导电图案24;第三半导体芯片574,通过延伸穿过第二半导体芯片573的导电通孔512电连接到导电图案24。在示出的实施例,外部接触端581将第二半导体芯片573与导电通孔511电连接,外部接触端582将第三半导体芯片574与导电通孔512电连接。
根据如上针对图3A-13E示例性描述的实施例,可以提供封装系统,其中,因为可以显著地增加卡主体和半导体封装之间的结合区域“A1”,从而保卡主体和半导体封装之间稳固地连接,所以基本上防止半导体封装与卡主体分离,如图3A中所示。换而言之,由于可以增大卡主体和封装之间的粘附,因此可以将卡主体和封装彼此稳固地固定。结果,可以显著增加封装系统或者IC卡的耐久性和可靠性。
另外,由于(至少部分地由于)该半导体封装的结构,所以在上述实施例中示例性描述的封装系统可以被制造得相对薄、廉价并且不复杂。具体地,半导体芯片可以设置在基底的开口内是事实,从而由于半导体芯片的厚度没有被加到电子系统的总厚度中而减小了电子系统的总厚度。结果,根据本发明的实施例可以得到更薄的半导体封装和电子系统,例如IC卡。
另外,根据以上示例性描述的实施例,与现有技术相比,因为本发明的方法需要更少的金属或者导电层,所以可以减少工艺步骤,从而显著降低了总体制造成本。
应该理解,可以结合器件例如IC卡、存储卡、USB卡、媒体播放器(例如,MP3播放器)的内部存储器封装、移动电话、数码照相机等来实施根据以上示例性描述的实施例提供的半导体系统和半导体封装。
参照整个说明书,“一个实施例”或者“实施例”意味着结合实施例描述的具体特征、结构或者特性包含在本发明的至少一个实施例中。因此,在整个说明书中,在各个位置中出现的短语“在一个实施例中”或者“在实施例中”不必须总是表示相同的实施例。另外,在一个或者多个实施例中,可以按照任何合适的方式来组合具体的特征、结构或者特性。
各种操作将被描述为按照最有助于理解本发明的方式执行的多个不连续的步骤。然而,描述步骤的顺序不暗示所述操作是存在顺序关系的或者执行步骤的顺序必须为步骤出现的顺序。
另外,为了避免不必要的细节使本发明的描述变得模糊,没有示出公知的结构和器件。
尽管以上已经具体示出和描述了本发明的实施例,但是本领域的普通技术人员应该理解,在不脱离由权利要求限定的本发明的精神和范围的情况下,可以对此进行各种形式和细节上的改变。
Claims (22)
1.一种半导体封装,包括:
基底,包括穿过基底延伸的第一通孔;
多个导电图案,在基底上面并且在第一通孔上方延伸;
第一半导体芯片,面向导电图案,第一半导体芯片的至少部分设置在第一通孔内;
多个第一外部接触端,位于第一通孔内并且多个第一外部接触端中的每个将第一半导体芯片电连接到多个导电图案中对应的导电图案,
在多个导电图案之间限定空间,所述半导体封装还包括阻挡构件,所述阻挡构件跨过所述空间并且在多个导电图案中的至少一对相邻的导电图案之间延伸,以防止在所述第一半导体芯片、所述基底和所述导电图案之间限定的空间中注入绝缘材料期间所述绝缘材料流到导电图案之间和流到导电图案上。
2.根据权利要求1所述的半导体封装,其中,第一外部接触端包括设置在第一半导体芯片上的导电凸块、导电球或者它们的组合。
3.根据权利要求1所述的半导体封装,其中,第一外部接触端和导电图案形成一体结构,第一外部接触端从导电图案突出。
4.根据权利要求1所述的半导体封装,其中,基底包括上表面和与上表面相对的下表面,其中,第一外部接触端的底表面位于基底的上表面和下表面之间。
5.根据权利要求1所述的半导体封装,其中,在第一区域和与第一区域分开的第二区域,通过基底支撑导电图案,其中,第一区域限定第一通孔的第一边缘,第二区域限定与第一通孔的第一边缘相对的第二边缘。
6.根据权利要求5所述的半导体封装,其中,导电图案包括在第一区域由基底支撑的接触部分和在第二区域由基底支撑的延伸部分,所述第一区域与所述第二区域彼此相对。
7.根据权利要求6所述的半导体封装,其中,所述接触部分具有矩形形状,所述延伸部分具有窄条形形状。
8.根据权利要求1所述的半导体封装,其中,所述阻挡构件设置在多个导电图案中的成对的相邻导电图案的下表面上。
9.根据权利要求1所述的半导体封装,其中,所述阻挡构件设置在在多个导电图案之间限定的所述空间的至少一部分内。
10.根据权利要求1所述的半导体封装,其中,所述阻挡构件的至少一部分设置在多个导电图案和第一半导体芯片之间。
11.根据权利要求1所述的半导体封装,其中,在平面图中,第一通孔具有基本上矩形的形状。
12.根据权利要求1所述的半导体封装,其中,第一外部接触端直接接触导电图案。
13.根据权利要求1所述的半导体封装,还包括:
第二半导体芯片,电结合到第一半导体芯片。
14.根据权利要求13所述的半导体封装,还包括:
导电通孔,延伸穿过第一半导体芯片,其中,导电通孔将第一半导体芯片和第二半导体芯片电连接。
15.根据权利要求13所述的半导体封装,其中,第二半导体芯片利用键合线电结合到导电图案。
16.一种形成半导体封装的方法,所述方法包括以下步骤:
提供包括上表面和与上表面相对的下表面的基底;
在基底内形成第一通孔,第一通孔从上表面延伸到下表面;
在基底的上表面上形成多个导电图案,其中,所述多个导电图案在第一通孔上方延伸;
将第一半导体芯片的至少一部分设置在第一通孔内;
利用位于第一通孔内的多个第一外部接触端将导电图案电连接到第一半导体芯片,其中多个第一外部接触端中的每个将第一半导体芯片电连接到多个导电图案中对应的导电图案,
其中,在多个导电图案之间限定空间,所述方法还包括以下步骤:设置阻挡构件,所述阻挡构件跨过所述空间并且在多个导电图案中的至少一对相邻的导电图案之间延伸,以防止在所述第一半导体芯片、所述基底和所述导电图案之间限定的空间中注入绝缘材料期间所述绝缘材料流到导电图案之间和流到导电图案上。
17.根据权利要求16所述的方法,其中,第一外部接触端和导电图案形成一体结构,第一外部接触端从导电图案突出,其中,将导电图案电连接到第一半导体芯片的步骤包括使第一半导体芯片接触第一外部接触端。
18.一种形成电子系统的方法,所述方法包括以下步骤:
提供基底,所述基底具有穿过基底延伸的第一通孔;
在基底上形成多个导电图案,其中,所述多个导电图案在第一通孔上方延伸;
将第一半导体芯片的至少一部分设置在第一通孔内;
利用位于第一通孔内的多个第一外部接触端将导电图案电连接到第一半导体芯片,其中多个第一外部接触端中的每个将第一半导体芯片电连接到多个导电图案中对应的导电图案;
在所述导电图案和第一半导体芯片之间提供绝缘材料;
将基底结合到卡主体,形成所述电子系统,其中,所述基底的至少一部分设置在限定在所述卡主体中的凹槽内,
其中,在多个导电图案之间限定空间,所述方法还包括以下步骤:设置阻挡构件,所述阻挡构件跨过所述空间并且在多个导电图案中的至少一对相邻的导电图案之间延伸,以防止在注入所述绝缘材料的工艺期间所述绝缘材料流到导电图案之间和流到导电图案上。
19.根据权利要求18所述的方法,还包括提供所述绝缘材料并且同时将所述基底结合到卡主体。
20.一种电子系统,包括:
半导体封装;
卡主体,容纳半导体封装,
其中,所述半导体封装包括:
基底,具有穿过基底延伸的第一通孔;
多个导电图案,在所述基底上并且在第一通孔上方延伸;
第一半导体芯片,面向导电图案,第一半导体芯片的至少一部分设置在第一通孔内;
多个第一外部接触端,位于第一通孔内,并且多个第一外部接触端中的每个将第一半导体芯片电连接到多个导电图案中对应的导电图案,在多个导电图案之间限定空间,所述半导体封装还包括阻挡构件,所述阻挡构件跨过所述空间并且在多个导电图案中的至少一对相邻的导电图案之间延伸,以防止在所述第一半导体芯片、所述基底和所述导电图案之间限定的空间中注入绝缘材料期间绝缘材料流到导电图案之间和流到导电图案上。
21.根据权利要求20所述的电子系统,其中,所述卡主体包括限定在其中的凹槽,其中,所述半导体封装设置在所述凹槽内。
22.根据权利要求20所述的电子系统,其中,所述卡主体包括集成电路卡。
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KR1020070017537A KR100891330B1 (ko) | 2007-02-21 | 2007-02-21 | 반도체 패키지 장치와, 반도체 패키지의 제조방법과,반도체 패키지 장치를 갖는 카드 장치 및 반도체 패키지장치를 갖는 카드 장치의 제조 방법 |
US11/959,276 US7728422B2 (en) | 2007-02-21 | 2007-12-18 | Semiconductor package, integrated circuit cards incorporating the semiconductor package, and method of manufacturing the same |
US11/959,276 | 2007-12-18 |
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US20100210074A1 (en) | 2010-08-19 |
KR20080077836A (ko) | 2008-08-26 |
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CN101252115A (zh) | 2008-08-27 |
US8329507B2 (en) | 2012-12-11 |
JP5164599B2 (ja) | 2013-03-21 |
US20080197479A1 (en) | 2008-08-21 |
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