CN101241894A - 智能卡金属载带及其制造方法和包括该载带的封装模块 - Google Patents

智能卡金属载带及其制造方法和包括该载带的封装模块 Download PDF

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CN101241894A
CN101241894A CNA2007101519148A CN200710151914A CN101241894A CN 101241894 A CN101241894 A CN 101241894A CN A2007101519148 A CNA2007101519148 A CN A2007101519148A CN 200710151914 A CN200710151914 A CN 200710151914A CN 101241894 A CN101241894 A CN 101241894A
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smart card
belt
substrate
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黄玉财
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Samsung Semiconductor China R&D Co Ltd
Samsung Electronics Co Ltd
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Samsung Semiconductor China R&D Co Ltd
Samsung Electronics Co Ltd
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Priority to CNA2007101519148A priority Critical patent/CN101241894A/zh
Priority to KR1020080073046A priority patent/KR101005266B1/ko
Publication of CN101241894A publication Critical patent/CN101241894A/zh
Priority to US12/212,575 priority patent/US7847380B2/en
Priority to CN2008102131327A priority patent/CN101431062B/zh
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K13/00Apparatus or processes specially adapted for manufacturing or adjusting assemblages of electric components
    • H05K13/02Feeding of components
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

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Abstract

本发明提供了一种智能卡金属载带及其制造方法和包括该载带的封装模块。该智能卡载带包括多个智能卡载带单元,每个智能卡载带单元包括:基板,由金属材料制成;焊盘,形成在基板的将要安装芯片的上表面上;镍层,形成在基板的下表面上和焊盘中;金层,形成在镍层上。

Description

智能卡金属载带及其制造方法和包括该载带的封装模块
技术领域
本发明涉及一种智能卡载带及其制造方法和包括该智能卡载带的封装模块,更具体地讲,本发明涉及一种全金属的智能卡载带及其制造方法和包括该全金属的智能卡载带的封装模块。
背景技术
目前智能卡封装所采用的载带大部分是有机基板。然而,有机基板的制造工艺需要涂胶、覆盖铜箔压合、蚀刻、电镀镍金等多个工艺步骤,其工艺复杂,并且有机载带的成本较高,从而导致封装成本高。目前,智能卡载带的生产成本超过封装材料总成本的50%。因此,为了进一步降低智能卡封装的成本,需要开发一种低成本的载带。
发明内容
本发明的目的在于提供一种制造工艺简单且成本低的智能卡载带及其制造方法和包括该智能卡载带的智能卡封装模块。
根据本发明的一方面,提供了一种智能卡载带,该智能卡载带包括多个智能卡载带单元,每个智能卡载带单元包括:基板,由金属材料制成;焊盘,形成在基板的将要安装芯片的上表面上;镍层,形成在基板的下表面上和焊盘中;金层,形成在镍层上。
优选地,所述基板由铜或合金制成。
优选地,每个智能卡载带单元通过金属连接区域与整个智能卡载带连接。
优选地,所述金属连接区域为邮票孔形状。
根据本发明的另一方面,提供了一种智能卡载带的制造方法,所述方法包括以下步骤:对基板进行冲压,形成对位孔,其中,所述基板由金属材料制成;通过蚀刻方法形成智能卡接触点区域间的隔离;通过半蚀刻方法在基板的将安装芯片的表面上形成焊盘;在基板的下表面上和焊盘中电镀镍,形成镍层;在镍层上电镀金,形成金层。
优选地,所述基板由铜或者合金制成。
根据本发明的又一方面,提供了一种包括智能卡载带的封装模块,其中,所述智能卡载带包括多个智能卡载带单元,每个智能卡载带单元包括:基板,由金属材料制成;焊盘,形成在基板的将要安装芯片的上表面上;镍层,形成在基板的下表面上和焊盘中;金层,形成在镍层上。
优选地,所述基板由铜或者合金制成。
优选地,每个智能卡载带单元通过金属连接区域与整个智能卡载带连接。
优选地,所述金属连接区域为邮票孔形状。
附图说明
下文中,将通过参照附图来详细描述本发明的示例性实施例,本发明的这些和/或其他方面及优点将会变得清楚和更易于理解,在附图中:
图1是示出根据本发明示例性实施例的智能卡金属载带的示意图;
图2是示出根据本发明示例性实施例的智能卡金属载带单元的结构示意图;
图3是沿着图2中的线A-A’截取的智能卡金属载带单元的剖视图;
图4示出了根据本发明示例性实施例的智能卡金属载带的制造工艺;
图5是根据本发明示例性实施例的封装的结构示意图;
图6是根据本发明示例性实施例的金属载带智能卡模块的剖视图;
图7是根据本发明示例性实施例的塑封胶后进行单个器件电气性能隔离的结构示意图。
具体实施方式
下文中,将参照附图来更充分地描述本发明,在附图中示出了本发明的示例性实施例。然而,本发明可以以许多不同的方式来实施,而不应该被理解为限于这里阐述的实施例。相反,提供这些实施例,使得该公开将是彻底和完全的,并将本发明的原理充分传达给本领域技术人员。在附图中,为了清晰起见,可以夸大层和区域的尺寸和相对尺寸。
在附图中,相同的标号始终表示相同的元件。以下,将参照附图来详细描述本发明的示例性实施例。
图1是示出根据本发明示例性实施例的智能卡金属载带的示意图,图2是示出根据本发明示例性实施例的智能卡金属载带单元的结构示意图。在图1和图2中,除了图中的白色区域外,其它区域均为金属区域,并且在一部分金属上电镀了镍金。从图1和图2中可以看出,智能卡金属载带包括多个智能卡金属载带单元,每个智能卡金属载带单元通过连接区域与整个载带连接,并且每个智能卡载带单元通过连接区域实现力学支撑,其中,连接区域为邮票孔设计并且连接区域由金属材料形成。通过蚀刻或者冲压工艺,智能卡金属载带单元的接触点区域被隔离成几个独立的区域,但是上述接触点区域通过连接区域与整个载带连接。
图3是沿着图2中的线A-A’截取的智能卡金属载带单元的剖视图。如图3的剖视图所示,智能卡金属载带单元包括:基板1,由金属材料制成,优选地,由铜或合金制成;焊盘3,形成在基板1的将要安装半导体芯片的上表面上;镍层2,形成在基板1的下表面上和焊盘3中,通过电镀金属镍(Ni)形成;金层4,形成在基板1的下表面上的镍层2上和焊盘3中的镍层2上,通过电镀金属金(Au)形成。与现有技术中采用有机材料作为基板不同,根据本发明示例性实施例的载带为金属材料,例如,铜或合金。
图4示出了根据本发明示例性实施例的智能卡金属载带的制造工艺。如图4中所示,首先,对基板1进行冲压,形成对位孔,本发明中形成对位孔的方法与现有技术中形成对位孔的方法相同,对此不作详细描述,其中,基板1由金属制成,优选地,由铜或合金制成。接着,通过蚀刻方法形成智能卡接触点区域间的隔离,金属载带单元的接触点区域被隔离成几个独立的区域,并通过邮票孔设计的金属连接区域实现与整个载带的连接和力学支撑。随后,通过半蚀刻方法在基板1的将安装半导体芯片的表面上形成焊盘3;最后,在基板1的下表面上和焊盘3中电镀镍,形成镍层2,并且在镍层2上电镀金,形成金层4。
图5是根据本发明示例性实施例的封装的结构示意图。通过塑封胶,对芯片和金线提供保护。本发明中所采用的塑封材料和塑封工艺与本领域技术人员通常使用的塑封材料和塑封工艺相同。因此,将省略对塑封材料和塑封工艺的进一步详细地解释。
图6是根据本发明示例性实施例的金属载带智能卡模块的剖视图。除了使用金属载带代替了传统的有机载带之外,图6中的封装结构与传统的智能卡模块类似。另外,为了实现良好的机械性能并提供稳定的力学支撑,使用塑封胶代替了UV胶。
图7是根据本发明示例性实施例的塑封胶后进行单个器件电气性能隔离的结构示意图。经过冲压,实现接触区域的电气性能隔离,可以进行电气性能测试。隔离开的区域由塑封胶提供力学支撑,而单个封装好的模块仍然有三处连接区域,与整个载带连接。
本发明通过用一层金属材料代替现有技术中的有机基板作为智能卡载带,减少了智能卡载带所需的工艺步骤,并降低了智能卡载带的生产成本,从而降低了智能卡载带封装的生产成本。
尽管已经结合示例性实施例示出和描述了本发明,但是本领域的技术人员应该清楚,在不脱离由权利要求限定的本发明的精神和范围的情况下,可以做出修改和变换。

Claims (10)

1、一种智能卡载带,包括多个智能卡载带单元,每个智能卡载带单元包括:
基板,由金属材料制成;
焊盘,形成在基板的将要安装芯片的上表面上;
镍层,形成在基板的下表面上和焊盘中;
金层,形成在镍层上。
2、根据权利要求1所述的智能卡载带,其中,所述基板由铜或合金制成。
3、根据权利要求1所述的智能卡载带,其中,每个智能卡载带单元通过金属连接区域与整个智能卡载带连接。
4、根据权利要求3所述的智能卡载带,其中,所述金属连接区域为邮票孔形状。
5、一种智能卡载带的制造方法,所述方法包括以下步骤:
对基板进行冲压,形成对位孔,其中,所述基板由金属材料制成;
通过蚀刻方法形成智能卡接触点区域间的隔离;
通过半蚀刻方法在基板的将安装芯片的表面上形成焊盘;
在基板的下表面上和焊盘中电镀镍,形成镍层;
在镍层上电镀金,形成金层。
6、根据权利要求5所述的制造方法,其中,所述基板由铜或者合金制成。
7、一种包括智能卡载带的封装模块,其中,所述智能卡载带包括多个智能卡载带单元,每个智能卡载带单元包括:
基板,由金属材料制成;
焊盘,形成在基板的将要安装芯片的上表面上;
镍层,形成在基板的下表面上和焊盘中;
金层,形成在镍层上。
8、根据权利要求7所述的封装模块,其中,所述基板由铜或者合金制成。
9、根据权利要求7所述的封装模块,其中,每个智能卡载带单元通过金属连接区域与整个智能卡载带连接。
10、根据权利要求9所述的封装模块,其中,所述金属连接区域为邮票孔形状。
CNA2007101519148A 2007-09-20 2007-09-20 智能卡金属载带及其制造方法和包括该载带的封装模块 Pending CN101241894A (zh)

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CNA2007101519148A CN101241894A (zh) 2007-09-20 2007-09-20 智能卡金属载带及其制造方法和包括该载带的封装模块
KR1020080073046A KR101005266B1 (ko) 2007-09-20 2008-07-25 스마트 카드용 테이프 기판, 반도체 모듈 및 그 제조 방법,및 스마트 카드
US12/212,575 US7847380B2 (en) 2007-09-20 2008-09-17 Tape substrate and semiconductor module for smart card, method of fabricating the same, and smart card
CN2008102131327A CN101431062B (zh) 2007-09-20 2008-09-18 智能卡用载带基板和智能卡用半导体模块

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