CN101211794A - 封装半导体元件方法、制作引线框架方法及半导体封装产品 - Google Patents

封装半导体元件方法、制作引线框架方法及半导体封装产品 Download PDF

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CN101211794A
CN101211794A CNA2007103011633A CN200710301163A CN101211794A CN 101211794 A CN101211794 A CN 101211794A CN A2007103011633 A CNA2007103011633 A CN A2007103011633A CN 200710301163 A CN200710301163 A CN 200710301163A CN 101211794 A CN101211794 A CN 101211794A
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semiconductor element
less important
chip base
partitioned portion
important part
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陈南璋
林泓均
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MediaTek Inc
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MediaTek Inc
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Abstract

一种封装半导体元件方法、制作引线框架方法及半导体封装产品，该封装半导体元件方法包含：将半导体元件安置于引线框架的芯片垫座的主要部分之上，该芯片垫座另有一个以上的次要部分与一个以上的分隔部分，该次要部分与该主要部分透过该分隔部分连接；将半导体元件的一组信号线分别连接到该引线框架的多个导脚；对该半导体元件与该引线框架进行模包装，其中该芯片垫座的底面曝露在模包装外；以及从芯片垫座的底面对该分隔部分进行分离蚀刻，使该主要部分与该次要部分电性分离。

Description

封装半导体元件方法、制作引线框架方法及半导体封装产品
技术领域
本发明有关于一种用于半导体元件的引线框架结构，特别是有关于一种具有多重外露式置晶座(exposed die pad)的引线框架封装构件及其制法。
背景技术
如本领域相关人员所知，为了避免外在环境因素的干扰与破坏，半导体晶片通常是以塑胶材料包覆成一封装构件。封装构件亦提供半导体晶片与印刷电路板之间的电路连结。这样的集成电路封装构件通常包括一金属引线框架、一设置在与金属引线框架一体成型的置晶座上的半导体晶片，以及电连结半导体晶片上的接合垫与引线框架各个导脚的金线。半导体晶片与引线框架最终会被模封材料包覆住。
目前的封装产业趋势是让封装构件的体积更小但具有更多功能。由于集成电路晶片的功能越来越复杂，使得引线框架封装构件的外部接脚数也增加许多。接脚数增加使每个晶片的封装成本升高。为了避免接脚数的增加造成封装构件体积变大，过去的作法是减少导脚间距。然而，导脚彼此太接近却容易产生互感(mutual inductance)及互电容(mutual capacitance)，这也是引线框架封装往往被认为不适合应用在高速半导体晶片的原因。前述的互感及互电容很可能会干扰到高速半导体晶片所传输的高速信号。
考量到这样的不利因素，许多的行动通讯装置，如行动电路，以及配备有可传输高频信号的个人通讯装置中的半导体晶片都是采用球型格栅阵列(ball grid array)封装，而不采用引线框架封装方式。若硬是将这样的高速半导体晶片以引线框架封装，则信号损失或者如AC杂讯等将会明显影响到晶片操作效能，而变成恼人的问题。
前述球型格栅阵列封装的缺点在于其成本较高且产品交期较长。此外，发展射频系统单晶片的挑战之一在于难以降低射频及模拟电路的功率消耗以及缩小无源元件及模拟电晶体的尺寸。由此可知，该技术领域仍需要一种改良的引线框架结构以及引线框架封装结构，其具有低成本的优点并且需能够应用在高速半导体晶片上，当传送高频信号时不会有明显的信号损失或杂讯。
发明内容
本发明的主要目的在提供一种具有多重外露式置晶座的引线框架封装构件及其制法，以解决已知技术的问题。
本发明第一具体实施例为一种封装半导体元件方法，包含：将半导体元件安置于引线框架的芯片垫座的主要部分之上，该芯片垫座另有一个以上的次要部分与一个以上的分隔部分，该次要部分与该主要部分透过该分隔部分连接；将半导体元件的一组信号线分别连接到该引线框架的多个导脚；对该半导体元件与该引线框架进行模包装，其中该芯片垫座的底面曝露在模包装外；以及从芯片垫座的底面对该分隔部分进行分离蚀刻，使该主要部分与该次要部分电性分离。
本发明第二具体实施例为一种制作引线框架的方法，该引线框架用于封装半导体元件，该方法包含：在金属片上制作一导线框主要图案；依据该导线框主要图案制作初步导线框；用遮罩在初步导线框上的芯片垫座区域定义主要部分，至少一次要部分，以及至少一分隔部分；以及对该分隔部分进行初步蚀刻，是该分隔部分的厚度比该主要部分与该次要部分的厚度薄。
本发明第三具体实施例为半导体封装产品，该半导体封装产品包含：半导体元件；芯片垫座，具有主要部分以及一个以上的次要部分，主要部分承载半导体元件；多个导脚，电连接半导体元件的多个信号线；以及封装模，覆盖半导体元件、芯片垫座以及部分的导脚，并曝露该芯片垫座的次要部分的底面，其中，该半导体元件有两个以上的电信号连接到次要部分，并透过该次要部分曝露的底面，将这些电信号连接到电路板的电信号接点。
透过本发明特殊的引线框架设计，利用新的导线脚设计的封装方法，使得封装的产品因为节省导脚、缩短信号路径等，而产生更好的电子特性，更小的封装体积或在同样的封装体积容纳更多的信号接点。
为让本发明的上述目的、特征、和优点能更明显易懂，下文特举较佳实施方式，并配合所附图式，作详细说明如下。然而如下的较佳实施方式与图式仅供参考与说明用，并非用来对本发明加以限制者。
附图说明
图1例示一个引线框架封装10的上方示意图。
图2为依据本发明实施例的引线框架封装的上方示意图。
图3例示引线框架封装的侧视剖面示意图。
图4是分离垫区14b与环绕分离垫区14b的孔洞40b的剖面示意图。
图5例示孔洞的设计上的变形。
图6则例示另一种孔洞的变形。
图7例示依据本发明的芯片垫座与作为范例的电感区。
图8例示制作依据本发明的具有多曝露垫区的引线框架封装的流程图。
图9为使用本发明两阶段蚀刻组装引线框架过程的剖面示意图。
图10为使用本发明两阶段蚀刻组装引线框架过程的剖面示意图。
图11为使用本发明两阶段蚀刻组装引线框架过程的剖面示意图。
图12为使用本发明两阶段蚀刻组装引线框架过程的剖面示意图。
图13为使用本发明两阶段蚀刻组装引线框架过程的剖面示意图。
图14例示具有第4图的倒T形开孔的引线框架封装的组装示意图。
图15例示具有第4图的倒T形开孔的引线框架封装的组装示意图。
图16例示具有第4图的倒T形开孔的引线框架封装的组装示意图。
图17例示具有第4图的倒T形开孔的引线框架封装的组装示意图。
图18例示SiP引线框架封装的上方示意图。
图19说明本发明用在轻点晶片(flip-chip)封装引线框架封装。
图20说明本发明用在轻点晶片(flip-chip)封装引线框架封装。
具体实施方式
以下所说明的引线框架(leadframe)封装(packaging)结构，可用于但不限于不显目四平包装(Low-Profile Quad Flat Pack，LQFP)的封装、薄四平包装(Thin Quad Flat Pack，TQFP)封装、四平非导脚(Quad Flat Non-leaded，QFN)封装、DFN封装、多区域QFN(multi-zone QFN)封装，以及多芯片(multi-die)封装，以及轻点晶片封装(flip-chip packaging)。
相对于现有技术，透过省下或释放原本是用来连接半导体芯片的接地垫(ground pad)、电源垫(power pad)或是其他类的信号垫的导脚(lead)，本发明能更进一步提升引线框架结构封装的极限。此外，透过使用芯片垫座(die pad)上的分离接地系统，本发明也可用来改善集成电路(integrated circuit)封装产品的电子效能。
图1例示一个引线框架封装10的上方示意图。如第1图所示，引线框架封装10包括作为半导体元件(semiconductor device)范例的半导体芯片(semiconductor die)12，安装于芯片垫座(die pad)14上。多个焊接垫(bondingpad)13安置于半导体芯片12的上表面。每一个焊接垫13透过焊接线18电连接导对应的导脚(lead)13。
通常被称作输出输入垫(input/output pad)的焊接垫13一般会包括电源垫(power pad)13a～13f、接地垫(ground pad)13g及13f，以及其他的信号垫。电源垫13a～13f透过作为信号线的焊接线(bond wire)18焊接到对应的导脚16a～16f。接地垫13g与13h透过焊接线26焊接到芯片垫座26。
最后会被安装到印刷电路板(Printed Circuit Board)的插座(socket)的导脚16，沿着芯片14的四边安置。半导体芯片12、芯片垫座14、导脚16的内侧以及焊接线18透过模包装材料(molding compound)20给封起来。
在这个例子中，芯片垫座14是一个单一、矩形的平面区域，具有四个从芯片垫座往外延伸的细长支撑杆(supporting bar)15。但是，请注意，其他形状的芯片垫座，例如没有四个细长支撑杆的芯片垫座，其实也可以使用一下介绍的本发明概念。芯片垫座14的底面刻意曝露出封装主体(package body)，以散放半导体芯片12所产生的热量，这称作曝露式芯片垫座(简称e-pad)设计。一般来说，芯片14曝露出来的底面点连接导印刷电路板的接地层。
然而，对于一些能够传输高频信号具有模拟/数字混合电路的单晶片(SoC)应用来说，这样的设计可能会让数字电路的接地杂讯影响到模拟电路的信号通道。
请参照图2与图3。图2为依据本发明实施例的引线框架封装10a的上方示意图。图3例示引线框架封装10a的侧视剖面示意图，其中相同的元件符号代表相同的元件、区域或是层。
如图2与图3所示，引线框架封装10a包含半导体芯片12，其安置在铜或C725、A192等铜合金的芯片垫座上。多个焊接垫安置在半导体芯片12的上方表面。有些焊接垫13透过焊接线18连接到对应的导脚16。
焊接垫13包含电源垫13a～13f、数字接地垫13g～13h、模拟接地垫13i～13j，以及其他的信号垫。本发明的其中一个特征就是电源垫13a～13f透过比较短的焊接线焊28接到一个分离垫区(separate pad segment)14，而不是接到导脚16a～16f。因此，原先需要保留用来连接电源垫13a～13f的导脚16a～16f就可以省下来用在别的地方，例如，用来连接半导体芯片12的其他信号垫，或是干脆把这些导脚省略，以降低引线框架封装10a的尺寸以及成本。
从一个角度来看，引线框架封装10的效能呈现在透过省下原本要用来连接电源垫13a～13f的导脚16a～16f。这是由于可使用导脚数目(lead pitch)增加，也由于芯片于印刷电路板之间的信号路径减低。
从另一个角度看，本发明的发明特征包括，由芯片垫座14分离出来的分离垫14a，并不直接于芯片垫座接触，而是完全与芯片垫座保持分离关系。此外，分离垫区14a也不会直接与任何导脚16接触，或是由任何导脚16加以支撑。因此，分离垫区14不会占用任何的导脚16。与芯片垫座14相似，分离垫区14a的底面也曝露在封装主题之外，使得分离垫区14a可以直接与印刷电路板上的电源层接触，而将电源信号传给半导体芯片12。
本发明的另一特征是半导体芯片12的数字接地垫13g～13h，透过焊接线26接到芯片垫座14，并且半导体芯片12的模拟接地13i与13j透过焊接线36焊接到另一个分离垫区14b。
根据本发明，芯片垫座14连接到数字接地信号，而分离垫区14b则连接到模拟接地信号。芯片垫座上的这种分离接地系统，避免了数字电路的杂讯干扰模拟信号路径。此外，模拟接地垫13i与13j接地，并且透过焊接线焊接到分离垫区14b，表示相对于比透过导脚16更短的信号传输路径。
相似的，分离垫区14b从芯片垫座14分离出来，并不直接与芯片垫座14接触，并且实际上是与芯片垫座14保持分离状态。
如图3所示，与分离垫区14a相似，分离垫区14b并不直接与任何导脚16接触。进一步来说，分离垫区14b并不需要来自导脚16或是芯片垫座14的结构上支撑。在分离垫区14a与芯片垫座14间的孔洞40a，以及在分离垫区14b与芯片垫座14间的孔洞40b都是用环氧树脂等模包装材料20来加以填充。
请注意在芯片垫座14之上，有三种不同的部分，也就是主要部分(primaryportion)，至少一个次要部分(secondary portion)，以及至少一个分隔部分(separating portion)，其中分隔部分用来分隔主要部分与次要部分。在图2中，分离垫区14a与14b可视为是两个次要部分的范例。作为分隔部分范例的孔洞40a与40b，则用来将次要部分的分离垫区14a与14b，与芯片垫座上的主要部分进行分隔。
分隔垫区14b的底面曝露在封装主体之外，使得分离垫区14b可以与印刷电路板上的模拟接地(AGND)层进行连接。芯片垫座14的曝露底面则与数字接地(DGND)层进行连接。如前所述，这种芯片垫座上的分离接地系统避免数字电路的杂讯干扰到模拟信号路径。
图4是分离垫区14b与环绕分离垫区14b的孔洞40b的剖面示意图。如图4所示，一个贵金属层52a，例如金、银、镍金或是其组合，安置在芯片垫座14与分离垫区14b的模上方(芯片方)。芯片垫座14与分离垫区14b的曝露底面方(印刷电路板方)，则都堵上一层贵金属52b。无源元件60可安置在芯片垫座14与分离垫区14间，跨过孔洞40b，以作为解除连接(decoupling)，防止静电(ESD，Electrostatic Discharge)或其他特定的电路设计，例如滤波器或匹配器(matching)等用途。
本发明的另一个特点是孔洞40b(或是孔洞40a)的部分区域还可以设计成具有倒T形状截面的结构。环氧树脂模包装材料20填入倒T形状截面的孔洞，可进一步增加封装的稳定性，并避免引线框架主体的变形。由于倒T形状的孔洞40b的设计，射入的模包装材料20可以牢牢抓住分离垫区40b，让其保持在固定位置。
图5例示另一种孔洞40b(或40a)的另一种设计上的变形。如图5所示，沙漏形状的孔洞40b在模上方或说芯片方具有梯状上部部分。图6则例示另一种孔洞40b(或40a)的变形。如图6所示，分离垫区14b具有锯齿形状的边缘70。这样的设计可以增加分离垫区14b与填入孔洞40b中的模包装材料间的附着力。
图7例示依据本发明的芯片垫座14与作为范例的电感区82与84。弯曲状的电感区82与螺旋状的电感区84，可用来作为垫座上的电感，可整合在形成引线框架的芯片垫座14时一起制作。弯曲电感区82与螺旋电感区84并不直接与芯片垫座14接触。进一步来说，电感区82与84并不需要任何来自导脚16或是芯片垫座14的支撑。
环氧树脂模包装材料填入位于弯曲电感区82与芯片垫座14间的孔洞82a，也填入位于弯曲电感区84与芯片垫座14间的孔洞84a。孔洞82a与84a也可以有部分区域有图4所示的倒T形状的截面。
由于电感区82与84并没有直接与导脚16连接，电感具有高Q参数，降低了寄生电容并降低了响应频率。
图8例示制作依据本发明的具有多曝露垫区的引线框架封装的流程图。从一个角度看，本发明的引线框架封装可使用两阶段蚀刻(etching)方法来实行。也就是说，芯片垫座首先经过第一次半蚀刻(标号102所示步骤)，也称作初次蚀刻，这个属于阶段100的步骤可以在引线框架制造工厂完成。此外，第二次的半蚀刻(标号202所示步骤)，也称为分离蚀刻，可以在阶段200，由后续的组装工厂在模包装程序后进行。在图8中，除了“背面加图案(Back-side Mark)”，“移除背面图案”，以及“模包装”(molding)后的“蚀刻”，其它步骤可直接使用传统的传统的引线框架封装制法来进行。由于需要调整改变的制法并不多，使得这个实施例得以快速导入现有制造工艺，也是本发明的优点之一。“背后加图案”是在底面要镀上Sn保护层前，先对将来要移除的分隔部分上遮罩。在镀上Sn或是其他贵金属等保护层时，便不会把这些贵金属镀在接下来准备要移除的分隔部分。接着，便是移除这些覆盖在分隔部分上的遮罩，并对这些区域进行蚀刻，移除剩下的分隔部分的厚度。第二次的半蚀刻将分离垫区14a与14b从芯片垫座的主要区域进行分离的动作。
请参考图9到图13，并且回头参照图8。图9到图13为使用本发明两阶段蚀刻组装引线框架过程的剖面示意图。请注意这边的元件或是层的厚度为了说明方便，并未用实际的比例绘制。如图9所示，在蚀刻或是冲压(stamping)以及镀膜(plating)，可获得引线框架300。引线框架300包括单一芯片垫座314以及周边导脚316。芯片垫座314的两面都镀(coat)有蚀刻遮罩322，由贵金属、金属合金或是光阻(photoresist)构成。蚀刻遮罩322具有孔洞开口324，其定义分离的垫座样态(pad pattern)350，以转换为后面所述的芯片垫座314。
如图10所示，第一次半蚀刻程序执行时，可透过蚀刻遮罩322，在芯片垫座的芯片方透过孔洞开口蚀刻预定厚度。如前所述，第一次半蚀刻的程序可在引线框架制作工厂完成。接着，经过半蚀刻的引线框架300运送到组装工厂。
如图11所示，在组装工厂，半导体芯片312被安置到芯片垫座314之上。焊接线318与336用来提供焊接垫313与导脚316，以及半导体芯片312上的焊接垫313与芯片垫座314之间的电性连接。
如图12所示，在焊接线后，如图11的整个组装可使用热塑材料(thermosetting compound)320加以包装。这个材料可以是低温硬化树脂(low-temperature hardening resin)。接着，模封装可以进行固化(curing)程序。如特殊指定，底面方或说印刷电路板方的包装封装则有曝露区域。
如图13所示，在包装后，包装的封装产品曝露出来的印刷电路板方经过第二次的蚀刻，把剩下来的芯片垫座的厚度，透过蚀刻遮罩322的孔洞开口324加以移除，因而形成了分离垫区314a，使其与芯片垫座314分离。分离垫区314a与芯片垫座314完全分离，而且没有与芯片垫座314有直接的接触。
图14到图17例示具有图4的倒T形开孔的引线框架封装的组装示意图。如图14所示，在蚀刻或是冲压以及电镀后，获得引线框架300。引线框架300包括单一芯片垫座314与周边导脚316。芯片垫座的两方都镀上蚀刻遮罩322。在曝露的底面，蚀刻遮罩322包括支撑杆(supporting bar)样态，以暂时连接分离垫区314a与芯片垫座314。蚀刻遮罩322可用贵金属、金属合金或是光阻来制作。蚀刻遮罩322具有孔洞开口324，其定义了分离垫区350，可以后来被转换成下面描述的芯片垫座314。
接下来，在图15中，第一次蚀刻(包括从芯片方向的半蚀刻以及从芯片垫座底面方向的半蚀刻)在芯片垫座的两个方向进行，从蚀刻遮罩322的孔洞开口，移除芯片垫座的整个厚度，以形成倒T形孔洞截面，以及分离垫区314a。在这个阶段，上述的支撑杆仍然连接在分离垫区314a与芯片垫座314之间，以避免分离垫区314从芯片垫座314掉落。这个第一次的蚀刻可以在引线框架工厂进行。引线框架接着被送到组装工厂。
如图16所示，在组装工厂内，半导体芯片312被安置在芯片垫座314之上。焊接线318与336提供半导体芯片的焊接垫313与导脚316之间，以及半导体芯片的焊接垫313与分离垫区314a的电性连接。
如图17所示，在焊接线后，图16所示的组合整个被热塑材料320模包装起来。这个材料可以是低温硬化树脂。接着，模封装可以进行硬化(curing)程序。如上所述，模封装的底面或说印刷电路板面被曝露出来。
根据本发明另一实施例，引线框架封装为多晶片模组(MCM，multi-chipmodule)或是封装内系统(SiP，System-in-Package)，包含了多个半导体芯片以及无源元件在单一的封装中。图18例示SiP引线框架封装的上方示意图。在图18中，SiP引线框架封装包含第一半导体芯片412，安置在主要芯片垫座414上。主要芯片垫座414具有四个细长的支撑杆415，从主要芯片垫座414的四个方向向外延伸。芯片垫座414的底面曝露在封装主体外，以将半导体芯片412所产生的热量散出。主要芯片垫座414的曝露底面可以电连接到印刷电路板的接地层。
第一半导体芯片412的上方有多个焊接垫413，透过焊接线418电连接到对应的导脚416。SiP的引线框架封装400更包括第二芯片垫座514。第二半导体芯片512安置在第二芯片垫座514上。第二芯片垫座514与主要芯片垫座414分离，而且没有直接与主要芯片垫座414接触。半导体芯片512的一部分焊接垫513透过焊接线518电连接到对应的导脚416。在这个实施例中，第一半导体芯片412为数字晶片，而第二半导体芯片为模拟晶片。
相似的，第二芯片垫座514的底面曝露在封装之外，以对半导体芯片512产生的热进行排除。第二芯片垫座514可直接与印刷电路板的模拟接地端等接地层电连接，以避免数字电路的杂讯干扰模拟信号路径。此外，分离垫区614也可以有与图3到图6所示的相同分离垫区14b，设计在主要芯片垫座414上。
分离垫区614的功能可提供高速信号到半导体芯片512，以建立较短的电路径，并且已达成较少的信号丢失。分离垫区614可与主要垫区414分离，而且不需要任何来自主要芯片垫座414或是导脚416的结构支撑。
另一种作法是，将无源元件安置跨接在主要芯片垫座414与第二芯片垫座514之间的孔洞540上。有些焊接垫413透过焊接线618，连接到第二半导体芯片512的焊接垫513。有些第二半导体芯片512的焊接垫513，则透过焊接线718连接到分离垫区614。整个组装用模包装材料420包装起来。
图19与图20说明本发明用在轻点晶片(flip-chip)封装引线框架封装900。图19是轻点晶片引线框架封装900的上方平面示意图，图20则是轻点晶片引线框架封装900的剖面示意图。如图19与图20所示，轻点晶片引线框架封装900包含芯片垫座914，具有四个细长支撑杆915，从芯片垫座914的主要区域四个角落往外延伸。芯片垫座914的曝露底面则电连接到印刷电路半的数字接地(DGND)层。跳点(Bump)或焊接球(solder ball)则配置在另一方，也就是芯片方，其与芯片垫座914的曝露方相反，用以电焊接主要芯片垫座与芯片垫座上的轻点晶片。
轻点晶片引线框架封装900更包括多个分离垫区914a～914d，每个连接到一个特殊的信号。举例来说，分离垫区914a连接到VDD1的电源信号，分离垫区914b连接到VDD2的电源信号，分离垫区914c连接到VDD3的电源信号，分离垫区914d则连接到模拟接地信号(AGND)。跳点(Bump)924a～924d则分别安置在分离垫区914a～914d，提供分离垫区与轻点晶片912之间的点焊接。
分离垫区914a～914d与芯片垫座914保持分离，并且如前所述，与芯片垫座没有直接接触。进一步，分离垫区914a～914d与导脚916也都保持分离。孔洞940a～940d可以有图4所示的倒T形横截面。分离垫区914a～914d的底面则曝露出来。
导脚916沿着芯片垫座914的四周配置。跳点(Bump)916a安置给对应的导脚916，以进行导脚916与轻点晶片912间的电焊接。除了底面外，轻点晶片912、芯片垫座914，分离垫区914a～914d，以及导脚916包装在模材料920中。模包装材料920填入孔洞940a～940d，使得分离垫区914a～914d可以更牢固的保持原来的位置。
以上所述仅为本发明的较佳实施例，凡依本发明申请专利范围所做的均等变化与修饰，皆应属本发明的涵盖范围。

Claims (25)

1.一种封装半导体元件方法，该封装半导体元件方法包含：
将半导体元件安置于引线框架的芯片垫座的主要部分之上，该芯片垫座另有一个以上的次要部分与一个以上的分隔部分，该次要部分与该主要部分透过该分隔部分连接；
将半导体元件的一组信号线分别连接到该引线框架的多个导脚；
对该半导体元件与该引线框架进行模包装，其中该芯片垫座的底面曝露在模包装外；以及
从芯片垫座的底面对该分隔部分进行分离蚀刻，使该主要部分与该次要部分电性分离。
2.如权利要求1所述的封装半导体元件方法，该分隔部分的厚度比该主要部分与该次要部分的厚度为薄。
3.如权利要求2所述的封装半导体元件方法，该封装半导体元件方法更包含对该芯片垫座进行初步蚀刻，以使得该分隔部分的厚度比该主要部分与该次要部分的厚度为薄。
4.如权利要求3所述的封装半导体元件方法，其中，藉由该初次蚀刻在该分隔部分的一局部区域蚀刻出一个倒T形孔，该T形孔于模包装时填入模包装材料，以增加该芯片垫座的稳定性。
5.如权利要求4所述的封装半导体元件方法，其中，该芯片垫座的曝露面于该T形孔处，附贴无源元件。
6.如权利要求3所述的封装半导体元件方法，其中，藉由该初次蚀刻在该分隔部分的一局部区域蚀刻出一个沙漏形状孔，该沙漏形状孔于模包装时填入模包装材料，以增加该芯片垫座的稳定性。
7.如权利要求1所述的封装半导体元件方法，其中，该分隔部分的一局部区域呈现锯齿状，以增加该芯片垫座的稳定性。
8.如权利要求1所述的封装半导体元件方法，该封装半导体元件方法更包含将该半导体元件的另一组信号线连接到该次要部分，以透过该次要部分曝露于该模包装的区域连接到电路板上的信号接点。
9.如权利要求6所述的封装半导体元件方法，其中，超过两个以上的电信号连接到同一个该次要部分。
10.如权利要求6所述的封装半导体元件方法，其中，该次要部分用来所连接的电信号为高频信号。
11.如权利要求1所述的封装半导体元件方法，该封装半导体元件方法更包含，将另一半导体元件安置于该次要部分上。
12.如权利要求1所述的封装半导体元件方法，该次要部分形成晶片外电感元件。
13.如权利要求1所述的封装半导体元件方法，其中，有两个次要部分提供两个接地接点。
14.如权利要求1所述的封装半导体元件方法，其中，该封装半导体元件方法更包含将该半导体元件的模拟电路接地信号与数位的接地导接到不同个次要部分的接地点。
15.一种制作引线框架的方法，该引线框架用于封装半导体元件，该制作引线框架方法方法包含：
在金属片上制作一导线框主要图案；
依据该导线框主要图案制作初步导线框；
用遮罩在初步导线框上的芯片垫座区域定义主要部分，至少一次要部分，以及至少一分隔部分；以及
对该分隔部分进行初步蚀刻，是该分隔部分的厚度比该主要部分与该次要部分的厚度薄。
16.如权利要求15所述的制作引线框架的方法，其中，藉由该初次蚀刻在该分隔部分的一局部区域蚀刻出一个倒T形孔，该T形孔于模包装时填入模包装材料，以增加该芯片垫座的稳定性。
17.如权利要求15所述的制作引线框架的方法，藉由该初次蚀刻在该分隔部分的一局部区域蚀刻出一个沙漏形状，该沙漏形状区域于模包装时填入模包装材料，以增加该芯片垫座的稳定性。
18.如权利要求15所述的制作引线框架的方法，其中，该分隔部分的一局部区域呈现锯齿状，以增加该芯片垫座的稳定性。
19.一种半导体封装产品，其特征在于，该半导体封装产品包含：
半导体元件；
芯片垫座，具有主要部分以及一个以上的次要部分，主要部分承载半导体元件；
多个导脚，电连接半导体元件的多个信号线；以及
封装模，覆盖半导体元件、芯片垫座以及部分的导脚，并曝露该芯片垫座的次要部分的底面，其中，该半导体元件有两个以上的电信号连接到次要部分，并透过该次要部分曝露的底面，将这些电信号连接到电路板的电信号接点。
20.如权利要求19所述的半导体封装产品，其特征在于，有两个次要部分提供两个接地接点。
21.如权利要求19所述的半导体封装产品，其特征在于，该半导体封装产品更包含将该半导体元件的模拟电路接地信号与数位的接地导接到不同个次要部分的接地点。
22.如权利要求19所述的半导体封装产品，其特征在于，该次要部分提供连接该半导体元件的高频信号。
23.如权利要求19所述的半导体封装产品，其特征在于，主要部分与该次要部分间由材料的分隔部分区隔，该分隔部分具有倒T形状。
24.如权利要求19所述的半导体封装产品，其特征在于，主要部分与该次要部分间由材料的分隔部分区隔，该分隔部分具有沙漏形状。
25.如权利要求19所述的半导体封装产品，其特征在于，该分隔部分的一局部区域呈现锯齿状，以增加该芯片垫座的稳定性。
CNA2007103011633A 2006-12-27 2007-12-26 封装半导体元件方法、制作引线框架方法及半导体封装产品 Pending CN101211794A (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103210487A (zh) * 2010-11-15 2013-07-17 夏普株式会社 半导体封装

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8133764B2 (en) * 2007-02-14 2012-03-13 Npx B.V. Embedded inductor and method of producing thereof
US8058720B2 (en) * 2008-11-19 2011-11-15 Mediatek Inc. Semiconductor package
US9177834B2 (en) 2014-02-19 2015-11-03 Freescale Semiconductor, Inc. Power bar design for lead frame-based packages

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03166756A (ja) * 1989-11-27 1991-07-18 Seiko Epson Corp 半導体集積回路用リードフレーム
JPH03166755A (ja) * 1989-11-27 1991-07-18 Seiko Epson Corp 半導体集積回路用リードフレーム
US6933594B2 (en) * 1998-06-10 2005-08-23 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation
US6989294B1 (en) * 1998-06-10 2006-01-24 Asat, Ltd. Leadless plastic chip carrier with etch back pad singulation
US7005326B1 (en) * 1998-06-24 2006-02-28 Amkor Technology, Inc. Method of making an integrated circuit package
US6238952B1 (en) * 2000-02-29 2001-05-29 Advanced Semiconductor Engineering, Inc. Low-pin-count chip package and manufacturing method thereof
US6483178B1 (en) * 2000-07-14 2002-11-19 Siliconware Precision Industries Co., Ltd. Semiconductor device package structure
SG120858A1 (en) * 2001-08-06 2006-04-26 Micron Technology Inc Quad flat no-lead (qfn) grid array package, methodof making and memory module and computer system including same
US6818973B1 (en) * 2002-09-09 2004-11-16 Amkor Technology, Inc. Exposed lead QFP package fabricated through the use of a partial saw process
TWI227051B (en) * 2004-04-09 2005-01-21 Airoha Tech Corp Exposed pad module integrated a passive device therein
TWI245392B (en) * 2004-06-29 2005-12-11 Advanced Semiconductor Eng Leadless semiconductor package and method for manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103210487A (zh) * 2010-11-15 2013-07-17 夏普株式会社 半导体封装
CN103210487B (zh) * 2010-11-15 2016-02-10 夏普株式会社 半导体封装

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