CN101416310B - 多管芯半导体封装 - Google Patents

多管芯半导体封装 Download PDF

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Publication number
CN101416310B
CN101416310B CN2004800049012A CN200480004901A CN101416310B CN 101416310 B CN101416310 B CN 101416310B CN 2004800049012 A CN2004800049012 A CN 2004800049012A CN 200480004901 A CN200480004901 A CN 200480004901A CN 101416310 B CN101416310 B CN 101416310B
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integrated circuit
electric interface
circuit lead
pad
contact
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CN101416310A (zh
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马克·A·格伯
达埃Y·洪
苏赫拉布·萨法伊
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NXP USA Inc
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Freescale Semiconductor Inc
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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

一种具有电互连框架(107)的多管芯半导体封装(101)。顶集成电路管芯(103)附着到框架的上接触面(109)的顶侧，底集成电路管芯(105)附着到框架的上接触面的底侧。顶管芯的管芯结合焊盘(113)电耦合(例如，线焊)到互连框架的下接触面(111)的焊盘。底集成电路管芯的管芯结合焊盘电耦合(例如，线焊)到框架的上接触面的结合焊盘。下接触面的结合焊盘作为封装的外部结合焊盘。框架可以包括内嵌结构(116)，每个内嵌结构都具有位于上接触面中的上部和位于下接触面中的下部。

Description

多管芯半导体封装
技术领域
本发明涉及半导体封装，特别涉及多管芯半导体封装。
背景技术
多管芯半导体封装包括多个集成电路(IC)管芯。对于一些封装，在封装中的一个管芯的操作会干扰封装中的另一个管芯的性能。例如，在具有包括内嵌存储器的数字集成电路的管芯和具有射频RF集成电路管芯的封装中，内嵌存储器会在具有RF集成电路的管芯附近产生热点。这些热点会干扰RF集成电路的电感的性能，由此降低RF集成电路的整体性能。
需要的是多管芯半导体封装的改进结构。
附图说明
通过参考附图，可以更好地理解本发明，并且使其许多目的、特征和优点对本领域技术人员更明显。
图1是根据本发明的多管芯半导体封装的一个实施例的部分侧剖面图。
图2是多管芯半导体封装的一个实施例的透视图，示出了根据本发明的顶集成电路管芯和电互连框架。
图3是根据本发明从其制得多管芯半导体封装的片材的一个实施例的部分底视图。
图4是根据本发明从其制得多管芯半导体封装的片材的一个实施例的部分顶视图。
图5是流程图，提出了制造根据本发明的多管芯半导体封装的阶段的一个实施例。
除非特别指出，否则在不同附图中使用的相同参考标记表示相同的项目。
具体实施方式
下述提出了实施本发明的详细说明。本说明意图阐明本发明，并且不应该看成是限制。
图1是根据本发明的多管芯半导体封装的侧剖面图。封装101包括集成电路(IC)管芯103和IC管芯105，它们密封在非导电密封材料104中。封装101包括互连框架107，用于在管芯103和105的集成电路与封装101外部的导电结构之间提供导电。在所示的实施例中，封装101是多管芯、部分阵列、无引线(no-lead)封装。
框架107包括上接触面109和下接触面111，其中上接触面109平行于下接触面111。在图1的实施例中，上接触面109通常位于平面110中，下接触面111通常位于平面112中。框架107包括多个导电结构，其在一个实施例中由铜制成。在一些实施例中，框架107的部分可以镀诸如例如镍、银、金或钯的第二金属。框架107包括多个焊盘(例如113)，其构成了下接触面111的部分。这些焊盘的每一个都作为接触点，用于将管芯103或105的信号或电源焊盘耦合到封装101附着到的器件的外部导电结构(例如，印刷电路板(未示出))。
管芯103附着到上接触面109的顶表面，管芯105附着到上接触面109的底表面。例如121的引线结合到位于管芯103的顶表面上的引线结合焊盘(例如129)并结合到下接触面111的焊盘(例如113)的顶表面123，以将管芯103的管芯结合焊盘电耦合到下接触面111的焊盘。
框架107包括内嵌结构(例如116)，每个内嵌结构包括位于上接触面109中的上部(例如118)和位于下接触面111中的下部(例如117)。管芯105附着到上接触面109的底表面。上部(例如118)作为用于结合引线(例如127)的结合焊盘，该结合引线被结合到位于管芯105的底表面上的管芯结合焊盘(例如131)。内嵌结构(例如116)的下部(例如117)作为封装结合焊盘，用于将管芯105的信号或电源管芯焊盘(例如131)耦合到封装101外部的导电结构。在所示的实施例中，管芯103的一些管芯结合焊盘经由引线(例如132)耦合到内嵌结构的上部(例如118)。
在一个实施例中，管芯103包括数字IC，诸如基带处理器或存储器。管芯105包括RF IC，诸如蜂窝电话的发射器或接收器。在其它实施例中，管芯105可以包括其它类型的模拟IC或可以包括数字IC。框架107提供管芯103和105之间的RF屏蔽。
如图1的实施例中所示，提供具有上和下接触面的电互连框架可以允许管芯位于框架的相对侧(例如，为了屏蔽目的)，并且还允许框架的部分作为两个管芯的外部的电源和信号焊盘。此外，利用上和下接触面可以降低多管芯封装的高度。此外，提供上和下接触面有助于降低封装的引线之间的交叉耦合(cross-coupling)，使得耦合到顶管芯的引线和耦合到底管芯的引线很少可能平行走向并且彼此紧邻。
封装101包括上接触面109的顶表面上的粘结剂流出控制环135，用于限制用来将管芯103附着到上接触面109的顶表面的粘结剂。封装101还包括第二粘结剂流出控制环137，用于限制用来将管芯105附着在上接触面109的底表面的粘结剂。在其它实施例中，通过使用一种管芯附着粘结剂膜或通过将管芯附着在附着到上接触面的另一类型插入结构，可以将管芯附着到上接触面109。
在一些实施例中，从管芯103的顶表面到管芯105的底表面的距离大于0.5mm，以便降低来自每个管芯的集成电路的干扰。将管芯放置在具有两个接触面的框架的相反侧可以增加顶管芯103和底管芯105的有效表面(在图1的实施例中，具有管芯结合焊盘的管芯的表面)之间的距离，而不显著增加封装的高度。
图2示出了封装101的透视图，虚构地示出了封装101的外部线，以便示出框架107的细节并示出管芯103附着在框架107的何处。上接触面109包括X标志203，管芯103附着到X标志。在所示的实施例中，管芯103和管芯105的接地管芯焊盘耦合到X标志203。在其它实施例中，上接触面可以具有将管芯附着于其上的其它的构造和/或结构，诸如实心标志。
如图2所示，在下接触面111的周边的外部两行上的焊盘(例如，113)与那些行的其它焊盘电气隔离。在其它实施例中，那些行的一些焊盘可以电气耦合到那些行的其它焊盘。所示引线121结合到管芯103的顶表面上的管芯结合焊盘129，以及下接触面111的焊盘113的顶表面123。为了简化，在图2中没有示出用于将管芯103的顶表面上的管芯结合焊盘耦合到下接触面111的其它焊盘的其它引线。
图5是流程图，提出了用于制造根据本发明的多管芯半导体封装的阶段。图3和4每一个示出了在制造工艺中的不同阶段的封装101。在图5的实施例中，从金属片(未示出)制得多个封装的框架。在一些实施例中，该片材由铜制得并且具有5-10毫米范围的厚度。制造封装的工艺可以包括在图5中没有示出的其它的常规阶段(例如清洗阶段)。
在503中，在对应于电互连框架的中心部分的位置腐蚀金属片以限定每个框架的上接触面(例如109)的结构。在505中，挤压金属片以形成上接触面和下接触面。在挤压操作期间，片材的部分变形以提供在上部(例如118)和下部(例如117)之间具有偏移的内嵌结构(例如116)。在507中，引线结合于其上的框架(例如107)的部分选择性地镀第二金属(例如，银、金、镍或钯)。在其它实施例中，可以镀整个片材。
在509中，将粘结剂涂覆到上接触面(例如109)的底表面的管芯附着区域，用于在511中将底管芯(例如105)附着在那些管芯附着区域。
在513中，将引线(例如127)结合到底管芯(例如105)的管芯结合焊盘以及内嵌结构(例如116)的上部(例如118)的底表面。在一个实施例中，这些引线(例如127)反针(reversed stitch)结合到底管芯(例如105)的结合焊盘以及内嵌结构(例如116)的上部(例如118)，从而降低引线的环路高度。图3是底视图，示出了制得封装101的片材的一部分。
在515中，将胶带(未示出)跨过片材的底部应用到下接触面(例如111)的底侧上。该胶带与上接触面(109)的底表面、底管芯(例如105)的底表面、或结合到底管芯的引线(例如131)不接触。该胶带提供了在523中密封的模子的部分。在一些实施例中，底座(未示出)位于胶带和底管芯105的顶表面(具有例如131的结合焊盘的管芯105的表面)之间。此外，在515中，片材被插入在脊形载体(未示出)中以支撑底管芯(例如105)并保护结合到底管芯的引线(例如127)。
在517中，将粘结剂涂覆到上接触面(例如109)的顶表面上的管芯附着区域，用于在519中将顶管芯(例如103)附着到那些管芯附着区域。在521中，引线(例如121)被结合到顶管芯(例如103)的管芯结合焊盘(例如129)以及下接触面(例如111)的焊盘(例如113)的顶表面。在一些实施例中，结合到顶管芯的管芯结合焊盘的引线可以结合到内嵌结构(例如116)的上部(例如118)的顶表面。图4示出了制得封装101的片材的一部分在阶段521期间的顶视图。在下接触面111中的虚线表示将在阶段527中去除的焊盘之间的空间。
在523中，第一和第二管芯以及至少一部分框架被密封。在525中，从框架的底侧去除胶带。
在527中，去除下接触层的部分以形成下接触面(例如111)的各焊盘(例如113)。参考图4，在一个实施例中，腐蚀片材来去除虚线之间示出的部分片材，以形成下接触面(例如111)的焊盘(例如113)。在其它的实施例中，在下接触面的焊盘之间的材料可以通过沿着虚线以特定深度切割框架来去除。在529中，通过例如用锯切割密封来将封装彼此分开。
在其它实施例中，具有倒装芯片构造的管芯可以被附着到上接触面的底表面。对于这些实施例，具有倒装芯片结构的管芯的焊球被焊接到内嵌结构(例如116)的上部(例如118)的底侧。对于这些实施例，相对于图1所示的视图，内嵌结构(例如116)的上部(例如118)延伸到位于管芯105之上。
在其它实施例中，电互连框架可以具有其它构造，以及/或者框架的焊盘可以具有其它形状并且/或者可以布置在其它方向。例如，下接触面的焊盘可以成对角线方向。此外，在其它实施例中，在此所示或所述的框架可以用于其它类型的封装中。
在本发明的一个方面中，半导体封装包括具有顶电接触面和底电接触面的电互连框架。顶电接触面基本上平行于底电接触面并且从底电接触面偏移。顶和底电接触面每个都具有顶表面和底表面。该半导体封装还包括附着在顶电接触面的顶表面的第一集成电路管芯和附着在顶电接触面的底表面的第二集成电路管芯。该半导体封装还包括具有连接到第二集成电路管芯上的焊盘的第一端和具有连接到顶电接触面的结构的底表面的第二端的导体。该半导体封装还包括具有连接到第一集成电路管芯上的焊盘的第一端和具有连接到底电接触面的结构的顶表面的第二端的第一引线。
在本发明的另一方面中，半导体封装包括金属电互连框架，该金属电互连框架包括具有第一多个焊盘的基本上平坦的顶电接触面且包括具有第二多个焊盘的基本上平坦的底电接触面。顶电接触面基本上平行于底电接触面并且从底电接触面偏移。顶和底电接触面二者均具有顶表面和底表面。该半导体封装还包括具有顶表面和底表面的第一集成电路管芯。第一集成电路管芯的底表面附着在顶电接触面的顶表面。第一集成电路管芯的顶表面具有线焊到第二多个焊盘的多个焊盘。该半导体封装还包括具有顶表面和底表面的第二集成电路管芯。第二集成电路管芯的底表面附着到顶电接触面的底表面。第二集成电路管芯的顶表面具有线焊到第一多个焊盘的多个焊盘。
在本发明的另一个方面中，一种制造半导体封装的方法包括提供互连框架并腐蚀预定图案到该互连框架的至少一部分中。该方法还包括在互连框架中形成顶接触面和底接触面。顶接触面从底接触面偏移并且基本上平行于底接触面。该方法还包括首先将第一集成电路管芯附着到顶接触面的底表面，并且将第一集成电路管芯电耦合到顶接触面的焊盘的底表面。该方法还包括将第二集成电路管芯附着在顶接触面的顶表面并且将第二集成电路管芯线焊到底接触面的焊盘上。
虽然示出并说明了本发明的特定实施例，但是本领域技术人员应该认识到，根据在此的讲述，可以进行进一步变化和修改而不偏离本发明及其更宽方面，因此，权利要求在它们的范围内包含了在本发明的实质精神和范围内的所有这些变化和修改。

Claims (10)

1.一种半导体封装，其包括：
具有顶电接触面和底电接触面的电互连框架，顶电接触面平行于底电接触面并且从底电接触面偏移，顶电接触面和底电接触面每个都具有顶表面和底表面，
附着在顶电接触面的顶表面的第一集成电路管芯；
附着在顶电接触面的底表面的第二集成电路管芯；
具有连接到第二集成电路管芯上的焊盘的第一端和具有连接到顶电接触面的焊盘的底表面的第二端的导体；以及
具有连接到第一集成电路管芯上的焊盘的第一端和具有连接到底电接触面的焊盘的顶表面的第二端的第一引线。
2.根据权利要求1的半导体封装，还包括具有连接到第一集成电路管芯上的第二焊盘的第一端和具有连接到顶电接触面的焊盘的顶表面的第二端的第二引线。
3.根据权利要求1的半导体封装，其中所述导体的特征在于是回流焊料。
4.根据权利要求1的半导体封装，其中第一集成电路管芯的有效表面距离第二集成电路管芯的有效表面为0.5毫米或更大。
5.根据权利要求1的半导体封装，其中第一集成电路管芯、第二集成电路管芯以及至少一部分电互连框架被非导电密封材料所密封。
6.根据权利要求1的半导体封装，其中所述电连接框架还包括内嵌结构，该内嵌结构包括位于顶电接触面中的顶部和位于底电接触面中的底部，其中所述导体的第二端连接到所述顶部的底表面。
7.一种半导体封装，其包括：
金属电互连框架，该金属互连框架包括具有第一多个焊盘的平坦的顶电接触面且包括具有第二多个焊盘的平坦的底电接触面，顶电接触面平行于底电接触面并且从底电接触面偏移，顶电接触面和底电接触面二者都具有顶表面和底表面；
具有顶表面和底表面的第一集成电路管芯，第一集成电路管芯的底表面附着在顶电接触面的顶表面，第一集成电路管芯的顶表面具有线焊到第二多个焊盘的多个焊盘；以及
具有顶表面和底表面的第二集成电路管芯，第二集成电路管芯的底表面附着到顶电接触面的底表面，第二集成电路管芯的顶表面具有线焊到第一多个焊盘的多个焊盘。
8.根据权利要求7的半导体封装，其中第一集成电路管芯包括数字电路并且第二集成电路管芯包括模拟电路。
9.一种制造半导体封装的方法，其包括：
提供互连框架；
将预定图案腐蚀到所述互连框架的至少一部分中；
在所述互连框架中形成顶接触面和底接触面，顶接触面从底接触面偏移并且平行于底接触面；
首先将第一集成电路管芯附着到顶接触面的底表面；
将第一集成电路管芯电耦合到顶接触面的焊盘的底表面；
将第二集成电路管芯附着在顶接触面的顶表面；以及
将第二集成电路管芯线焊到底接触面的焊盘。
10.根据权利要求9的方法，其中：
在互连框架中形成顶接触面和底接触面还包括在框架中形成多个内嵌结构，所述多个内嵌结构中的每个内嵌结构具有位于顶接触面中的上部和位于底接触面中的底部；
将第一集成电路管芯电耦合到顶接触面的焊盘的底表面包括将第一集成电路管芯电耦合到所述多个内嵌结构的上部的底表面。
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Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6608375B2 (en) * 2001-04-06 2003-08-19 Oki Electric Industry Co., Ltd. Semiconductor apparatus with decoupling capacitor
US6818973B1 (en) * 2002-09-09 2004-11-16 Amkor Technology, Inc. Exposed lead QFP package fabricated through the use of a partial saw process
US6998709B2 (en) * 2003-11-05 2006-02-14 Broadcom Corp. RFIC die-package configuration
US20080179722A1 (en) * 2007-01-31 2008-07-31 Cyntec Co., Ltd. Electronic package structure
US7999734B2 (en) * 2007-03-29 2011-08-16 Silicon Laboratories Inc. Apparatus having integrated radio and GPS receivers
US8203214B2 (en) * 2007-06-27 2012-06-19 Stats Chippac Ltd. Integrated circuit package in package system with adhesiveless package attach
US7919848B2 (en) * 2007-08-03 2011-04-05 Stats Chippac Ltd. Integrated circuit package system with multiple devices
US8513817B2 (en) 2011-07-12 2013-08-20 Invensas Corporation Memory module in a package
US8823165B2 (en) 2011-07-12 2014-09-02 Invensas Corporation Memory module in a package
US8502390B2 (en) 2011-07-12 2013-08-06 Tessera, Inc. De-skewed multi-die packages
US8441111B2 (en) 2011-10-03 2013-05-14 Invensas Corporation Stub minimization for multi-die wirebond assemblies with parallel windows
WO2013052544A1 (en) 2011-10-03 2013-04-11 Invensas Corporation Stub minimization with terminal grids offset from center of package
US8659143B2 (en) 2011-10-03 2014-02-25 Invensas Corporation Stub minimization for wirebond assemblies without windows
US8659141B2 (en) 2011-10-03 2014-02-25 Invensas Corporation Stub minimization using duplicate sets of terminals for wirebond assemblies without windows
JP5947904B2 (ja) 2011-10-03 2016-07-06 インヴェンサス・コーポレイション 直交するウインドウを有するマルチダイ・ワイヤボンド・アセンブリのためのスタブ最小化
KR101894823B1 (ko) 2011-10-03 2018-09-04 인벤사스 코포레이션 평행한 윈도우를 갖는 다중-다이 와이어 본드 어셈블리를 위한 스터브 최소화
US8436477B2 (en) 2011-10-03 2013-05-07 Invensas Corporation Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate
US8629545B2 (en) 2011-10-03 2014-01-14 Invensas Corporation Stub minimization for assemblies without wirebonds to package substrate
US8436457B2 (en) 2011-10-03 2013-05-07 Invensas Corporation Stub minimization for multi-die wirebond assemblies with parallel windows
US8848392B2 (en) 2012-08-27 2014-09-30 Invensas Corporation Co-support module and microelectronic assembly
US9368477B2 (en) 2012-08-27 2016-06-14 Invensas Corporation Co-support circuit panel and microelectronic packages
US8848391B2 (en) 2012-08-27 2014-09-30 Invensas Corporation Co-support component and microelectronic assembly
US8787034B2 (en) 2012-08-27 2014-07-22 Invensas Corporation Co-support system and microelectronic assembly
US20140103508A1 (en) * 2012-10-11 2014-04-17 Texas Instruments Incorporated Encapsulating package for an integrated circuit
US9070423B2 (en) 2013-06-11 2015-06-30 Invensas Corporation Single package dual channel memory with co-support
US9070657B2 (en) 2013-10-08 2015-06-30 Freescale Semiconductor, Inc. Heat conductive substrate for integrated circuit package
US9123555B2 (en) 2013-10-25 2015-09-01 Invensas Corporation Co-support for XFD packaging
US9281296B2 (en) 2014-07-31 2016-03-08 Invensas Corporation Die stacking techniques in BGA memory package for small footprint CPU and memory motherboard design
US9691437B2 (en) 2014-09-25 2017-06-27 Invensas Corporation Compact microelectronic assembly having reduced spacing between controller and memory packages
US9484080B1 (en) 2015-11-09 2016-11-01 Invensas Corporation High-bandwidth memory application with controlled impedance loading
US9679613B1 (en) 2016-05-06 2017-06-13 Invensas Corporation TFD I/O partition for high-speed, high-density applications
US11328984B2 (en) 2017-12-29 2022-05-10 Texas Instruments Incorporated Multi-die integrated circuit packages and methods of manufacturing the same

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5637913A (en) * 1992-03-27 1997-06-10 Hitachi, Ltd. Leadframe semiconductor integrated circuit device using the same and method of and process for fabricating the two
CN1162366A (zh) * 1994-06-28 1997-10-15 英特尔公司 利用偏离连线和支撑块空腔制造双面连线集成电路封装
CN2465328Y (zh) * 2001-02-20 2001-12-12 华东先进电子股份有限公司 双面晶片封装体
US6340839B1 (en) * 1998-09-25 2002-01-22 Nec Corporation Hybrid integrated circuit

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US13643A (en) * 1855-10-09 Vibrating- pump
JPH01220837A (ja) 1988-02-29 1989-09-04 Nec Corp 半導体集積回路装置
JPH01272144A (ja) 1988-04-25 1989-10-31 Hitachi Ltd 半導体装置とその組立方法
US5147815A (en) * 1990-05-14 1992-09-15 Motorola, Inc. Method for fabricating a multichip semiconductor device having two interdigitated leadframes
JP3011510B2 (ja) * 1990-12-20 2000-02-21 株式会社東芝 相互連結回路基板を有する半導体装置およびその製造方法
US5222014A (en) * 1992-03-02 1993-06-22 Motorola, Inc. Three-dimensional multi-chip pad array carrier
US5422435A (en) * 1992-05-22 1995-06-06 National Semiconductor Corporation Stacked multi-chip modules and method of manufacturing
JP3289000B2 (ja) * 1993-08-09 2002-06-04 株式会社日立製作所 半導体装置の製造方法
KR0149798B1 (ko) * 1994-04-15 1998-10-01 모리시다 요이치 반도체 장치 및 그 제조방법과 리드프레임
JP2972096B2 (ja) * 1994-11-25 1999-11-08 シャープ株式会社 樹脂封止型半導体装置
JPH1079405A (ja) * 1996-09-04 1998-03-24 Hitachi Ltd 半導体装置およびそれが実装された電子部品
US6225688B1 (en) * 1997-12-11 2001-05-01 Tessera, Inc. Stacked microelectronic assembly and method therefor
JP2975979B2 (ja) * 1996-12-30 1999-11-10 アナムインダストリアル株式会社 ボールグリッドアレイ半導体パッケージ用可撓性回路基板
JP3545200B2 (ja) * 1997-04-17 2004-07-21 シャープ株式会社 半導体装置
US6329224B1 (en) * 1998-04-28 2001-12-11 Tessera, Inc. Encapsulation of microelectronic assemblies
JP3494901B2 (ja) * 1998-09-18 2004-02-09 シャープ株式会社 半導体集積回路装置
JP3485507B2 (ja) * 1999-10-25 2004-01-13 沖電気工業株式会社 半導体装置
US6376914B2 (en) * 1999-12-09 2002-04-23 Atmel Corporation Dual-die integrated circuit package
JP2002026243A (ja) * 2000-07-10 2002-01-25 Sony Corp 半導体装置
JP4637380B2 (ja) * 2001-02-08 2011-02-23 ルネサスエレクトロニクス株式会社 半導体装置
TW525274B (en) * 2001-03-05 2003-03-21 Samsung Electronics Co Ltd Ultra thin semiconductor package having different thickness of die pad and leads, and method for manufacturing the same
US6603072B1 (en) * 2001-04-06 2003-08-05 Amkor Technology, Inc. Making leadframe semiconductor packages with stacked dies and interconnecting interposer
US6713852B2 (en) * 2002-02-01 2004-03-30 Texas Instruments Incorporated Semiconductor leadframes plated with thick nickel, minimum palladium, and pure tin
US6781243B1 (en) * 2003-01-22 2004-08-24 National Semiconductor Corporation Leadless leadframe package substitute and stack package

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5637913A (en) * 1992-03-27 1997-06-10 Hitachi, Ltd. Leadframe semiconductor integrated circuit device using the same and method of and process for fabricating the two
CN1162366A (zh) * 1994-06-28 1997-10-15 英特尔公司 利用偏离连线和支撑块空腔制造双面连线集成电路封装
US6340839B1 (en) * 1998-09-25 2002-01-22 Nec Corporation Hybrid integrated circuit
CN2465328Y (zh) * 2001-02-20 2001-12-12 华东先进电子股份有限公司 双面晶片封装体

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