CN101188231B - 半导体器件和半导体晶片及其制造方法 - Google Patents
半导体器件和半导体晶片及其制造方法 Download PDFInfo
- Publication number
- CN101188231B CN101188231B CN200710199542.6A CN200710199542A CN101188231B CN 101188231 B CN101188231 B CN 101188231B CN 200710199542 A CN200710199542 A CN 200710199542A CN 101188231 B CN101188231 B CN 101188231B
- Authority
- CN
- China
- Prior art keywords
- semiconductor chip
- semiconductor
- wafer
- circuit formation
- protective film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Pressure Sensors (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004-194667 | 2004-06-30 | ||
| JP2004194667A JP4383274B2 (ja) | 2004-06-30 | 2004-06-30 | 半導体装置および半導体ウエハの製造方法 |
| JP2004194667 | 2004-06-30 |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005100810989A Division CN100463172C (zh) | 2004-06-30 | 2005-06-29 | 半导体器件和半导体晶片及其制造方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101188231A CN101188231A (zh) | 2008-05-28 |
| CN101188231B true CN101188231B (zh) | 2010-04-14 |
Family
ID=35600009
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200710199542.6A Expired - Lifetime CN101188231B (zh) | 2004-06-30 | 2005-06-29 | 半导体器件和半导体晶片及其制造方法 |
| CNB2005100810989A Expired - Lifetime CN100463172C (zh) | 2004-06-30 | 2005-06-29 | 半导体器件和半导体晶片及其制造方法 |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005100810989A Expired - Lifetime CN100463172C (zh) | 2004-06-30 | 2005-06-29 | 半导体器件和半导体晶片及其制造方法 |
Country Status (3)
| Country | Link |
|---|---|
| US (2) | US7663244B2 (enExample) |
| JP (1) | JP4383274B2 (enExample) |
| CN (2) | CN101188231B (enExample) |
Families Citing this family (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4383274B2 (ja) * | 2004-06-30 | 2009-12-16 | Necエレクトロニクス株式会社 | 半導体装置および半導体ウエハの製造方法 |
| KR100809696B1 (ko) * | 2006-08-08 | 2008-03-06 | 삼성전자주식회사 | 사이즈가 상이한 복수의 반도체 칩이 적층된 멀티 칩패키지 및 그 제조방법 |
| JP5489512B2 (ja) * | 2009-04-06 | 2014-05-14 | キヤノン株式会社 | 半導体装置の製造方法 |
| WO2010116694A2 (en) | 2009-04-06 | 2010-10-14 | Canon Kabushiki Kaisha | Method of manufacturing semiconductor device |
| JP5409084B2 (ja) | 2009-04-06 | 2014-02-05 | キヤノン株式会社 | 半導体装置の製造方法 |
| JP5353628B2 (ja) * | 2009-10-15 | 2013-11-27 | 住友ベークライト株式会社 | 半導体装置の製造方法 |
| JP2011108770A (ja) * | 2009-11-16 | 2011-06-02 | Sumitomo Bakelite Co Ltd | 半導体装置の製造方法、半導体装置、および電子部品の製造方法、電子部品 |
| JP5601079B2 (ja) * | 2010-08-09 | 2014-10-08 | 三菱電機株式会社 | 半導体装置、半導体回路基板および半導体回路基板の製造方法 |
| JP5717502B2 (ja) * | 2011-03-30 | 2015-05-13 | 信越ポリマー株式会社 | 半導体チップ用保持具及びその使用方法 |
| US8916421B2 (en) | 2011-08-31 | 2014-12-23 | Freescale Semiconductor, Inc. | Semiconductor device packaging having pre-encapsulation through via formation using lead frames with attached signal conduits |
| US9142502B2 (en) * | 2011-08-31 | 2015-09-22 | Zhiwei Gong | Semiconductor device packaging having pre-encapsulation through via formation using drop-in signal conduits |
| JP6157356B2 (ja) * | 2011-11-10 | 2017-07-05 | シチズン時計株式会社 | 光集積デバイス |
| US8597983B2 (en) | 2011-11-18 | 2013-12-03 | Freescale Semiconductor, Inc. | Semiconductor device packaging having substrate with pre-encapsulation through via formation |
| WO2015046334A1 (ja) | 2013-09-27 | 2015-04-02 | 株式会社ダイセル | 半導体素子三次元実装用充填材 |
| JP2020013911A (ja) * | 2018-07-19 | 2020-01-23 | 東京エレクトロン株式会社 | 基板処理システム及び基板処理方法 |
| KR102498148B1 (ko) * | 2018-09-20 | 2023-02-08 | 삼성전자주식회사 | 반도체 장치의 제조 방법 |
| CN114121845A (zh) * | 2020-09-01 | 2022-03-01 | Jmj韩国株式会社 | 半导体封装 |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6087719A (en) * | 1997-04-25 | 2000-07-11 | Kabushiki Kaisha Toshiba | Chip for multi-chip semiconductor device and method of manufacturing the same |
Family Cites Families (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3770631B2 (ja) | 1994-10-24 | 2006-04-26 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
| US5861666A (en) * | 1995-08-30 | 1999-01-19 | Tessera, Inc. | Stacked chip assembly |
| JP3563604B2 (ja) * | 1998-07-29 | 2004-09-08 | 株式会社東芝 | マルチチップ半導体装置及びメモリカード |
| JP2000114206A (ja) | 1998-10-05 | 2000-04-21 | Sony Corp | 半導体パッケージの製造方法 |
| JP2000208702A (ja) | 1999-01-14 | 2000-07-28 | Hitachi Ltd | 半導体装置およびその製造方法 |
| US6307270B1 (en) * | 1999-08-05 | 2001-10-23 | Ming-Tung Shen | Electro-optic device and method for manufacturing the same |
| JP2001250913A (ja) | 1999-12-28 | 2001-09-14 | Mitsumasa Koyanagi | 3次元半導体集積回路装置及びその製造方法 |
| JP4137328B2 (ja) | 1999-12-28 | 2008-08-20 | 光正 小柳 | 3次元半導体集積回路装置の製造方法 |
| US6559539B2 (en) * | 2001-01-24 | 2003-05-06 | Hsiu Wen Tu | Stacked package structure of image sensor |
| US6627983B2 (en) * | 2001-01-24 | 2003-09-30 | Hsiu Wen Tu | Stacked package structure of image sensor |
| SG111919A1 (en) * | 2001-08-29 | 2005-06-29 | Micron Technology Inc | Packaged microelectronic devices and methods of forming same |
| US6611052B2 (en) * | 2001-11-16 | 2003-08-26 | Micron Technology, Inc. | Wafer level stackable semiconductor package |
| TWI234253B (en) | 2002-05-31 | 2005-06-11 | Fujitsu Ltd | Semiconductor device and manufacturing method thereof |
| JP2004140037A (ja) * | 2002-10-15 | 2004-05-13 | Oki Electric Ind Co Ltd | 半導体装置、及びその製造方法 |
| JP3908146B2 (ja) | 2002-10-28 | 2007-04-25 | シャープ株式会社 | 半導体装置及び積層型半導体装置 |
| JP3566957B2 (ja) * | 2002-12-24 | 2004-09-15 | 沖電気工業株式会社 | 半導体装置及びその製造方法 |
| JP4383274B2 (ja) * | 2004-06-30 | 2009-12-16 | Necエレクトロニクス株式会社 | 半導体装置および半導体ウエハの製造方法 |
-
2004
- 2004-06-30 JP JP2004194667A patent/JP4383274B2/ja not_active Expired - Lifetime
-
2005
- 2005-06-02 US US11/142,417 patent/US7663244B2/en not_active Expired - Lifetime
- 2005-06-29 CN CN200710199542.6A patent/CN101188231B/zh not_active Expired - Lifetime
- 2005-06-29 CN CNB2005100810989A patent/CN100463172C/zh not_active Expired - Lifetime
-
2007
- 2007-08-06 US US11/834,094 patent/US7812457B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6087719A (en) * | 1997-04-25 | 2000-07-11 | Kabushiki Kaisha Toshiba | Chip for multi-chip semiconductor device and method of manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2006019429A (ja) | 2006-01-19 |
| US20060014364A1 (en) | 2006-01-19 |
| CN101188231A (zh) | 2008-05-28 |
| US7812457B2 (en) | 2010-10-12 |
| JP4383274B2 (ja) | 2009-12-16 |
| CN100463172C (zh) | 2009-02-18 |
| US20070278698A1 (en) | 2007-12-06 |
| CN1716601A (zh) | 2006-01-04 |
| US7663244B2 (en) | 2010-02-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20240332227A1 (en) | Semiconductor element with bonding layer having low-k dielectric material | |
| US7812457B2 (en) | Semiconductor device and semiconductor wafer and a method for manufacturing the same | |
| EP3803972B1 (en) | Die stacking for multi-tier 3d integration | |
| TWI531046B (zh) | 半導體裝置結構與其製法 | |
| TWI812168B (zh) | 三維元件結構及其形成方法 | |
| TWI418000B (zh) | 半導體結構及其形成方法 | |
| US11830837B2 (en) | Semiconductor package with air gap | |
| US7795137B2 (en) | Manufacturing method of semiconductor device | |
| US11817306B2 (en) | Method for manufacturing semiconductor package with air gap | |
| TW201842635A (zh) | 具有熱導柱之積體電路封裝 | |
| KR101372018B1 (ko) | 집적 회로들의 형성 방법들 및 결과적인 구조들 | |
| CN103137566B (zh) | 用于形成集成电路的方法 | |
| US20110278569A1 (en) | Wafer level integration module with interconnects | |
| US7948088B2 (en) | Semiconductor device | |
| US8329573B2 (en) | Wafer level integration module having controlled resistivity interconnects | |
| CN100463190C (zh) | Soi衬底及其制造方法 | |
| CN100449762C (zh) | 半导体芯片及其制造方法以及半导体器件 | |
| TW202435410A (zh) | 半導體元件 | |
| US20240332130A1 (en) | High density vertical interconnect | |
| TW202329248A (zh) | 半導體結構的製造方法 | |
| TWI521665B (zh) | 矽貫穿電極以及其形成方法 | |
| CN105845665A (zh) | 一种半导体器件及其制作方法和电子装置 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: SHENZHEN FANGDA AUTOMATION SYSTEM CO., LTD. Free format text: FORMER OWNER: FANGDA GROUP CO., LTD. Effective date: 20101102 |
|
| C56 | Change in the name or address of the patentee | ||
| CP01 | Change in the name or title of a patent holder |
Address after: Kanagawa, Japan Patentee after: Renesas Electronics Corp. Address before: Kanagawa, Japan Patentee before: NEC ELECTRONICS Corp. |
|
| ASS | Succession or assignment of patent right |
Owner name: DESAILA ADVANCED TECHNOLOGY COMPANY Free format text: FORMER OWNER: RENESAS ELECTRONICS CORPORATION Effective date: 20141013 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20141013 Address after: American California Patentee after: Desella Advanced Technology Co. Address before: Kanagawa, Japan Patentee before: Renesas Electronics Corp. |
|
| CX01 | Expiry of patent term |
Granted publication date: 20100414 |
|
| CX01 | Expiry of patent term |