CN101064345B - 薄膜晶体管及其制造方法 - Google Patents
薄膜晶体管及其制造方法 Download PDFInfo
- Publication number
- CN101064345B CN101064345B CN2006101494339A CN200610149433A CN101064345B CN 101064345 B CN101064345 B CN 101064345B CN 2006101494339 A CN2006101494339 A CN 2006101494339A CN 200610149433 A CN200610149433 A CN 200610149433A CN 101064345 B CN101064345 B CN 101064345B
- Authority
- CN
- China
- Prior art keywords
- layer
- source
- silicon
- ohm
- raceway groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 9
- 238000004519 manufacturing process Methods 0.000 title abstract description 12
- 238000002161 passivation Methods 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 50
- 239000010703 silicon Substances 0.000 claims description 50
- 239000000463 material Substances 0.000 claims description 41
- 239000012212 insulator Substances 0.000 claims description 34
- 229920002120 photoresistant polymer Polymers 0.000 claims description 28
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 25
- 238000000034 method Methods 0.000 claims description 25
- 150000003376 silicon Chemical class 0.000 claims description 25
- 238000000059 patterning Methods 0.000 claims description 11
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 238000004151 rapid thermal annealing Methods 0.000 claims description 7
- 239000007790 solid phase Substances 0.000 claims description 7
- 238000004380 ashing Methods 0.000 claims description 6
- 238000002425 crystallisation Methods 0.000 claims description 6
- 230000008025 crystallization Effects 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 149
- 239000011248 coating agent Substances 0.000 description 8
- 238000000576 coating method Methods 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 238000004140 cleaning Methods 0.000 description 5
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 239000007772 electrode material Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 2
- 230000005527 interface trap Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 2
- 238000003949 trap density measurement Methods 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 1
- 229910004205 SiNX Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000007687 exposure technique Methods 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- KYKLWYKWCAYAJY-UHFFFAOYSA-N oxotin;zinc Chemical compound [Zn].[Sn]=O KYKLWYKWCAYAJY-UHFFFAOYSA-N 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
- H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
本发明提供了一种薄膜晶体管(TFT)及其制造方法。该TFT包括：衬底；沟道，形成于该衬底上；源欧姆层和漏欧姆层，形成于该沟道的两端上；热氧化层，形成于所述源欧姆层和漏欧姆层之间的沟道的表面上；栅绝缘体，覆盖该源欧姆层和漏欧姆层以及该热氧化层；栅，形成于该栅绝缘体上；ILD(层间电介质)层，覆盖该栅；源电极和漏电极，通过形成于该ILD层以及该栅绝缘体内的接触孔而接触该源欧姆层和漏欧姆层；以及钝化层，覆盖该源电极和漏电极。
Description
技术领域
本发明涉及薄膜晶体管(TFT)，具体地涉及TFT以及可以有效地降低制备工艺中出现的缺陷的该TFT的制造方法。
背景技术
使用有机发光二极管(OLED)的有源矩阵(AM)型显示器基本上包括开关晶体管和驱动晶体管。众所周知，开关晶体管需要低截止漏电流特性，而驱动晶体管需要高迁移率特性。
已经进行了各种研究以降低具有高迁移率的多晶硅TFT内的截止电流。降低截止电流的一个通常方法是使用轻掺杂漏区(LDD)或偏移(off-set)结构。
OLED中采用的TFT包括多晶硅沟道和具有附加欧姆层的源区和漏区，并具有顶栅结构，如图1所示。图1为驱动OLED显示器的驱动晶体管以及连接到该驱动晶体管的OLED的一部分的剖面视图。
参考图1，缓冲层11形成于衬底10上，沟道12由多晶硅形成于缓冲层11上呈岛状。源欧姆层13s和漏欧姆层13d由掺杂硅层形成于沟道12的两端上，源电极14s和漏电极14d由金属材料形成于源欧姆层13s和漏欧姆层13d上。栅绝缘体15形成于所得到的堆叠结构上，栅16形成于栅绝缘体15上介于源电极14s和漏电极14d之间。钝化层17由绝缘材料形成以覆盖栅16，为OLED的元件的电极18形成于钝化层17上以电连接到漏电极14d。
用于该OLED的传统晶体管的结构缺点为，源欧姆层13s和漏欧姆层13d分别与源电极14s和漏电极14d形成了堆叠结构。该堆叠结构的台阶覆盖率差，且形成于该堆叠结构上的栅绝缘体15可能破裂。通过具有足够厚度的栅绝缘体15可以解决该台阶覆盖率差的问题。然而，这种情况下，栅绝缘体15厚度增加可能导致该传统TFT的特性的恶化。此外，蚀刻剂在栅16的图案化期间可能通过栅绝缘体15的破裂部分渗入位于源欧姆层13s和漏欧姆层13d上的源电极14s和漏电极14d，并损伤该源电极14s和漏电极 14d。如果在清洗沟道12的表面时，清洗溶液溶解了形成源电极14s和漏电极14d的材料，则该源电极14s和漏电极14d可能被该清洗溶液污染。结果，沟道12的界面变得更差。
发明内容
本发明提供了一种TFT及该TFT的制造方法，该方法可以防止形成于欧姆层上的金属电极被污染。
本发明还提供了一种TFT及该TFT的制造方法，该方法可以减轻由于栅绝缘体上的堆叠结构引起的台阶覆盖率的恶化。
本发明还提供了一种TFT及该TFT的制造方法，其中该TFT包括具有改善的界面特性的堆叠结构。
根据本发明的一个方面，提供了一种薄膜晶体管(TFT)，其包括：衬底；沟道，形成于该衬底上；源欧姆层和漏欧姆层，形成于该沟道的两端上；热氧化层，形成于所述源欧姆层和漏欧姆层之间的沟道的表面上；栅绝缘体，覆盖该源欧姆层和漏欧姆层以及该热氧化层；栅，形成于该栅绝缘体上；ILD(层间电介质)层，覆盖该栅；源电极和漏电极，通过形成于该ILD层以及该栅绝缘体内的接触孔而接触该源欧姆层和漏欧姆层；以及，钝化层，覆盖该源电极和漏电极。
接触源欧姆层和漏欧姆层的该沟道的两个端部比该沟道的中心部分厚。
根据本发明的另一个方面，提供了一种制造TFT的方法，其包括：依次在衬底上形成硅沟道材料层和硅欧姆材料层；图案化该硅沟道材料层和该硅欧姆材料层以形成硅沟道以及接触该硅沟道两端的源欧姆层和漏欧姆层；在所述源欧姆层和漏欧姆层之间的硅沟道的表面上形成热氧化层；形成覆盖该源欧姆层和漏欧姆层以及热氧化层的栅绝缘体；在该栅绝缘体上形成与该硅沟道相对应的栅；在该栅绝缘体上形成ILD层以覆盖该栅；形成贯穿该源欧姆层和漏欧姆层上的ILD层和栅绝缘体的接触孔；形成通过该ILD层上的接触孔分别接触源欧姆层和漏欧姆层的源电极和漏电极；以及，形成覆盖该ILD层上的源电极和漏电极的钝化层。
该硅沟道材料层和该硅欧姆材料层的图案化可包括：在该硅欧姆材料层上形成光敏抗蚀剂掩模，该光敏抗蚀剂掩模包括对应于该源欧姆层和漏欧姆层的第一部分以及置于该源欧姆层和漏欧姆层之间的第二部分，其中该第二 部分比该第一部分薄；除去未被该光敏抗蚀剂掩模覆盖的该硅欧姆材料层的部分以及该硅沟道材料层的一部分；灰化该光敏抗蚀剂掩模的整个表面，被灰化的厚度至少对应于该光敏抗蚀剂掩模的第二部分，从而除去该光敏抗蚀剂掩模的第二部分；除去未被该光敏抗蚀剂掩模的第一部分覆盖的该硅欧姆材料层的一部分；以及，除去该光敏抗蚀剂掩模。
可以通过使用狭缝掩模或半色调掩模的光刻方法形成包括该第一和第二部分的该光敏抗蚀剂掩模。
在形成该硅沟道以及接触该硅沟道两端的该源欧姆层和漏欧姆层之前，该方法可进一步包括使用SPC(固相结晶)使该硅沟道材料层多晶化。可以使用RTA(快速热退火)执行该SPC。
附图说明
通过参考附图详细地描述本发明的示范性实施方案，本发明的上述和其他特征和优点将变得更加显而易见。附图中：
图1为传统顶栅型TFT的示意性剖面视图；
图2为根据本发明一个实施方案的TFT的示意性剖面视图；
图3为根据本发明另一个实施方案的TFT的一部分的示意性剖面视图；
图4A至4P为示出了根据本发明一个实施方案的TFT制造方法的剖面视图。
具体实施方式
以下，将参考附图更全面地描述本发明，其中在附图中示出了本发明的示范性实施方案。
图2为根据本发明一个实施方案的OLED中采用的多晶硅TFT的示意性剖面视图。参考图2，缓冲层21形成于衬底20上，沟道22由多晶硅形成于缓冲层21上呈岛状。众所周知，缓冲层21可具有单一氧化硅层结构或者氧化硅层和氧氮化硅层的双层结构。
源欧姆层23s和漏欧姆层23d由掺杂硅层形成于沟道22的两端上。源欧姆层23s和漏欧姆层23d被沟道22图案化，由此该源欧姆层23s和漏欧姆层23d的外边缘而非彼此面对的内边缘与该沟道22的外边缘一致。
栅绝缘体24和栅25依次形成于源欧姆层23s和漏欧姆层23d上。栅25置于该源欧姆层23s和漏欧姆层23d之间。层间电介质(ILD)层26形成于栅25上，源电极27s和漏电极27d形成于该ILD层26上。源电极27s和漏电极27d通过贯穿ILD层26和栅绝缘体24的接触孔H分别接触该源欧姆层23s和漏欧姆层23d。
钝化层28形成于该ILD层26上以覆盖该源电极27s和漏电极27d。为该OLED的元件的电极29形成于钝化层28上，从而通过形成于该钝化层28内的通路孔28a接触漏电极27d。
具有上述结构的本发明TFT的特征在于，由硅层形成的源欧姆层23s和漏欧姆层23d与在源欧姆层23s和漏欧姆层23d、栅绝缘体24以及ILD层26上的源电极27s和漏电极27d分离。因此栅绝缘体24下方的堆叠结构变薄。结果，栅绝缘体24的台阶覆盖率得以改善。
图3为根据本发明另一个实施方案的TFT的一部分的剖面视图。参考图3，使用热氧化在沟道22的表面上形成氧化硅层22a。沟道22的中心部分比位于源欧姆层23s和漏欧姆层23d下方的沟道22的部分薄。在形成和图案化该源欧姆层23s和漏欧姆层23d时，未被该源欧姆层23s和漏欧姆层23d覆盖的沟道22的表面的中心部分被蚀刻。此外，沟道22的中心部分的表面被蚀刻以彻底除去残留在沟道22表面上的硅欧姆材料，从而防止源欧姆层23s和漏欧姆层23d之间的短路。在图案化该源欧姆层23s和漏欧姆层23d时，采用附加的蚀刻工艺形成沟道22的这种过蚀刻部分。沟道22的过蚀刻部分可以被选择性地应用。使用热氧化形成于沟道22表面上的氧化硅层22a有助于改善界面特性，例如减少栅绝缘体24和沟道22之间的界面陷阱密度。可以选择性地形成和应用该氧化硅层22a。
现在将参考图4A至4P详细地描述根据本发明一个实施方案的TFT制造方法。
如图4A所示，在由塑料或玻璃形成的衬底20上依次沉积厚度为100nm至500nm的氧化硅(SiO2)、厚度为100nm至200nm的非晶氧化物(a-Si)、以及厚度为50nm至100nm的n+掺杂非晶硅，以获得缓冲层21、硅沟道材料层22’，以及欧姆材料层23。使用等离子体增强化学气相沉积(PECVD)进行该沉积。之后，使用快速热退火(RTA)进行固相结晶(SPC)，从而使该沟道材料层22’和欧姆材料层23多晶化。在此，在700℃至750℃的温度下执行该RTA约5分钟至20分钟。
如图4B所示，光敏抗蚀剂掩模30形成于欧姆材料层23上。光敏抗蚀剂掩模30包括：厚的第一部分31，对应于置于上述TFT的沟道22的两端上的源欧姆层23s和漏欧姆层23d；以及薄的第二部分32，置于该第一部分31之间。使用呈现局部不同曝光量的狭缝掩模或半色调掩模曝光光敏抗蚀剂或者通过不同的曝光技术，可以获得具有厚度不同的第一部分31和第二部分32的光敏抗蚀剂掩模30。使用这种狭缝掩模或半色调掩模根据曝光量差异制造固相光敏抗蚀剂掩模的技术在本领域是公知的，因此在此不再赘述。
如图4C所示，未被光敏抗蚀剂掩模30覆盖的欧姆材料层23和沟道材料层22’的部分被蚀刻。因此，由于图案化该欧姆材料层23下方的沟道材料层22’而形成了硅沟道22，欧姆材料层23以半成品状态残留于硅沟道22上并具有和硅沟道22相同的图案。
如图4D所示，光敏抗蚀剂掩模30在氧气和等离子体气氛中被灰化，从而除去光敏抗蚀剂掩模30的第二部分32并留下第一部分31。这里，第一部分31也被灰化，因此在第二部分32被除去时变得更薄。
如图4E所示，使用蚀刻剂将未被光敏抗蚀剂掩模30的第一部分31覆盖的硅沟道22表面蚀刻至薄的厚度，以彻底除去残留在硅沟道22暴露表面上的欧姆材料层23的残余物。光敏抗蚀剂30被剥离，随后使用氟化氢(HF)清洁。
如图4F所示，在700℃至750℃高温下氧气气氛中执行热氧化，从而在硅沟道22表面上形成氧化物层22a。这里，氧化物层22a形成于硅沟道22的表面以及源欧姆层23s和漏欧姆层23d的表面上。
如图4G所示，使用PECVD在所得的堆叠结构上形成由SiO2形成的厚度为50至100nm的栅绝缘体24。
如图4H所示，栅25形成于栅绝缘体24上。栅材料层被沉积和图案化以形成栅25。使用溅射方法进行该栅层的沉积，使用普通光刻方法进行该栅材料层的图案化。栅25具有单一金属层结构或多金属层结构，例如Mo的单一层结构或者Al和Mo、AlNd和Mo、或者Mo、Al和Mo的多层结构。栅25的这种结构是公知的，并不限制本发明的范围。
如图4I所示，ILD层26形成于栅绝缘体24上以覆盖栅25。ILD层26为使用PECVD形成的SiO2层。
如图4J所示，接触孔H形成为穿透ILD层26和栅绝缘体24，从而到达源欧姆层23s和漏欧姆层23d的表面。
如图4K所示，电极材料层27形成于ILD层26上。这里，电极材料层27填充接触孔H，从而电连接到源欧姆层23s和漏欧姆层23d。电极材料层27可由公知的材料形成，例如，和形成栅25的材料相同的材料。
如图4L所示，电极材料层27被图案化，从而得到连接到源欧姆层23s的源电极27s和连接到漏欧姆层23d的漏电极27d。
如图4M所示，形成钝化层28以覆盖源电极27s和漏电极27d。钝化层28可以是使用PECVD形成的SiNx层。
如图4N所示，使用普通图案化方法在钝化层28内形成通路孔28a，从而到达漏电极27d。
如图4O所示，如果钝化层28的表面不平整并因此将被平整化，则平整层30被另外形成。通路孔30a形成于平整层30内，从而到达钝化层28的通路孔28a。这里，钝化层28的通路孔28a以及平整层30的通路孔30a可同时形成。
如图4P所示，形成作为OLED的元件的电极，例如阳极29。对于OLED的情形，阳极29由透明导电材料形成，例如氧化铟锡(ITO)或氧化锌锡(IZO)。
之后可执行用于制造OLED显示器的另外工艺以获得期望的显示器。
如前所述，根据本发明，可以获得适用于OLED显示器的顶栅型TFT。传统顶栅型TFT在清洗界面时受到形成源电极和漏电极的金属的污染，因此沟道和栅之间的界面特性非常可能变差。然而，在本发明中，当沟道被清洗时，源层和漏层尚未由金属形成。因此，可以防止本发明的顶栅型TFT受到该金属材料的污染。
此外，欧姆层可以与电极分离。因此，不会出现差的台阶覆盖率。结果，栅绝缘体不会破裂。即使该栅绝缘体破裂，金属电极并不形成于该栅绝缘体的下方。因此，蚀刻剂不会渗入电极。结果，电极不会被该蚀刻剂溶解。
此外，该沟道可以被氧化以减小界面陷阱密度，从而将该TFT的特性维持在高质量状态。根据本发明的制造顶栅型TFT的方法适用于制造OLED显示器。
尽管已经参考本发明的示范性实施方案具体地示出和描述了本发明，但是本领域技术人员将会理解，在不离开由权利要求界定的本发明的精神和范围的条件下，可以对本发明进行各种形式和细节上的改变。
Claims (9)
1.一种薄膜晶体管，包括：
衬底；
沟道，形成于该衬底上；
源欧姆层和漏欧姆层，形成于该沟道的两端上；
热氧化层，形成于所述源欧姆层和漏欧姆层之间的沟道的表面上；
栅绝缘体，覆盖该源欧姆层和漏欧姆层以及该热氧化层；
栅，形成于该栅绝缘体上；
层间电介质层，覆盖该栅；
源电极和漏电极，通过形成于该层间电介质层以及该栅绝缘体内的接触孔而接触该源欧姆层和漏欧姆层；以及
钝化层，覆盖该源电极和漏电极。
2.权利要求1所述的薄膜晶体管，其中接触该源欧姆层和漏欧姆层的该沟道的两个端部比该沟道的中心部分厚。
3.一种薄膜晶体管制造方法，包括：
依次在衬底上形成硅沟道材料层和硅欧姆材料层；
图案化该硅沟道材料层和该硅欧姆材料层以形成硅沟道以及接触该硅沟道的两端的源欧姆层和漏欧姆层；
在所述源欧姆层和漏欧姆层之间的硅沟道的表面上形成热氧化层；
形成覆盖该源欧姆层和漏欧姆层以及热氧化层的栅绝缘体；
在该栅绝缘体上形成与该硅沟道相对应的栅；
在该栅绝缘体上形成层间电介质层以覆盖该栅；
形成贯穿该源欧姆层和漏欧姆层上的该层间电介质层和栅绝缘体的接触孔；
形成通过该层间电介质层上的接触孔分别接触该源欧姆层和漏欧姆层的源电极和漏电极；以及
形成覆盖该层间电介质层上的该源电极和漏电极的钝化层。
4.权利要求3所述的方法，其中该硅沟道材料层和该硅欧姆材料层的图案化包括：
在该硅欧姆材料层上形成光敏抗蚀剂掩模，该光敏抗蚀剂掩模包括对应于该源欧姆层和漏欧姆层的第一部分以及置于该源欧姆层和漏欧姆层之间的第二部分，其中该第二部分比该第一部分薄；
除去未被该光敏抗蚀剂掩模覆盖的该硅欧姆材料层的部分以及该硅沟道材料层的部分；
灰化该光敏抗蚀剂掩模的整个表面，被灰化的厚度至少对应于该光敏抗蚀剂掩模的第二部分，从而除去该光敏抗蚀剂掩模的第二部分；
除去未被该光敏抗蚀剂掩模的第一部分覆盖的该硅欧姆材料层的一部分；以及
除去该光敏抗蚀剂掩模。
5.权利要求4所述的方法，其中通过使用狭缝掩模和半色调掩模之一的光刻方法形成包括该第一部分和第二部分的该光敏抗蚀剂掩模。
6.权利要求5所述的方法，在形成该硅沟道以及接触该硅沟道两端的该源欧姆层和漏欧姆层之前，进一步包括使用固相结晶使该硅沟道材料层多晶化。
7.权利要求6所述的方法，其中使用快速热退火执行该固相结晶。
8.权利要求3所述的方法，在形成该硅沟道以及接触该硅沟道两端的该源欧姆层和漏欧姆层之前，进一步包括使用固相结晶使该硅沟道材料层多晶化。
9.权利要求8所述的方法，其中使用快速热退火执行该固相结晶。
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020060038334A KR100763913B1 (ko) | 2006-04-27 | 2006-04-27 | 박막 트랜지스터의 제조방법 |
| KR38334/06 | 2006-04-27 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101064345A CN101064345A (zh) | 2007-10-31 |
| CN101064345B true CN101064345B (zh) | 2010-12-01 |
Family
ID=38647539
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2006101494339A Expired - Fee Related CN101064345B (zh) | 2006-04-27 | 2006-11-20 | 薄膜晶体管及其制造方法 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US20070252207A1 (zh) |
| JP (1) | JP2007300080A (zh) |
| KR (1) | KR100763913B1 (zh) |
| CN (1) | CN101064345B (zh) |
Families Citing this family (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2448174B (en) * | 2007-04-04 | 2009-12-09 | Cambridge Display Tech Ltd | Organic thin film transistors |
| GB0814534D0 (en) * | 2008-08-08 | 2008-09-17 | Cambridge Display Tech Ltd | Transistors |
| KR101501920B1 (ko) * | 2008-09-11 | 2015-03-12 | 엘지디스플레이 주식회사 | 박막트랜지스터의 제조방법 |
| KR101065407B1 (ko) * | 2009-08-25 | 2011-09-16 | 삼성모바일디스플레이주식회사 | 유기 발광 표시 장치 및 그 제조 방법 |
| KR101700154B1 (ko) | 2009-11-20 | 2017-01-26 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 래치 회로와 회로 |
| KR101650878B1 (ko) * | 2010-03-22 | 2016-08-25 | 삼성디스플레이 주식회사 | 박막 트랜지스터의 제조 방법 및 이를 이용한 표시 기판의 제조 방법 |
| KR101073786B1 (ko) | 2010-04-16 | 2011-10-13 | 선문대학교 산학협력단 | 박막트랜지스터의 제조방법 |
| CN102790068B (zh) * | 2012-07-26 | 2014-10-22 | 北京京东方光电科技有限公司 | 一种传感器的制造方法 |
| KR20140115191A (ko) * | 2013-03-20 | 2014-09-30 | 삼성디스플레이 주식회사 | 박막 트랜지스터 및 이를 포함하는 유기 발광 표시 장치 |
| CN103715147B (zh) | 2013-12-27 | 2016-08-17 | 京东方科技集团股份有限公司 | 互补型薄膜晶体管驱动背板及其制作方法、显示面板 |
| CN104779171A (zh) * | 2015-05-05 | 2015-07-15 | 京东方科技集团股份有限公司 | 低温多晶硅薄膜晶体管及制作方法、阵列基板、显示装置 |
| KR102478470B1 (ko) | 2015-06-25 | 2022-12-19 | 삼성디스플레이 주식회사 | 박막 트랜지스터 기판, 및 유기 발광 표시 장치 |
| CN105261636B (zh) * | 2015-11-05 | 2018-04-27 | 京东方科技集团股份有限公司 | 一种薄膜晶体管、其制备方法、阵列基板及显示装置 |
| CN105321825A (zh) * | 2015-11-18 | 2016-02-10 | 武汉华星光电技术有限公司 | 低温多晶硅薄膜晶体管及其制作方法 |
| CN105390443B (zh) * | 2015-12-03 | 2018-11-23 | 深圳市华星光电技术有限公司 | Tft基板的制作方法 |
| CN105428243B (zh) * | 2016-01-11 | 2017-10-24 | 京东方科技集团股份有限公司 | 一种薄膜晶体管及制作方法、阵列基板和显示装置 |
| CN108110061A (zh) * | 2017-12-22 | 2018-06-01 | 信利（惠州）智能显示有限公司 | 低温多晶硅薄膜晶体管及其制作方法和显示装置 |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5693959A (en) * | 1995-04-10 | 1997-12-02 | Canon Kabushiki Kaisha | Thin film transistor and liquid crystal display using the same |
| US6303946B1 (en) * | 1997-07-18 | 2001-10-16 | Lg. Philips Lcd Co., Ltd. | Thin film transistor substrate and liquid crystal display unit having a low-resistance silicon compound film |
| CN1532945A (zh) * | 2003-03-19 | 2004-09-29 | 鸿富锦精密工业（深圳）有限公司 | 薄膜晶体管及其制造方法及显示装置 |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5322807A (en) * | 1992-08-19 | 1994-06-21 | At&T Bell Laboratories | Method of making thin film transistors including recrystallization and high pressure oxidation |
| JPH08172202A (ja) * | 1994-12-20 | 1996-07-02 | Sharp Corp | 薄膜トランジスタおよびその製造方法 |
| JPH11317529A (ja) | 1999-02-15 | 1999-11-16 | Casio Comput Co Ltd | 薄膜トランジスタの製造方法 |
| KR100336579B1 (ko) * | 2000-06-30 | 2002-05-16 | 박종섭 | 자기정렬 저면게이트 박막트랜지스터 제조방법 |
| KR20030091644A (ko) * | 2002-05-23 | 2003-12-03 | 엘지.필립스 엘시디 주식회사 | 다결정 박막트랜지스터 및 그 제조방법 |
| KR100925545B1 (ko) * | 2002-12-30 | 2009-11-05 | 엘지디스플레이 주식회사 | 액정표시장치의 박막 트랜지스터 및 그 제조방법 |
| KR100626051B1 (ko) * | 2004-12-24 | 2006-09-21 | 삼성에스디아이 주식회사 | 유기 박막 트랜지스터, 그 제조방법 및 이를 구비한 평판디스플레이 장치 |
| KR100662790B1 (ko) * | 2004-12-28 | 2007-01-02 | 엘지.필립스 엘시디 주식회사 | 액정표시장치 및 그 제조방법 |
-
2006
- 2006-04-27 KR KR1020060038334A patent/KR100763913B1/ko not_active IP Right Cessation
- 2006-11-20 CN CN2006101494339A patent/CN101064345B/zh not_active Expired - Fee Related
-
2007
- 2007-02-15 US US11/706,316 patent/US20070252207A1/en not_active Abandoned
- 2007-04-02 JP JP2007096523A patent/JP2007300080A/ja active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5693959A (en) * | 1995-04-10 | 1997-12-02 | Canon Kabushiki Kaisha | Thin film transistor and liquid crystal display using the same |
| US6303946B1 (en) * | 1997-07-18 | 2001-10-16 | Lg. Philips Lcd Co., Ltd. | Thin film transistor substrate and liquid crystal display unit having a low-resistance silicon compound film |
| CN1532945A (zh) * | 2003-03-19 | 2004-09-29 | 鸿富锦精密工业（深圳）有限公司 | 薄膜晶体管及其制造方法及显示装置 |
Non-Patent Citations (2)
| Title |
|---|
| JP平2-65138A 1990.03.05 |
| JP特开2000-286423A 2000.10.13 |
Also Published As
| Publication number | Publication date |
|---|---|
| US20070252207A1 (en) | 2007-11-01 |
| KR100763913B1 (ko) | 2007-10-05 |
| JP2007300080A (ja) | 2007-11-15 |
| CN101064345A (zh) | 2007-10-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101064345B (zh) | 薄膜晶体管及其制造方法 | |
| KR101213708B1 (ko) | 어레이 기판 및 이의 제조방법 | |
| US8329523B2 (en) | Array substrate for dislay device and method of fabricating the same | |
| KR101019048B1 (ko) | 어레이 기판 및 이의 제조방법 | |
| US6329672B1 (en) | Thin film transistor having a second gate metal layer preventing formation of hillocks | |
| KR101128333B1 (ko) | 어레이 기판 및 이의 제조방법 | |
| US6395586B1 (en) | Method for fabricating high aperture ratio TFT's and devices formed | |
| US9761616B2 (en) | Manufacturing method of array substrate with reduced number of patterning processes array substrate and display device | |
| KR101246789B1 (ko) | 어레이 기판 및 이의 제조방법 | |
| US8476123B2 (en) | Method for manufacturing thin film transistor array panel | |
| US20100090208A1 (en) | Thin film transistor substrate, method of manufacturing the same, and display apparatus having the same | |
| KR101246790B1 (ko) | 어레이 기판 및 이의 제조방법 | |
| KR20110058356A (ko) | 어레이 기판 및 이의 제조방법 | |
| KR101030968B1 (ko) | 어레이 기판 및 이의 제조방법 | |
| CN114284299A (zh) | 显示面板及其制备方法、移动终端 | |
| KR20120067108A (ko) | 어레이 기판 및 이의 제조방법 | |
| KR20070050572A (ko) | 박막 트랜지스터 기판의 제조방법 | |
| KR101484965B1 (ko) | 어레이 기판의 제조방법 | |
| CN108321122B (zh) | Cmos薄膜晶体管及其制备方法和显示装置 | |
| KR20110056899A (ko) | 어레이 기판 및 이의 제조방법 | |
| KR100752370B1 (ko) | 박막트랜지스터 및 그 제조 방법 | |
| KR20040013537A (ko) | 박막 트랜지스터 기판 및 그의 제조 방법 | |
| KR101713146B1 (ko) | 어레이 기판 및 이의 제조 방법 | |
| KR101588447B1 (ko) | 어레이 기판 및 이의 제조방법 | |
| JP3310567B2 (ja) | 半導体装置の製造方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20101201 Termination date: 20181120 |