CN101006583A - 集成电路电阻器 - Google Patents
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Abstract
提供了一种集成电路电阻器，其包括电触点(16)和(18)之间的台面(14)。通过在台面(14)中形成凹陷(20)和(22)，有选择地增大了电触点(16)和(18)之间的电阻。凹陷(20)和(22)的大小可被用于调节触点(16)和(18)之间的电阻的值。
Description
技术领域
本发明总体涉及电子器件领域，更具体而言涉及经改进的集成电路电阻器及其形成方法。
背景技术
为形成满足当今集成电子器件市场需要的复杂系统，集成电路必须包含都形成在共同的衬底上的多种有源和无源元件。对于某些应用，具有相对较大的电阻值的电阻器已经成为了在尝试减小集成器件的总体大小时的限制因素。
构造电阻器和集成电路的典型技术包括在半导体衬底的外表面或外层上沉积或生长半导体膜。然后在膜上制作的接触点，并且膜的面积和触点的间距被用于调整电阻器的电阻值。这些技术可有效地用于产生具有数欧姆到数百欧姆量级的相对较低的电阻值的电阻器。但是，如果特定的电子电路需要电阻为好几千欧姆的电阻器，则这些技术将会要求将衬底面积的大部分专用于形成这些电阻器。
发明内容
因此，提供了一种新的集成电路电阻器构造方法，它基本上消除或减小了与现有技术和结构相关联的问题和缺点。
根据本发明的一个实施例，从半导体衬底的表面向外形成了器件。在半导体衬底的外表面上形成了半导体层。在半导体层的外表面上制作彼此间隔预定距离的第一和第二触点。从半导体层的外表面去除半导体层的一部分，以在间隔开的第一和第二触点之间形成凹陷，以便第一和第二触点之间经由半导体层的电阻增大预定的量。
根据本发明的一个特定实施例，半导体层包括多个层，所述多个层包括蚀刻终止层，以便能够去除外延层的某些部分。
根据本发明的另一实施例，去除半导体层的某些部分以增大第一和第二接触点之间的电阻的步骤是在用于在外延层中第一和第二触点之间产生至少两个凹陷的至少两个蚀刻步骤中完成的。以这种方式，第一和第二凹陷的大小可被调整，以便能够非常精确地调节第一和第二接触点之间的电阻的值。
附图说明
通过参考附图可以更全面地理解本发明及其优点，附图中类似的标号指示类似的特征，其中：
图1A至1E是示出根据本发明一个实施例形成集成电路电阻器的方法的一系列顺序的、放大许多的截面前视图。
具体实施方式
参考图1A，其中示出了半导体衬底10。衬底10可包括硅、锗、砷化镓、硅锗、磷化铟、氮化镓、磷化镓铟、碳化硅，或其他合适的材料。利用传统的外延技术，半导体材料的外延层12被形成在衬底10的外表面上。外延层12可包括任意数目的顺序形成的包括不同材料的层。正如这里将讨论的，外延层12可包括填隙式蚀刻终止层，该填隙式蚀刻终止层可用于之后的蚀刻过程中，以提供可以非常精确地控制的蚀刻深度。例如，一种可能的形成外延层12的顺序包括首先形成超晶格缓冲层，该超晶格缓冲层包括15埃的砷化镓层与200埃的砷化镓铝层的交替序列。可重复形成这些交替序列十次，以产生厚度约为2,150埃的超晶格缓冲层。超晶格缓冲层的外表面随后可经历合适的底部硅脉冲掺杂。
然后形成厚度约为50埃的砷化镓铝间隔层。接下来，可形成厚度约为135埃的砷化镓铟沟道层。随后，可形成额外的30埃的砷化镓铝间隔层，之后是第二硅脉冲掺杂步骤。接下来，外延地生长500埃的砷化镓铝层，其中N型离子的浓度为3E17cm-3。接下来，可形成150埃的砷化镓层，其中N型掺杂同样达到3E17cm-3的浓度。接下来，形成厚度为10到20埃量级的砷化铝蚀刻终止层，并掺杂以浓度为1.2E18cm-3的N型离子。砷化铝蚀刻终止层将会充当之后在外延层12中的蚀刻步骤的蚀刻终止。通过形成掺杂了浓度达到3E17cm-3的N型离子、厚度约为150埃的砷化镓层，可以完成外延层12。最后，500埃的砷化镓层被形成在层12的外表面上，并且被掺杂以浓度达到3E18cm-3的N型离子。
如这里将会讨论的，由于使用单个蚀刻终止层，因此先前描述的技术和离子浓度将会允许在外延层12中形成单个凹陷。正如将会说明的，在之后的步骤中，外延层12中凹陷的形成被用于形成高电阻且精确受控的电阻器。
如果为了更大的电阻和值控制而需要双凹陷蚀刻，则可使用不同的配方来包括两个蚀刻终止层。在这种情况下，在先前描述的第二硅脉冲掺杂步骤之后跟着的可以是不同的过程，此过程开始于形成约220埃厚的掺杂了浓度达到3E17cm-3的N型离子的砷化镓铝层。然后可形成厚度为10到20埃量级的砷化铝或磷化镓铟的第一蚀刻终止层。在第一蚀刻终止层之后，可形成约430埃厚的砷化镓铝层，然后掺杂以浓度达到3E17cm-3的N型离子。然后可形成厚度为50埃量级的砷化铝或磷化镓铟的第二蚀刻终止层。随后可通过形成掺杂了浓度达到3E18cm-3的N型离子的550埃厚的砷化镓层来完成层12的结构。
利用第二种替换过程，可以使用两个蚀刻终止层，以利用两个随后的蚀刻步骤形成双凹陷结构。这里将讨论在高质量、高值且值非常精确的集成电路电阻器的形成过程中对这些随后的蚀刻步骤的使用。
参考图1B，传统的光刻蚀刻技术被用于从外延层12形成台面区域14。或者，通过反向植入周围区域，可产生掺杂的半导体的隔离区域。然后，从台面14向外淀积导电材料层，并利用传统的光刻技术对其进行摹制和蚀刻，以形成第一触点16和第二触点18。触点16和18可包括高掺杂半导体材料，或者合适的金属材料，例如铝、铜或金。触点16和18形成与层12(尤其是台面14)的低电阻欧姆触点。
参考图1C，利用光刻方法执行第一蚀刻过程，以掩蔽除了台面14的外表面的选定区域之外的整个外表面。该蚀刻过程导致了第一凹陷区域的形成，在图1C中将其总地标示为20。利用先前描述的层12的示例性形成，凹陷20的形成将包括向下蚀刻到先前描述的位于最外部的蚀刻终止层。该蚀刻过程例如可使用合适的活性蚀刻溶液，例如氢氟酸或盐酸。凹陷20的深度可为500-550埃量级。
参考图1D，类似的光刻过程被用于在先前描述的第一凹陷区域20内形成第二凹陷区域22。第二凹陷区域22具有额外的约430-440埃的深度，并且可利用与先前用于构造凹陷20的化学作用和技术相同的化学作用和技术来构造。
触点16和触点18之间的导电路径经过台面14。通过经由先前描述的凹陷20和22的形成来有选择地去除材料，触点16和触点18之间的路径的电阻值得以增大。通过调整凹陷20和22的大小和深度，触点16和触点18之间的路径的整体电阻可得以非常精确的控制。利用蚀刻终止层，可将凹陷20和22的深度控制在误差几埃的范围内。通过使用传统的光刻掩膜，很容易控制凹陷的横向大小。重要的是，凹陷20和22在触点16和18之间的确切布置不是那么关键，因为比起凹陷20和22在台面14内的定位来，电阻值与去除的材料量更紧密相关。
虽然已经参考了可用于形成各种层的特定材料详细描述了本发明，但是本发明也可以使用其他类型的材料来实现合适的结构。例如，器件可包括以下材料的层：砷化镓、硅、锗、磷化铟、氮化镓、磷化镓铟、碳化硅，砷化镓铝、硅锗、砷化镓铟，或氮化镓。
虽然已经参考包括两个蚀刻终止层和形成两个凹陷区域以调整电阻值的体系结构描述了本发明的教导，但是本发明的教导不应当局限于这种或任何特定的体系结构。例如，为了从台面14精确地去除材料，并不需要蚀刻终止层。例如，密集记时的蚀刻或机械或等离子蚀刻技术可被用于精确地去除特定量的材料。此外，虽然示出了两个凹陷的形成，但是可以使用任意数目的凹陷来实现本发明的特定实施例。例如，单个凹陷或多于两个凹陷也同样可以起作用。
参考图1E，其中示出了根据实施例构造的集成电路电阻器的最终结构。从触点16和18以及台面14向外淀积了隔离绝缘层24。随后形成导电触点26和18以便能够与先前形成的触点16和18接触。隔离绝缘层24例如可包括合适的氧化物层或氮化物层。触点26和28例如可包括合适的金属材料，例如铝、金或铜。
此外，虽然所描述的实施例的教导提及了仅从外延层去除材料，但是本发明的教导并不局限于这种技术。例如，穿过外层进入主衬底层地去除材料的蚀刻技术也会影响接触点之间的电阻。虽然已经参考了示出的实施例详细描述了本发明，但是不应当将其理解为局限于这个或任何特定的实施例，而仅由所附权利要求所限。
此外，这里描述的对蚀刻过程的控制是通过使用蚀刻终止层来完成的。但是，本发明的教导并不局限于这种或任何蚀刻控制技术。作为示例(而非限制)，也可使用能够通过仔细控制蚀刻过程的时间来控制蚀刻深度的蚀刻过程，并且产生合适的效用。
Claims (19)
1.一种集成电路器件，包括：
包括第一外表面的半导体衬底；
从所述第一外表面向外形成的半导体层，该半导体层包括第二外表面，并在所述第二外表面中限定了凹陷；
从所述第二外表面向外形成的第一和第二触点，该第一和第二触点之间限定了电阻区域，通过经由去除所述半导体层的选择性部分来形成所述凹陷，增大了所述电阻区域的电阻。
2.如权利要求1所述的器件，其中所述半导体层包括第一蚀刻终止层。
3.如权利要求2所述的器件，其中所述半导体层内包括第二蚀刻终止层，该第二蚀刻终止层与所述第一蚀刻终止层平行并与之间隔开来。
4.如权利要求1所述的器件，其中，通过去除所述半导体衬底的某些部分，所述电阻区域的电阻值进一步增大。
5.如权利要求1所述的器件，其中所述半导体衬底包括砷化镓。
6.如权利要求1所述的器件，其中所述半导体层包括砷化镓。
7.一种形成集成电路器件的方法，包括：
在半导体衬底的外表面上形成半导体层；
在所述半导体层的外表面上形成彼此间隔开来并且其间限定了电阻区域的电触点；以及
通过去除所述半导体层在所述电阻区域中的选定部分来在所述半导体层的外表面中形成凹陷，以增大所述电触点之间经由所述电阻区域的电阻。
8.如权利要求7所述的方法，其中去除所述半导体层的选定部分的步骤包括以下步骤：有选择地蚀刻所述半导体层直到达到所述半导体层内的蚀刻终止层为止。
9.如权利要求8所述的方法，还包括以下步骤：在第二蚀刻步骤中蚀刻所述半导体层的额外部分直到达到第二蚀刻终止层为止。
10.如权利要求7所述的方法，还包括以下步骤：通过去除所述半导体衬底的某些部分来额外增大所述电触点之间的电阻。
11.如权利要求7所述的方法，其中形成半导体层的步骤包括以下步骤：形成包括多个不同层的层，所述多个不同层中的至少一些部分地包括半导体材料，所述多个层是利用外延过程形成的。
12.如权利要求7所述的方法，其中形成电触点的步骤包括以下步骤：形成一对材料体，所述材料体包含从由高掺杂半导体材料、铜、金和铝构成的群组中选择出来的材料。
13.一种利用权利要求7所述的方法制造的集成电路器件。
14.一种形成集成电路器件的方法，包括：
在半导体衬底的外表面上形成半导体层，包括第一和第二蚀刻终止层；
在所述半导体层的外表面上形成彼此间隔开来并且其间限定了电阻区域的电触点；
通过蚀刻所述半导体层在所述电阻区域中从所述第二蚀刻终止层向外布置的某些部分来在所述半导体层的外表面中形成第一凹陷，以增大所述电触点之间经由所述电阻区域的电阻；以及
通过蚀刻所述半导体层在所述电阻区域中的所述第一凹陷中从所述第一蚀刻终止层向外布置的某些部分来在所述半导体层的外表面中形成第二凹陷，以进一步增大所述电触点之间经由所述电阻区域的电阻。
15.如权利要求14所述的方法，还包括以下步骤：通过去除所述半导体衬底的某些部分来额外增大所述电触点之间的电阻。
16.如权利要求14所述的方法，其中形成半导体层的步骤包括以下步骤：形成包括砷化镓的层。
17.如权利要求14所述的方法，其中形成半导体层的步骤包括以下步骤：形成包括多个不同层的层，所述多个不同层中的至少一些部分地包括半导体材料，所述多个层是利用外延过程形成的。
18.如权利要求14所述的方法，其中形成电触点的步骤包括以下步骤：形成一对材料体，所述材料体包括从由高掺杂半导体材料、铜、金和铝构成的群组中选择出来的材料。
19.一种利用权利要求14所述的方法制造的集成电路器件。
Applications Claiming Priority (2)
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|---|---|---|---|
| US10/917,935 US7199016B2 (en) | 2004-08-13 | 2004-08-13 | Integrated circuit resistor |
| US10/917,935 | 2004-08-13 |
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| CN (1) | CN100524759C (zh) |
| AT (1) | ATE494634T1 (zh) |
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| WO (1) | WO2006020887A1 (zh) |
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2004
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| Publication number | Publication date |
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| US20060033177A1 (en) | 2006-02-16 |
| ATE494634T1 (de) | 2011-01-15 |
| JP5183199B2 (ja) | 2013-04-17 |
| KR20070050080A (ko) | 2007-05-14 |
| US7199016B2 (en) | 2007-04-03 |
| CN100524759C (zh) | 2009-08-05 |
| DE602005025781D1 (de) | 2011-02-17 |
| WO2006020887A1 (en) | 2006-02-23 |
| US20070138646A1 (en) | 2007-06-21 |
| KR101164272B1 (ko) | 2012-07-09 |
| JP2008510308A (ja) | 2008-04-03 |
| EP1790009B1 (en) | 2011-01-05 |
| EP1790009A1 (en) | 2007-05-30 |
| US7884442B2 (en) | 2011-02-08 |
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