CN100472650C - 半导体存储器件和半导体集成电路 - Google Patents
半导体存储器件和半导体集成电路 Download PDFInfo
- Publication number
- CN100472650C CN100472650C CNB2003101186832A CN200310118683A CN100472650C CN 100472650 C CN100472650 C CN 100472650C CN B2003101186832 A CNB2003101186832 A CN B2003101186832A CN 200310118683 A CN200310118683 A CN 200310118683A CN 100472650 C CN100472650 C CN 100472650C
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- Prior art keywords
- mos transistor
- raceway groove
- bit line
- storage unit
- memory cell
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 48
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Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
- Y10S257/903—FET configuration adapted for use as static memory cell
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
- Y10S257/903—FET configuration adapted for use as static memory cell
- Y10S257/904—FET configuration adapted for use as static memory cell with passive components,, e.g. polysilicon resistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Memories (AREA)
- Dram (AREA)
- Static Random-Access Memory (AREA)
Abstract
Description
Claims (6)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP347998/2002 | 2002-11-29 | ||
JP2002347998A JP4219663B2 (ja) | 2002-11-29 | 2002-11-29 | 半導体記憶装置及び半導体集積回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1505045A CN1505045A (zh) | 2004-06-16 |
CN100472650C true CN100472650C (zh) | 2009-03-25 |
Family
ID=32462900
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2003101186832A Expired - Fee Related CN100472650C (zh) | 2002-11-29 | 2003-11-28 | 半导体存储器件和半导体集成电路 |
Country Status (5)
Country | Link |
---|---|
US (3) | US7110283B2 (zh) |
JP (1) | JP4219663B2 (zh) |
KR (1) | KR20040047712A (zh) |
CN (1) | CN100472650C (zh) |
TW (1) | TW200416733A (zh) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060081467A1 (en) * | 2004-10-15 | 2006-04-20 | Makoto Nagashima | Systems and methods for magnetron deposition |
KR101142996B1 (ko) * | 2004-12-31 | 2012-05-08 | 재단법인서울대학교산학협력재단 | 표시 장치 및 그 구동 방법 |
KR100682218B1 (ko) * | 2005-05-30 | 2007-02-12 | 주식회사 하이닉스반도체 | 비휘발성 반도체 메모리 장치 |
JP2007234073A (ja) * | 2006-02-27 | 2007-09-13 | Fujitsu Ltd | 半導体記憶装置 |
JP5158624B2 (ja) * | 2006-08-10 | 2013-03-06 | ルネサスエレクトロニクス株式会社 | 半導体記憶装置 |
US7564725B2 (en) * | 2007-08-31 | 2009-07-21 | Texas Instruments Incorporated | SRAM bias for read and write |
US7787303B2 (en) * | 2007-09-20 | 2010-08-31 | Cypress Semiconductor Corporation | Programmable CSONOS logic element |
TWI399754B (zh) * | 2008-03-17 | 2013-06-21 | Elpida Memory Inc | 具有單端感測放大器之半導體裝置 |
KR101105002B1 (ko) * | 2010-01-23 | 2012-01-16 | 배신영 | 병마개 |
US8824186B2 (en) * | 2010-06-09 | 2014-09-02 | Radiant Technologies, Inc. | Embedded non-volatile memory circuit for implementing logic functions across periods of power disruption |
US8310856B2 (en) * | 2010-06-09 | 2012-11-13 | Radiant Technology | Ferroelectric memories based on arrays of autonomous memory bits |
KR101715048B1 (ko) | 2010-09-13 | 2017-03-13 | 삼성전자주식회사 | 부스팅 전하 누설을 감소시키기 위한 메모리 장치 및 이를 포함하는 시스템 |
KR101893848B1 (ko) | 2011-06-16 | 2018-10-04 | 삼성전자주식회사 | 수직 소자 및 비-수직 소자를 갖는 반도체 소자 및 그 형성 방법 |
KR101420538B1 (ko) | 2012-12-27 | 2014-07-16 | 삼성전기주식회사 | 게이트 드라이버 |
CN108346442B (zh) * | 2017-01-25 | 2020-12-15 | 中芯国际集成电路制造(上海)有限公司 | 灵敏放大器 |
TW201915818A (zh) * | 2017-10-05 | 2019-04-16 | 香港商印芯科技股份有限公司 | 光學識別模組 |
US10957366B2 (en) | 2018-05-24 | 2021-03-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Circuits and methods for compensating a mismatch in a sense amplifier |
KR102684115B1 (ko) * | 2019-07-19 | 2024-07-12 | 에스케이하이닉스 주식회사 | 반도체 메모리 소자 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5047979A (en) * | 1990-06-15 | 1991-09-10 | Integrated Device Technology, Inc. | High density SRAM circuit with ratio independent memory cells |
CN1311532A (zh) * | 2000-02-28 | 2001-09-05 | 因芬尼昂技术股份公司 | 用于dram存储器的带有垂直晶体管的写入放大器/读出放大器 |
US6421265B1 (en) * | 2001-03-22 | 2002-07-16 | Integrated Devices Technology, Inc. | DRAM-based CAM cell using 3T or 4T DRAM cells |
US6442060B1 (en) * | 2000-05-09 | 2002-08-27 | Monolithic System Technology, Inc. | High-density ratio-independent four-transistor RAM cell fabricated with a conventional logic process |
Family Cites Families (34)
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KR0141494B1 (ko) * | 1988-01-28 | 1998-07-15 | 미다 가쓰시게 | 레벨시프트회로를 사용한 고속센스 방식의 반도체장치 |
US5020028A (en) * | 1989-08-07 | 1991-05-28 | Standard Microsystems Corporation | Four transistor static RAM cell |
JPH04168694A (ja) | 1990-10-31 | 1992-06-16 | Mitsubishi Electric Corp | 半導体記憶装置 |
KR920022532A (ko) * | 1991-05-13 | 1992-12-19 | 문정환 | 이중 수직 채널을 갖는 스태틱램 및 그 제조방법 |
US5398200A (en) * | 1992-03-02 | 1995-03-14 | Motorola, Inc. | Vertically formed semiconductor random access memory device |
US5303190A (en) * | 1992-10-27 | 1994-04-12 | Motorola, Inc. | Static random access memory resistant to soft error |
JPH06162776A (ja) * | 1992-11-18 | 1994-06-10 | Nec Corp | 半導体メモリ回路 |
JPH0757476A (ja) | 1993-08-12 | 1995-03-03 | Nec Corp | 半導体メモリ集積回路 |
US5453949A (en) * | 1994-08-31 | 1995-09-26 | Exponential Technology, Inc. | BiCMOS Static RAM with active-low word line |
US5670803A (en) * | 1995-02-08 | 1997-09-23 | International Business Machines Corporation | Three-dimensional SRAM trench structure and fabrication method therefor |
JP3606951B2 (ja) * | 1995-06-26 | 2005-01-05 | 株式会社ルネサステクノロジ | 半導体記憶装置 |
US6028340A (en) * | 1995-07-10 | 2000-02-22 | Lg Semicon Co., Ltd. | Static random access memory cell having a field region |
JP2996168B2 (ja) | 1996-02-23 | 1999-12-27 | 日本電気株式会社 | 半導体メモリ集積回路装置 |
JPH10283776A (ja) * | 1997-04-04 | 1998-10-23 | Mitsubishi Electric Corp | 半導体記憶装置 |
US6005296A (en) * | 1997-05-30 | 1999-12-21 | Stmicroelectronics, Inc. | Layout for SRAM structure |
EP0920025B1 (en) | 1997-11-28 | 2004-02-11 | STMicroelectronics S.r.l. | A low power RAM memory cell |
US6028801A (en) * | 1998-06-29 | 2000-02-22 | Conexant Systems, Inc. | High speed sensing of dual port static RAM cell |
US6207998B1 (en) * | 1998-07-23 | 2001-03-27 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with well of different conductivity types |
JP2001155486A (ja) | 1999-11-25 | 2001-06-08 | Nec Corp | 半導体スタティックメモリ |
AU2000224587A1 (en) * | 2000-02-04 | 2001-08-14 | Hitachi Ltd. | Semiconductor device |
JP3326560B2 (ja) | 2000-03-21 | 2002-09-24 | 日本テキサス・インスツルメンツ株式会社 | 半導体メモリ装置 |
US6903411B1 (en) * | 2000-08-25 | 2005-06-07 | Agere Systems Inc. | Architecture for circuit connection of a vertical transistor |
US6549450B1 (en) * | 2000-11-08 | 2003-04-15 | Ibm Corporation | Method and system for improving the performance on SOI memory arrays in an SRAM architecture system |
US6483739B2 (en) * | 2000-12-31 | 2002-11-19 | Texas Instruments Incorporated | 4T memory with boost of stored voltage between standby and active |
US6434040B1 (en) * | 2001-02-23 | 2002-08-13 | Silicon Access Networks | Loadless NMOS four transistor SRAM cell |
JP2003007059A (ja) * | 2001-06-22 | 2003-01-10 | Mitsubishi Electric Corp | 半導体記憶装置 |
US6584030B2 (en) * | 2001-08-28 | 2003-06-24 | Micron Technology, Inc. | Memory circuit regulation system and method |
JP4167458B2 (ja) * | 2002-07-24 | 2008-10-15 | 松下電器産業株式会社 | 半導体メモリ装置及び半導体集積回路 |
US6677633B2 (en) * | 2002-09-24 | 2004-01-13 | Hitachi, Ltd. | Semiconductor device |
US6741493B1 (en) * | 2002-11-07 | 2004-05-25 | International Business Machines Corporation | Split local and continuous bitline requiring fewer wires |
JP2004362695A (ja) * | 2003-06-05 | 2004-12-24 | Renesas Technology Corp | 半導体記憶装置 |
JP4574136B2 (ja) * | 2003-07-29 | 2010-11-04 | 株式会社日立製作所 | 半導体集積回路装置 |
US7403426B2 (en) * | 2005-05-25 | 2008-07-22 | Intel Corporation | Memory with dynamically adjustable supply |
US7420854B2 (en) * | 2006-07-26 | 2008-09-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | SRAM device and operating method |
-
2002
- 2002-11-29 JP JP2002347998A patent/JP4219663B2/ja not_active Expired - Fee Related
-
2003
- 2003-11-06 TW TW092131123A patent/TW200416733A/zh unknown
- 2003-11-28 US US10/722,461 patent/US7110283B2/en not_active Expired - Fee Related
- 2003-11-28 KR KR1020030085364A patent/KR20040047712A/ko not_active Application Discontinuation
- 2003-11-28 CN CNB2003101186832A patent/CN100472650C/zh not_active Expired - Fee Related
-
2006
- 2006-09-19 US US11/522,904 patent/US7310279B2/en not_active Expired - Fee Related
-
2007
- 2007-10-31 US US11/979,128 patent/US7460392B2/en not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5047979A (en) * | 1990-06-15 | 1991-09-10 | Integrated Device Technology, Inc. | High density SRAM circuit with ratio independent memory cells |
CN1311532A (zh) * | 2000-02-28 | 2001-09-05 | 因芬尼昂技术股份公司 | 用于dram存储器的带有垂直晶体管的写入放大器/读出放大器 |
US6442060B1 (en) * | 2000-05-09 | 2002-08-27 | Monolithic System Technology, Inc. | High-density ratio-independent four-transistor RAM cell fabricated with a conventional logic process |
US6421265B1 (en) * | 2001-03-22 | 2002-07-16 | Integrated Devices Technology, Inc. | DRAM-based CAM cell using 3T or 4T DRAM cells |
Also Published As
Publication number | Publication date |
---|---|
TW200416733A (en) | 2004-09-01 |
US20040108526A1 (en) | 2004-06-10 |
US20070014169A1 (en) | 2007-01-18 |
US7310279B2 (en) | 2007-12-18 |
US7460392B2 (en) | 2008-12-02 |
JP2004186197A (ja) | 2004-07-02 |
US7110283B2 (en) | 2006-09-19 |
CN1505045A (zh) | 2004-06-16 |
US20080068877A1 (en) | 2008-03-20 |
KR20040047712A (ko) | 2004-06-05 |
JP4219663B2 (ja) | 2009-02-04 |
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C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
ASS | Succession or assignment of patent right |
Owner name: NEC CORP. Free format text: FORMER OWNER: RENESAS TECHNOLOGY CORP. Effective date: 20100812 |
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C41 | Transfer of patent application or patent right or utility model | ||
C56 | Change in the name or address of the patentee |
Owner name: RENESAS ELECTRONICS CO., LTD. Free format text: FORMER NAME: NEC CORP. |
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COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: TOKYO, JAPAN TO: KANAGAWA, JAPAN |
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CP01 | Change in the name or title of a patent holder |
Address after: Kanagawa, Japan Patentee after: Renesas Electronics Corp. Address before: Kanagawa, Japan Patentee before: NEC ELECTRONICS Corp. |
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TR01 | Transfer of patent right |
Effective date of registration: 20100812 Address after: Kanagawa, Japan Patentee after: NEC ELECTRONICS Corp. Address before: Tokyo, Japan Patentee before: Renesas Technology Corp. |
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C17 | Cessation of patent right | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090325 Termination date: 20131128 |