CN100416817C - 半导体装置及其制造方法 - Google Patents
半导体装置及其制造方法 Download PDFInfo
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- CN100416817C CN100416817C CNB011325992A CN01132599A CN100416817C CN 100416817 C CN100416817 C CN 100416817C CN B011325992 A CNB011325992 A CN B011325992A CN 01132599 A CN01132599 A CN 01132599A CN 100416817 C CN100416817 C CN 100416817C
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- Prior art keywords
- conductive layer
- wiring
- insulating barrier
- carbon
- film
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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Abstract
提供一种半导体装置,具有半导体基板和在该半导体基板上的导电层,所述导电层含有铜,所述导电层的表面区域具有C-H键和C-C键中的至少一种,所述表面区域中的形成C-H键的C原子和形成C-C键的C原子的总量占所述表面区域中的元素总量为30%以上。
Description
(本申请基于并要求在先的日本专利申请No.2000-27221(2000年9月7日递交)和No.2001-218528(2001年7月18日递交)为优先权,它们的全部内容在此引入作为参考)
技术领域
本发明涉及半导体装置及其制造方法,尤其涉及包含铜布线的半导体装置及其制造方法。
背景技术
在现有的半导体装置中,作为布线材料采用铝。近年来,逐渐用电阻率低且廉价的铜取代铝作为布线材料。但是,如果在含氧的气氛中对Cu布线热处理,其表面进行氧化,结果使布线的电阻大大增加。
图1A~1C是示意性地分别展示现有技术中的多层布线的形成工艺的一例的剖面图。图1A中,在半导体基板2上形成第一层间绝缘膜13,第一铜布线14埋入第一层间绝缘膜13。“铜布线14”是以Cu为主要成分的布线,例如在其侧壁和底面上形成有含Ta、TaN、Ti、TiN等的单层或多层。
该工艺首先,如图1A所示,在第一层间绝缘膜13和第一铜布线14上形成层间绝缘膜23作为连续膜,在层间绝缘膜23上形成光刻胶图案5。此时,“层间绝缘膜23”具有单层或多层结构,含有氮化硅膜(下面称“SiN膜)、氧化硅膜、有机硅氧化膜、和有机绝缘膜等。然后,如图1B所示,以光刻胶图案5为掩模进行反应性离子蚀刻(下面称“RIE),由此在层间绝缘膜23上形成第二铜布线用的沟。另外,为了引线接触,使在层间绝缘膜23上设计的沟的底面的一部分上露出第一铜布线14。
然后,通过在含氧气氛中进行灰化处理去除光刻胶图案5。这时,第一铜布线14的露出部分因暴露在高温的氧中被氧化,结果如图1C所示,形成Cu2O等构成的氧化膜14a。由于Cu氧化变成Cu2O,膨胀到原来的堆积层的1.65倍。因此,如图1C所示地形成氧化膜14a的情况下,容易在其周围形成裂纹。
类似的问题在铜用作焊盘之类的电极材料时,也同样地会发生。
图2A和2B是分别示意性地展示现有技术的键合工艺的一例的剖面图。图2A中,在半导体基板2上形成层间绝缘膜13,在层间绝缘膜13中埋入铜制的焊盘4。在层间绝缘膜13上依次层积SiN膜6和层间绝缘膜23。
图2A所示的金线到焊盘4上的引线键合通常在对半导体基板2高温加热的状态下和大气中进行。因此,焊盘4的表面因暴露在高温的氧中而氧化,结果如图2B所示,形成Cu2O等构成的氧化膜4a。从而在焊盘4的周围产生裂纹,发生剥离。
作为防止出现结合图1A~1C、2A和2B说明的裂纹的工艺,已知有图3A~3F、4A~4C所示的工艺。
图3A~3F是分别示意性地展示现有技术的多层布线的形成工艺的另一例子。该工艺首先如图13A所示地形成铜布线14后,如图3B所示,形成SiN膜16、层间绝缘膜23和光刻胶图案5。之后如图3C所示,以光刻胶图案5为掩模用RIE在层间绝缘膜23上形成沟。在该蚀刻时,SiN膜16起到蚀刻停止膜的作用。然后,在含氧11的气氛中进行灰化处理,由此除去光刻胶图案5。然后,如图3E所示,用蚀刻除去SiN膜16的位于沟内的部分,如图3F所示用铜填埋沟得到铜布线24。根据该工艺,在灰化时,由于在层间绝缘膜23上设置的沟内用SiN膜16覆盖铜布线14,铜布线14没有氧化。因此,可以防止裂纹的产生。
图4A~4C分别示意地展示现有技术中的键合工艺的另一例的剖面图。在该工艺中,首先如图4A所示,在半导体基板2上形成层间绝缘膜13、铜制的焊盘4、SiN膜6和绝缘膜23。然后,如图4B所示,用铝电极7覆盖在SiN膜6和绝缘膜23上设置的沟的侧壁和底面。然后,把Au引线8键合到该铝电极7上。在该工艺中,由于在沟内用铝电极7覆盖焊盘4,在键合Au引线8时焊盘不被氧化。
如上所述,在结合图1A~1C、2A和2B说明的工艺中铜布线14和铜焊盘4的表面氧化。另一方面,在结合图3A~3F、和4A~4C说明的工艺中可以防止铜布线14和铜焊盘4的表面氧化,但是形成SiN膜16的工序和蚀刻工序或形成铝电极7的工序成为不可缺少的。
伴随着铜布线或铜焊盘的氧化还会出现其它的问题。例如,铜布线和层间绝缘膜之间出现电位差,氧化铜离子化容易向绝缘膜中扩散。这种扩散也会增加布线电阻和布线间的电容。另外,在埋有铜布线的层间绝缘膜的表面上,一般地用化学汽相淀积(以下称“CVD”)法形成SiN膜或SiCH膜等作为扩散防止膜。这些SiN膜或SiCH膜和氧化铜层之间很难以良好的状态维持密合性。
通过例如,用以NH3气或H2气为原料的等离子体对铜布线表面进行处理,可以抑制与铜布线的氧化相关的问题。但是,这种等离子体处理,会出现下面说明的问题。
在现有的具有多层布线结构的半导体装置中,层间绝缘膜一般采用介电率K为4.1左右的氧化硅膜。最近,正在研究作为层间绝缘膜使用介电率小于3.0的有机硅膜或有机膜、作为布线材料使用铜的多层布线结构的实用化。用这种结构可以同时降低布线电阻值和布线间的电容。
但是,在对有机硅膜或有机膜实施上述等离子体处理时,从其表面区域夺走有机成分,表面区域成为脆弱的变质层。该变质层与层间绝缘膜和扩散膜之间的密合性低,在后面的热处理工序中发生扩散防止膜从层间绝缘膜上剥离。而且该变质层容易吸附水分。一般地,吸收水分的绝缘膜的介电率有增加的倾向,若形成变质层会损害降低布线间电容的效果。而且,吸收水分的绝缘膜在热处理工序中产生气体,所以助长扩散防止膜的剥离。
而且,在用涂敷法形成扩散防止膜的场合,难以在真空中连续地进行上述等离子体处理和形成扩散防止膜。因此,即使铜布线表面因等离子体处理而还原,以后也会再次氧化。如果在铜布线的表面形成氧化膜,由于其表面电阻增加布线电阻增加,而且布线间电容也增加。
发明内容
根据本发明第一方面,提供一种半导体装置,具有半导体基板和在该半导体基板上的导电层,所述导电层含有铜,所述导电层的表面区域具有C-H键和C-C键中的至少一种且检测不到碳化铜,所述表面区域中的形成C-H键的C原子和形成C-C键的C原子的总量占所述表面区域中的元素总量的30%以上。
根据本发明第二方面,提供一种半导体装置,具有半导体基板和在半导体基板上的导电层,所述导电层含有铜,在所述导电层的表面提供含有碳的粒子且检测不到碳化铜。
根据本发明第三方面,提供一种半导体装置的制造方法,包括下列步骤:在半导体基板上形成含有铜的第一导电层;向所述第一导电层的表面提供含有碳的物质;以及在残留有基于所述含有碳的物质导入的碳的所述第一导电层的表面上形成第二导电层,所述第一和第二导电层在上述残留有碳的表面上相互接触。
根据本发明第四方面,提供一种半导体装置的制造方法,包括下列步骤:在含有碳的第一绝缘层上形成导电层,所述绝缘层设在半导体基板上;对所述导电层和所述绝缘层的露出面进行含碳的等离子体处理;以及在所述处理后在所述导电层和所述第一绝缘层上形成第二绝缘层。
附图说明
图1A~1C是分别示意性地展示现有技术的多层布线的形成工艺的一例的剖面图;
图2A和2B是分别示意性地展示现有技术的键合工艺的一例的剖面图;
图3A~3C是分别示意性地展示现有技术的多层布线的形成工艺的另一例的剖面图;
图4A~4C是分别示意性地展示现有技术的键合工艺的另一例的剖面图;
图5A和5B是分别示意性地展示根据本发明的第一实施方案的半导体装置的制造工艺中可利用的处理的剖面图;
图6是展示对图5A和5B所示的结构进行氧化处理时形成的氧化膜的厚度的图;
图7A~7C是分别示意性地展示根据本发明的第二实施方案的半导体装置的制造工艺的剖面图;
图8A~8E是分别示意性地展示根据本发明的第三实施方案的半导体装置的制造工艺的剖面图;
图9是示意性地展示根据本发明的第四实施方案的半导体装置的制造工艺的剖面图;
图10A和10B是展示对如图9所示照射激光束后的焊盘表面用XPS测定后得到的Cls和Cu2p3波谱的图;
图11A和11B是展示对照射激光束后的焊盘表面用XPS测定后得到的Cls和Cu2p3波谱的图;
图12是展示对图9所示的结构进行氧化处理时形成的氧化膜的厚度的图;
图13A和13B是示意性地展示如图9所示照射激光束前后的布线的剖面图;
图14A~14C是分别示意性地展示根据本发明的第五实施方案的半导体装置的制造工艺的剖面图;
图15A~15G是分别示意性地展示根据本发明的第六实施方案的半导体装置的制造工艺的剖面图;
图16A~16C是分别示意性地展示根据本发明的第七实施方案的半导体装置的制造工艺的剖面图;
具体实施方式
下面,结合附图对本发明的各实施方案进行详细说明。另外,各图中同样的部件采用同一标号,并省略重复说明。
图5A和5B是分别示意性地展示在根据本发明的第一实施方案中可利用的处理的剖面图。在图5A和5B中,在表面上设置有晶体管的半导体基板2上形成第一层间绝缘膜13。在第一层间绝缘膜13上设置沟,向该沟内埋入铜制的布线14。并在第一层间绝缘膜13和布线14上依次层叠分别设有开口的SiN膜16和第二层间绝缘膜23。
在图5A所示的结构中,布线14的一部分从SiN膜16和第二层间绝缘膜23上设置的开口内露出。因此,在含氧气氛中对图5A所示的结构进行热处理时,布线14的露出部分被氧化。针对这一点,在本方案中先进行上述热处理,然后如图5B所示,用含碳的等离子体10对布线14的露出部分进行表面处理。由此,可以防止因此后的热处理使布线14的表面氧化。因此,用本实施方案,可以防止裂纹和剥离的发生且简化制造工艺。
下面,说明上述的等离子体处理的一例。
通过向反应室内供给的原料气体采用含CO的气体的RIE产生等离子体10,用该等离子体10对布线14的露出部分表面处理。向反应室内供给的原料气体的流量为350sccm,反应室内的CO分压为50毫乇。等离子体功率为400W,采用等离子体10的表面处理,即等离子体处理进行10秒。
在该等离子体处理之后,用X射线电子光谱(以下称XPS)对布线14的表面进行成分分析。结果如下表所示。
在上述表中,“CuCO3”表示在布线14的表面区域中,形成CuCo3的碳原子相对于全部原子的浓度。“C-H键/C-C键”表示在布线14的表面区域中,形成C-H键的C原子和形成C-C键的C原子的总量相对于全部原子的浓度。而“共计”表示在布线14的表面区域中,碳原子相对于全部原子的浓度。
从上表明显可以看出,与未进行等离子体处理的场合相比,在进行了等离子体处理的场合表面区域中的碳原子浓度要高得多。这个结果表明,通过等离子体处理可向布线14的表面区域导入碳原子或含碳原子的物质。另外,即使在不进行等离子体处理的场合(“未处理”),布线14的表面区域也含有碳原子。这是因为布线14的表面区域被大气中存在的含碳元素的物质污染的缘故。另外,从上表可以明显看出,与不进行等离子体处理的场合相比,浓度“CuCO3”大幅度降低,浓度“C-H键/C-C键”大幅度增加。另外,在每种场合中都从布线14的表面区域检测出碳化铜。
然后,在大气中200℃温度下对等离子体处理后的布线14进行热处理,调查热处理时间与在布线14表面形成的氧化膜厚度的关系。另外,同样地,在大气中200℃温度下对等离子体处理前的布线14进行热处理,调查热处理时间与在布线14表面形成的氧化膜厚度的关系。
图6示出对图5A和5B所示的结构进行氧化处理时形成的氧化膜的厚度。图中,横轴是热处理时间,纵轴是氧化膜的厚度。另外,图中的曲线31示出进行等离子体处理时得到的数据,曲线32是不进行等离子体处理时得到的数据。
从图6可以明显地看出,不进行等离子体处理时,在热处理的开始和同时,开始形成氧化膜。相反地,在进行等离子体处理时,直到热处理开始后20分钟,还几乎未形成氧化膜。即,如果是20分钟以内的热处理,通过进行等离子体处理可以防止氧化膜的形成。
例如,可如下所述地说明得到的上述结果。
在例如200℃的热处理温度下,CO和CO2的吉布斯自由能比Cu2O的低。即,氧与碳结合比与铜结合更稳定。另外,与CuCO3相比,C-H键和C-C键与氧的反应性更强。
如上所述,通过进行等离子体热处理,可以大幅度提高布线14的表面区域中的“C-H键/C-C键”浓度。因此,进行了等离子体处理的情况下,在含氧的气氛中热处理时,在布线14的表面区域C-H键和C-C键优先与氧反应,结果抑制了铜的氧化。
因C-H键或C-C键与氧反应生成的CO和CO2在上述温度下是气体,从布线14表面迅速放到气氛中。因此,根据本实施方案,伴随着含氧气氛中的热处理,布线14的表面区域中的碳原子浓度低。因此,若采用本实施方案,通过适当地设定等离子体处理条件或上述热处理条件等,在上述热处理时可以消耗掉在布线14的表面区域中引入的C-H键或C-C键中的多数。即,若采用本实施方案,上述热处理后可以把布线14表面区域中的碳原子浓度抑制到十分低,而且,不会妨碍第一布线14和在其上形成的第二布线(图中未示出)之间的引线接触。
若用Ar溅射和XPS对实施等离子体处理的布线14的表面进行成分分析,结果表明在布线14的从表面到的区域内检测不出C-H键和C-C键。而且在该表面区域内不仅有C-H键和C-C键,还有铜。因此,若采用本实施方案,即使例如,在上述热处理后在布线14的表面区域中残留有C-H键或C-C键,也不会妨害第一布线14和在其上形成的第二布线(图中未示出)之间的引线接触。
在本实施方案中,上述抑制铜的氧化的效果,通常在“C-H键/C-C键”为30原子%以上时可以得到。另外,优选地,该“C-H键/C-C键”浓度在布线14的表面区域的铜原子的浓度以上。
另一方面,在布线14的表面区域,“C-H键/C-C键”浓度优选地为铜原子浓度的10倍以下。此时,一般地可以把上述热处理后的布线14的表面区域中的碳原子浓度抑制到十分低,而且,不会妨害第一布线14和在其上形成的第二布线之间的引线接触。
除了C-H键和C-C键以外,布线14的表面区域还含有其它形态的C原子。该表面区域可以含有例如,碳酸铜或碳酸铜之类的含有碳但又不含C-H键或C-C键的化合物。
“C-H键/C-C键”浓度与“共计”浓度的比值,优选为0.7以上,更优选为0.8以上,最优选为0.85以上。如上所述,与C-H键和/或C-C键相比,CuCO3之类的没有C-H键和/或C-H键的化合物与氧的反应性差。因此,在“C-H键/C-C键”浓度与“共计”浓度的比设定为如上所述时,抑制铜的氧化的效果比较显著。另外,上述等离子体处理或第四实施方案中说明的激光束照射后,通常,“C-H键/C-C键”浓度与“CuCO3”浓度的比为2倍以上。
下面,说明本发明的第二实施方案。
图7A~7C是分别示意性地展示根据本发明第二实施方案的半导体装置的制造工艺的剖面图。本实施方案的工艺,除了对焊盘进行上述等离子体处理外,与第一实施方案的工艺基本相同。
在图7A所示的结构中,在半导体基板2上形成层间绝缘膜13。在层间绝缘膜13上形成铜制的焊盘4,在层间绝缘膜13和焊盘4上形成绝缘膜23。在绝缘膜23上设置开口,焊盘4的一部分从该开口内露出。
在本实施方案中,如图7B所示,对焊盘4的露出部分用第一实施方案中说明的等离子体10处理。通过该处理,与第一实施方案中说明的同样地,向焊盘4的表面区域导入C-H键和C-C键。因此,如图7C所示,在大气中把Au引线8键合到焊盘4时可抑制焊盘4的氧化。
或者,在焊盘14上形成凸点时,用本实施方案通过等离子体处理可以防止焊盘4的氧化,所以无需用铝电极等覆盖焊盘4的露出部分。另外,在本实施方案中,焊盘4的表面区域不仅含有C-H键或C-C键还含有铜,所以不会妨害金和铜的合金化。因此,若采用本实施方案,可以防止裂纹和剥离的发生,且可以简化制造工艺。
下面,说明本发明的第三实施方案。
图8A~8E是分别示意性地展示根据本发明第三实施方案的半导体装置的制造工艺的剖面图。本实施方案的工艺,除了在形成层间绝缘膜23之前进行上述等离子体处理外,与第一实施方案的工艺基本相同。
本实施方案的工艺中,首先,在表面上形成了晶体管等的半导体基板2上形成第一层间绝缘膜13。然后,在层间绝缘膜13上形成布线用的沟,用溅射法等向该沟填埋以铜为主要成分的层。并用化学机械抛光(下称“CMP”)法除去铜层的位于沟外侧的部分,形成布线14。然后,用第一实施方案说明的等离子体10对布线14的表面进行处理。通过该处理,与第一实施方案说明的同样地,向布线14的表面区域导入C-H键或C-C键。由此得到图8A所示的结构。
然后,在层间绝缘膜13和布线14上堆积第二层间绝缘膜23。然后如图8B所示,在层间绝缘膜23上用光刻技术形成光刻胶图案5。通过以该光刻胶图案5作蚀刻掩模的RIE对层间绝缘膜23构图,得到图8C所示的结构。
然后,如图8D所示,通过在含氧11的气氛中灰化处理,除去光刻胶图案5。在该灰化时,与第一实施方案说明的同样地,向布线14的表面区域中导入的C-H键和C-C键防止铜的氧化。
然后,如图8E所示,用溅射法等在设置在层间绝缘膜23上的沟的底面和侧壁上形成阻挡金属层27,用铜层填埋该沟。并用CMP法除去铜层的位于沟外侧的部分,形成布线24。阻挡金属层27具有防止铜从布线24向层间绝缘膜23扩散的作用。
若采用本实施方案,可以得到与第一实施方案说明的同样的效果。另外,在本实施方案中,由于在形成层间绝缘膜23之前进行等离子体处理,在图8C所示的结构中,不仅布线14的从层间绝缘膜23上设置的开口内露出的部分而且布线14的被层间绝缘膜23覆盖的部分也导入了C-H键或C-C键。灰化时,向前者导入的C-H键和C-C键的至少一部分被消耗掉,而向后者导入的C-H键和C-C键未被消耗。因此,在图8E所示的结构中,位于两端的两个布线14的表面区域中的碳原子浓度比中央的布线14的表面区域的碳原子浓度高得多。
在上述第一到第三实施方案中,主要以采用CO气的RIE的等离子体处理为主进行了说明。若以比较长的时间如60秒进行该RIE,则在布线14或焊盘4上形成厚的非晶态碳层。此时,即使在400℃以上的高温氧化气氛中暴露布线14和焊盘4,也完全不发生铜的氧化。但是,在这种情况下,即使在氧化气氛中热处理后,非晶态碳层也会残留。因此,例如在Au引线8键合到焊盘4上时,会妨害金和铜的合金化,使Au引线8和焊盘4的连接成为不可能。另外,在多层布线结构中,由于布线14和布线24之间夹有非晶态碳层,增加了引线接触电阻。
通过进行采用CO气的RIE,并接着进行采用O2气的RIE,除去非晶态碳层的剩余部分,可以避免这种连接不良的发生和接触电阻的增大。例如,进行60秒的采用CO气的RIE,之后进行30秒的采用O2气的RIE时,可以防止铜的氧化、连接不良的发生以及接触电阻的增大。
另外,为了把布线14电气连接到焊盘4之外的目的进行氧化气氛中的热处理时,也可采用以下的方法。即,首先,在布线14和焊盘4上形成十分厚的非晶态碳层。然后,在氧化气氛中进行热处理。之后,通过采用O2气的RIE除去布线14和焊盘4上残留的非晶态碳层。这种方法对于在氧化气氛中进行400℃以上的高温下的热处理的场合是有效的。
在第一到第三实施方案中,作为等离子体的原料气体,可以使用含有CO、CO2、C2H4、C2H2、CH3OH、以及C2H5OH等的含碳化合物的气体。另外,若作为原料气体采用含有CF4、C4F8、和SF5等的含氟的化合物的气体对布线14进行RIE而处理时,在布线14的表面形成CuF2。在布线14的表面形成CuF2时,也可以抑制铜的氧化,可以与Au引线键合,且可把引线接触电阻降到十分低。
用上述原料气体生成等离子体时,除了RIE法,也可以利用例如等离子体CVD法、ECR法、光CVD法和热CVD法等。
上述等离子体处理和用于在层间绝缘膜23等上形成开口的RIE处理,在不存在氧时也可以连续地进行。通过例如,在上述等离子体处理中利用RIE时,在同一反应室内进行这些处理并改变向反应室内供给的气体成分等,可以实现这一点。
下面,说明本发明的第四实施方案。
图9是示意性地展示根据本发明第四实施方案的半导体装置的制造工艺的剖面图。
在图9所示的结构中,在半导体基板2上形成层间绝缘膜13。在层间绝缘膜13中埋入铜制的布线14,在层间绝缘膜13和布线14上形成层间绝缘膜23。在层间绝缘膜23上设置开口,布线14的一部分从该开口内露出。
除了用进行激光束照射取代等离子体处理,本实施方案的工艺与第一实施方案的工艺基本相同。
即,在本实施方案的工艺中,如图9所示,在大气中用激光束12照射布线14的露出部分。由此,可向布线14的表面区域中导入C-H键或C-C键。
下面,说明上述激光束照射的一例。
采用波长266nm的Q开关YAG第四谐波激光,在大气中向布线14的露出部分照射一个脉冲的激光束。脉冲宽度为5~10纳秒,每个脉冲的照射能量是1~2J/cm2。之后,用XPS对焊盘4的表面进行成分分析。
图10A和10B是用XPS测定图9所示的激光束照射后的焊盘4表面得到的Cls和Cu2p3谱线的图。图11A和11B是用XPS测定未照射激光束的焊盘4表面得到的Cls和Cu2p3谱线的图。图中,横轴是结合能,纵轴是强度。
从图10A、10B和图11A、11B得到的碳原子浓度标在上面的表中。
从上表可以明显看出,与未进行激光束照射的场合(“未处理”)相比,照射激光束时的表面区域中的碳原子浓度高得多。该结果表明,通过激光束照射向布线14的表面区域中导入的碳原子或含碳原子的物质。另外,从上表可以明显看出,与未进行激光束照射的场合(“未处理”)相比,照射激光束时的“CuCO3”浓度大幅度下降,而“C-H键/C-C键”浓度大幅度上升。即,与上述第一到三实施方案中说明的等离子体处理同样地,具有向布线14的表面区域中导入C-H键和C-C键的效果。
然后,在大气中200℃温度下对等离子体处理后的布线14进行热处理,调查热处理时间与在布线14表面形成的氧化膜厚度的关系。另外,同样地,在大气中200℃温度下对等离子体处理前的布线14进行热处理,调查热处理时间与在布线14表面形成的氧化膜厚度的关系。
图12示出对图9所示的结构进行氧化处理时形成的氧化膜的厚度。图中,横轴是热处理时间,纵轴是氧化膜的厚度。另外,图中的曲线31示出进行等离子体处理时得到的数据,曲线32是不进行等离子体处理时得到的数据。
从图12可以明显地看出,不进行等离子体处理时,在热处理的开始和同时开始形成氧化膜。相反地,在进行等离子体处理时,直到热处理开始后20分钟,还几乎未形成氧化膜。即,若采用本实施方案,可得到与第一实施方案中说明的同样的效果。另外,从图6的曲线31和图12的曲线33的比较可明显看出,通过照射激光束可以得到比等离子体处理更大的氧化防止效果。
下面,用透射电子显液镜(以下称TEM)观察进行激光束照射后的布线14。
图13A是示意地示出图9所示的激光束照射前的布线14的剖面图。图13B是示意地示出图9所示的激光束照射后的布线14的剖面图。图中,标号141表示晶界。
在上述激光束照射之前,通常,如图13A所示,布线14中的晶界141到达布线14的露出面。若进行上述激光束照射,通常,布线14的表面熔融并发生再结晶。该熔融/再结晶通常如图13B所示,在布线14的表面上形成凹凸结构,而且在以布线14表面到数千的区域内生长晶粒,结果,到达布线14的露出面的晶界141消失。因此,通过用TEM等研究布线14的表面结构和晶界等,可以判断对布线14进行的激光束照射是否完成。
在以上说明的第四实施方案中,通过在在大气中照射激光束向布线14的表面区域导入C-H键或C-C键,但在含有碳或碳化合物的气氛中进行激光束照射也可以得到同样的效果。
另外,在第四实施方案中虽然使用了波长266nm的Q开关YAG第四谐波激光,但也可以使用其它的激光。使用波长在紫外区的激光时,可以高效率地对气相中或布线14上的碳或碳化合物光分解,可向布线14的表面区域中高效率地导入C-H键或C-C键。这种激光可以举出例如,上述波长为266nm的Q开关YAG第四谐波激光、或波长248nm的KrF激态激光。用波长248nm的KrF激态激光对布线14照射一个脉冲的激光束时,可以是例如,脉冲宽度为10~30纳秒,照射能量为1~2J/cm2。另外,可以使用的激光或照射条件,不受上述限制,可进行种种变更。
而且,在第四实施方案中是为了向布线14的表面区域中导入C-H键或C-C键而利用大气中的激光束照射,但也可以是向焊盘4的表面区域中导入C-H键或C-C键而利用大气中的激光束照射。此时,可以得到与第二实施方案中说明的同样的效果。另外,上述激光束照射在氧化气氛中热处理前的任何时候都可以,例如,可以在形成绝缘膜23之前进行。
下面,说明本发明的第五实施方案。
图14A~14C是分别示意性地展示根据本发明第五实施方案的半导体装置的制造工艺的剖面图。
在图14A所示的结构中,在半导体基板2上形成层间绝缘膜13。在层间绝缘膜13上埋置铜制的焊盘4,在层间绝缘膜13和焊盘4上依次层积SiN膜6和绝缘膜23。在SiN膜6和绝缘膜23上设置开口。焊盘4的一部分从该开口内露出。
本实施方案的工艺,除了对进行下述处理以取代上述等离子体处理外,与第二实施方案的工艺基本相同。即,在本实施方案的工艺中,首先,准备如图14A所示的结构。然后,如图14B所示,在焊盘4涂敷含有含碳粒子35和溶剂36的溶液,形成涂膜37。并如图14C所示,对粒子35残留在焊盘4上的涂膜31干燥处理。之后,与第二实施方案说明的同样地进行键合。
这样地,在含碳粒子35附着在焊盘4上的状态下进行键合时,在粒子35的近傍抑制铜的氧化。因此,可以得到与第二实施方案说明的相同效果。这种效果可以从例如以下的试验结果来验证。
在铜制的焊盘4上涂敷在溶剂36中分散直径1μm~5μm的碳微粒35得到的溶液,形成涂膜37。然后,从涂膜37中挥发溶剂,碳微粒附着在焊盘4上。碳微粒35之间的平均距离为10μm以下。而且,在大气中200~350℃的温度下进行热氧化处理。结果表明,铜的氧化速度显著降低。
在以上说明的第五实施方案中,虽然是为防止焊盘4的氧化而利用粒子35,但也可以是为防止布线14的氧化而利用粒子35。这时,可以得到与第一和第三实施方案中说明的同样的效果。另外,参照图14B和14C说明的工序在氧化气氛中的热处理前的任何时候进行都可以,例如,也可以在形成绝缘膜23之前进行。
在本实施方案中,热氧化处理结束时粒子35可以完全消耗掉,也可以残留在焊盘4上。当热氧化处理后粒子35残留在焊盘4上时,也可以利用采用例如O2气等的RIE等除去这些粒子35。此时,对于防止成为高速动作处理用半导体装置的问题的布线间静电电容增大等是有利的。或者,当热氧化处理后粒子35残留在焊盘4上时,也可以不除去这些粒子35。由于在粒子35间的间隙处,铜可以与金合金化,所以可以把Au引线键合到焊盘4上。
在本实施方案中,粒子35可以是导电性的,也可以绝缘性的。在哪一种情况下,只要粒子35之间有间隙,An引线就可以与焊盘4直接接触,所以不会产生与表面电阻有关的问题。
另外,在本实施方案中,如上所述,由于涂敷含有粒子35和溶剂36的溶液,粒子35不仅附着在焊盘4上,还附着在绝缘膜23上。此时,即使粒子35是导电性的碳微粒,只在粒子35之间的间隙充分大,就不会发生电流泄露。
本实施方案中,通常地,附着在焊盘4上的粒子35的半径在约10μm以内的范围内时,可发挥防止铜氧化的作用。因此,如果附着在例如,焊盘4上的粒子35之间的距离为10μm以下,就可以防止焊盘4的整个表面上的铜的氧化。
在以上说明的第一到第五实施方案中,虽然说明了通过等离子体处理、激光束照射或涂敷向布线14或焊盘4的表面供给碳,但碳的供给方法并不仅限于这些。例如,也可以利用离子注入法或热扩散法等。
下面,说明本发明的第六实施方案。
图15A~15G是分别示意性地展示根据本发明第六实施方案的半导体装置的制造工艺的剖面图。在本实施方案的工艺中,首先如图15A所示,在半导体基板2上形成第一层间绝缘膜13。在本实施方案中,层间绝缘膜13是含有聚甲基硅氧烷的绝缘膜等的含碳的绝缘膜。
然后,在绝缘膜13上形成图中未示出的反射防止膜,在该反射防止膜上用光刻技术形成图中未示出的光刻胶图案。并通过以该光刻胶图案为蚀刻掩模的RIE对反射防止膜和绝缘膜13构图。然后用O2-RIE除去反射防止膜和光刻胶图案。通过以上方法,如图15B所示在绝缘膜13上形成沟。
然后,用溅射法形成例如TaN制的阻挡金属层17,覆盖在绝缘膜13上设置的沟和侧壁和底面。接着用电镀法用铜层填埋上述沟。并如图15C所示,用CMP法除去阻挡金属层17和铜层的位于沟外侧的部分,形成铜制的第一布线14。
然后,进行与第一到第三实施方案中说明的同样的等离子体处理。即,对绝缘膜13的形成阻挡金属层和布线14的面以采用含碳气体如CH4气作为原料气体的等离子体处理30秒钟。接着,通过采用SiH4和NH3气体作为原料气体的等离子体CVD法,如图15D所示在绝缘膜13上堆积例如SiN制的扩散防止膜16。
然后,如图15E所示,在扩散防止膜16上形成第二层间绝缘膜23。在本实施方案中,第二层间绝缘膜23和第一层间绝缘膜13同样地,也是诸如含有聚甲基硅氧烷的绝缘膜的含碳绝缘膜。
然后,通过与参照图15B说明的同样的方法,如图15F所示在绝缘膜23上形成布线用的沟,同时在绝缘膜23和扩散防止膜16上形成引线孔。为了形成引线孔而进行蚀刻时,布线14的露出面被氧化。此时,根据需要,用湿蚀刻等除去在布线14的表面上形成的氧化膜。
然后,通过与参照图15C说明的同样的方法,如图15G所示,形成例如TaN制的阻挡金属层27和铜制的第二布线24。由此可以得到图15G所示的二层布线结构。当布线的层叠数目为3以上时,可以再反复进行等离子体处理工序和参照图15D~15G说明的工序。
若采用上述工艺,先形成扩散防止膜16,然后绝缘膜13的形成阻挡金属层17和布线14的面进行含碳的等离子体表面处理。通过该等离子体处理,向绝缘膜13的表面区域中导入碳。因此,若采用本实施方案,可以抑制从绝缘膜13夺走有机成分,可以防止绝缘膜13的表面区域成为脆弱的变质层。
另外,在本实施方案中,与第一实施方案中说明的同样地,通过等离子体处理使布线14的表面区域还原的同时向布线14的表面区域中导入碳。因此,若采用本实施方案,即使在上述等离子体处理和形成扩散防止膜16之间,布线14暴露在氧化气氛中,也可以防止布线14的氧化。而且,实施过等离子体处理的布线14的表面区域,对于湿蚀刻有高的耐腐蚀性。
即,若采用本实施方案,可以同时减小布线电阻和布线间电容,防止剥离的发生,并可以简化制造工艺。
在上述第六实施方案中,层间绝缘膜13和23是诸如含有有机硅氧化物的膜或含有有机材料的膜的含碳绝缘膜。作为这样的有机硅氧化物,可举出例如聚甲基硅氧烷等。多数场合下,聚甲基硅氧烷之类的有机硅氧化物的介电率R小于3.0。因此,通过使用这样的材料可以减小布线间电容。
可以用例如下面说明的涂敷法得到绝缘膜13和23。以形成含聚甲基硅氧烷的绝缘膜13的情况为例进行说明。即,首先,在溶剂中溶解聚甲基硅氧烷得到漆状溶液,然后,用旋涂法等之类的涂敷法把该溶液涂在基板2上。并施行热处理,从涂膜挥发溶剂等的同时,把聚甲基硅氧烷固着在基板2上。由此,可得到绝缘膜13。
在该成膜方法中,作为上述热处理,也可以依次进行80℃×1分钟、200℃×1分钟、和420℃×30分钟的热处理。进行这种分阶段热处理时,可以从涂膜中均匀地挥发出溶剂。由此,可以提高绝缘膜13的表面平坦性。
另外,在上述成膜方法中,也可以在氮气氛之类的不活泼气氛中进行上述热处理。由此可以抑制聚甲基硅氧烷和气氛中含的物质发生不期望的反应。
图16A~16C是分别示意性地展示本发明第七实施方案的半导体装置的制造工艺的剖面图。本实施方案的艺是,首先实施在第六实施方案中参照图15A~15C说明的工序。由此,得到图16A所示的结构。
然后,进行与第一到第三实施方案中说明的同样的等离子体处理。即,以采用含碳气体如CH4气作为原料气体的等离子体对绝缘膜13的形成了阻挡金属层17和布线14的面进行处理30秒钟。根据一个例子,这样的等离子体处理后,布线14的表面区域中碳原子浓度为约38原子%,表面区域中的碳几乎都形成C-C键和C-H键。
之后,如图16B所示,在绝缘膜13上用涂敷法形成含有机材料的扩散防止膜16。例如,首先,在溶剂中溶解聚芳撑得到漆状溶液,然后,用旋涂法等之类的涂敷法把该溶液涂在绝缘膜13上。并施行热处理,从涂膜挥发溶剂等的同时,把聚芳撑固着在绝缘膜13上。由此,可得到扩散防止膜16。
在该成膜方法中,作为上述热处理,也可以依次进行800℃×1分钟、200℃×1分钟、和400℃×30分钟的热处理。另外,在上述成膜方法中,也可以在氮气氛之类的不活泼气氛中进行上述热处理。由此可以抑制聚甲基硅氧烷和气氛中含的物质发生不期望的反应。
在绝缘膜13上形成扩散防止膜16后,实施第六实施方案中参照图15E~15G说明的工序。如上所述,可得到图16C所示的二层布线结构。另外,布线的叠层数目在3以上时,可以再反复进行等离子体处理工序和参照图16B和16C说明的工序。
在本实施方案中进行与第六实施方案中进行的同样的等离子体处理。因此,与第六实施方案同样地,若采用本实施方案也可以减小布线电阻和布线间电容,防止剥离的发生,并可简化制造工艺。另外,在本实施方案中,由于扩散防止膜16和层间绝缘膜13和23的材料都是有机材料,它们之间密合性比较高。另外,与第六实施方案同样地,本实施方案中层间绝缘膜13和23也是含碳的绝缘膜,所以可减小布线间电容。
而且,如下所述,若采用本实施方案,也不局限于用涂敷法形成扩散防止膜16,可以防止布线14的氧化。通过在形成扩散防止膜16时进行的热处理,发生交联反应,生成反应副反物H2O。在有水的情况下加热时铜易氧化,本实施方案中由于在形成扩散防止膜14之前对布线14时行等离子体处理抑制了布线14的氧化。
另外,在本实施方案中由于在形成扩散防止膜16时采用涂敷法,与利用CVD法等的场合相比,可以减少设备费和处理时间等。形成扩散防止膜16时可以采用涂敷法的主要理由是通过上述等离子体处理可以防止布线14的氧化。
在上述第六和第七实施方案中虽然说明了用涂敷法形成层间绝缘膜13和23,但也可以用等离子体CVD法等形成层间绝缘膜13和23。例如,也可以通过采用含三甲基硅烷((CH3)3SiH)或四甲基硅烷((CH3)4Si)等的有机硅烷的气体和含O2或N2O等的氧化性气体的等离子体CVD法形成层间绝缘膜13和23。通常这样的方法得到的膜具有低介电率。
另外,虽然在上述第六和第七实施方案中,作为层间绝缘膜13和23的材料采用了聚甲基硅氧烷等的有机硅氧化物,但层间绝缘膜13和23并不特别限于含有机材料的绝缘膜之类的含碳的绝缘膜。例如,作为层间绝缘膜13和23的材料,也可以使用在聚芳撑、聚芳醚和聚酰胺等的骨架中含有碳原子的物质。通常用这些材料得到的膜具有低介电率。
而且,在第六和第七实施方案中,虽然进行的是采用含甲烷(CH4)的气体的等离子体处理,但也可以进行采用其它气体的等离子体处理。例如,可以用含有含碳化合物的气体。在使用这样的气体中的、含有乙烷(C2H6)或丙烷(C3H8)之类的含碳和氢的化合物的气体时,可以得到与使用含甲烷的气体时同样的效果。
在第六实施方案中,虽然通过采用SiH4气和NH3气作为原料气体的等离子体CVD法形成扩散防止膜16,但作为原料气体也可以采用其它气体。作为扩散防止膜16,也可以通过采用含例如三甲基硅烷((CH3)3SiH)或四甲基硅烷((CH3)4Si)等的有机硅的气体和氧化性气体的等离子体CVD法,形成SiCH膜或SiCHO膜。
另外,在第七实施方案中,虽然作为扩散防止膜16用涂敷法形成了含聚芳撑的绝缘膜,但也可以取代而采用其它的材料。例如,可以用聚醚等的含碳和氢的化合物。
本领域技术人员可以很容易地想到其它优点和变更。因此,本发明的范围并不仅限于在此描述的细节和代表性的实施方案,在不背离所附权利要求书限定的总的发明构思和其等同物的范围和精神的前提下,可以做出种种变更。
Claims (17)
1. 一种半导体装置的制造方法,包括下列步骤:
在半导体基板上形成含有铜的第一导电层;
向所述第一导电层的表面提供含有碳的物质;以及
在残留有基于所述含有碳的物质导入的碳的所述第一导电层的表面上形成第二导电层,所述第一和第二导电层在上述残留有碳的表面上相互接触。
2. 如权利要求1所述的方法,其中:在供给所述含有碳的物质的步骤和形成所述第二导电层的步骤之间,还具有在含有氧的气氛中暴露所述第一导电层的步骤。
3. 如权利要求1所述的方法,其中:所述第二导电层的形成在含有氧的气氛中进行。
4. 如权利要求1所述的方法,其中还包括下列步骤:
在形成所述第一导电层之前,在所述半导体基板上形成第一绝缘层,在它们之间夹着所述第一绝缘层向所述半导体基板上形成所述第一导电层;
在所述第一导电层上形成第二绝缘层;
在所述第二绝缘层上形成光刻胶图案;
把所述光刻胶图案用作蚀刻掩模,通过蚀刻对所述第二绝缘层构图,露出所述第一导电层的表面的一部分;以及
在所述蚀刻之后去除所述光刻胶图案,并在除去所述光刻胶图案之后形成所述第二导电层。
5. 如权利要求4所述的方法,其中:在形成所述第二绝缘膜之前供给所述含有碳的物质。
6. 如权利要求4所述的方法,其中:在所述蚀刻之后供给所述含有碳的物质。
7. 如权利要求6所述的方法,其中:在一个反应室内连续地进行所述含有碳的物质的供给和所述蚀刻。
8. 如权利要求1所述的方法,其中:所述物质的供给包括用含有碳的等离子体对所述第一导电层的表面进行处理。
9. 如权利要求1所述的方法,其中:所述物质的供给包括在含有碳的气氛中用激光束照射所述第一导电层的所述表面。
10. 如权利要求1所述的方法,其中:所述含有碳的物质的供给包括在所述第一导电层的所述表面上形成含有碳的膜;以及用蚀刻部分地除去所述含有碳的膜。
11. 如权利要求1所述的方法,其中:所述含有碳的物质的供给包括在所述第一导电层的所述表面上涂敷含有溶剂和粒子的溶液而形成涂膜,每个所述粒子都含有碳且分散在所述溶剂中;以及使所述粒子残留在所述第一导电层的所述表面上,且使所述涂膜干燥。
12. 一种半导体装置的制造方法,包括下列步骤:
在含有碳的第一绝缘层上形成导电层,所述绝缘层设在半导体基板上;
对所述导电层和所述绝缘层的露出面进行含碳的等离子体处理;以及
在所述处理后在所述导电层和所述第一绝缘层上形成第二绝缘层。
13. 如权利要求12所述的方法,其中:所述等离子体还含有氢。
14. 如权利要求12所述的方法,其中:所述第一绝缘层具有有机硅氧化物。
15. 如权利要求12所述的方法,其中:所述第二绝缘层具有有机材料。
16. 如权利要求12所述的方法,其中:用涂敷技术形成所述第二绝缘层。
17. 如权利要求12所述的方法,其中:
所述导电层是第一布线,且该方法还包括下列步骤:
在所述第二绝缘层上形成第三绝缘层;
在所述第二绝缘层上和所述第三绝缘层上形成孔,所述第一布线的表面的一部分从所述孔内露出;以及
在所述第三绝缘层上形成第二布线,所述第二布线通过所述孔与所述第一布线电气连接。
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JP2001218528A JP2003031580A (ja) | 2001-07-18 | 2001-07-18 | 半導体装置の製造方法 |
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KR (2) | KR100443028B1 (zh) |
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JP2004247675A (ja) * | 2003-02-17 | 2004-09-02 | Renesas Technology Corp | 半導体装置の製造方法 |
JP2004311924A (ja) * | 2003-03-26 | 2004-11-04 | Seiko Epson Corp | 強誘電体キャパシタおよびその製造方法、強誘電体メモリ、圧電素子。 |
JP2005167081A (ja) * | 2003-12-04 | 2005-06-23 | Renesas Technology Corp | 半導体装置およびその製造方法 |
US20070072413A1 (en) * | 2005-09-23 | 2007-03-29 | Seung-Man Choi | Methods of forming copper interconnect structures on semiconductor substrates |
WO2008111125A1 (ja) * | 2007-03-13 | 2008-09-18 | Fujitsu Limited | 半導体装置および半導体装置の製造方法 |
US9385034B2 (en) * | 2007-04-11 | 2016-07-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Carbonization of metal caps |
US7977798B2 (en) * | 2007-07-26 | 2011-07-12 | Infineon Technologies Ag | Integrated circuit having a semiconductor substrate with a barrier layer |
US20090223700A1 (en) * | 2008-03-05 | 2009-09-10 | Honeywell International Inc. | Thin flexible circuits |
US20150206798A1 (en) * | 2014-01-17 | 2015-07-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect Structure And Method of Forming |
CN103839604A (zh) * | 2014-02-26 | 2014-06-04 | 京东方科技集团股份有限公司 | 导电膜及其制备方法、阵列基板 |
US20150340611A1 (en) * | 2014-05-21 | 2015-11-26 | Sony Corporation | Method for a dry exhumation without oxidation of a cell and source line |
US9412658B2 (en) * | 2014-09-19 | 2016-08-09 | International Business Machines Corporation | Constrained nanosecond laser anneal of metal interconnect structures |
US9460959B1 (en) * | 2015-10-02 | 2016-10-04 | Applied Materials, Inc. | Methods for pre-cleaning conductive interconnect structures |
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KR20230023492A (ko) * | 2021-08-10 | 2023-02-17 | 엘지이노텍 주식회사 | 회로기판 및 이를 포함하는 패키지 기판 |
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US6828684B2 (en) | 2004-12-07 |
US20020050647A1 (en) | 2002-05-02 |
US20030181041A1 (en) | 2003-09-25 |
KR100511039B1 (ko) | 2005-08-30 |
KR20040047759A (ko) | 2004-06-05 |
KR100443028B1 (ko) | 2004-08-07 |
TW523792B (en) | 2003-03-11 |
US6566261B2 (en) | 2003-05-20 |
KR20020019887A (ko) | 2002-03-13 |
CN1343006A (zh) | 2002-04-03 |
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