CN100397627C - 电路装置及其制造方法 - Google Patents

电路装置及其制造方法 Download PDF

Info

Publication number
CN100397627C
CN100397627C CNB2005100525405A CN200510052540A CN100397627C CN 100397627 C CN100397627 C CN 100397627C CN B2005100525405 A CNB2005100525405 A CN B2005100525405A CN 200510052540 A CN200510052540 A CN 200510052540A CN 100397627 C CN100397627 C CN 100397627C
Authority
CN
China
Prior art keywords
sealing resin
substrate
circuitry substrate
conductive pattern
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB2005100525405A
Other languages
English (en)
Other versions
CN1755919A (zh
Inventor
新井一正
久保田裕
五十岚优助
西塔秀史
茂木昌巳
坂本则明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Northeast Sanyo Semi-Conductive Co Ltd
Sanyo Electric Co Ltd
Original Assignee
Northeast Sanyo Semi-Conductive Co Ltd
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Northeast Sanyo Semi-Conductive Co Ltd, Sanyo Electric Co Ltd filed Critical Northeast Sanyo Semi-Conductive Co Ltd
Publication of CN1755919A publication Critical patent/CN1755919A/zh
Application granted granted Critical
Publication of CN100397627C publication Critical patent/CN100397627C/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • AHUMAN NECESSITIES
    • A47FURNITURE; DOMESTIC ARTICLES OR APPLIANCES; COFFEE MILLS; SPICE MILLS; SUCTION CLEANERS IN GENERAL
    • A47JKITCHEN EQUIPMENT; COFFEE MILLS; SPICE MILLS; APPARATUS FOR MAKING BEVERAGES
    • A47J27/00Cooking-vessels
    • A47J27/02Cooking-vessels with enlarged heating surfaces
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565Moulds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293Organic, e.g. plastic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49517Additional leads
    • H01L23/49531Additional leads the additional leads being a wiring board
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/28Applying non-metallic protective coatings
    • H05K3/285Permanent coating compositions
    • AHUMAN NECESSITIES
    • A47FURNITURE; DOMESTIC ARTICLES OR APPLIANCES; COFFEE MILLS; SPICE MILLS; SUCTION CLEANERS IN GENERAL
    • A47JKITCHEN EQUIPMENT; COFFEE MILLS; SPICE MILLS; APPARATUS FOR MAKING BEVERAGES
    • A47J27/00Cooking-vessels
    • A47J27/002Construction of cooking-vessels; Methods or processes of manufacturing specially adapted for cooking-vessels
    • AHUMAN NECESSITIES
    • A47FURNITURE; DOMESTIC ARTICLES OR APPLIANCES; COFFEE MILLS; SPICE MILLS; SUCTION CLEANERS IN GENERAL
    • A47JKITCHEN EQUIPMENT; COFFEE MILLS; SPICE MILLS; APPARATUS FOR MAKING BEVERAGES
    • A47J36/00Parts, details or accessories of cooking-vessels
    • A47J36/02Selection of specific materials, e.g. heavy bottoms with copper inlay or with insulating inlay
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135Double encapsulation or coating and encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0103Zinc [Zn]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01047Silver [Ag]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/157Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19041Component type being a capacitor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/30107Inductance
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3511Warping
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0271Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/05Insulated conductive substrates, e.g. insulated metal substrate
    • H05K1/056Insulated conductive substrates, e.g. insulated metal substrate the metal substrate being covered by an organic insulating layer
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0203Fillers and particles
    • H05K2201/0206Materials
    • H05K2201/0209Inorganic, non-metallic particles
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/06Thermal details
    • H05K2201/068Thermal details wherein the coefficient of thermal expansion is important
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03Metal processing
    • H05K2203/0315Oxidising metal
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/28Applying non-metallic protective coatings
    • H05K3/284Applying non-metallic protective coatings for encapsulating mounted components
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S220/00Receptacles
    • Y10S220/912Cookware, i.e. pots and pans

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Food Science & Technology (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

一种电路装置及其制造方法,可抑制密封树脂(14)的硬化收缩引起的混合集成电路装置(10)的挠曲。混合集成电路装置(10)包括:导电图案(13),其设在电路衬底(11)的上面;电路元件(14),其固定在导电图案(13)上;金属细线(15),其电连接电路元件(14)和导电图案;引线(16),其与导电图案(13)连结构成输出或输入,并向外部延伸;密封树脂(14),其由热硬性树脂构成,使电路衬底(11)的至少下面露出,利用传递模模制进行覆盖。这里,通过使密封树脂(14)的热膨胀系数小于电路衬底(11)的热膨胀系数,可防止后处理工序中电路衬底11的挠曲。

Description

电路装置及其制造方法
技术领域
本发明涉及电路装置及其制造方法,尤其是涉及降低了密封树脂的热硬化引起的衬底的挠曲的电路装置及其制造方法。
背景技术
参照图7说明现有混合集成电路装置100A的结构。
参照图7(A),说明现有混合集成电路装置100的结构。在矩形衬底101的上面介由绝缘层102形成有导电图案103。通过在导电图案103的所希望的部位固定电路元件,形成规定的电路。这里,作为电路元件半导体元件105A及片状元件105B与导电图案103连接。半导体元件105A的下面介由焊锡等接合材料106固定在导电图案103上。片状元件105B两端的电极介由接合材料106固定在导电图案103上。引线104连接在形成于衬底101的周边部的导电图案103上,作为外部端子起作用。
但是,在上述混合集成电路装置100A中,存在因温度变化引起的应力在接合材料106上产生裂纹的问题。以片状元件105B为例说明该问题,在以铝为衬底101的材料的情况下,衬底101的热膨胀系数为23×10-6/℃。与此相对,片状元件105的热膨胀系数小。具体地说,片状电阻的热膨胀系数为7×10-6/℃,片状电容器的热膨胀系数为10×10-6/℃。因此,片状元件105B和衬底101的热膨胀系数差异很大,故在温度变化时,结合两者的接合材料106上会作用很大的应力。因此,在接合材料106上产生裂纹,发生连接不良的问题。
参照图7(B)说明抑制接合材料106的裂纹的结构(参照下述专利文献1)。这里,片状元件105B和接合材料106被被覆树脂108覆盖。这里,被覆树脂108的热膨胀系数与由铝构成的衬底101的热膨胀系数(23×10-6/℃)大致相等。由此,热膨胀系数小的片状元件105B被和铝衬底101热膨胀系数实质上相等的被覆树脂108包围,从而可降低温度变化时施加在接合材料106上的应力。
在图7(C)所示的混合集成电路装置100C中,利用具有近似于衬底101的热膨胀系数的密封树脂109整面覆盖衬底101的上面及侧面。这里,密封树脂109由传递模模制形成。
专利文献1:特开平5-102645号公报。
但是,使用近似于衬底101的热膨胀系数的密封树脂109整面密封衬底101的上面时,因密封树脂109的硬化收缩会产生衬底101挠曲的问题。这是由于当增大密封树脂109的热膨胀系数时,热硬化时硬化收缩的量也会增大。尤其是在衬底101的平面尺寸大于或等于6cm×4cm时,该挠曲的问题会显著发生。并且,如图7(C)所示,在衬底101的下面自密封树脂109露出的情况下,由于向衬底101的上方作用很大的收缩应力,故会对衬底101作用很强的弯曲应力。由于装置整体大幅度挠曲,还会产生不能使装置接触散热片等散热体的问题。
发明内容
本发明的电路装置包括:导电图案,其设在电路衬底的上面;电路元件,其与所述导电图案电连接;密封树脂,其至少覆盖所述电路衬底的上面,密封所述电路元件,其特征在于,所述密封树脂的热膨胀系数在填充了填充物的状态下在15×10-6/℃~23×10-6/℃的范围内,所述电路衬底以向下面侧凸出而弯曲的状态由所述密封树脂覆盖。
在本发明的电路装置中,所述电路衬底的下面自所述密封树脂露出。
在本发明的电路装置中,所述密封树脂通过传递模模制形成。
在本发明的电路装置中,所述电路元件介由无铅焊锡固定在所述导电图案上。
在本发明的电路装置中,所述电路衬底的上面整个面及侧面通过所述密封树脂一体覆盖。
本发明的电路装置的制造方法包括:将由导电图案及电路元件构成的电路形成于电路衬底的上面的工序;为覆盖所述电路元件,用混入了填充物的密封树脂至少覆盖所述电路衬底的上面的工序,其特征在于,在所述覆盖工序使用的所述密封树脂的热膨胀系数在填充了填充物的状态下在15×10-6/℃~23×10-6/℃的范围内,所述电路衬底以向下面侧凸出而弯曲的状态由所述密封树脂覆盖。
另外,本发明的电路装置的制造方法的特征在于,其包括:将由导电图案及电路元件构成的电路形成于电路衬底的上面的工序;为覆盖所述电路元件,用热膨胀系数在15×10-6/℃~23×10-6/℃范围内的、混入了填充物的密封树脂至少覆盖所述电路衬底的上面的工序;在通过加热所述密封树脂所述电路衬底向下面方向弯曲为凸状的状态下,使所述密封树脂硬化的工序;在使所述电路衬底的弯曲降低的状态下,使所述密封树脂或所述电路衬底的下面与散热体的表面接触的工序。
在本发明的电路装置的制造方法中,所述密封树脂是通过传递模模制形成的热硬性树脂。
在本发明的电路装置的制造方法中,所述电路衬底由铝构成。
本发明的电路装置的制造方法如下,准备形成有以铜为主材料的导电图案的铝或铜的衬底,将电路元件安装在所述衬底上,用传递模模制树脂,以覆盖所述衬底的至少上面,其特征在于,在15×10-6/℃~23×10-6/℃的范围内选择混入了填充物的树脂的热膨胀系数,使所述模制时所述树脂的硬化收缩被抑制,硬化后衬底下面稍向下凸。
通常,在考虑应力时,液状或流动状的密封树脂硬化形成固体时的硬化收缩和硬化后树脂的热引起的膨胀收缩要分别考虑。
如图7(B)所示,考虑到密封树脂的膨胀收缩,最好衬底101和被覆树脂108热膨胀系数实质上相等。由此,压缩力总是施加在焊锡上,且衬底的伸缩和密封树脂的伸缩一致,故应力难于施加在焊锡上。在如图7(B)所示,液状或流动状的密封树脂局部涂敷硬化形成固体时,与此收缩力相对,衬底的刚性足够强,故不需要考虑挠曲的问题。
但是,当考虑密封树脂的硬化收缩时,如图7(C)所示,被覆的树脂的量(体积)越多,密封树脂的硬化收缩带来的影响越大。且由于该收缩力较大,故会产生衬底的挠曲。
为了抑制该挠曲,在本申请中,树脂的热膨胀系数选择实质上与铝衬底相同的材料,为了抑制收缩,混入了约80%左右的填充物。该填充物本来就是固体,不存在硬化收缩,故密封树脂整体的硬化时的收缩减小。且以硬化后的加入了填充物的树脂考虑时,热膨胀系数最好为约15×10-6/℃~23×10-6/℃的范围。
总之,为了抑制硬化时的收缩只要添加填充物即可,且硬化后的填充了填充物的密封树脂的热膨胀系数最好接近铝衬底。但是,考虑到硬化收缩量,密封树脂的热膨胀系数比铝小一些可与衬底的膨胀收缩取得平衡。
在本发明中,由于使用热膨胀系数比电路衬底小一些的添加了填充物的密封树脂,故可降低形成密封树脂时产生的硬化收缩。因此,可防止密封树脂的硬化收缩导致的剥离等。且可抑制装置整体的挠曲。
另外,根据本发明的电路装置的制造方法,可利用密封树脂的硬化收缩使电路衬底向下面方向弯曲一些,使密封树脂或电路衬底与散热体接触。因此,可使密封树脂或电路衬底的下面与散热体密切接触,可提高散热性能。
附图说明
图1是本发明混合集成电路装置的立体图(A),剖面图(B),剖面图(C);
图2是表示密封树脂的热膨胀系数和衬底的挠曲的关系的曲线图(A),混合集成电路装置的剖面图(B),混合集成电路装置的剖面图(C);
图3(A)~(D)是表示本发明混合集成电路装置的制造方法的剖面图;
图4是表示本发明混合集成电路装置的制造方法的剖面图(A)、剖面图(B);
图5是表示本发明混合集成电路装置的制造方法的剖面图;
图6是表示本发明混合集成电路装置的制造方法的剖面图(A)、剖面图(B);
图7(A)~(C)是现有混合集成电路装置的剖面图。
具体实施方式
混合集成电路装置10的结构
参照图1说明本发明的混合集成电路装置10的结构。首先,在矩形电路衬底11的上面形成有绝缘层18。规定形状的导电图案13形成于绝缘层18的表面上。另外,在导电图案13的规定部位电连接有半导体元件15A及片状元件15B。形成于电路衬底11上面的导电图案13、半导体元件15A及片状元件15B被密封树脂14覆盖。
电路衬底11是由铝或铜等金属构成的衬底。在电路衬底11的材料采用铝时,电路衬底11的热膨胀系数是23×10-6/℃左右。电路衬底11的具体尺寸例如为纵×横×厚=61mm×42.5mm×1.5mm左右。
电路衬底11的侧面由第一倾斜部S1及第二倾斜部S2构成,向外部突出。第一倾斜部S 1自电路衬底11的上面连续向斜下方延伸。第二倾斜部S2自电路衬底11的下面连续向斜上方延伸。利用该结构可使电路衬底11的侧面和密封树脂的附着牢固。另外,电路衬底11的侧面也可以是平坦面。
在电路衬底11的上面及下面形成有第一氧化膜12A及第二氧化膜12B。
第一氧化膜12A覆盖电路衬底11的整个上面而形成。具体地说,第一氧化膜12A的组成式为Al2O3,厚度范围为1μm~5μm。通过在电路衬底11的上面形成第一氧化膜12A可提高绝缘层18的附着性能。在本实施例中,第一氧化膜12A形成得非常薄。因此,可将半导体元件15A等产生的热高效率地排出到外部。第一氧化膜12A的厚度只要可确保绝缘层18和电路衬底11的附着性能,则也可以等于或小于1μm。
第二氧化膜12B覆盖电路衬底11的整个下面而形成。第二氧化膜12B与第一氧化膜12A同样由Al2O3构成,厚度范围为7μm~13μm左右。第二氧化膜12B在各制造工序中具有机械性保护电路衬底11的下面的作用。另外,第二氧化膜12B在利用湿式蚀刻构图导电图案13的工序中,具有保护电路衬底11的下面不受蚀刻剂影响的作用。因此,第二氧化膜12B比第一氧化膜12A厚。通过加厚第二氧化膜12B,还可降低密封树脂14的硬化收缩引起的电路元件15的挠曲。
绝缘层18覆盖电路衬底11的整个上面而形成。绝缘层18由高浓度充填了Al2O3等填充物的环氧树脂构成。通过充填填充物降低了绝缘层18的热阻抗。因此,自内装的电路元件产生的热介由电路衬底11被良好地排出外部。
导电图案13由铜等金属构成,形成于绝缘层18的表面上,实现规定的电路。在导出引线16的边形成由导电图案13构成的焊盘。
半导体元件15A及片状元件15B等电路元件介由焊锡等接合材料固定在导电图案13的规定部位。半导体元件15A采用晶体管、LSI芯片、二极管等。这里,半导体元件15A和导电图案13介由金属细线17连接。片状元件15B采用片状电阻或片状电容器等。片状元件15B两端的电极介由焊锡等接合材料固定在导电图案13上。另外,片状元件15B采用电感、热敏电阻、天线、振荡器等两端具有电极部的元件。另外,树脂密封型封装等也可以作为电路元件固定在导电图案13上。
结合电路元件的接合材料采用焊锡或导电性膏等。这里,焊锡可使用铅共晶焊锡或无铅焊锡。导电性膏采用Ag膏、Cu膏等。
使用无铅焊锡固定电路元件时必须留意热应力引起的裂纹的产生。其理由是无铅焊锡是拉伸弹性模量大且容易产生裂纹的材料。作为一例,铅共晶焊锡的拉伸弹性模量为25.8GPa,与此相对,具有Sn-3.0Ag-0.5Cu组成的无铅焊锡的拉伸弹性模量为41.6GPa。无铅焊锡具体可采用Sn-Ag系、Sn-Ag-Cu系、Sn-Cu系、Sn-Zn系或在它们中添加Bi或In的组成的焊锡。
引线16固定在设于电路衬底11的周边部的焊盘上,具有和外部进行输入输出的作用。这里,在一个边上设有多个引线16。引线16也可从电路衬底11的4边导出,也可从相对的两个边导出。
密封树脂14通过使用热硬性树脂的传递模模制形成。在图1(B)中,利用密封树脂14密封导电图案13、半导体元件15A、片状元件15B、金属细线17。电路衬底11的上面及侧面由密封树脂14覆盖。电路衬底11的下面自密封树脂14露出外部。另外,如图1(C)所示,也可以由密封树脂14覆盖包括下面的电路衬底11整体。由热硬性树脂构成的密封树脂14硬化时收缩,故会持续向电路元件及焊锡等作用压缩应力。
在本实施例中,选择与电路衬底11的热膨胀系数实质上相同的密封树脂,并在其中添加氧化铝等填充物,从而减少树脂自身的体积,由此抑制树脂硬化时的收缩。例如将约80%重量的填充物混入密封树脂14。
由于衬底是在两侧用螺丝等加压安装,故硬化后,常温下如图2B所示必须是多少向下凸的形状。
在本实施例中,加入填充物的密封树脂14的热膨胀系数小于电路衬底11的热膨胀系数。由此,可降低密封树脂14的硬化收缩引起的电路衬底11的挠曲。且可使硬化后的电路衬底11向下凸一些。而且,由于使安装时的热引起的密封树脂14的伸缩尽可能接近电路衬底11,故可抑制焊料等的裂纹。
如在背景技术中说明的,在采用铝衬底作为电路衬底11时,电路衬底11和片状元件15B的热膨胀系数相差很大。因此,会有很大的热应力作用在连接两者的焊锡上。因此,通过使密封树脂14的热膨胀系数为与电路衬底11同等的23×10-6/℃左右,降低了热应力。
但是,热硬性树脂在硬化时收缩起作用。因此,在使用具有大于或大于23×10-6/℃的热膨胀系数的密封树脂14时,热硬化引起的收缩量会增大,有时会产生电路衬底11过度挠曲的问题。
因此,在本实施例中,加入填充物抑制硬化时的收缩,含有填充物的密封树脂14的热膨胀系数设定在15×10-6/℃~23×10-6/℃之间。由此,可确保电路元件的连接可靠性,同时可防止热硬化时电路衬底11的挠曲。根据实验,当按上述范围使用添加了填充物的树脂的热膨胀系数时,与密封树脂14的热膨胀系数为23×10-6/℃的情况相比,可使电路元件15的连接可靠性为相同程度。且可降低本装置的挠曲。
参照图2说明密封装置4的热膨胀系数和混合集成电路装置10的挠曲的关系。图2(A)是表示两者的关系的曲线图。图2(B)及图2(C)是挠曲状态的混合集成电路装置10的剖面图。
图2(A)所示的曲线的横轴表示添加了填充物的密封树脂14的热膨胀系数。纵轴表示混合集成电路装置10的挠曲量。这里,调节填充物的混入量,使用不同热膨胀系数的密封树脂14进行多个混合集成电路装置10的树脂密封及加热硬化,测定了各混合集成电路装置10产生的挠曲量。具体的挠曲量的计测方法是:首先将结束加热硬化的混合集成电路装置10载置在平坦面上。然后,计测混合集成电路装置10的上面的高度,将其高低差作为混合集成电路装置10的挠曲的量。空白的圆所示的各点表示实验结果。虚线曲线是由这些实验结果算出的近似曲线L。
从曲线所示的实验结果可知,当使用热膨胀系数大的密封树脂(填充物少的)时,混合集成电路装置10的挠曲量大。例如当使用热膨胀系数为15×10-6/℃左右的密封树脂(填充物多的)14时,可得到未发生挠曲的平坦的混合集成电路装置10。另外,随着密封树脂14的热膨胀系数增加,装置产生的挠曲量也增加。
在密封树脂14的热膨胀系数等于或大于15×10-6/℃时,挠曲量为正值,随着热膨胀系数的增加,混合集成电路装置10的挠曲增大。在挠曲量为正值时,形成图2(B)所示的断面形状。即,内装于混合集成电路装置10的电路衬底11向下面方向弯曲。且装置整体弯曲成向下方凸状。若为该断面形状,则通过将装置两端向下方按压可使装置整体平坦。
具体地说,参照图1(A),通过在密封树脂14的周边部设置固定部26,利用小螺钉等固定装置将该固定部26向下方按压,可使混合集成电路装置10整体平坦化。
在加入了填充物的密封树脂14的热膨胀系数等于或小于15×10-6/℃时,挠曲量为负值。在挠曲量为负值时,混合集成电路装置10的断面形状形成图2(C)所示的状态。也就是说,装置整体相对于上方凸状弯曲。在该状态下,即使将装置的两端向下方按压,装置整体也不会平坦。即使使混合集成电路装置10的下面与散热片等接触,两者之间也会形成间隙。因此,混合集成电路装置10的散热性能降低。
在本实施例中,将加入了填充物的密封树脂14的热膨胀系数设定在15×10-6/℃~23×10-6/℃的范围内。
通过使密封树脂14的热膨胀系数等于或小于23×10-6/℃,可使混合集成电路装置10的挠曲量等于或小于一定量。具体地说,可使该挠曲量等于或小于50μm。并且,通过加入填充物可减小硬化收缩引起的应力。因此,可抑制装置内部的电路因硬化收缩而被破坏的现象。而且,由于硬化后的温度变化导致的密封树脂14的伸缩与电路衬底11同等,故可提高可靠性。尤其是,由于在焊锡等焊料构成的连接部总是作用压缩应力,故可抑制产生裂纹的现象。
另外,通过使添加了填充物的密封树脂14的热膨胀系数等于或大于15×10-6/℃,可抑制混合集成电路装置10向上凸状弯曲的现象。也就是说,可抑制混合集成电路装置10的断面形状形成图2(C)所示的形状。当产生图2(C)所示的挠曲时,装置下面不会与散热体密切接触,散热性能降低。
混合集成电路装置10的制造方法
参照图3~图6说明混合集成电路装置的制造方法。
参照图3(A),首先介由绝缘层18将导电箔20贴附在金属衬底19的上面。在金属衬底19的上面整面形成第一氧化膜12A。因此,使第一氧化膜12A和绝缘层18电结合,由此,绝缘层18和金属衬底19粘接。另外,通过进行湿式蚀刻,对导电箔20进行构图,形成导电图案13。导电箔20的蚀刻是将金属衬底19整体浸渍于蚀刻剂中进行的。
图3(B)显示形成导电图案13后的金属衬底19的剖面。这里,在金属衬底19的上面形成多个由导电图案13构成的单元21。在此,单元是指构成一个混合集成电路装置的部位。单元21也可以矩阵状形成多个。
参照图3(C),然后在金属衬底19的上面及下面形成第一槽22A及第二槽22B。第一槽22A及第二槽22B使用高速旋转的切割锯形成。
参照图3(D),然后将电路元件电连接在导电图案13上。这里,半导体元件15A及片状元件15B等电路元件介由焊锡等被固定在导电图案13上。另外,半导体元件15A表面的电极介由金属细线与导电图案13电连接。半导体元件15A也可以载置于固定在导电图案13上的散热片25的上面。
下面参照图4说明分离金属衬底19的工序。分离金属衬底19的方法可采用折曲分割方法和切断分割方法两种方法。
参照图4(A),说明利用折曲分离金属衬底19的方法。在此,以形成有第一槽22A及第二槽22B的部位为支点,折曲金属衬底19。在该图中,固定纸面上位于右侧的单元21,折曲位于左侧的单元21。通过将该折曲上下方向进行多次,使单元21相互之间分离。在本实施例中,在单元21相互之间的边界形成有第一及第二槽22A、22B。因此,各单元21仅由未形成槽的厚度部分连结。因此,由上述折曲进行的分离可容易地进行。
参照图4(B)说明由切断进行的金属衬底19的分离方法。这里,通过将切割刀23按压在第一槽22A并使其旋转分割金属衬底19。切割刀23具有圆板状的形状,其周端部形成锐角。切割刀23的中心部固定在支承部24上,使切割刀23可自由旋转。也就是说,切割刀23不具有驱动力。通过将切割刀23按压在第一槽22A的底部并使其移动,使切割刀23旋转,分离金属衬底19。使用该方法不会产生切断引起的导电性粉尘。因此,可防止该粉尘导致的短路。
另外,利用上述之外的方法也可以分离金属衬底19。具体地说,可利用使用冲压机进行的穿孔、剪切等分离金属衬底19。
参照图5,然后形成密封树脂14,至少覆盖电路衬底11的上面。这里,利用使用模型31进行的传递模模制,形成混入了填充物的热硬性树脂构成的密封树脂14。具体地说,将电路衬底11收纳在模型31的型腔33中,从浇口32将密封树脂14注入型腔33的内部。
在密封密封树脂14时,模型31被加热到170℃左右。因此,由热硬性树脂构成的密封树脂14在注入型腔33的同时进行热硬化。该热硬化在数十秒至百秒左右的时间内进行。通过进行热硬化密封树脂14会产生硬化收缩,但密封树脂14的热膨胀系数等于或小于23×10-6/℃,硬化收缩的量降低。因此,硬化收缩引起的电路衬底11的过度挠曲被抑制。
参照图6,然后使混合集成电路装置10与散热片28接触。首先,如图6(A)所示,在形成平坦面的散热片28的上面涂敷润滑脂29。散热片28由铜等金属构成,具有将自混合集成电路装置10产生的热排出到外部的功能。润滑脂29设于混合集成电路装置10的下面和散热片28的上面之间,具有提高散热性能的作用。润滑脂29涂敷在与混合集成电路装置10的中央部对应的部位。
然后,在将混合集成电路装置10载置于散热片28的上部后,使其下面与散热片28的上面接触。具体地说,通过用小螺钉30将设于混合集成电路装置10两端的固定部26向下按压,使混合集成电路装置10的下面与散热片28的上部紧密附着。混合集成电路装置10利用密封树脂14的热硬化弯曲为向下突出。因此,利用小螺钉30的按压力使弯曲的混合集成电路装置10平坦化,从而可使涂敷在中央部的润滑脂29扩散到周边部。另外利用小螺钉30的按压力,混合集成电路装置10的弯曲在被降低的状态下固定。由此,混合集成电路装置10的下面与散热片28的上面紧密附着。
参照图6(B),通过使用小螺钉30按压混合集成电路装置10的周边部,混合集成电路装置10的下面紧密附着在散热片28的上面。因此,内装于混合集成电路装置10的电路元件产生的热量介由散热片28排放到外部。在该图中,自密封树脂14露出的电路衬底11的下面与散热片28的上面接触。但是,如图1(C)所示,有时覆盖电路衬底11的下面而形成密封树脂14。这种情况下,由密封树脂14构成的混合集成电路装置10的下面与散热片28的上面接触。

Claims (10)

1.一种电路装置,其包括:导电图案,其设在电路衬底的上面;电路元件,其与所述导电图案电连接;密封树脂,其至少覆盖所述电路衬底的上面,密封所述电路元件,其特征在于,所述密封树脂的热膨胀系数在填充了填充物的状态下在15×10-6/℃~23×10-6/℃的范围内,所述电路衬底以向下面侧凸出而弯曲的状态由所述密封树脂覆盖。
2.如权利要求1所述的电路装置,其特征在于,所述电路衬底的下面自所述密封树脂露出。
3.如权利要求1所述的电路装置,其特征在于,所述密封树脂通过传递模模制形成。
4.如权利要求1所述的电路装置,其特征在于,所述电路元件介由无铅焊锡固定在所述导电图案上。
5.如权利要求1所述的电路装置,其特征在于,所述电路衬底的上面整个面及侧面通过所述密封树脂一体覆盖。
6.一种电路装置的制造方法,其包括:将由导电图案及电路元件构成的电路形成于电路衬底的上面的工序;为覆盖所述电路元件,用填充了填充物的密封树脂至少覆盖所述电路衬底的上面的工序,其特征在于,在所述覆盖工序使用的所述密封树脂的热膨胀系数在填充了填充物的状态下在15×10-6/℃~23×10-6/℃的范围内,所述电路衬底以向下面侧凸出而弯曲的状态由所述密封树脂覆盖。
7.一种电路装置的制造方法,其特征在于,其包括:将由导电图案及电路元件构成的电路形成于电路衬底的上面的工序;为覆盖所述电路元件,用热膨胀系数在15×10-6/℃~23×10-6/℃范围内的、填充了填充物的密封树脂至少覆盖所述电路衬底的上面的工序;在通过加热所述密封树脂所述电路衬底向下面方向弯曲为凸状的状态下,使所述密封树脂硬化的工序;在使所述电路衬底的弯曲降低的状态下,使所述密封树脂或所述电路衬底的下面与散热体的表面接触的工序。
8.如权利要求6或7所述的电路装置的制造方法,其特征在于,所述密封树脂是通过传递模模制形成的热硬性树脂。
9.如权利要求6或7所述的电路装置的制造方法,其特征在于,所述电路衬底由铝构成。
10.一种电路装置的制造方法,准备形成有以铜为主材料的导电图案的铝或铜的衬底,将电路元件安装在所述衬底上,用传递模模制树脂,以覆盖所述衬底的至少上面,其特征在于,在15×10-6/℃~23×10-6/℃的范围内选择混入了填充物的树脂的热膨胀系数,使所述模制时所述树脂的硬化收缩被抑制,硬化后衬底下面稍向下凸。
CNB2005100525405A 2004-09-30 2005-02-28 电路装置及其制造方法 Expired - Fee Related CN100397627C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2004288213A JP2006100752A (ja) 2004-09-30 2004-09-30 回路装置およびその製造方法
JP288213/04 2004-09-30

Publications (2)

Publication Number Publication Date
CN1755919A CN1755919A (zh) 2006-04-05
CN100397627C true CN100397627C (zh) 2008-06-25

Family

ID=36097706

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2005100525405A Expired - Fee Related CN100397627C (zh) 2004-09-30 2005-02-28 电路装置及其制造方法

Country Status (5)

Country Link
US (1) US20060065421A1 (zh)
JP (1) JP2006100752A (zh)
KR (1) KR100726902B1 (zh)
CN (1) CN100397627C (zh)
TW (1) TWI271130B (zh)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5095957B2 (ja) * 2006-05-31 2012-12-12 オンセミコンダクター・トレーディング・リミテッド 回路装置の製造方法
JP4760543B2 (ja) * 2006-06-01 2011-08-31 株式会社デンソー モールドパッケージおよびその製造方法
JP4308241B2 (ja) 2006-11-10 2009-08-05 インターナショナル・ビジネス・マシーンズ・コーポレーション ジョブ実行方法、ジョブ実行システム及びジョブ実行プログラム
WO2008120280A1 (ja) * 2007-03-29 2008-10-09 Fujitsu Limited 歪み低減固定構造
KR101011199B1 (ko) * 2007-11-01 2011-01-26 파나소닉 주식회사 실장 구조체
TWI322652B (en) * 2007-11-06 2010-03-21 Yu Hsueh Lin Structure and manufacturing method of circuit substrate board
JP5256128B2 (ja) * 2009-06-18 2013-08-07 日立オートモティブシステムズ株式会社 電子回路封入装置
CN101944489B (zh) * 2009-07-07 2012-06-20 株式会社村田制作所 复合基板的制造方法
JP2011100718A (ja) * 2009-10-05 2011-05-19 Yazaki Corp コネクタ
US8383946B2 (en) 2010-05-18 2013-02-26 Joinset, Co., Ltd. Heat sink
JP5774292B2 (ja) 2010-11-04 2015-09-09 セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー 回路装置およびその製造方法
JP5796956B2 (ja) 2010-12-24 2015-10-21 セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー 回路装置およびその製造方法
JP2013069748A (ja) * 2011-09-21 2013-04-18 Toshiba Corp ベースプレートおよび半導体装置
JP2015018979A (ja) * 2013-07-12 2015-01-29 イビデン株式会社 プリント配線板
DE102013219992A1 (de) * 2013-10-02 2015-04-02 Conti Temic Microelectronic Gmbh Schaltungsvorrichtung und Verfahren zu deren Herstellung
JP6483498B2 (ja) 2014-07-07 2019-03-13 ローム株式会社 電子装置およびその実装構造
JP6327140B2 (ja) * 2014-12-15 2018-05-23 株式会社デンソー 電子装置
JP6693441B2 (ja) * 2017-02-27 2020-05-13 オムロン株式会社 電子装置およびその製造方法
DE102020204941A1 (de) * 2020-04-20 2020-10-29 Robert Bosch Gesellschaft mit beschränkter Haftung Verfahren und Vorrichtung zum Herstellen eines mit einer aushärtbaren Vergussmasse versehenen Substrats

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4720424A (en) * 1984-06-18 1988-01-19 Hoebbst Celanese Corporation Electronic component encapsulated with a composition comprising a polymer which is capable of forming an anisotropic melt phase and substantially incapable of further chain growth upon heating
JPH05102645A (ja) * 1991-05-23 1993-04-23 Sanyo Electric Co Ltd 混成集積回路
CN1113608A (zh) * 1994-01-13 1995-12-20 三星电子株式会社 用于半导体器件的引线框架
US6046506A (en) * 1997-03-24 2000-04-04 Rohm Co., Ltd. Semiconductor device with package
CN1388580A (zh) * 2001-05-30 2003-01-01 株式会社萌利克 半导体器件
US20040182601A1 (en) * 2002-11-26 2004-09-23 Hiromichi Watanabe Substrate for circuit wiring

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3658750A (en) * 1969-02-13 1972-04-25 Hitachi Ltd Thermosetting resin composition and electrical appliances using the same
US4754101A (en) * 1986-10-23 1988-06-28 Instrument Specialties Co., Inc. Electromagnetic shield for printed circuit board
JP3163622B2 (ja) * 1990-07-05 2001-05-08 日産自動車株式会社 電気自動車
US5136366A (en) * 1990-11-05 1992-08-04 Motorola, Inc. Overmolded semiconductor package with anchoring means
US5369056A (en) * 1993-03-29 1994-11-29 Staktek Corporation Warp-resistent ultra-thin integrated circuit package fabrication method
JPH08298299A (ja) * 1995-04-27 1996-11-12 Hitachi Ltd 半導体装置
US5773895A (en) * 1996-04-03 1998-06-30 Intel Corporation Anchor provisions to prevent mold delamination in an overmolded plastic array package
JP3379349B2 (ja) * 1996-09-05 2003-02-24 株式会社日立製作所 モールド型電子部品及びその製法
JPH10135377A (ja) * 1996-11-01 1998-05-22 Hitachi Ltd モールド型半導体装置
JPH1117071A (ja) * 1997-06-23 1999-01-22 Hitachi Ltd 半導体装置
US6011301A (en) * 1998-06-09 2000-01-04 Stmicroelectronics, Inc. Stress reduction for flip chip package
US6143981A (en) * 1998-06-24 2000-11-07 Amkor Technology, Inc. Plastic integrated circuit package and method and leadframe for making the package
US6448633B1 (en) * 1998-11-20 2002-09-10 Amkor Technology, Inc. Semiconductor package and method of making using leadframe having lead locks to secure leads to encapsulant
FI982586A (fi) * 1998-11-30 2000-05-31 Nokia Mobile Phones Ltd Elektroninen laite
US6178097B1 (en) * 1999-01-22 2001-01-23 Dial Tool Industries, Inc. RF shield having removable cover
WO2000049652A1 (fr) * 1999-02-18 2000-08-24 Seiko Epson Corporation Materiau de liaison, dispositif semi-conducteur et procede de fabrication, carte et dispositif electronique
US6320762B1 (en) * 1999-04-09 2001-11-20 Shiaw-Jong S. Chen Fixed conductive pin for printed wiring substrate electronics case and method of manufacture therefor
US6274808B1 (en) * 1999-05-06 2001-08-14 Lucent Technologies, Inc. EMI shielding enclosure
KR20010037247A (ko) * 1999-10-15 2001-05-07 마이클 디. 오브라이언 반도체패키지
US6417532B2 (en) * 2000-01-28 2002-07-09 Kabushiki Kaisha Toshiba Power semiconductor module for use in power conversion units with downsizing requirements
US7042068B2 (en) * 2000-04-27 2006-05-09 Amkor Technology, Inc. Leadframe and semiconductor package made using the leadframe
US7064009B1 (en) * 2001-04-04 2006-06-20 Amkor Technology, Inc. Thermally enhanced chip scale lead on chip semiconductor package and method of making same
US6552261B2 (en) * 2001-04-27 2003-04-22 Bmi, Inc. Push-fit shield
JP3541831B2 (ja) * 2001-10-26 2004-07-14 日産自動車株式会社 車両の駆動力制御装置
JP3585121B2 (ja) * 2002-02-20 2004-11-04 トヨタ自動車株式会社 動力出力装置およびこれを備える自動車
JP3896029B2 (ja) * 2002-04-24 2007-03-22 三洋電機株式会社 混成集積回路装置の製造方法
US20040018260A1 (en) * 2002-06-19 2004-01-29 Novemed Group Limited Novel botanical extract of Tripterygium Wilfordii Hook F.
JP3993807B2 (ja) * 2002-08-30 2007-10-17 京セラ株式会社 半導体装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4720424A (en) * 1984-06-18 1988-01-19 Hoebbst Celanese Corporation Electronic component encapsulated with a composition comprising a polymer which is capable of forming an anisotropic melt phase and substantially incapable of further chain growth upon heating
JPH05102645A (ja) * 1991-05-23 1993-04-23 Sanyo Electric Co Ltd 混成集積回路
CN1113608A (zh) * 1994-01-13 1995-12-20 三星电子株式会社 用于半导体器件的引线框架
US6046506A (en) * 1997-03-24 2000-04-04 Rohm Co., Ltd. Semiconductor device with package
CN1388580A (zh) * 2001-05-30 2003-01-01 株式会社萌利克 半导体器件
US20040182601A1 (en) * 2002-11-26 2004-09-23 Hiromichi Watanabe Substrate for circuit wiring

Also Published As

Publication number Publication date
CN1755919A (zh) 2006-04-05
US20060065421A1 (en) 2006-03-30
KR100726902B1 (ko) 2007-06-11
TWI271130B (en) 2007-01-11
TW200611614A (en) 2006-04-01
JP2006100752A (ja) 2006-04-13
KR20060043018A (ko) 2006-05-15

Similar Documents

Publication Publication Date Title
CN100397627C (zh) 电路装置及其制造方法
CN106486431B (zh) 具有增强的热耗散的电子功率模块及其制造方法
EP3499560B1 (en) Semiconductor module and method for producing the same
JP3121562B2 (ja) フリップ・チップ・パッケージおよびその製法
US6432750B2 (en) Power module package having insulator type heat sink attached to rear surface of lead frame and manufacturing method thereof
CN101253627B (zh) 电路装置及其制造方法
EP1039538A1 (en) Semiconductor device having an improved structure for preventing cracks, improved small-sized semiconductor and method of manufacturing the same
CN104145331B (zh) 半导体装置和其制造方法
CN1783487B (zh) 电路装置及其制造方法
EP3358920B1 (en) Electronic control device, and manufacturing method for vehicle-mounted electronic control device
KR101316289B1 (ko) 회로 장치 및 그 제조 방법
JP2005109100A (ja) 半導体装置およびその製造方法
CN110379718A (zh) 具有改进电可接入性的封装结构的电子装置和制造方法
JP2014183302A (ja) 半導体モジュール及びその製造方法
CN107431067A (zh) 功率模块
JP2010050323A (ja) 電子装置およびその製造方法
CN108321092A (zh) 电路部件的制造方法和电路部件
CN100336209C (zh) 混合集成电路装置的制造方法
CN101925989B (zh) 用于半导体封装的滚压囊封方法
CN107851620B (zh) 功率半导体模块
CN205319149U (zh) 半导体封装体
JP6104545B2 (ja) 半導体装置の製造方法、および成形部材
CN112510005A (zh) 智能功率模块和智能功率模块的封装方法
CN102104030A (zh) 重构晶片的组装
JP5308107B2 (ja) 回路装置の製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20080625

Termination date: 20210228