CN100380528C - 难以发生熔断器的切断的误识别的半导体装置 - Google Patents
难以发生熔断器的切断的误识别的半导体装置 Download PDFInfo
- Publication number
- CN100380528C CN100380528C CNB200310114243XA CN200310114243A CN100380528C CN 100380528 C CN100380528 C CN 100380528C CN B200310114243X A CNB200310114243X A CN B200310114243XA CN 200310114243 A CN200310114243 A CN 200310114243A CN 100380528 C CN100380528 C CN 100380528C
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- CN
- China
- Prior art keywords
- mentioned
- circuit
- node
- signal
- inner node
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/027—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in fuses
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/18—Auxiliary circuits, e.g. for writing into memory
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
Landscapes
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Dram (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
Claims (10)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55262/2003 | 2003-03-03 | ||
JP2003055262A JP2004265523A (ja) | 2003-03-03 | 2003-03-03 | 半導体装置 |
JP55262/03 | 2003-03-03 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1527325A CN1527325A (zh) | 2004-09-08 |
CN100380528C true CN100380528C (zh) | 2008-04-09 |
Family
ID=32905882
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB200310114243XA Expired - Fee Related CN100380528C (zh) | 2003-03-03 | 2003-11-04 | 难以发生熔断器的切断的误识别的半导体装置 |
Country Status (6)
Country | Link |
---|---|
US (1) | US6949986B2 (zh) |
JP (1) | JP2004265523A (zh) |
KR (1) | KR100518394B1 (zh) |
CN (1) | CN100380528C (zh) |
DE (1) | DE10341767A1 (zh) |
TW (1) | TWI234165B (zh) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4545416B2 (ja) * | 2003-11-04 | 2010-09-15 | パナソニック株式会社 | Prom回路 |
US7190629B2 (en) * | 2005-02-08 | 2007-03-13 | Micron Technology, Inc. | Circuit and method for reading an antifuse |
KR100739927B1 (ko) * | 2005-06-29 | 2007-07-16 | 주식회사 하이닉스반도체 | 반도체 메모리 장치의 리페어 입출력 퓨즈 회로 |
KR100660899B1 (ko) * | 2005-12-15 | 2006-12-26 | 삼성전자주식회사 | 누설 전류 패스를 제거할 수 있는 퓨즈 회로 |
JP4871031B2 (ja) | 2006-06-06 | 2012-02-08 | ルネサスエレクトロニクス株式会社 | 半導体装置およびヒューズの判定方法 |
KR101110794B1 (ko) * | 2009-05-13 | 2012-02-24 | 주식회사 하이닉스반도체 | 퓨즈 회로 및 리던던시 회로 |
KR101046726B1 (ko) * | 2009-05-19 | 2011-07-05 | 주식회사 하이닉스반도체 | 반도체 장치의 퓨즈회로 및 퓨즈상태 모니터링 방법 |
JP2012109403A (ja) * | 2010-11-17 | 2012-06-07 | Elpida Memory Inc | 半導体装置及びその制御方法 |
KR102031147B1 (ko) * | 2013-04-04 | 2019-10-14 | 에스케이하이닉스 주식회사 | 메모리 장치, 메모리 장치 및 메모리 시스템의 동작방법 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5566107A (en) * | 1995-05-05 | 1996-10-15 | Micron Technology, Inc. | Programmable circuit for enabling an associated circuit |
US5825698A (en) * | 1996-10-30 | 1998-10-20 | Samsung Electronics, Co., Ltd. | Redundancy decoding circuit for a semiconductor memory device |
JP2001210093A (ja) * | 2000-01-25 | 2001-08-03 | Mitsubishi Electric Corp | リペア信号発生回路 |
US6353562B2 (en) * | 2000-02-09 | 2002-03-05 | Infineon Technologies Ag | Integrated semiconductor memory with redundant units for memory cells |
US6465818B1 (en) * | 1999-01-11 | 2002-10-15 | Kabushiki Kaisha Toshiba | Semiconductor memory device capable of performing data writing or erasing operation and data reading operation in parallel |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6015946A (ja) * | 1983-07-08 | 1985-01-26 | Hitachi Ltd | 集積回路 |
JP2595271B2 (ja) * | 1987-12-21 | 1997-04-02 | 株式会社日立製作所 | プログラム回路 |
JPH0364062A (ja) * | 1989-08-01 | 1991-03-19 | Mitsubishi Electric Corp | 半導体集積回路装置 |
JPH04290458A (ja) * | 1991-03-19 | 1992-10-15 | Fujitsu Ltd | 半導体装置 |
JPH07226439A (ja) * | 1994-02-09 | 1995-08-22 | Hitachi Ltd | 半導体集積回路 |
JP2727978B2 (ja) * | 1994-08-24 | 1998-03-18 | 日本電気株式会社 | ビットスライスレイアウトセル |
JPH09266282A (ja) * | 1996-03-29 | 1997-10-07 | Fujitsu Ltd | ゲートアレイ装置 |
JP2859234B2 (ja) * | 1996-12-26 | 1999-02-17 | 日本電気アイシーマイコンシステム株式会社 | 半導体集積回路装置 |
JPH11185495A (ja) * | 1997-12-22 | 1999-07-09 | Mitsubishi Electric Corp | 半導体記憶装置 |
US6144591A (en) * | 1997-12-30 | 2000-11-07 | Mosaid Technologies Incorporated | Redundancy selection circuit for semiconductor memories |
US6084803A (en) * | 1998-10-23 | 2000-07-04 | Mosel Vitelic, Inc. | Initialization of non-volatile programmable latches in circuits in which an initialization operation is performed |
JP3642555B2 (ja) * | 1999-06-29 | 2005-04-27 | 株式会社東芝 | 半導体装置及びそのテスト方法 |
JP3636965B2 (ja) * | 2000-05-10 | 2005-04-06 | エルピーダメモリ株式会社 | 半導体装置 |
JP2002074979A (ja) * | 2000-08-31 | 2002-03-15 | Mitsubishi Electric Corp | プログラム回路およびそれを用いた半導体記憶装置 |
JP2002300023A (ja) * | 2001-04-02 | 2002-10-11 | Mitsubishi Electric Corp | 半導体集積回路装置 |
JP2003263900A (ja) * | 2002-03-12 | 2003-09-19 | Mitsubishi Electric Corp | 半導体記憶装置 |
KR101110794B1 (ko) * | 2009-05-13 | 2012-02-24 | 주식회사 하이닉스반도체 | 퓨즈 회로 및 리던던시 회로 |
-
2003
- 2003-03-03 JP JP2003055262A patent/JP2004265523A/ja active Pending
- 2003-08-26 US US10/647,385 patent/US6949986B2/en not_active Expired - Lifetime
- 2003-09-02 TW TW092124191A patent/TWI234165B/zh not_active IP Right Cessation
- 2003-09-10 DE DE10341767A patent/DE10341767A1/de not_active Withdrawn
- 2003-11-03 KR KR10-2003-0077243A patent/KR100518394B1/ko not_active IP Right Cessation
- 2003-11-04 CN CNB200310114243XA patent/CN100380528C/zh not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5566107A (en) * | 1995-05-05 | 1996-10-15 | Micron Technology, Inc. | Programmable circuit for enabling an associated circuit |
US5825698A (en) * | 1996-10-30 | 1998-10-20 | Samsung Electronics, Co., Ltd. | Redundancy decoding circuit for a semiconductor memory device |
US6465818B1 (en) * | 1999-01-11 | 2002-10-15 | Kabushiki Kaisha Toshiba | Semiconductor memory device capable of performing data writing or erasing operation and data reading operation in parallel |
JP2001210093A (ja) * | 2000-01-25 | 2001-08-03 | Mitsubishi Electric Corp | リペア信号発生回路 |
US6353562B2 (en) * | 2000-02-09 | 2002-03-05 | Infineon Technologies Ag | Integrated semiconductor memory with redundant units for memory cells |
Also Published As
Publication number | Publication date |
---|---|
CN1527325A (zh) | 2004-09-08 |
KR20040078875A (ko) | 2004-09-13 |
JP2004265523A (ja) | 2004-09-24 |
DE10341767A1 (de) | 2004-09-23 |
KR100518394B1 (ko) | 2005-09-29 |
TW200418040A (en) | 2004-09-16 |
TWI234165B (en) | 2005-06-11 |
US20040174204A1 (en) | 2004-09-09 |
US6949986B2 (en) | 2005-09-27 |
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C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
ASS | Succession or assignment of patent right |
Owner name: RENESAS ELECTRONICS CORPORATION Free format text: FORMER OWNER: RENESAS TECHNOLOGY CORP. Effective date: 20101019 |
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C41 | Transfer of patent application or patent right or utility model | ||
COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: TOKYO TO, JAPAN TO: KAWASAKI CITY, KANAGAWA PREFECTURE, JAPAN |
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TR01 | Transfer of patent right |
Effective date of registration: 20101019 Address after: Kawasaki, Kanagawa, Japan Patentee after: Renesas Electronics Corporation Address before: Tokyo, Japan, Japan Patentee before: Renesas Technology Corp. |
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C17 | Cessation of patent right | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20080409 Termination date: 20121104 |