CA2095058A1 - Semiconductor device with bumps - Google Patents

Semiconductor device with bumps

Info

Publication number
CA2095058A1
CA2095058A1 CA002095058A CA2095058A CA2095058A1 CA 2095058 A1 CA2095058 A1 CA 2095058A1 CA 002095058 A CA002095058 A CA 002095058A CA 2095058 A CA2095058 A CA 2095058A CA 2095058 A1 CA2095058 A1 CA 2095058A1
Authority
CA
Canada
Prior art keywords
bump
metal material
semiconductor chip
layers
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
CA002095058A
Other languages
English (en)
French (fr)
Inventor
Masanori Nishiguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Publication of CA2095058A1 publication Critical patent/CA2095058A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H10W72/012—
    • H10W72/071—
    • H10W72/20—
    • H10W72/01231—
    • H10W72/01235—
    • H10W72/01251—
    • H10W72/01255—
    • H10W72/222—
    • H10W72/223—
    • H10W72/234—
    • H10W72/252—
    • H10W72/923—
    • H10W72/952—

Landscapes

  • Wire Bonding (AREA)
CA002095058A 1992-05-06 1993-04-28 Semiconductor device with bumps Abandoned CA2095058A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP04113570A JP3141364B2 (ja) 1992-05-06 1992-05-06 半導体チップ
JP113570/1992 1992-05-06

Publications (1)

Publication Number Publication Date
CA2095058A1 true CA2095058A1 (en) 1993-11-07

Family

ID=14615601

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002095058A Abandoned CA2095058A1 (en) 1992-05-06 1993-04-28 Semiconductor device with bumps

Country Status (8)

Country Link
US (1) US5461261A (enExample)
EP (1) EP0568995A3 (enExample)
JP (1) JP3141364B2 (enExample)
KR (1) KR930024090A (enExample)
AU (1) AU663777B2 (enExample)
CA (1) CA2095058A1 (enExample)
MY (1) MY131396A (enExample)
TW (1) TW260825B (enExample)

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US5634268A (en) * 1995-06-07 1997-06-03 International Business Machines Corporation Method for making direct chip attach circuit card
EP0852032A1 (en) * 1995-07-20 1998-07-08 Dallas Semiconductor Corporation Single chip microprocessor, math co-processor, random number generator, real-time clock and ram having a one-wire interface
JP3310499B2 (ja) * 1995-08-01 2002-08-05 富士通株式会社 半導体装置
US5789271A (en) * 1996-03-18 1998-08-04 Micron Technology, Inc. Method for fabricating microbump interconnect for bare semiconductor dice
US5808360A (en) * 1996-05-15 1998-09-15 Micron Technology, Inc. Microbump interconnect for bore semiconductor dice
US5912510A (en) * 1996-05-29 1999-06-15 Motorola, Inc. Bonding structure for an electronic device
US5620611A (en) * 1996-06-06 1997-04-15 International Business Machines Corporation Method to improve uniformity and reduce excess undercuts during chemical etching in the manufacture of solder pads
JP3980066B2 (ja) * 1996-09-20 2007-09-19 株式会社ルネサステクノロジ 液晶表示装置の製造方法
US5841198A (en) * 1997-04-21 1998-11-24 Lsi Logic Corporation Ball grid array package employing solid core solder balls
US6082610A (en) * 1997-06-23 2000-07-04 Ford Motor Company Method of forming interconnections on electronic modules
US6107122A (en) * 1997-08-04 2000-08-22 Micron Technology, Inc. Direct die contact (DDC) semiconductor package
US6372624B1 (en) 1997-08-04 2002-04-16 Micron Technology, Inc. Method for fabricating solder bumps by wave soldering
TW453137B (en) * 1997-08-25 2001-09-01 Showa Denko Kk Electrode structure of silicon semiconductor device and the manufacturing method of silicon device using it
KR100447895B1 (ko) * 1997-09-13 2004-10-14 삼성전자주식회사 칩 스케일 패키지 및 그 제조방법
JP4066522B2 (ja) * 1998-07-22 2008-03-26 イビデン株式会社 プリント配線板
US6242935B1 (en) 1999-01-21 2001-06-05 Micron Technology, Inc. Interconnect for testing semiconductor components and method of fabrication
JP3553413B2 (ja) * 1999-04-26 2004-08-11 富士通株式会社 半導体装置の製造方法
JP4593717B2 (ja) * 2000-02-23 2010-12-08 京セラ株式会社 回路基板及びそれを用いた回路装置
US6429531B1 (en) * 2000-04-18 2002-08-06 Motorola, Inc. Method and apparatus for manufacturing an interconnect structure
US6610591B1 (en) 2000-08-25 2003-08-26 Micron Technology, Inc. Methods of ball grid array
US6348740B1 (en) * 2000-09-05 2002-02-19 Siliconware Precision Industries Co., Ltd. Bump structure with dopants
DE10063914A1 (de) * 2000-12-20 2002-07-25 Pac Tech Gmbh Kontakthöckeraufbau zur Herstellung eines Verbindungsaufbaus zwischen Substratanschlussflächen
US20020151164A1 (en) * 2001-04-12 2002-10-17 Jiang Hunt Hang Structure and method for depositing solder bumps on a wafer
US6902098B2 (en) * 2001-04-23 2005-06-07 Shipley Company, L.L.C. Solder pads and method of making a solder pad
US6527159B2 (en) * 2001-07-12 2003-03-04 Intel Corporation Surface mounting to an irregular surface
US7057294B2 (en) * 2001-07-13 2006-06-06 Rohm Co., Ltd. Semiconductor device
US7547623B2 (en) 2002-06-25 2009-06-16 Unitive International Limited Methods of forming lead free solder bumps
US7223633B2 (en) 2002-11-27 2007-05-29 Intel Corporation Method for solder crack deflection
JP4115306B2 (ja) * 2003-03-13 2008-07-09 富士通株式会社 半導体装置の製造方法
TWI229436B (en) * 2003-07-10 2005-03-11 Advanced Semiconductor Eng Wafer structure and bumping process
KR100712534B1 (ko) * 2005-09-22 2007-04-27 삼성전자주식회사 콘택 저항을 최소화할 수 있는 볼을 갖는 패키지 및 테스트장치, 그리고 그 패키지의 제조 방법
US20070102815A1 (en) * 2005-11-08 2007-05-10 Kaufmann Matthew V Bumping process with self-aligned A1-cap and the elimination of 2nd passivation layer
WO2007120418A2 (en) * 2006-03-13 2007-10-25 Nextwire Systems, Inc. Electronic multilingual numeric and language learning tool
JP4219951B2 (ja) * 2006-10-25 2009-02-04 新光電気工業株式会社 はんだボール搭載方法及びはんだボール搭載基板の製造方法
US20090020876A1 (en) * 2007-07-20 2009-01-22 Hertel Thomas A High temperature packaging for semiconductor devices
US8293587B2 (en) * 2007-10-11 2012-10-23 International Business Machines Corporation Multilayer pillar for reduced stress interconnect and method of making same
US7947592B2 (en) * 2007-12-14 2011-05-24 Semiconductor Components Industries, Llc Thick metal interconnect with metal pad caps at selective sites and process for making the same
US7994043B1 (en) 2008-04-24 2011-08-09 Amkor Technology, Inc. Lead free alloy bump structure and fabrication method
JP5535448B2 (ja) * 2008-05-19 2014-07-02 シャープ株式会社 半導体装置、半導体装置の実装方法、および半導体装置の実装構造
JP2011138913A (ja) * 2009-12-28 2011-07-14 Citizen Holdings Co Ltd 半導体発光素子とその製造方法
TWM397591U (en) * 2010-04-22 2011-02-01 Mao Bang Electronic Co Ltd Bumping structure
JP5774292B2 (ja) * 2010-11-04 2015-09-09 セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー 回路装置およびその製造方法
WO2012085724A1 (en) * 2010-12-21 2012-06-28 Koninklijke Philips Electronics N.V. Method of fabricating a flip chip electrical coupling, a flip chip electrical coupling, and a device comprising a flip chip electrical coupling
US8387854B2 (en) * 2011-02-25 2013-03-05 Memsic, Inc. Method for mounting a three-axis MEMS device with precise orientation
WO2013147808A1 (en) * 2012-03-29 2013-10-03 Intel Corporation Functional material systems and processes for package-level interconnects
DE102012216546B4 (de) 2012-09-17 2023-01-19 Infineon Technologies Ag Verfahren zum verlöten eines halbleiterchips mit einem träger
US20150318254A1 (en) * 2013-12-17 2015-11-05 Oracle International Corporation Electroplated solder with eutectic chemical composition
US9748196B2 (en) * 2014-09-15 2017-08-29 Advanced Semiconductor Engineering, Inc. Semiconductor package structure including die and substrate electrically connected through conductive segments
KR102860672B1 (ko) * 2020-07-30 2025-09-17 삼성디스플레이 주식회사 전자장치

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1483574A (enExample) * 1965-06-24 1967-09-06
US3436818A (en) * 1965-12-13 1969-04-08 Ibm Method of fabricating a bonded joint
US3986255A (en) * 1974-11-29 1976-10-19 Itek Corporation Process for electrically interconnecting chips with substrates employing gold alloy bumps and magnetic materials therein
US3959522A (en) * 1975-04-30 1976-05-25 Rca Corporation Method for forming an ohmic contact
JPS5839047A (ja) * 1981-09-02 1983-03-07 Hitachi Ltd 半導体装置およびその製法
JPS6187396A (ja) * 1984-10-05 1986-05-02 株式会社日立製作所 電子回路装置とその製造方法
US4875617A (en) * 1987-01-20 1989-10-24 Citowsky Elya L Gold-tin eutectic lead bonding method and structure
US4922322A (en) * 1989-02-09 1990-05-01 National Semiconductor Corporation Bump structure for reflow bonding of IC devices
US5197654A (en) * 1991-11-15 1993-03-30 Avishay Katz Bonding method using solder composed of multiple alternating gold and tin layers

Also Published As

Publication number Publication date
KR930024090A (ko) 1993-12-21
US5461261A (en) 1995-10-24
JP3141364B2 (ja) 2001-03-05
JPH05315338A (ja) 1993-11-26
MY131396A (en) 2007-08-30
TW260825B (enExample) 1995-10-21
AU663777B2 (en) 1995-10-19
EP0568995A2 (en) 1993-11-10
AU3820593A (en) 1993-11-11
EP0568995A3 (en) 1993-12-08

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Legal Events

Date Code Title Description
FZDE Discontinued