CA1205922A - Self-aligned manufacture of fet - Google Patents

Self-aligned manufacture of fet

Info

Publication number
CA1205922A
CA1205922A CA000436664A CA436664A CA1205922A CA 1205922 A CA1205922 A CA 1205922A CA 000436664 A CA000436664 A CA 000436664A CA 436664 A CA436664 A CA 436664A CA 1205922 A CA1205922 A CA 1205922A
Authority
CA
Canada
Prior art keywords
gate electrode
manufacturing
etching
schottky
mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA000436664A
Other languages
English (en)
French (fr)
Inventor
Kiichi Ueyanagi
Yasunari Umemoto
Susumu Takahashi
Michiharu Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Application granted granted Critical
Publication of CA1205922A publication Critical patent/CA1205922A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/2654—Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds
    • H01L21/26546—Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/061—Manufacture or treatment of FETs having Schottky gates
    • H10D30/0612—Manufacture or treatment of FETs having Schottky gates of lateral single-gate Schottky FETs
    • H10D30/0616—Manufacture or treatment of FETs having Schottky gates of lateral single-gate Schottky FETs using processes wherein the final gate is made before the completion of the source and drain regions, e.g. gate-first processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/80—FETs having rectifying junction gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/80—FETs having rectifying junction gate electrodes
    • H10D30/87—FETs having Schottky gate electrodes, e.g. metal-semiconductor FETs [MESFET]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/083—Ion implantation, general
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/143—Shadow masking

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)
CA000436664A 1982-09-16 1983-09-14 Self-aligned manufacture of fet Expired CA1205922A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP57159611A JPS5950567A (ja) 1982-09-16 1982-09-16 電界効果トランジスタの製造方法
JP159611/82 1982-09-16

Publications (1)

Publication Number Publication Date
CA1205922A true CA1205922A (en) 1986-06-10

Family

ID=15697490

Family Applications (1)

Application Number Title Priority Date Filing Date
CA000436664A Expired CA1205922A (en) 1982-09-16 1983-09-14 Self-aligned manufacture of fet

Country Status (6)

Country Link
US (1) US4546540A (en, 2012)
EP (1) EP0106174B1 (en, 2012)
JP (1) JPS5950567A (en, 2012)
KR (1) KR920002090B1 (en, 2012)
CA (1) CA1205922A (en, 2012)
DE (1) DE3379296D1 (en, 2012)

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US5536967A (en) * 1980-12-30 1996-07-16 Fujitsu Limited Semiconductor device including Schottky gate of silicide and method for the manufacture of the same
US4694563A (en) * 1981-01-29 1987-09-22 Sumitomo Electric Industries, Ltd. Process for making Schottky-barrier gate FET
JPS60137070A (ja) * 1983-12-26 1985-07-20 Toshiba Corp 半導体装置の製造方法
GB2156579B (en) * 1984-03-15 1987-05-07 Standard Telephones Cables Ltd Field effect transistors
JPH0713978B2 (ja) * 1984-05-17 1995-02-15 ソニー株式会社 半導体装置の製造方法
JPS61108175A (ja) * 1984-11-01 1986-05-26 Toshiba Corp 半導体装置及び製造方法
JPS61117868A (ja) * 1984-11-14 1986-06-05 Toshiba Corp 半導体装置及びその製造方法
US5187111A (en) * 1985-09-27 1993-02-16 Kabushiki Kaisha Toshiba Method of manufacturing Schottky barrier gate FET
US4847212A (en) * 1987-01-12 1989-07-11 Itt Gallium Arsenide Technology Center Self-aligned gate FET process using undercut etch mask
US4782032A (en) * 1987-01-12 1988-11-01 Itt Gallium Arsenide Technology Center, A Division Of Itt Corporation Method of making self-aligned GaAs devices having TiWNx gate/interconnect
US5140387A (en) * 1985-11-08 1992-08-18 Lockheed Missiles & Space Company, Inc. Semiconductor device in which gate region is precisely aligned with source and drain regions
DE3576610D1 (de) * 1985-12-06 1990-04-19 Ibm Verfahren zum herstellen eines voellig selbstjustierten feldeffekttransistors.
US4673446A (en) * 1985-12-12 1987-06-16 The United States Of America As Represented By The Secretary Of The Navy Method of forming thermally stable high resistivity regions in n-type indium phosphide by oxygen implantation
US4670090A (en) * 1986-01-23 1987-06-02 Rockwell International Corporation Method for producing a field effect transistor
JPS62199068A (ja) * 1986-02-27 1987-09-02 Toshiba Corp 半導体装置及びその製造方法
JPH07120673B2 (ja) * 1986-03-06 1995-12-20 住友電気工業株式会社 ショットキゲート電界効果トランジスタの製造方法
US4735913A (en) * 1986-05-06 1988-04-05 Bell Communications Research, Inc. Self-aligned fabrication process for GaAs MESFET devices
JPS62262466A (ja) * 1986-05-09 1987-11-14 Toshiba Corp Ｍｅｓ　ｆｅｔの製造方法
US4738934A (en) * 1986-05-16 1988-04-19 American Telephone And Telegraph Company, At&T Bell Laboratories Method of making indium phosphide devices
US4745082A (en) * 1986-06-12 1988-05-17 Ford Microelectronics, Inc. Method of making a self-aligned MESFET using a substitutional gate with side walls
US4731339A (en) * 1986-08-25 1988-03-15 Rockwell International Corporation Process for manufacturing metal-semiconductor field-effect transistors
JPS63155671A (ja) * 1986-12-18 1988-06-28 Nec Corp 半導体装置の製造方法
US4849376A (en) * 1987-01-12 1989-07-18 Itt A Division Of Itt Corporation Gallium Arsenide Technology Center Self-aligned refractory gate process with self-limiting undercut of an implant mask
FR2613134B1 (fr) * 1987-03-24 1990-03-09 Labo Electronique Physique Dispositif semiconducteur du type transistor a effet de champ
US4808545A (en) * 1987-04-20 1989-02-28 International Business Machines Corporation High speed GaAs MESFET having refractory contacts and a self-aligned cold gate fabrication process
US5229323A (en) * 1987-08-21 1993-07-20 Kabushiki Kaisha Toshiba Method for manufacturing a semiconductor device with Schottky electrodes
US4792531A (en) * 1987-10-05 1988-12-20 Menlo Industries, Inc. Self-aligned gate process
US5093280A (en) * 1987-10-13 1992-03-03 Northrop Corporation Refractory metal ohmic contacts and method
JPH01161773A (ja) * 1987-12-18 1989-06-26 Agency Of Ind Science & Technol 化合物半導体装置の製造方法
NL8801772A (nl) * 1988-07-13 1990-02-01 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting waarbij op een oppervlak van een halfgeleiderlichaam geisoleerde geleidersporen worden aangebracht.
JPH02138750A (ja) * 1988-08-24 1990-05-28 Mitsubishi Electric Corp 半導体装置の製造方法
JPH02103939A (ja) * 1988-10-12 1990-04-17 Mitsubishi Electric Corp 半導体装置の製造方法
US5237192A (en) * 1988-10-12 1993-08-17 Mitsubishi Denki Kabushiki Kaisha MESFET semiconductor device having a T-shaped gate electrode
US5201994A (en) * 1988-11-18 1993-04-13 Kabushiki Kaisha Tokuda Seisakusho Dry etching method
JPH02271537A (ja) * 1989-04-12 1990-11-06 Mitsubishi Electric Corp 半導体装置及びその製造方法
US4874713A (en) * 1989-05-01 1989-10-17 Ncr Corporation Method of making asymmetrically optimized CMOS field effect transistors
US5053348A (en) * 1989-12-01 1991-10-01 Hughes Aircraft Company Fabrication of self-aligned, t-gate hemt
KR920007357B1 (ko) * 1990-03-12 1992-08-31 재단법인 한국전자통신연구소 내열성 게이트를 이용한 갈륨비소 반도체 소자의 제조방법
US5158896A (en) * 1991-07-03 1992-10-27 International Business Machines Corporation Method for fabricating group III-V heterostructure devices having self-aligned graded contact diffusion regions
JP2702338B2 (ja) * 1991-10-14 1998-01-21 三菱電機株式会社 半導体装置、及びその製造方法
JPH05291307A (ja) * 1991-12-05 1993-11-05 Samsung Electron Co Ltd 化合物半導体装置及びその製造方法
US5468689A (en) * 1993-11-16 1995-11-21 At&T Corp. Method for preparation of silicon nitride gallium diffusion barrier for use in molecular beam epitaxial growth of gallium arsenide
US5505816A (en) * 1993-12-16 1996-04-09 International Business Machines Corporation Etching of silicon dioxide selectively to silicon nitride and polysilicon
US5482872A (en) * 1994-01-31 1996-01-09 Motorola, Inc. Method of forming isolation region in a compound semiconductor substrate
KR950034830A (ko) * 1994-04-29 1995-12-28 빈센트 비. 인그라시아 전계 효과 트랜지스터 및 이 트랜지스터의 제조 방법
JP3734586B2 (ja) * 1997-03-05 2006-01-11 富士通株式会社 半導体装置及びその製造方法
US6319742B1 (en) * 1998-07-29 2001-11-20 Sanyo Electric Co., Ltd. Method of forming nitride based semiconductor layer

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Publication number Priority date Publication date Assignee Title
US3994758A (en) * 1973-03-19 1976-11-30 Nippon Electric Company, Ltd. Method of manufacturing a semiconductor device having closely spaced electrodes by perpendicular projection
US3906541A (en) * 1974-03-29 1975-09-16 Gen Electric Field effect transistor devices and methods of making same
US4075652A (en) * 1974-04-17 1978-02-21 Matsushita Electronics Corporation Junction gate type gaas field-effect transistor and method of forming
JPS5928992B2 (ja) * 1975-02-14 1984-07-17 日本電信電話株式会社 Ｍｏｓトランジスタおよびその製造方法
IT1041193B (it) * 1975-08-08 1980-01-10 Selenia Ind Elettroniche Perfezionamenti nei procedimenti per la fabbricazione di dispositivi a semiconduttor
US4393578A (en) * 1980-01-02 1983-07-19 General Electric Company Method of making silicon-on-sapphire FET
JPS57128071A (en) * 1981-01-30 1982-08-09 Fujitsu Ltd Field-effect type semiconductor device and manufacture thereof
US4414737A (en) * 1981-01-30 1983-11-15 Tokyo Shibaura Denki Kabushiki Kaisha Production of Schottky barrier diode
US4389768A (en) * 1981-04-17 1983-06-28 International Business Machines Corporation Self-aligned process for fabricating gallium arsenide metal-semiconductor field effect transistors
US4441931A (en) * 1981-10-28 1984-04-10 Bell Telephone Laboratories, Incorporated Method of making self-aligned guard regions for semiconductor device elements

Also Published As

Publication number Publication date
KR920002090B1 (ko) 1992-03-10
DE3379296D1 (en) 1989-04-06
US4546540A (en) 1985-10-15
EP0106174B1 (en) 1989-03-01
EP0106174A3 (en) 1986-07-23
EP0106174A2 (en) 1984-04-25
JPH0354464B2 (en, 2012) 1991-08-20
KR840005933A (ko) 1984-11-19
JPS5950567A (ja) 1984-03-23

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