ATE509366T1 - Verfahren zur herstellung eines halbleiterbauelements, hergestellt auf einer oberfläche aus silizium mit 110- kristallebenenrichtung - Google Patents

Verfahren zur herstellung eines halbleiterbauelements, hergestellt auf einer oberfläche aus silizium mit 110- kristallebenenrichtung

Info

Publication number
ATE509366T1
ATE509366T1 AT02800747T AT02800747T ATE509366T1 AT E509366 T1 ATE509366 T1 AT E509366T1 AT 02800747 T AT02800747 T AT 02800747T AT 02800747 T AT02800747 T AT 02800747T AT E509366 T1 ATE509366 T1 AT E509366T1
Authority
AT
Austria
Prior art keywords
silicon surface
semiconductor device
producing
plane direction
crystal plane
Prior art date
Application number
AT02800747T
Other languages
English (en)
Inventor
Tadahiro Ohmi
Sugawa Shigetoshi
Original Assignee
Tadahiro Ohmi
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tadahiro Ohmi filed Critical Tadahiro Ohmi
Application granted granted Critical
Publication of ATE509366T1 publication Critical patent/ATE509366T1/de

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/60Electrodes characterised by their materials
    • H10D64/66Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/693Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00Bonding of wafers, substrates or parts of devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/40Crystalline structures
    • H10D62/405Orientations of crystalline planes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/01Manufacture or treatment
    • H10D64/013Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01332Making the insulator
    • H10D64/01336Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid
    • H10D64/01344Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid in a nitrogen-containing ambient, e.g. N2O oxidation

Landscapes

  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
  • Recrystallisation Techniques (AREA)
  • Formation Of Insulating Films (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
AT02800747T 2001-10-03 2002-10-02 Verfahren zur herstellung eines halbleiterbauelements, hergestellt auf einer oberfläche aus silizium mit 110- kristallebenenrichtung ATE509366T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2001307899A JP2003115587A (ja) 2001-10-03 2001-10-03 <110>方位のシリコン表面上に形成された半導体装置およびその製造方法
PCT/JP2002/010288 WO2003032399A1 (en) 2001-10-03 2002-10-02 Semiconductor device fabricated on surface of silicon having <110> direction of crystal plane and its production method

Publications (1)

Publication Number Publication Date
ATE509366T1 true ATE509366T1 (de) 2011-05-15

Family

ID=19127284

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02800747T ATE509366T1 (de) 2001-10-03 2002-10-02 Verfahren zur herstellung eines halbleiterbauelements, hergestellt auf einer oberfläche aus silizium mit 110- kristallebenenrichtung

Country Status (8)

Country Link
US (1) US6903393B2 (de)
EP (1) EP1434253B1 (de)
JP (1) JP2003115587A (de)
KR (1) KR100614822B1 (de)
AT (1) ATE509366T1 (de)
IL (2) IL156116A0 (de)
TW (1) TW561588B (de)
WO (1) WO2003032399A1 (de)

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US8080459B2 (en) * 2002-09-24 2011-12-20 Vishay-Siliconix Self aligned contact in a semiconductor device and method of fabricating the same
JP4954437B2 (ja) * 2003-09-12 2012-06-13 公益財団法人国際科学振興財団 半導体装置の製造方法
AU2003264642B2 (en) 2002-12-02 2009-08-06 Tadahiro Ohmi Semiconductor Device and Method of Manufacturing the Same
JP2004319907A (ja) * 2003-04-18 2004-11-11 Tadahiro Omi 半導体装置の製造方法および製造装置
JP4239676B2 (ja) * 2003-05-15 2009-03-18 信越半導体株式会社 Soiウェーハおよびその製造方法
JP2004356114A (ja) * 2003-05-26 2004-12-16 Tadahiro Omi Pチャネルパワーmis電界効果トランジスタおよびスイッチング回路
JP4712292B2 (ja) * 2003-09-02 2011-06-29 財団法人国際科学振興財団 半導体装置及びその製造方法
JP4619637B2 (ja) * 2003-09-09 2011-01-26 財団法人国際科学振興財団 半導体装置及びその製造方法
US9685524B2 (en) 2005-03-11 2017-06-20 Vishay-Siliconix Narrow semiconductor trench structure
KR100942106B1 (ko) * 2005-06-08 2010-02-12 고쿠리츠다이가쿠호진 도호쿠다이가쿠 플라즈마 질화 처리 방법, 반도체 장치의 제조 방법 및플라즈마 처리 장치
JP5128064B2 (ja) * 2005-06-17 2013-01-23 国立大学法人東北大学 半導体装置
JP2007073800A (ja) * 2005-09-08 2007-03-22 Seiko Epson Corp 半導体装置
JP2007073799A (ja) * 2005-09-08 2007-03-22 Seiko Epson Corp 半導体装置
WO2007063963A1 (ja) 2005-12-02 2007-06-07 Tohoku University 半導体装置
TWI489557B (zh) * 2005-12-22 2015-06-21 維雪 希里康尼克斯公司 高移動率p-通道溝槽及平面型空乏模式的功率型金屬氧化物半導體場效電晶體
EP1976017A4 (de) 2005-12-22 2011-05-25 Univ Tohoku Halbleiterbauelement
US7573104B2 (en) * 2006-03-06 2009-08-11 International Business Machines Corporation CMOS device on hybrid orientation substrate comprising equal mobility for perpendicular devices of each type
US8409954B2 (en) * 2006-03-21 2013-04-02 Vishay-Silconix Ultra-low drain-source resistance power MOSFET
KR100980529B1 (ko) 2006-03-27 2010-09-06 도쿄엘렉트론가부시키가이샤 플라즈마 처리 장치
WO2007138937A1 (en) * 2006-05-26 2007-12-06 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US9437729B2 (en) 2007-01-08 2016-09-06 Vishay-Siliconix High-density power MOSFET with planarized metalization
US9947770B2 (en) * 2007-04-03 2018-04-17 Vishay-Siliconix Self-aligned trench MOSFET and method of manufacture
US9484451B2 (en) 2007-10-05 2016-11-01 Vishay-Siliconix MOSFET active area and edge termination area charge balance
JP2010018504A (ja) * 2008-07-14 2010-01-28 Japan Atomic Energy Agency Si(110)表面の一次元ナノ構造及びその製造方法
JP4875115B2 (ja) * 2009-03-05 2012-02-15 株式会社東芝 半導体素子及び半導体装置
US9443974B2 (en) * 2009-08-27 2016-09-13 Vishay-Siliconix Super junction trench power MOSFET device fabrication
US9425306B2 (en) 2009-08-27 2016-08-23 Vishay-Siliconix Super junction trench power MOSFET devices
US9431530B2 (en) 2009-10-20 2016-08-30 Vishay-Siliconix Super-high density trench MOSFET
US9412883B2 (en) 2011-11-22 2016-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for MOS capacitors in replacement gate process
US9842911B2 (en) 2012-05-30 2017-12-12 Vishay-Siliconix Adaptive charge balanced edge termination
US9209304B2 (en) * 2014-02-13 2015-12-08 Taiwan Semiconductor Manufacturing Co., Ltd. N/P MOS FinFET performance enhancement by specific orientation surface
US9887259B2 (en) 2014-06-23 2018-02-06 Vishay-Siliconix Modulated super junction power MOSFET devices
CN106575666B (zh) 2014-08-19 2021-08-06 维西埃-硅化物公司 超结金属氧化物半导体场效应晶体管
CN115483211A (zh) 2014-08-19 2022-12-16 维西埃-硅化物公司 电子电路
DE102020209092A1 (de) * 2020-07-21 2022-01-27 Sicrystal Gmbh Kristallstrukturorientierung in Halbleiter-Halbzeugen und Halbleitersubstraten zum Verringern von Sprüngen und Verfahren zum Einstellen von dieser

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US3476991A (en) * 1967-11-08 1969-11-04 Texas Instruments Inc Inversion layer field effect device with azimuthally dependent carrier mobility
JPS5432451Y1 (de) * 1975-06-19 1979-10-08
JPS6170748A (ja) * 1984-09-14 1986-04-11 Hitachi Ltd 半導体装置
EP0354449A3 (de) * 1988-08-08 1991-01-02 Seiko Epson Corporation Einkristall-Halbleitersubstrat
JP3038939B2 (ja) * 1991-02-08 2000-05-08 日産自動車株式会社 半導体装置
JP4521542B2 (ja) * 1999-03-30 2010-08-11 ルネサスエレクトロニクス株式会社 半導体装置および半導体基板
JP4397491B2 (ja) * 1999-11-30 2010-01-13 財団法人国際科学振興財団 111面方位を表面に有するシリコンを用いた半導体装置およびその形成方法
WO2001069673A1 (en) * 2000-03-13 2001-09-20 Tadahiro Ohmi Flash memory device and method for manufacturing the same, and method for forming dielectric film
US6586792B2 (en) * 2001-03-15 2003-07-01 Micron Technology, Inc. Structures, methods, and systems for ferroelectric memory transistors
US6514828B2 (en) * 2001-04-20 2003-02-04 Micron Technology, Inc. Method of fabricating a highly reliable gate oxide
JP2010018504A (ja) * 2008-07-14 2010-01-28 Japan Atomic Energy Agency Si(110)表面の一次元ナノ構造及びその製造方法

Also Published As

Publication number Publication date
EP1434253B1 (de) 2011-05-11
TW561588B (en) 2003-11-11
US20040032003A1 (en) 2004-02-19
IL156116A0 (en) 2003-12-23
JP2003115587A (ja) 2003-04-18
KR20040037278A (ko) 2004-05-06
EP1434253A4 (de) 2006-10-04
WO2003032399A1 (en) 2003-04-17
EP1434253A1 (de) 2004-06-30
KR100614822B1 (ko) 2006-08-25
US6903393B2 (en) 2005-06-07
IL156116A (en) 2009-09-22

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