ATE408896T1 - Verfahren zur selektiven ätzung von dotiertem siliziumoxid auf undotiertem siliziumoxid - Google Patents

Verfahren zur selektiven ätzung von dotiertem siliziumoxid auf undotiertem siliziumoxid

Info

Publication number
ATE408896T1
ATE408896T1 AT01956164T AT01956164T ATE408896T1 AT E408896 T1 ATE408896 T1 AT E408896T1 AT 01956164 T AT01956164 T AT 01956164T AT 01956164 T AT01956164 T AT 01956164T AT E408896 T1 ATE408896 T1 AT E408896T1
Authority
AT
Austria
Prior art keywords
etchant
silicon oxide
c2hxfy
undoped
present
Prior art date
Application number
AT01956164T
Other languages
English (en)
Inventor
Kei-Yu Ko
Li Li
Guy Blalock
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Application granted granted Critical
Publication of ATE408896T1 publication Critical patent/ATE408896T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/069—Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts

Landscapes

  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Formation Of Insulating Films (AREA)
AT01956164T 2000-07-05 2001-07-05 Verfahren zur selektiven ätzung von dotiertem siliziumoxid auf undotiertem siliziumoxid ATE408896T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US61004900A 2000-07-05 2000-07-05

Publications (1)

Publication Number Publication Date
ATE408896T1 true ATE408896T1 (de) 2008-10-15

Family

ID=24443420

Family Applications (1)

Application Number Title Priority Date Filing Date
AT01956164T ATE408896T1 (de) 2000-07-05 2001-07-05 Verfahren zur selektiven ätzung von dotiertem siliziumoxid auf undotiertem siliziumoxid

Country Status (8)

Country Link
EP (1) EP1297564B1 (de)
JP (1) JP2004503082A (de)
KR (1) KR100750081B1 (de)
CN (1) CN1211841C (de)
AT (1) ATE408896T1 (de)
AU (1) AU2001278191A1 (de)
DE (1) DE60135844D1 (de)
WO (1) WO2002003439A2 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10311691A1 (de) * 2003-03-17 2004-10-07 Infineon Technologies Ag Herstellungsverfahren für eine Halbleiterstruktur
US8778804B2 (en) * 2009-01-30 2014-07-15 Fei Company High selectivity, low damage electron-beam delineation etch
CN102945892B (zh) * 2012-11-07 2015-08-05 南通大学 一种太阳能电池制造方法
US10217681B1 (en) 2014-08-06 2019-02-26 American Air Liquide, Inc. Gases for low damage selective silicon nitride etching

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3420347A1 (de) * 1983-06-01 1984-12-06 Hitachi, Ltd., Tokio/Tokyo Gas und verfahren zum selektiven aetzen von siliciumnitrid
JPS61251138A (ja) * 1985-04-30 1986-11-08 Matsushita Electric Ind Co Ltd ドライエツチング方法
US5562801A (en) * 1994-04-28 1996-10-08 Cypress Semiconductor Corporation Method of etching an oxide layer
US6066555A (en) * 1995-12-22 2000-05-23 Cypress Semiconductor Corporation Method for eliminating lateral spacer erosion on enclosed contact topographies during RF sputter cleaning
US5814563A (en) * 1996-04-29 1998-09-29 Applied Materials, Inc. Method for etching dielectric using fluorohydrocarbon gas, NH3 -generating gas, and carbon-oxygen gas
US6849557B1 (en) * 1997-04-30 2005-02-01 Micron Technology, Inc. Undoped silicon dioxide as etch stop for selective etch of doped silicon dioxide
US6018184A (en) * 1998-01-22 2000-01-25 Micron Technology, Inc. Semiconductor structure useful in a self-aligned contact having multiple insulation layers of non-uniform thickness
US6117791A (en) * 1998-06-22 2000-09-12 Micron Technology, Inc. Etchant with selectivity for doped silicon dioxide over undoped silicon dioxide and silicon nitride, processes which employ the etchant, and structures formed thereby

Also Published As

Publication number Publication date
KR20030038651A (ko) 2003-05-16
EP1297564A2 (de) 2003-04-02
KR100750081B1 (ko) 2007-08-21
WO2002003439A8 (en) 2002-07-04
JP2004503082A (ja) 2004-01-29
CN1211841C (zh) 2005-07-20
AU2001278191A1 (en) 2002-01-14
CN1451176A (zh) 2003-10-22
DE60135844D1 (de) 2008-10-30
WO2002003439A2 (en) 2002-01-10
WO2002003439A3 (en) 2002-06-06
EP1297564B1 (de) 2008-09-17

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Legal Events

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RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties
REN Ceased due to non-payment of the annual fee