ATE408896T1 - Verfahren zur selektiven ätzung von dotiertem siliziumoxid auf undotiertem siliziumoxid - Google Patents

Verfahren zur selektiven ätzung von dotiertem siliziumoxid auf undotiertem siliziumoxid

Info

Publication number
ATE408896T1
ATE408896T1 AT01956164T AT01956164T ATE408896T1 AT E408896 T1 ATE408896 T1 AT E408896T1 AT 01956164 T AT01956164 T AT 01956164T AT 01956164 T AT01956164 T AT 01956164T AT E408896 T1 ATE408896 T1 AT E408896T1
Authority
AT
Austria
Prior art keywords
etchant
silicon oxide
c2hxfy
undoped
present
Prior art date
Application number
AT01956164T
Other languages
English (en)
Inventor
Kei-Yu Ko
Li Li
Guy Blalock
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Application granted granted Critical
Publication of ATE408896T1 publication Critical patent/ATE408896T1/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Formation Of Insulating Films (AREA)
AT01956164T 2000-07-05 2001-07-05 Verfahren zur selektiven ätzung von dotiertem siliziumoxid auf undotiertem siliziumoxid ATE408896T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US61004900A 2000-07-05 2000-07-05

Publications (1)

Publication Number Publication Date
ATE408896T1 true ATE408896T1 (de) 2008-10-15

Family

ID=24443420

Family Applications (1)

Application Number Title Priority Date Filing Date
AT01956164T ATE408896T1 (de) 2000-07-05 2001-07-05 Verfahren zur selektiven ätzung von dotiertem siliziumoxid auf undotiertem siliziumoxid

Country Status (8)

Country Link
EP (1) EP1297564B1 (de)
JP (1) JP2004503082A (de)
KR (1) KR100750081B1 (de)
CN (1) CN1211841C (de)
AT (1) ATE408896T1 (de)
AU (1) AU2001278191A1 (de)
DE (1) DE60135844D1 (de)
WO (1) WO2002003439A2 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10311691A1 (de) * 2003-03-17 2004-10-07 Infineon Technologies Ag Herstellungsverfahren für eine Halbleiterstruktur
US8778804B2 (en) * 2009-01-30 2014-07-15 Fei Company High selectivity, low damage electron-beam delineation etch
CN102945892B (zh) * 2012-11-07 2015-08-05 南通大学 一种太阳能电池制造方法
US10217681B1 (en) 2014-08-06 2019-02-26 American Air Liquide, Inc. Gases for low damage selective silicon nitride etching

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3420347A1 (de) * 1983-06-01 1984-12-06 Hitachi, Ltd., Tokio/Tokyo Gas und verfahren zum selektiven aetzen von siliciumnitrid
JPS61251138A (ja) * 1985-04-30 1986-11-08 Matsushita Electric Ind Co Ltd ドライエツチング方法
US5562801A (en) * 1994-04-28 1996-10-08 Cypress Semiconductor Corporation Method of etching an oxide layer
US6066555A (en) * 1995-12-22 2000-05-23 Cypress Semiconductor Corporation Method for eliminating lateral spacer erosion on enclosed contact topographies during RF sputter cleaning
US5814563A (en) * 1996-04-29 1998-09-29 Applied Materials, Inc. Method for etching dielectric using fluorohydrocarbon gas, NH3 -generating gas, and carbon-oxygen gas
US6849557B1 (en) * 1997-04-30 2005-02-01 Micron Technology, Inc. Undoped silicon dioxide as etch stop for selective etch of doped silicon dioxide
US6018184A (en) * 1998-01-22 2000-01-25 Micron Technology, Inc. Semiconductor structure useful in a self-aligned contact having multiple insulation layers of non-uniform thickness
US6117791A (en) * 1998-06-22 2000-09-12 Micron Technology, Inc. Etchant with selectivity for doped silicon dioxide over undoped silicon dioxide and silicon nitride, processes which employ the etchant, and structures formed thereby

Also Published As

Publication number Publication date
WO2002003439A2 (en) 2002-01-10
DE60135844D1 (de) 2008-10-30
CN1211841C (zh) 2005-07-20
WO2002003439A8 (en) 2002-07-04
KR100750081B1 (ko) 2007-08-21
JP2004503082A (ja) 2004-01-29
EP1297564A2 (de) 2003-04-02
AU2001278191A1 (en) 2002-01-14
WO2002003439A3 (en) 2002-06-06
CN1451176A (zh) 2003-10-22
KR20030038651A (ko) 2003-05-16
EP1297564B1 (de) 2008-09-17

Similar Documents

Publication Publication Date Title
KR960009043A (ko) 질화 규소의 에칭 방법
ATE354176T1 (de) Verfahren und zusammensetzung zur entfernung von photoresist in der halbleiterfertigung
ATE408896T1 (de) Verfahren zur selektiven ätzung von dotiertem siliziumoxid auf undotiertem siliziumoxid
EP0265584A3 (de) Verfahren und Materialien zum Ätzen von Siliziumdioxid unter Verwendung eines Ätzstops aus Siliziumnitrid oder siliziumreichem Siliziumdioxid
KR960012359A (ko) 실리콘 질화물의 에칭 방법
KR970008397A (ko) 식각용액 및 이를 이용한 반도체 장치의 식각방법
KR950034853A (ko) 반도체 장치의 채널 영역 제조 방법
JP2006128613A (ja) 半導体素子の製造方法
KR950021178A (ko) 반도체 장치의 제조 방법
KR100196523B1 (ko) 반도체 소자 제조방법
KR930020600A (ko) 폴리실리콘의 식각후 발생되는 폴리머 제거방법
KR970016833A (ko) 버퍼 산화 식각용액(boe)을 이용한 콘택홀의 형성방법
KR20050022617A (ko) 리세스 채널 ｍｏｓｆｅｔ용 리세스 트렌치 형성방법
KR970003641A (ko) 잔류 폴리실리콘 제거 방법
KR930001335A (ko) 반도체 장치의 다결정 실리콘층 식각방법
KR950012676A (ko) 반도체장치의 소자분리방법
KR960026215A (ko) 콘택 홀 형성방법
KR980005578A (ko) 반도체 소자의 콘택홀 형성방법
KR19990053457A (ko) 반도체장치의 트렌치 제조방법
KR940009758A (ko) 산화막 건식 식각후 잔류물 제거방법
Jarreau Plasma process-induced defects of Cz-silicon during oxide over-etch.
KR970072134A (ko) 반도체 장치의 실리콘 나이트라이드막 에칭 방법
KR970052203A (ko) 반도체 소자의 콘택홀 제조방법
KR970053388A (ko) 반도체 장치의 쉘로우 트랜치 아이솔레이션 형성 방법
JPH10209123A (ja) ドライエッチング時に生成される側壁保護膜の洗浄方法

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties
REN Ceased due to non-payment of the annual fee