ATE242547T1 - Verfahren zur herstellung eines halbleitersubstrats - Google Patents

Verfahren zur herstellung eines halbleitersubstrats

Info

Publication number
ATE242547T1
ATE242547T1 AT94309852T AT94309852T ATE242547T1 AT E242547 T1 ATE242547 T1 AT E242547T1 AT 94309852 T AT94309852 T AT 94309852T AT 94309852 T AT94309852 T AT 94309852T AT E242547 T1 ATE242547 T1 AT E242547T1
Authority
AT
Austria
Prior art keywords
semiconductor substrate
bonded
substrate
producing
heat treatment
Prior art date
Application number
AT94309852T
Other languages
English (en)
Inventor
Kenji Yamagata
Takao Yonehara
Original Assignee
Canon Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Kk filed Critical Canon Kk
Application granted granted Critical
Publication of ATE242547T1 publication Critical patent/ATE242547T1/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
AT94309852T 1993-12-28 1994-12-28 Verfahren zur herstellung eines halbleitersubstrats ATE242547T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33749493 1993-12-28

Publications (1)

Publication Number Publication Date
ATE242547T1 true ATE242547T1 (de) 2003-06-15

Family

ID=18309184

Family Applications (1)

Application Number Title Priority Date Filing Date
AT94309852T ATE242547T1 (de) 1993-12-28 1994-12-28 Verfahren zur herstellung eines halbleitersubstrats

Country Status (8)

Country Link
US (2) US5695557A (de)
EP (1) EP0663688B1 (de)
KR (1) KR0145786B1 (de)
CN (1) CN1036813C (de)
AT (1) ATE242547T1 (de)
CA (1) CA2139187C (de)
DE (1) DE69432784T2 (de)
TW (1) TW330313B (de)

Families Citing this family (267)

* Cited by examiner, † Cited by third party
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US5695557A (en) 1997-12-09
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EP0663688B1 (de) 2003-06-04
DE69432784D1 (de) 2003-07-10
US5980633A (en) 1999-11-09
CN1109636A (zh) 1995-10-04
KR0145786B1 (ko) 1998-11-02
TW330313B (en) 1998-04-21
DE69432784T2 (de) 2004-05-19
EP0663688A2 (de) 1995-07-19

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