WO2023088067A1 - 浮栅型分栅闪存器件及其制造方法 - Google Patents

浮栅型分栅闪存器件及其制造方法 Download PDF

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WO2023088067A1
WO2023088067A1 PCT/CN2022/128196 CN2022128196W WO2023088067A1 WO 2023088067 A1 WO2023088067 A1 WO 2023088067A1 CN 2022128196 W CN2022128196 W CN 2022128196W WO 2023088067 A1 WO2023088067 A1 WO 2023088067A1
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layer
gate
polysilicon
floating
floating gate
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许昭昭
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华虹半导体(无锡)有限公司
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates

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  • the invention relates to the technical field of semiconductors, in particular to a floating gate split-gate flash memory device and a manufacturing method thereof.
  • Split-gate floating gate (Floating-gate) flash memory technology is widely used in various embedded electronic products such as financial IC cards, automotive electronics and other applications.
  • This flash memory can increase the storage integration density, which is conducive to saving chip area, Reduce manufacturing costs.
  • the manufacturing method of the sub-gate floating gate flash memory device of existing 2-bit/cell comprises the following steps:
  • Step 1 implanting and forming a P-type well 101 on the P-type substrate, and thermally oxidizing and growing a floating gate oxide layer 102, a first floating gate polysilicon (Poly) layer 103, and a first silicon nitride layer 502 on the P-type well 101;
  • the STI Shallow-Trench-Isolation, Shallow Trench Isolation
  • the STI forms the shallow trench 501; at the same time defines the active area of the flash memory and the peripheral logic area.
  • Step 2 sequentially deposit inter-polysilicon ONO (Oxide-Nitride-Oxide, oxide/nitride/oxide) layer 104, first control gate polysilicon layer 105, and thick silicon nitride layer 504; photolithography defines the flash memory cell area, and Etching removes the thick silicon nitride layer in the area of the opening.
  • ONO Oxide-Nitride-Oxide, oxide/nitride/oxide
  • Step 3 depositing a first silicon oxide layer, and using anisotropic etching to form a first spacer dielectric layer 112, the width of the bottom of the sidewall defines the length of the control gate.
  • Step 4 using the first sidewall dielectric layer as a hard mask, performing anisotropic etching on the control gate polysilicon to form a self-aligned control gate, and etching the ONO layer.
  • Step 5 depositing an insulating dielectric layer and anisotropically etching to form a second spacer dielectric layer 106 , using the second sidewall and the first sidewall together as a hard mask, and self-aligned etching to form a floating gate.
  • Step 6 depositing the selection gate dielectric layer 107 and the selection gate polysilicon layer 108 in sequence, and forming a self-aligned selection gate by CMP (Chemical Mechanical Polish, chemical mechanical polishing).
  • CMP Chemical Mechanical Polish, chemical mechanical polishing
  • Step seven thermal oxidation forms silicon oxide on the polysilicon layer 108 of the selection gate, and uses the first spacer 112 and the selection gate dielectric layer 107 as a hard mask, and the remaining thick silicon nitride layer 504 on both sides, the first control
  • the gate polysilicon layer 105, the inter-polysilicon ONO layer 104, and the first floating gate polysilicon layer 103 are removed, and sequentially perform LDD (Lightly Doped Drain, lightly doped drain) implantation to form the first LDD region 110, and deposit and etch to form the third side
  • LDD Lightly Doped Drain, lightly doped drain
  • source and drain implantation forms source and drain regions (ie, source and drain regions) 111
  • a metal silicide process forms a low-resistivity metal silicide 113 .
  • the present invention provides a floating-gate split-gate flash memory device and a manufacturing method thereof.
  • a floating gate split-gate flash memory device characterized in that it includes a P-type well, a selection gate oxide layer, a selection gate polysilicon layer, an ONO layer between polysilicon,
  • the oxide layer and the selection gate polysilicon layer are sequentially located on the P-type well, the hard mask layer is located on the selection gate polysilicon layer, and the floating gate dielectric layer is deposited on the hard mask layer, selection gate oxide layer, selection gate polysilicon layer, P On the P-type well, the second floating gate polysilicon layer is located between the inter-polysilicon ONO layer and the floating gate dielectric layer, the second control gate polysilicon layer is located outside the inter-polysilicon ONO layer,
  • both the second control gate polysilicon layer and the second floating gate polysilicon layer are sidewall type polysilicon.
  • the inter-polysilicon ONO layer includes a second silicon oxide layer, a second silicon nitride layer, and a third silicon oxide layer, and the second silicon nitride layer is located between the second silicon oxide layer and the third silicon oxide layer.
  • the inter-polysilicon ONO layer has a U-shape.
  • the present invention also provides a method for manufacturing a floating-gate split-gate flash memory device, which is characterized in that it includes the following steps:
  • Step 11 implanting on the P-type substrate to form a P-type well, and sequentially forming a selection gate oxide layer, a selection gate polysilicon layer, and a hard mask layer on the P-type well;
  • Step 12 depositing and forming a fourth sidewall dielectric layer, using the sidewall dielectric layer and the hard mask layer as the hard mask layer to self-align and sequentially anisotropically etch the selection gate oxide layer and the selection gate polysilicon layer;
  • Step 13 sequentially deposit and form a floating gate dielectric layer and a second floating gate polysilicon layer, selectively etch the floating gate in the width direction of the device to form floating gate polysilicon blocks that are isolated from each other, and then deposit to form a control gate and a floating gate polysilicon layer.
  • Step 14 depositing and forming a second control gate polysilicon layer and anisotropically etching the second control gate polysilicon layer;
  • Step fifteen sequentially anisotropically etching the inter-polysilicon ONO layer between the control gate and the floating gate, the second floating gate polysilicon layer, and performing LDD implantation to form a second LDD region;
  • Step sixteen depositing and etching to form a fifth sidewall dielectric layer and a sixth sidewall dielectric layer, and performing source-drain heavily doped implantation to form source-drain regions.
  • the morphology of the hard mask layer is defined by photolithography, and the photoresist is removed.
  • the steps 13, 14 and 16 are all deposited by chemical vapor deposition process.
  • the positive progress effect of the present invention lies in: the present invention changes the original CG and FG from the longitudinal coupling to the combination of longitudinal and transverse coupling, the device structure shrinks as the device continues to shrink, the longitudinal coupling gradually decreases, and the proportion of the transverse coupling is the main Therefore, the overlapping area of CG and FG can be increased by increasing the height of the control gate of the device, and the coupling coefficient from CG to FG of the device can be increased.
  • the overlapping area of WL-FG depends on WL -The thickness of Poly, the thickness of WL-Poly is less than 500A, and the height of CG-Poly>1000A can effectively reduce the coupling coefficient of WL-FG and increase the coupling coefficient of CG-FG at the same time, the second control gate polysilicon layer and the second floating gate
  • the polysilicon layer is all sidewall type polysilicon, which can realize self-aligned etching of the control gate and the floating gate, and is beneficial to reducing the size of the device.
  • 1 to 7 are diagrams of process steps of a split-gate floating-gate flash memory device in the prior art.
  • FIG. 8 is a schematic diagram of the relationship between the current on the bit line and the voltage of CG in the prior art.
  • 9 to 14 are diagrams of process steps of the floating-gate split-gate flash memory device of the present invention.
  • FIG. 15 is a schematic diagram of the relationship between the current on the bit line and the voltage of CG in the present invention.
  • the floating gate split-gate flash memory device of the present invention includes a P-type well 101, a selection gate oxide layer 1021, a selection gate polysilicon layer 1031, an inter-polysilicon ONO layer, a second control gate polysilicon layer 1051, a hard mask layer 1061, and a floating gate medium.
  • Second floating gate polysilicon layer 1081 is located on the selection gate polysilicon layer 1031, and the floating gate dielectric layer 1071 is deposited on the hard mask layer 1061, selection gate oxide layer 1021, selection gate polysilicon layer 1031, P-type
  • the second floating gate polysilicon layer 1081 is located between the inter-polysilicon ONO layer and the floating gate dielectric layer 1071
  • the second control gate polysilicon layer 1051 is located outside the inter-polysilicon ONO layer
  • the second LDD region 1091, the source-drain region 111 Both are located on top of both sides of the P-type well 101
  • the fifth sidewall dielectric layer 1101 and the sixth sidewall dielectric layer 1102 are located outside the second control gate polysilicon layer
  • Both the second control gate polysilicon layer 1051 and the second floating gate polysilicon layer 1081 are sidewall type polysilicon, which can realize self-aligned etching of the control gate and the floating gate, which is beneficial to reducing the size of the device.
  • the inter-polysilicon ONO layer includes a second silicon oxide layer 1041, a second silicon nitride layer 1042, and a third silicon oxide layer 1043, and the second silicon nitride layer 1042 is located between the second silicon oxide layer 1041 and the third silicon oxide layer 1043 , can obtain higher critical electric field strength and lower defect density.
  • the shape of the inter-polysilicon ONO layer is U-shaped, which is convenient for covering the floating gate dielectric layer 1071 and the like.
  • the floating gate dielectric layer 1071 is made of silicon oxide.
  • the manufacturing method of the floating gate split-gate flash memory device of the present invention includes the following steps:
  • Step 11 Implant the P-type well 101 on the P-type substrate, and sequentially form the selection gate oxide layer 1021, the selection gate polysilicon layer 1031, and the hard mask layer 1061 on the P-type well 101; The topography of the film layer 1061 is removed, and the photoresist is removed.
  • the hard mask layer 1061 is also used as an isolation dielectric layer between the floating gate layers.
  • Step 12 depositing and forming the fourth sidewall dielectric layer 5021, using the sidewall dielectric layer 5021 and the hard mask layer 1061 as the hard mask layer to self-align and sequentially anisotropically etch the selection gate oxide layer 1021, the selection gate polysilicon layer 1031;
  • Step 13 sequentially deposit and form the floating gate dielectric layer 1071 and the second floating gate polysilicon layer 1081, selectively etch the floating gate in the width direction of the device to form floating gate polysilicon blocks isolated from each other, and then deposit to form the control gate Inter-polysilicon ONO layer between the floating gate;
  • Step fourteen depositing and forming a second control gate polysilicon layer 1051 and anisotropically etching the second control gate polysilicon layer 1051;
  • Step fifteen sequentially anisotropically etching the inter-polysilicon ONO layer between the control gate and the floating gate, the second floating gate polysilicon layer 1081, and performing LDD implantation to form a second LDD region 1091;
  • step sixteen deposit and etch to form a fifth sidewall dielectric layer 1101 and a sixth sidewall dielectric layer 1102 , and perform source-drain heavily doped implantation to form source-drain regions 111 .
  • the inter-polysilicon ONO layer includes a second silicon oxide layer 1041, a second silicon nitride layer 1042, and a third silicon oxide layer 1043, and the second silicon nitride layer 1042 is located between the second silicon oxide layer 1041 and the third silicon oxide layer 1043 , can obtain higher critical electric field strength and lower defect density.
  • Step 13, step 14, and step 16 are all deposited by chemical vapor deposition process, which can control the density and purity of the coating.
  • the upper side is the relationship curve of the prior art
  • the lower side is the relationship curve of the present invention.
  • the present invention changes the original CG and FG from the longitudinal coupling to the combination of longitudinal and lateral coupling.
  • the longitudinal coupling gradually decreases, and the proportion of the lateral coupling is the main one. Therefore,
  • the overlapping area of CG and FG can be increased by increasing the height of the control gate of the device, and the coupling coefficient from CG to FG of the device can be increased.
  • the size of the device can be reduced It will not reduce the coupling coefficient of CG-FG, which is conducive to the miniaturization of devices, to enhance the control ability of CG, reduce the effect of device leakage, and improve the performance of flash memory devices; the overlapping area of WL-FG depends on the WL-Poly
  • the thickness of WL-Poly is less than 500A, and the height of CG-Poly>1000A can effectively reduce the coupling coefficient of WL-FG and increase the coupling coefficient of CG-FG at the same time.
  • the second control gate polysilicon layer and the second floating gate polysilicon layer are both It is sidewall type polysilicon, which can realize self-aligned etching of control gate and floating gate, which is conducive to reducing the size of the device.

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Abstract

本发明公开了一种浮栅型分栅闪存器件及其制造方法，该浮栅型分栅闪存器件包括P型阱等，选择栅氧化层、选择栅多晶硅层依次位于P型阱上，硬质掩膜层位于选择栅多晶硅层的上面，浮栅介质层沉积在硬质掩膜层、选择栅氧化层、选择栅多晶硅层、P型阱上，第二浮栅多晶硅层位于多晶硅间ONO层和浮栅介质层之间，第二控制栅多晶硅层位于多晶硅间ONO层的外侧，第二LDD区、源漏区都位于P型阱的两侧顶部，第五侧墙介质层、第六侧墙介质层依次位于第二控制栅多晶硅层的外侧。本发明将原有的CG和FG由纵向耦合变成纵向和横向的组合耦合，该器件结构随器件不断微缩，纵向耦合逐渐减小，达到增强CG控制能力，减小器件漏电的效果。

Description

浮栅型分栅闪存器件及其制造方法 技术领域
本发明涉及半导体技术领域，特别是涉及一种浮栅型分栅闪存器件及其制造方法。
背景技术
分栅(split-gate)浮栅(Floating-gate)闪存技术被广泛用于各种嵌入式电子产品如金融IC卡、汽车电子等应用，该闪存可以提高存储集成密度，有利于节省芯片面积、降低制造成本。
如图1至图7，现有的2-bit/cell(二比特每存储单元)的分栅浮栅闪存器件的制造方法包括以下步骤：
步骤一，在P型衬底上注入形成P型阱101，P型阱101上热氧化生长浮栅氧化层102、第一浮栅多晶硅(Poly)层103和第一氮化硅层502；进行STI(Shallow-Trench-Isolation，浅沟隔离)工艺形成浅沟槽501；同时定义闪存和外围逻辑区的有源区。
步骤二，依次沉积多晶硅间ONO(Oxide-Nitride-Oxide，氧化物/氮化物/氧化物)层104、第一控制栅多晶硅层105、厚氮化硅层504；光刻定义闪存单元区域，并刻蚀去除开口区域的厚氮化硅层。
步骤三，沉积第一氧化硅层，并利用各向异性刻蚀形成第一侧墙介质层112，该侧墙的底部宽度定义了控制栅的长度。
步骤四，利用第一侧墙介质层作为硬质掩膜，对控制栅多晶硅进行各向异性刻蚀，形成自对准的控制栅，并刻蚀ONO层。
步骤五，沉积绝缘介质层，并各向异性刻蚀形成第二侧墙介质层106，利用第二侧墙和第一侧墙共同作为硬质掩膜，自对准刻蚀形成浮栅。
步骤六，依次沉积选择栅介质层107和选择栅多晶硅层108，并通过 CMP(Chemical Mechanical Polish，化学机械研磨)方式形成自对准的选择栅。
步骤七，热氧化在选择栅多晶硅层108上方形成氧化硅，并与第一侧墙112、选择栅介质层107作为硬质掩膜，将两侧剩余的厚氮化硅层504、第一控制栅多晶硅层105、多晶硅间ONO层104、第一浮栅多晶硅层103去除，并依次进行LDD(Lightly Doped Drain，轻掺杂漏)注入形成第一LDD区110，沉积和刻蚀形成第三侧墙介质层109，源漏注入形成源漏区(即源区和漏区)111，金属硅化工艺形成低电阻率的金属硅化物113。
而对浮栅型分栅闪存器件的进一步微缩发现，由于CG(Control-Gate，控制栅)与FG(Floating Gate,浮栅)交叠的面积的减小，CG至FG的耦合系数大幅下降，而WL(Word-Line字线)至FG的耦合系数从原有的13.7％迅速增加至24.6％，WL耦合系数的迅速增大使得器件CG的关断能力(CG的控制能力)变差，漏电十分严重(BL(Bit Line，位线)上的电流和CG的电压关系曲线显示亚阈值摆幅达到800mV/decade，如图9所示)。因此如何增大CG的耦合系数(即增大CG与FG的交叠面积)、减小WL的耦合系数对于进一步微缩浮栅型分栅闪存十分关键。其中，图8的横坐标代表控制栅电压，图8的纵坐标代表位线电流。
发明内容
针对上述情况，为了克服现有技术的缺陷，本发明提供一种浮栅型分栅闪存器件及其制造方法。
本发明是通过下述技术方案来解决上述技术问题的：一种浮栅型分栅闪存器件，其特征在于，其包括P型阱、选择栅氧化层、选择栅多晶硅层、多晶硅间ONO层、第二控制栅多晶硅层、硬质掩膜层、浮栅介质层、第二浮栅多晶硅层、第二LDD区、第五侧墙介质层、第六侧墙介质层、源漏区，选择栅氧化层、选择栅多晶硅层依次位于P型阱上，硬质掩膜层位于选择栅多晶硅层的上面，浮栅介质层沉积在硬质掩膜层、选择栅氧化层、选择栅多晶硅层、P型阱上，第二浮栅多晶硅层位于多晶硅间ONO层和浮栅介质层之间， 第二控制栅多晶硅层位于多晶硅间ONO层的外侧，第二LDD区、源漏区都位于P型阱的两侧顶部，第五侧墙介质层、第六侧墙介质层依次位于第二控制栅多晶硅层的外侧。
优选地，所述第二控制栅多晶硅层和第二浮栅多晶硅层均为侧墙型多晶硅。
优选地，所述多晶硅间ONO层包括第二氧化硅层、第二氮化硅层、第三氧化硅层，第二氮化硅层位于第二氧化硅层和第三氧化硅层之间。
优选地，所述多晶硅间ONO层的形状为U形状。
本发明还提供一种浮栅型分栅闪存器件的制造方法，其特征在于，其包括以下步骤：
步骤十一，在P型衬底上注入形成P型阱，P型阱上依次形成选择栅氧化层、选择栅多晶硅层、硬质掩膜层；
步骤十二，沉积形成第四侧墙介质层，以侧墙介质层和硬质掩膜层为硬质掩膜层自对准依次各向异性刻蚀选择栅氧化层、选择栅多晶硅层；
步骤十三，依次沉积形成浮栅介质层、第二浮栅多晶硅层，光刻选择性刻蚀在器件的宽度方向上将浮栅形成相互隔离的浮栅多晶硅块，再沉积形成控制栅与浮栅之间的多晶硅间ONO层；
步骤十四，沉积形成第二控制栅多晶硅层并各向异性刻蚀第二控制栅多晶硅层；
步骤十五，依次各向异性刻蚀控制栅与浮栅之间的多晶硅间ONO层、第二浮栅多晶硅层，并进行LDD注入形成第二LDD区；
步骤十六，沉积并刻蚀形成第五侧墙介质层和第六侧墙介质层，进行源漏重掺杂注入形成源漏区。
优选地，所述步骤十一光刻定义出硬质掩膜层的形貌，并去除光刻胶。
优选地，所述步骤十三、步骤十四、步骤十六都采用化学气相沉积工艺进行沉积。
本发明的积极进步效果在于：本发明将原有的CG和FG由纵向耦合变成纵向和横向的组合耦合，该器件结构随器件不断微缩，纵向耦合逐渐减小，横向耦合的占比为主要的，因此可通过增加器件控制栅的高度来增加CG和FG的交叠面积，提高器件的CG至FG的耦合系数，由于是通过横向耦合(交叠面积只与CG的高度有关)，所以缩小器件的尺寸并不会减小CG-FG的耦合系数，有利于器件的微缩，达到增强CG控制能力，减小器件漏电的效果，提高闪存器件的性能；WL-FG的交叠面积取决于WL-Poly的厚度，WL-Poly的厚度小于500A，CG-Poly高度>1000A可有效地降低WL-FG的耦合系数、同时增加CG-FG的耦合系数，第二控制栅多晶硅层和第二浮栅多晶硅层均为侧墙型多晶硅，可实现控制栅、浮栅自对准刻蚀，有利于缩小器件的尺寸。
附图说明
图1至图7为现有技术分栅浮栅闪存器件的工艺步骤图。
图8为现有技术位线上的电流和CG的电压关系曲线的示意图。
图9至图14为本发明浮栅型分栅闪存器件的工艺步骤图。
图15为本发明位线上的电流和CG的电压关系曲线的示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。
本发明浮栅型分栅闪存器件包括P型阱101、选择栅氧化层1021、选择栅多晶硅层1031、多晶硅间ONO层、第二控制栅多晶硅层1051、硬质掩膜层1061、浮栅介质层1071、第二浮栅多晶硅层1081、第二LDD区1091、第五侧墙介质层1101、第六侧墙介质层1102、源漏区111，选择栅氧化层1021、选择栅多晶硅层1031依次位于P型阱101上，硬质掩膜层1061位于选择栅多晶硅层1031的上面，浮栅介质层1071沉积在硬质掩膜层1061、选择栅氧化层1021、选择栅多晶硅层1031、P型阱101上，第二浮栅多晶硅层1081 位于多晶硅间ONO层和浮栅介质层1071之间，第二控制栅多晶硅层1051位于多晶硅间ONO层的外侧，第二LDD区1091、源漏区111都位于P型阱101的两侧顶部，第五侧墙介质层1101、第六侧墙介质层1102依次位于第二控制栅多晶硅层1051的外侧。
第二控制栅多晶硅层1051和第二浮栅多晶硅层1081均为侧墙型多晶硅，可实现控制栅、浮栅自对准刻蚀，有利于缩小器件的尺寸。
多晶硅间ONO层包括第二氧化硅层1041、第二氮化硅层1042、第三氧化硅层1043，第二氮化硅层1042位于第二氧化硅层1041和第三氧化硅层1043之间，能获得较高的临界电场强度和较低的缺陷密度。
多晶硅间ONO层的形状为U形状，方便包覆浮栅介质层1071等。
浮栅介质层1071采用氧化硅。
如图9至图14所示，本发明浮栅型分栅闪存器件的制造方法包括以下步骤：
步骤十一，在P型衬底上注入形成P型阱101，P型阱101上依次形成选择栅氧化层1021、选择栅多晶硅层1031、硬质掩膜层1061；光刻定义出硬质掩膜层1061的形貌，并去除光刻胶，硬质掩膜层1061除了用作硬质掩膜层之外，还用作浮栅层之间的隔离介质层。
步骤十二，沉积形成第四侧墙介质层5021，以侧墙介质层5021和硬质掩膜层1061为硬质掩膜层自对准依次各向异性刻蚀选择栅氧化层1021、选择栅多晶硅层1031；
步骤十三，依次沉积形成浮栅介质层1071、第二浮栅多晶硅层1081，光刻选择性刻蚀在器件的宽度方向上将浮栅形成相互隔离的浮栅多晶硅块，再沉积形成控制栅与浮栅之间的多晶硅间ONO层；
步骤十四，沉积形成第二控制栅多晶硅层1051并各向异性刻蚀第二控制栅多晶硅层1051；
步骤十五，依次各向异性刻蚀控制栅与浮栅之间的多晶硅间ONO层、 第二浮栅多晶硅层1081，并进行LDD注入形成第二LDD区1091；
步骤十六，沉积并刻蚀形成第五侧墙介质层1101和第六侧墙介质层1102，进行源漏重掺杂注入形成源漏区111。
多晶硅间ONO层包括第二氧化硅层1041、第二氮化硅层1042、第三氧化硅层1043，第二氮化硅层1042位于第二氧化硅层1041和第三氧化硅层1043之间，能获得较高的临界电场强度和较低的缺陷密度。
步骤十三、步骤十四、步骤十六都采用化学气相沉积工艺进行沉积，可以控制涂层的密度和涂层纯度。
从图15看出，侧上方是现有技术关系曲线，侧下方是本发明关系曲线，增加CG和FG的交叠面积同时保证WL与FG的有效交叠面积基本不变后，在不改变任何注入条件的情况下，Sub-threshold slope(次临界斜率)减小了50％。由于CG的控制栅的耦合面积的大幅增加，漏电流Ir01降低>7个数量级，同时读电流Ir10也增加了50％，大大增加了存储器件的读电流的窗口。
综上所述，本发明将原有的CG和FG由纵向耦合变成纵向和横向的组合耦合，该器件结构随器件不断微缩，纵向耦合逐渐减小，横向耦合的占比为主要的，因此可通过增加器件控制栅的高度来增加CG和FG的交叠面积，提高器件的CG至FG的耦合系数，由于是通过横向耦合(交叠面积只与CG的高度有关)，所以缩小器件的尺寸并不会减小CG-FG的耦合系数，有利于器件的微缩，达到增强CG控制能力，减小器件漏电的效果，提高闪存器件的性能；WL-FG的交叠面积取决于WL-Poly的厚度，WL-Poly的厚度小于500A，CG-Poly高度>1000A可有效地降低WL-FG的耦合系数、同时增加CG-FG的耦合系数，第二控制栅多晶硅层和第二浮栅多晶硅层均为侧墙型多晶硅，可实现控制栅、浮栅自对准刻蚀，有利于缩小器件的尺寸。
上述具体实施方式为本发明的优选实施例，并不能对本发明进行限定，其他的任何未背离本发明的技术方案而所做的改变或其它等效的置换方式，都包含在本发明的保护范围之内。

Claims (8)

  1. 一种浮栅型分栅闪存器件，其特征在于，其包括P型阱、选择栅氧化层、选择栅多晶硅层、多晶硅间ONO层、第二控制栅多晶硅层、硬质掩膜层、浮栅介质层、第二浮栅多晶硅层、第二LDD区、第五侧墙介质层、第六侧墙介质层、源漏区，选择栅氧化层、选择栅多晶硅层依次位于P型阱上，硬质掩膜层位于选择栅多晶硅层的上面，浮栅介质层沉积在硬质掩膜层、选择栅氧化层、选择栅多晶硅层、P型阱上，第二浮栅多晶硅层位于多晶硅间ONO层和浮栅介质层之间，第二控制栅多晶硅层位于多晶硅间ONO层的外侧，第二LDD区、源漏区都位于P型阱的两侧顶部，第五侧墙介质层、第六侧墙介质层依次位于第二控制栅多晶硅层的外侧。
  2. 如权利要求1所述的浮栅型分栅闪存器件，其特征在于，所述第二控制栅多晶硅层和第二浮栅多晶硅层均为侧墙型多晶硅。
  3. 如权利要求1所述的浮栅型分栅闪存器件，其特征在于，所述多晶硅间ONO层包括第二氧化硅层、第二氮化硅层、第三氧化硅层，第二氮化硅层位于第二氧化硅层和第三氧化硅层之间。
  4. 如权利要求1所述的浮栅型分栅闪存器件，其特征在于，所述多晶硅间ONO层的形状为U形状。
  5. 如权利要求1所述的浮栅型分栅闪存器件，其特征在于，所述浮栅介质层采用氧化硅。
  6. 一种浮栅型分栅闪存器件的制造方法，其特征在于，其包括以下步骤：
    步骤十一，在P型衬底上注入形成P型阱，P型阱上依次形成选择栅氧化层、选择栅多晶硅层、硬质掩膜层；
    步骤十二，沉积形成第四侧墙介质层，以侧墙介质层和硬质掩膜层为硬质掩膜层自对准依次各向异性刻蚀选择栅氧化层、选择栅多晶硅层；
    步骤十三，依次沉积形成浮栅介质层、第二浮栅多晶硅层，光刻选择性 刻蚀在器件的宽度方向上将浮栅形成相互隔离的浮栅多晶硅块，再沉积形成控制栅与浮栅之间的多晶硅间ONO层；
    步骤十四，沉积形成第二控制栅多晶硅层并各向异性刻蚀第二控制栅多晶硅层；
    步骤十五，依次各向异性刻蚀控制栅与浮栅之间的多晶硅间ONO层、第二浮栅多晶硅层，并进行LDD注入形成第二LDD区；
    步骤十六，沉积并刻蚀形成第五侧墙介质层和第六侧墙介质层，进行源漏重掺杂注入形成源漏区。
  7. 如权利要求6所述的浮栅型分栅闪存器件的制造方法，其特征在于，所述步骤十一光刻定义出硬质掩膜层的形貌，并去除光刻胶。
  8. 如权利要求6所述的浮栅型分栅闪存器件的制造方法，其特征在于，所述步骤十三、步骤十四、步骤十六都采用化学气相沉积工艺进行沉积。
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