WO2022068767A1 - 一种三维存储器及其制作方法 - Google Patents

一种三维存储器及其制作方法 Download PDF

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Publication number
WO2022068767A1
WO2022068767A1 PCT/CN2021/120889 CN2021120889W WO2022068767A1 WO 2022068767 A1 WO2022068767 A1 WO 2022068767A1 CN 2021120889 W CN2021120889 W CN 2021120889W WO 2022068767 A1 WO2022068767 A1 WO 2022068767A1
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Prior art keywords
dummy
gate line
gap
dummy portion
dimensional memory
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PCT/CN2021/120889
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English (en)
French (fr)
Inventor
张中
韩玉辉
孔翠翠
张坤
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长江存储科技有限责任公司
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Application filed by 长江存储科技有限责任公司 filed Critical 长江存储科技有限责任公司
Priority to CN202310099374.2A priority Critical patent/CN115988878A/zh
Priority to CN202180003290.3A priority patent/CN114080680B/zh
Priority to US17/559,181 priority patent/US20220115392A1/en
Publication of WO2022068767A1 publication Critical patent/WO2022068767A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

Definitions

  • This application is a divisional application for a patent application with an application date of September 29, 2020, an application number of 202011046857.9, and the title of the invention is a three-dimensional memory and its manufacturing method.
  • the invention belongs to the technical field of semiconductor integrated circuits, and relates to a three-dimensional memory and a manufacturing method thereof.
  • planar flash memory With the development of planar flash memory, the production process of semiconductors has made great progress. However, in recent years, the development of planar flash memory has encountered various challenges: physical limits, existing development technology limits, and storage electron density limits. In this context, in order to solve the difficulties encountered by planar flash memory and pursue lower production costs per unit storage unit, various three-dimensional (3D) flash memory structures have emerged, such as 3D NOR (3D or non) flash memory and 3D NAND (3D and not) flash memory. Among them, 3D NAND memory is based on its small size and large capacity, and the high integration of storage cells using three-dimensional mode layer-by-layer stacking is the design concept to produce high storage density per unit area and high-efficiency storage unit performance. The memory has become an emerging memory The mainstream process of design and production.
  • gate line slits are used to provide etchant application channels to remove sacrificial layers in the stack structure and obtain lateral grooves, and to provide thin film deposition material channels to deposit conductor layers in lateral grooves In the trench, and the gate line slot can be used to make an array common source (ACS), it can be used to divide the memory array area or the step connection area into a plurality of small areas.
  • ACS array common source
  • the purpose of the present invention is to provide a three-dimensional memory and a manufacturing method thereof, which are used to solve the problem of forming a process window for forming a gate line gap when the gate line gap and the dummy structure overlap in the prior art. lowering problem.
  • the present invention provides a three-dimensional memory, comprising:
  • a stacked structure comprising gate line layers and dielectric layers alternately stacked in a vertical direction;
  • a dummy structure penetrating the laminated structure in a vertical direction, the dummy structure comprising a first dummy part and a second dummy part;
  • a gate line slot which penetrates the stacked structure in a vertical direction, one end of the gate line slot extends into the gap formed by the first dummy part and/or the second dummy part, the first dummy part overlapping with at least one of the second dummy parts and the projection part of the grid line slit on a horizontal plane.
  • the width of the overlapping portion of the dummy structure and the projection of the gate line slit on the horizontal plane is M
  • the width of the gate line slit is N
  • the first dummy portion and the second dummy portion are independently provided, and the gap is located between the first dummy portion and the second dummy portion.
  • the first dummy portion and the second dummy portion are arranged in parallel along the extending direction of the gate line slit.
  • the gap is located between the first dummy part and the second dummy part
  • the dummy structure further includes a third dummy part
  • the third dummy part is located in the gap and is connected to the The first dummy portion and the second dummy portion are connected, and the third dummy portion is spaced from the gate line gap by a predetermined distance.
  • the gaps are respectively located in an area enclosed by the first dummy portion and an area enclosed by the second dummy portion
  • the dummy structure further includes a third dummy portion, and the third dummy portion is located in the area.
  • the first dummy portion and the second dummy portion are respectively connected to the first dummy portion and the second dummy portion, and the third dummy portion is spaced from the gate line slit by a predetermined distance.
  • the gap is located between the first dummy portion and the second dummy portion
  • the dummy structure further includes a third dummy portion
  • the third dummy portion is connected to the first dummy portion away from the One end of the gate line slit and one end of the second dummy portion are away from one end of the gate line slit, and the third dummy portion is spaced from the gate line slit by a predetermined distance.
  • the three-dimensional memory includes a plurality of blocks in which the stacked structure is divided by the gate line slits in a first horizontal direction, and the blocks include a plurality of blocks sequentially arranged in a second horizontal direction.
  • a core area, a step area and a second core area, the first horizontal direction and the second horizontal direction are perpendicular to each other.
  • the plurality of blocks include adjacent first blocks and second blocks, and the gate line gaps include spaces between the first block and the second block and are respectively located in the first block and the second block.
  • a core region and a first gate line slot and a second gate line slot of the second core region, one end of the first gate line slot facing the step region is connected to the dummy structure, and the second gate line The dummy structure is connected to one end of the slit facing the step area.
  • the gap is located between the first dummy portion and the second dummy portion
  • the dummy structure further includes a third dummy portion
  • the third dummy portion is connected to the first dummy portion away from the One end of the gate line slit and one end of the second dummy portion are away from one end of the gate line slit, and the third dummy portion is spaced from the gate line slit by a predetermined distance.
  • the grid line slits include a plurality of spaced third grid line slits located on a side of the first block away from the second block and a plurality of spaced third grid line slits located on the second block away from the first block. a plurality of spaced fourth gate line slits on one side of the block, the third gate line slit and the fourth gate line slit are located in the step area, between two adjacent third gate line slits The dummy structure is used for connection; and the two adjacent fourth gate line slits are connected through the dummy structure.
  • the first dummy portion and the second dummy portion are independently arranged, and the gap is located between the first dummy portion and the second dummy portion; or the gap is located in the first dummy portion.
  • the dummy structure further includes a third dummy part, the third dummy part is located in the gap and is connected with the first dummy part and the second dummy part connected, and the third dummy portion is spaced a predetermined distance from the gate line gap; or the gap is located in the area enclosed by the first dummy portion and the area enclosed by the second dummy portion, respectively.
  • the dummy structure further includes a third dummy portion, the third dummy portion is located between the first dummy portion and the second dummy portion and is respectively connected with the first dummy portion and the second dummy portion, and The third dummy portion is spaced from the gate line slit by a predetermined distance.
  • the first block is provided with a first retaining wall structure located in the step area at an edge area away from the second block, and the second block is located at a distance away from the first block.
  • the edge area is provided with a second barrier wall structure located in the step area, the third grid line slot is located on the side of the first barrier wall structure away from the second barrier wall structure, and the fourth grid line slot
  • the first retaining wall structure and the second retaining wall structure both include conductive layers and insulating layers alternately stacked in a vertical direction.
  • the dummy structure adopts insulating material.
  • the bottom surface of the dummy structure is lower than the bottom surface of the gate line slit.
  • it further includes a polysilicon layer, the stacked structure is disposed on the polysilicon, and the bottom of the gate line gap extends at least to the surface of the polysilicon layer.
  • the present invention also provides a method for making a three-dimensional memory, comprising the following steps:
  • a substrate is provided, and a stacked structure is formed on the substrate, the stacked structure includes a gate line sacrificial layer and a dielectric layer alternately stacked in a vertical direction;
  • the dummy structure penetrates the laminated structure in a vertical direction, and the dummy structure includes a first dummy part and a second dummy part;
  • the gate line slot penetrates the stacked structure in a vertical direction, and one end of the gate line slot extends into the gap formed by the first dummy part and/or the second dummy part, At least one of the first dummy portion and the second dummy portion overlaps with a projection portion of the grid line slit on a horizontal plane.
  • the width of the overlapping portion of the dummy structure and the projection of the gate line slit on the horizontal plane is M
  • the width of the gate line slit is N
  • the first dummy portion and the second dummy portion are independently provided, and the gap is located between the first dummy portion and the second dummy portion.
  • the gap is located between the first dummy part and the second dummy part
  • the dummy structure further includes a third dummy part
  • the third dummy part is located in the gap and is connected to the The first dummy portion and the second dummy portion are connected, and the third dummy portion is spaced from the gate line gap by a predetermined distance; or the gap is located in the area surrounded by the first dummy portion and the The area enclosed by the second dummy part
  • the dummy structure further includes a third dummy part, the third dummy part is located between the first dummy part and the second dummy part and is respectively connected with the first dummy part
  • the third dummy part is connected to the second dummy part, and the third dummy part is spaced from the gate line gap by a preset distance; or the gap is located between the first dummy part and the second dummy part, so
  • the dummy structure further includes a third dummy portion, the third dummy portion is
  • the three-dimensional memory includes a plurality of blocks in which the stacked structure is divided by the gate line slits in a first horizontal direction, and the blocks include a plurality of blocks sequentially arranged in a second horizontal direction.
  • a core area, a step area and a second core area, the first horizontal direction and the second horizontal direction are perpendicular to each other.
  • the plurality of blocks include adjacent first blocks and second blocks, and the gate line gaps include spaces between the first block and the second block and are respectively located in the first block and the second block.
  • a core region and a first gate line slot and a second gate line slot of the second core region, one end of the first gate line slot facing the step region is connected to the dummy structure, and the second gate line The dummy structure is connected to one end of the slit facing the step area.
  • the gap is located between the first dummy portion and the second dummy portion
  • the dummy structure further includes a third dummy portion
  • the third dummy portion is connected to the first dummy portion away from the One end of the gate line slit and one end of the second dummy portion are away from one end of the gate line slit, and the third dummy portion is spaced from the gate line slit by a predetermined distance.
  • the grid line slits include a plurality of spaced third grid line slits located on a side of the first block away from the second block and a plurality of spaced third grid line slits located on the second block away from the first block.
  • the first dummy portion and the second dummy portion are independently arranged, and the gap is located between the first dummy portion and the second dummy portion; or the gap is located in the first dummy portion.
  • the dummy structure further includes a third dummy part, the third dummy part is located in the gap and is connected with the first dummy part and the second dummy part connected, and the third dummy portion is spaced a predetermined distance from the gate line gap; or the gap is located in the area enclosed by the first dummy portion and the area enclosed by the second dummy portion, respectively.
  • the dummy structure further includes a third dummy portion, the third dummy portion is located between the first dummy portion and the second dummy portion and is respectively connected with the first dummy portion and the second dummy portion, and The third dummy portion is spaced from the gate line slit by a predetermined distance.
  • the first block is provided with a first retaining wall structure located in the step area at an edge area away from the second block, and the second block is located at a distance away from the first block.
  • the edge area is provided with a second barrier wall structure located in the step area, the third grid line slot is located on the side of the first barrier wall structure away from the second barrier wall structure, and the fourth grid line slot on the side of the second retaining wall structure away from the first retaining wall structure, the first retaining wall structure and the second retaining wall structure both include the gate line sacrificial layers stacked alternately in the vertical direction with the dielectric layer.
  • the substrate sequentially includes a bottom polysilicon layer, a first spacer layer, a middle polysilicon layer, a second spacer layer and a top polysilicon layer from bottom to top, and the bottom of the dummy structure extends at least to the second spacer layer surface, and the bottom of the gate line slot extends at least to the surface of the top polysilicon layer.
  • the dummy structure includes a first dummy part and a second dummy part, a gap is formed between the first dummy part and the second dummy part, and one end of the gate line gap extends into In the gap, at least one of the first dummy portion and the second dummy portion overlaps with the projection portion of the grid line slit on the horizontal plane, so as to realize the connection between the dummy structure and the grid line slit .
  • the dummy structure design which wraps the end of the gate line gap but does not completely overlap, can effectively improve the process window problem of gate line gap etching at the junction of the dummy structure and the gate line gap, and effectively reduce/eliminate the dummy structure and the gate line.
  • the weak point at the junction of the gap helps to improve the reliability of the device.
  • FIG. 1 shows a cross-sectional view of the three-dimensional memory of the present invention.
  • FIG. 2 shows a partial top view of the three-dimensional memory of the present invention.
  • FIG. 3 shows a first plan view of the gap connection between the dummy structure and the gate line.
  • FIG. 4 shows a second plan view in which the dummy structure and the gate line are gap-connected.
  • FIG. 5 shows a third plan view of the dummy structure connected to the gate line slot.
  • FIG. 6 shows a fourth plan view of the dummy structure connected to the gate line slot.
  • FIG. 7 shows a plan layout of the three-dimensional memory of the present invention.
  • FIG. 8 is a process flow diagram of a method for fabricating a three-dimensional memory of the present invention.
  • FIG. 9 is a schematic diagram of forming a stacked structure on a substrate according to the method for fabricating a three-dimensional memory of the present invention.
  • FIG. 10 is a schematic diagram of forming a dummy structure for the fabrication method of the three-dimensional memory of the present invention.
  • FIG. 11 is a schematic diagram illustrating the formation of gate line slits in the method for fabricating a three-dimensional memory of the present invention.
  • FIG. 12 is a partial top view of the structure obtained in step S3 of the manufacturing method of the three-dimensional memory of the present invention.
  • the middle part of the gate line gap between two blocks is removed.
  • silicon nitride/silicon oxide left after the gate line sacrificial layer (silicon nitride) is removed to achieve isolation between blocks.
  • a dummy structure should be used to assist in realizing the isolation between blocks.
  • the grid line gaps on the great wall are designed to be intermittent, and the dummy structure is used to realize the isolation between the blocks.
  • the present invention improves the above-mentioned problems through a new dummy structure design, which is specifically referred to in the following embodiments.
  • FIG. 1 is a cross-sectional view of the three-dimensional memory, including a stacked structure, a dummy structure 1 and a gate line gap 2 , wherein the stacked structure is included in the The gate line layers 3 and the isolation layers 4 are alternately stacked in the vertical direction, the dummy structure 1 and the gate line gap 2 all penetrate the stacked structure in the vertical direction.
  • the gate line layer 3 includes but is not limited to a tungsten layer
  • the isolation layer 4 includes but is not limited to a silicon oxide layer
  • the dummy structure 1 and the gate line gap are filled with insulating material 5 .
  • the three-dimensional memory further includes a polysilicon layer, the stacked structure is disposed on the polysilicon layer, and the bottom of the gate line gap 2 extends at least to the surface of the polysilicon layer.
  • the polysilicon layer includes a bottom polysilicon layer 6 , a first spacer layer 7 , a middle polysilicon layer 8 , a second spacer layer 9 and a top polysilicon layer 10 in sequence from bottom to top. Bottoms of the gate line gap 2 and the dummy structure 1 are both higher than the top surface of the middle polysilicon layer 8 .
  • the bottom of the gate line gap 2 reaches the surface of the top polysilicon layer 10
  • the bottom surface of the dummy structure 1 is lower than the bottom surface of the gate line gap 2 and reaches the surface of the second spacer layer 9 .
  • the material of the first spacer layer 7 or the second spacer layer 9 includes but is not limited to silicon oxynitride.
  • a base layer 11 , a protective layer 12 , a silicon nitride layer 13 , and a silicon oxide layer 14 are also provided under the polysilicon layer in sequence from bottom to top, and the base layer 11 includes but is not limited to Si substrate, Ge substrate, SiGe substrate, Silicon On Insulator (SOI) substrate or Germanium On Insulator (GOI) substrate, etc., and the substrate layer 11 may be P-type doped or N-type doped.
  • the material of the protective layer 12 includes but is not limited to silicon oxide.
  • FIG. 2 is a partial top view of the three-dimensional memory, wherein the aforementioned FIG. 1 presents the section along the line A-A' of FIG. 2 .
  • the dummy structure 1 includes a first dummy portion 101 and a second dummy portion 102 , and one end of the gate line slot 2 extends into the first dummy portion 101 and/or the In the gap formed by the second dummy portion 102 , at least one of the first dummy portion 101 and the second dummy portion 102 overlaps with the projected portion of the grid line slot 2 on the horizontal plane.
  • the width of the gap formed by the first dummy portion 101 and/or the second dummy portion 102 is smaller than the width of the gate line slit 2 to ensure that the dummy structure 1 and the gate line slit 2 are in a horizontal plane.
  • the gate line gap 2 is located in the middle of the gap formed by the first dummy portion 101 and the second dummy portion 102 .
  • the first dummy portion 101 and the second dummy portion 102 overlaps with the projection of the grid line slit 2 on the horizontal plane; or the grid line slit 2 is located in the middle of the gap formed by the first dummy portion 101 or the second dummy portion 102, the Both sides of the first dummy portion 101 or the second dummy portion 102 and the gate line slit 2 have overlapping portions; and under non-ideal conditions, the gate line slit 2 deviates from the center of the gap, but because of the gap
  • the width is smaller than the width of the gate line slot 2 , no matter which side the gate line slot 2 is offset to, it can ensure that the dummy structure 1 and the projection of the gate line slot 2 on the horizontal plane overlap.
  • the width of the overlapping portion of the projection of the dummy structure 1 and the gate line slit 2 on the horizontal plane is M
  • the width of the gate line slit 2 is N, where M ⁇ 0.1N. That is to say, the ratio of the width of the overlapped portion to the total width of the gate line gap 2 is very small, which can effectively reduce/eliminate the fragile point at the junction of the dummy structure 1 and the gate line gap 2, which helps to improve device reliability.
  • the dummy structure 1 may have various forms.
  • FIG. 3 is a first plan view of the dummy structure 1 connected to the gate line slot 2 , wherein the first dummy portion 101 and the second dummy portion 102 of the dummy structure 1 are The gap is located between the first dummy part 101 and the second dummy part 102 .
  • the first dummy portion 101 and the second dummy portion 102 are arranged in parallel along the extending direction of the gate line slit 2 and are linear.
  • FIG. 4 is a second plan view showing the connection between the dummy structure 1 and the gate line gap 2 , wherein the gap is located between the first dummy portion 101 and the second dummy portion 102 , the dummy structure 1 further includes a third dummy part 103, the third dummy part 103 is located in the gap and connected with the first dummy part 101 and the second dummy part 102, and the first dummy part 103 The three dummy portions 103 are spaced apart from the gate line gap 2 by a predetermined distance.
  • FIG. 5 is a third plan view of the connection between the dummy structure 1 and the gate line gap 2 , wherein the gap is located in the area surrounded by the first dummy portion 101 and the second The area surrounded by the dummy part 102, the dummy structure further includes a third dummy part 103, the third dummy part 103 is located between the first dummy part 101 and the second dummy part 102 and is respectively connected to the The first dummy portion 101 is connected to the second dummy portion 102 , and the third dummy portion 103 is spaced from the gate line gap 2 by a predetermined distance.
  • FIG. 6 is a fourth plan view of the connection between the dummy structure 1 and the gate line gap 2 , wherein the gap is located between the first dummy portion 101 and the second dummy portion 102 , the first dummy part 101 and the second dummy part 102 of the dummy structure 1 are connected by a third dummy part 103 , specifically, the third dummy part 103 is connected to the first dummy part One end of 101 away from the gate line slot 2 and one end of the second dummy portion 102 away from the gate line slot 2 , and the third dummy portion 103 is spaced from the gate line slot 2 by a predetermined distance.
  • the dummy structures shown in FIG. 3 , FIG. 4 and FIG. 5 are more suitable for the connection between two gate line gaps, and the dummy structure shown in FIG. 6 is more suitable for connecting a single gate Grid line gap.
  • the dummy structure may also adopt other forms of wrapping the end of the grid line slot, and the protection scope of the present invention should not be unduly limited here.
  • FIG. 7 is a plan layout diagram of the three-dimensional memory.
  • the three-dimensional memory includes a plurality of the stacked structures divided by the gate line slits in the first horizontal direction Y.
  • a block the block includes a first core area, a step area and a second core area sequentially arranged in the second horizontal direction X, the first horizontal direction Y and the second horizontal direction X are perpendicular to each other, so
  • the step area is provided with a step structure 19, and the step structure 19 serves as a connection area, which includes multiple steps, and a plurality of contacts 20 connected to the gate line layer are provided on the mesa of the step.
  • the plurality of blocks include the adjacent first block 15 and the second block 16 , and the gate line gap is located between the first block 15 and the second block 16 and respectively located in
  • the first gate line slit 17 and the second gate line slit 18 of the first core area and the second core area are connected with a dummy structure 1a at one end of the first gate line slit 17 facing the step area.
  • One end of the second gate line gap 18 facing the step region is connected with a dummy structure 1b.
  • the dummy structures 1 a connected to the first gate line slits 17 and the dummy structures 1 b connected to the second gate line slits 17 are in the shape shown in FIG. 6 .
  • the dummy structure 1b and the second gate line slot 18 are sequentially connected to realize the isolation between the first block 15 and the second block 16 .
  • both the first block 15 and the second block 16 include a plurality of finger structures, for example, 2-10 finger structures.
  • the first block 15 sequentially includes a first finger structure 15a, a second finger structure 15b and a third finger
  • the second block 16 includes a fourth finger structure 16a, a fifth finger structure 16b and a sixth finger structure 16c in sequence, wherein, in each block, adjacent finger structures pass through each other.
  • the intermittently arranged gate line slits are divided, and the purpose of using the intermittently arranged gate line slits is to keep the gate line layers of adjacent finger structures still connected.
  • a top select gate cutout 21 is provided in the middle of the storage region of the finger structure, and the top select gate cutout 21 divides the top select gate layer of the storage region into two parts, so as to divide the storage region into two parts. independently programmable (read/write) pages.
  • the grid line gap further includes a plurality of spaced third grids located on the side of the first block 15 away from the second block 16 .
  • the slits 24 are located in the step area, and two adjacent third gate line slits 24 are connected by a dummy structure 1c; and two adjacent fourth gate line slits 25 are connected by a dummy structure 1d.
  • the dummy structure 1c and the dummy structure 1d preferably adopt the dummy structure forms shown in FIG. 3 , FIG. 4 , and FIG. 5 .
  • the edge region of the first block 15 away from the second block 16 (in this embodiment, the edge region of the first finger structure 15 a ) is provided with a first retaining wall structure 22 .
  • a second retaining wall structure 23 is provided in the edge region of the second block 16 away from the first block 15 (in this embodiment, the edge region of the sixth finger structure 16c ), and the third gate line slot 1c Located on the side of the first blocking wall structure 22 away from the second blocking wall structure 23 , the fourth grid line slot 1d is located on a side of the second blocking wall structure 23 away from the first blocking wall structure 23 .
  • the first retaining wall structure 22 and the second retaining wall structure 23 both include conductive layers (such as tungsten layers) and insulating layers (such as silicon oxide layers) alternately stacked in a vertical direction, wherein the first A retaining wall structure 22 and the second retaining wall structure 23 are used for electrical connection between two ends of the block structure.
  • the cross-sectional areas of the first retaining wall structure 22 and the second retaining wall structure 23 may gradually increase from top to bottom, wherein the dashed frame area in the first finger-shaped structure 15a is shown as the first The projected area of a conductive wall 22 on the horizontal plane is larger than the top area of the first conductive wall 22.
  • the dotted frame area in the sixth finger structure 16c is shown as the second conductive wall 23 on the horizontal plane. , the area of which is larger than the top area of the second conductive wall 23 .
  • the dummy structure includes a first dummy portion and a second dummy portion, a gap is formed between the first dummy portion and the second dummy portion, and one end of the gate line gap extends into the gap wherein, at least one of the first dummy portion and the second dummy portion overlaps with the projected portion of the grid line slit on the horizontal plane, so as to realize the connection between the dummy structure and the grid line slit.
  • the dummy structure design which wraps the end of the gate line gap but does not completely overlap, can effectively improve the process window problem of gate line gap etching at the junction of the dummy structure and the gate line gap, and effectively reduce/eliminate the dummy structure and the gate line.
  • the weak point at the junction of the gap helps to improve the reliability of the device.
  • FIG. 8 is a process flow diagram of the method, including the following steps:
  • S1 providing a substrate, and forming a stacked structure on the substrate, the stacked structure including a gate line sacrificial layer and an isolation layer alternately stacked in a vertical direction;
  • step S1 is performed: providing a substrate, and forming a stacked structure on the substrate.
  • the stacked structure includes gate line sacrificial layers 26 and isolation layers 4 alternately stacked in a vertical direction.
  • the gate line sacrificial layer 26 includes, but is not limited to, a silicon nitride layer
  • the isolation layer 4 includes, but is not limited to, a silicon oxide layer.
  • the gate line sacrificial layer will be removed in the subsequent process, and the gate line material, such as tungsten, will be filled again to obtain the gate line.
  • the substrate includes, from bottom to top, a base layer 11 , a protective layer 12 , a silicon nitride layer 13 , a silicon oxide layer 14 , a bottom polysilicon layer 6 , a first spacer layer 7 , a middle polysilicon layer 8 , and a second Spacer layer 9 and top polysilicon layer 10
  • the base layer 11 includes but not limited to Si substrate, Ge substrate, SiGe substrate, Silicon On Insulator (SOI) substrate or Germanium On Insulator (GOI) substrate etc., and the base layer 11 may be P-type doped or N-type doped.
  • the material of the protective layer 12 includes but is not limited to silicon oxide.
  • the material of the first spacer layer 7 or the second spacer layer 9 includes but is not limited to silicon oxynitride.
  • the middle polysilicon layer 8 serves as a sacrificial layer, which will be removed and refilled later. It should be pointed out that this is only an example, in other embodiments, the structural layers in the substrate can be adjusted as required, and the protection scope of the present invention should not be unduly limited here.
  • step S2 is performed: forming a dummy structure 1 through one or more wet etching and/or dry etching processes (eg, deep reactive ion etching (DRIE)), and filling the dummy structure with insulating material 5 1, wherein the dummy structure 1 runs through the stacked structure in a vertical direction.
  • DRIE deep reactive ion etching
  • step S3 is performed: gate line slits 2 are formed by one or more wet etching and/or dry etching processes, and the gate line slits 2 penetrate the stacked structure in a vertical direction. In this embodiment, the bottom of the gate line gap 2 reaches the surface of the top polysilicon layer 10 .
  • the dummy structure 1 includes a first dummy portion 101 and a second dummy portion 102, and one end of the gate line slot 2 extends into the In the gap formed by the first dummy portion 101 and/or the second dummy portion 102 , at least one of the first dummy portion 101 and the second dummy portion 102 and the gate line gap 2 are in a horizontal plane.
  • the projections on partially overlap.
  • the width of the gap formed by the first dummy portion 101 and/or the second dummy portion 102 is smaller than the width of the gate line slit 2 to ensure that the dummy structure 1 and the gate line slit 2 are in a horizontal plane.
  • the gate line gap 2 is located in the middle of the gap formed by the first dummy portion 101 and the second dummy portion 102 .
  • the first dummy portion 101 and the second dummy portion 102 overlaps with the projection of the grid line slit 2 on the horizontal plane; or the grid line slit 2 is located in the middle of the gap formed by the first dummy portion 101 or the second dummy portion 102, the Both sides of the first dummy portion 101 or the second dummy portion 102 and the gate line slit 2 have overlapping portions; and under non-ideal conditions, the gate line slit 2 deviates from the center of the gap, but because of the gap
  • the width is smaller than the width of the gate line slot 2 , no matter which side the gate line slot 2 is offset to, it can ensure that the dummy structure 1 and the projection of the gate line slot 2 on the horizontal plane overlap.
  • the width of the overlapping portion of the projection of the dummy structure 1 and the gate line slit 2 on the horizontal plane is M
  • the width of the gate line slit 2 is N, where M ⁇ 0.1N. That is to say, the width of the overlapped portion accounts for a very small proportion of the total width of the gate line gap 2 , so that the fragile point at the junction of the dummy trench structure 1 and the gate line gap 2 can be effectively reduced/eliminated, which helps to improve device reliability.
  • the dummy structure 1 may have various forms.
  • FIG. 3 is a first plan view of the dummy structure 1 connected to the gate line slot 2 , wherein the first dummy portion 101 and the second dummy portion 102 of the dummy structure 1 are The gap is located between the first dummy part 101 and the second dummy part 102 .
  • the first dummy portion 101 and the second dummy portion 102 are arranged in parallel along the extending direction of the gate line slit 2 and are linear.
  • FIG. 4 is a second plan view showing the connection between the dummy structure 1 and the gate line gap 2 , wherein the gap is located between the first dummy portion 101 and the second dummy portion 102 , the dummy structure 1 further includes a third dummy part 103, the third dummy part 103 is located in the gap and connected with the first dummy part 101 and the second dummy part 102, and the first dummy part 103 The three dummy portions 103 are spaced apart from the gate line slit 2 by a predetermined distance.
  • FIG. 5 shows a third plan view of the dummy structure 1 connected to the gate line gap 2 , wherein the gap is located in the area surrounded by the first dummy portion 101 and the second In the area enclosed by the dummy portion 102, the dummy structure further includes a third dummy portion 103, and the third dummy portion 103 is located between the first dummy portion 101 and the second dummy portion 102 and is respectively connected to the The first dummy portion 101 is connected to the second dummy portion 102 , and the third dummy portion 103 is spaced from the gate line gap 2 by a predetermined distance.
  • FIG. 6 is a fourth plan view of the connection between the dummy structure 1 and the gate line gap 2 , wherein the gap is located between the first dummy portion 101 and the second dummy portion 102 , the first dummy part 101 and the second dummy part 102 of the dummy structure 1 are connected by a third dummy part 103 , specifically, the third dummy part 103 is connected to the first dummy part One end of 101 away from the gate line slot 2 and one end of the second dummy portion 102 away from the gate line slot 2 , and the third dummy portion 103 is spaced from the gate line slot 2 by a predetermined distance.
  • FIG. 12 presents three different forms of dummy structures at the same time, but in practical applications, the same or different forms of dummy structures can be flexibly selected according to needs, and the protection scope of the present invention should not be unduly limited here. .
  • the dummy structure shown in FIG. 3 , FIG. 4 and FIG. 5 is more suitable for connection between two gate line slits
  • the dummy structure shown in FIG. 6 is more suitable for connecting a single gate line slit.
  • the dummy structure may also adopt other forms of wrapping the end of the grid line slot, and the protection scope of the present invention should not be unduly limited here.
  • the gate line sacrificial layer may be subsequently removed to obtain a lateral groove, and a gate line layer may be deposited in the lateral groove.
  • the interface area between the dummy structure and the gate line gap is very small, and the mutual influence is small, so that the process window of the gate line gap etching at the interface between the dummy structure and the gate line gap can be enlarged, effectively Reducing/eliminating the fragile point at the junction of the dummy structure and the gate line gap helps to improve device reliability.
  • the dummy structure includes a first dummy part and a second dummy part, a gap is formed between the first dummy part and the second dummy part, and one end of the gate line gap extends into the gap, at least one of the first dummy portion and the second dummy portion overlaps with the projected portion of the grid line slit on the horizontal plane, so as to realize the connection between the dummy structure and the grid line slit. connect.
  • the dummy structure design which wraps the end of the gate line gap but does not completely overlap, can effectively improve the process window problem of gate line gap etching at the junction of the dummy structure and the gate line gap, and effectively reduce/eliminate the dummy structure and the gate line.
  • the weak point at the junction of the gap helps to improve the reliability of the device. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial application value.

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Abstract

本发明提供一种三维存储器及其制作方法，该三维存储器包括叠层结构、虚设结构及栅线缝隙，其中，叠层结构包括在垂直方向上交替堆叠的栅线层与隔离层，虚设结构及栅线缝隙均沿垂直方向贯穿叠层结构，虚设结构包括第一虚设部与第二虚设部，栅线缝隙的一端伸入由第一虚设部与/或第二虚设部形成的间隙中，第一虚设部与第二虚设部中的至少一个与栅线缝隙在水平面上的投影部分重叠，以实现虚设结构与栅线缝隙的连接。这种将栅线缝隙端部包裹住，但又不完全重叠的虚设结构设计可以有效改善虚设结构与栅线缝隙交界处栅线缝隙刻蚀的工艺窗口问题，有效减少/消除虚设结构与栅线缝隙交界处的脆弱点，有助于提高器件可靠性。

Description

一种三维存储器及其制作方法
本申请是针对申请日为2020年09月29日，申请号为202011046857.9，发明名称为一种三维存储器及其制作方法的专利申请提出的分案申请。
技术领域
本发明属于半导体集成电路技术领域，涉及一种三维存储器及其制作方法。
背景技术
随着平面型闪存存储器的发展，半导体的生产工艺取得了巨大的进步。但是最近几年，平面型闪存的发展遇到了各种挑战：物理极限、现有显影技术极限以及存储电子密度极限等。在此背景下，为解决平面闪存遇到的困难以及追求更低的单位存储单元的生产成本，各种不同的三维(3D)闪存存储器结构应运而生，例如3D NOR(3D或非)闪存和3D NAND(3D与非)闪存。其中，3D NAND存储器以其小体积、大容量为出发点，将储存单元采用三维模式层层堆叠的高度集成为设计理念，生产出高单位面积存储密度，高效存储单元性能的存储器，已经成为新兴存储器设计和生产的主流工艺。
在三维存储器的制作过程中，栅线缝隙(GLS)用于提供蚀刻剂施加通道以去除叠层结构中的牺牲层并得到横向凹槽，并提供薄膜沉积材料通道以将导体层沉积在横向凹槽中，并且栅线缝隙可以用于制作阵列公共源极(ACS)，可以用于将存储阵列区域或台阶连接区域划分为多个小区域。
但是，当需要形成与栅线缝隙(GLS)连接的虚设沟道孔(dummy CH)时，由于栅线缝隙与虚设沟道孔交界的地方会存在脆弱点(weak point)，降低了形成栅线缝隙的工艺窗口，导致工艺难度增加。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种三维存储器及其制作方法，用于解决现有技术中当栅线缝隙与虚设结构交叠时，形成栅线缝隙的工艺窗口降低的问题。
为实现上述目的及其他相关目的，本发明提供一种三维存储器，包括：
叠层结构，包括在垂直方向上交替堆叠的栅线层与电介质层；
虚设结构，沿垂直方向贯穿所述叠层结构，所述虚设结构包括第一虚设部与第二虚设部；
栅线缝隙，沿垂直方向贯穿所述叠层结构，所述栅线缝隙的一端伸入由所述第一虚设部 与/或所述第二虚设部形成的间隙中，所述第一虚设部与所述第二虚设部中的至少一个与所述栅线缝隙在水平面上的投影部分重叠。
可选地，在垂直于所述栅线缝隙的延伸方向上，所述虚设结构与所述栅线缝隙在水平面上的投影的重叠部分的宽度为M，所述栅线缝隙的宽度为N，其中，M<0.1N。
可选地，所述第一虚设部与所述第二虚设部之间独立设置，所述间隙位于所述第一虚设部和所述第二虚设部之间。
可选地，所述第一虚设部及所述第二虚设部沿所述栅线缝隙的延伸方向平行设置。
可选地，所述间隙位于所述第一虚设部和所述第二虚设部之间，所述虚设结构还包括第三虚设部，所述第三虚设部位于所述间隙中并与所述第一虚设部及所述第二虚设部连接，且所述第三虚设部与所述栅线缝隙间隔预设距离。
可选地，所述间隙分别位于所述第一虚设部围成的区域以及所述第二虚设部围成的区域，所述虚设结构还包括第三虚设部，所述第三虚设部位于所述第一虚设部及所述第二虚设部之间且分别与所述第一虚设部和所述第二虚设部连接，且所述第三虚设部与所述栅线缝隙间隔预设距离。
可选地，所述间隙位于所述第一虚设部和所述第二虚设部之间，所述虚设结构还包括第三虚设部，所述第三虚设部连接于所述第一虚设部远离所述栅线缝隙的一端及所述第二虚设部远离所述栅线缝隙的一端，且所述第三虚设部与所述栅线缝隙间隔预设距离。
可选地，所述三维存储器包括在第一水平方向上由所述栅线缝隙将所述叠层结构进行划分的多个区块，所述区块包括在第二水平方向上依次设置的第一核心区、台阶区及第二核心区，所述第一水平方向与所述第二水平方向相互垂直。
可选地，多个区块包括相邻的第一区块和第二区块，所述栅线缝隙包括位于所述第一区块与所述第二区块之间且分别位于所述第一核心区和所述第二核心区的第一栅线缝隙和第二栅线缝隙，所述第一栅线缝隙朝向所述台阶区的一端连接有一所述虚设结构，所述第二栅线缝隙朝向所述台阶区的一端连接有一所述虚设结构。
可选地，所述间隙位于所述第一虚设部和所述第二虚设部之间，所述虚设结构还包括第三虚设部，所述第三虚设部连接于所述第一虚设部远离所述栅线缝隙的一端及所述第二虚设部远离所述栅线缝隙的一端，且所述第三虚设部与所述栅线缝隙间隔预设距离。
可选地，所述栅线缝隙包括位于所述第一区块远离所述第二区块的一侧的多条间隔的第三栅线缝隙以及位于所述第二区块远离所述第一区块的一侧的多条间隔的第四栅线缝隙，所述第三栅线缝隙和所述第四栅线缝隙位于所述台阶区，相邻两条所述第三栅线缝隙之间通过所述虚设结构连接；相邻两条所述第四栅线缝隙之间通过所述虚设结构连接。
可选地，所述第一虚设部与所述第二虚设部之间独立设置，所述间隙位于所述第一虚设部和所述第二虚设部之间；或者所述间隙位于所述第一虚设部和所述第二虚设部之间，所述虚设结构还包括第三虚设部，所述第三虚设部位于所述间隙中并与所述第一虚设部及所述第二虚设部连接，且所述第三虚设部与所述栅线缝隙间隔预设距离；或者所述间隙分别位于所述第一虚设部围成的区域以及所述第二虚设部围成的区域，所述虚设结构还包括第三虚设部，所述第三虚设部位于所述第一虚设部及所述第二虚设部之间且分别与所述第一虚设部和所述第二虚设部连接，且所述第三虚设部与所述栅线缝隙间隔预设距离。
可选地，所述第一区块在远离所述第二区块的边缘区域设有位于所述台阶区的第一挡墙结构，所述第二区块在远离所述第一区块的边缘区域设有位于所述台阶区的第二挡墙结构，所述第三栅线缝隙位于所述第一挡墙结构远离所述第二挡墙结构的一侧，所述第四栅线缝隙位于所述第二挡墙结构远离所述第一挡墙结构的一侧，所述第一挡墙结构及所述第二挡墙结构均包括在垂直方向上交替堆叠的导电层及绝缘层。
可选地，所述虚设结构采用绝缘材料。
可选地，所述虚设结构的底面低于所述栅线缝隙的底面。
可选地，还包括多晶硅层，所述叠层结构设于所述多晶硅上，所述栅线缝隙的底部至少延伸至所述多晶硅层表面。
本发明还提供一种三维存储器的制作方法，包括以下步骤：
提供一衬底，形成叠层结构于所述衬底上，所述叠层结构包括在垂直方向上交替堆叠的栅线牺牲层与电介质层；
形成虚设结构，所述虚设结构沿垂直方向贯穿所述叠层结构，所述虚设结构包括第一虚设部与第二虚设部；
形成栅线缝隙，所述栅线缝隙沿垂直方向贯穿所述叠层结构，所述栅线缝隙的一端伸入由所述第一虚设部和/或所述第二虚设部形成的间隙中，所述第一虚设部与所述第二虚设部中的至少一个与所述栅线缝隙在水平面上的投影部分重叠。
可选地，在垂直于所述栅线缝隙的延伸方向上，所述虚设结构与所述栅线缝隙在水平面上的投影的重叠部分的宽度为M，所述栅线缝隙的宽度为N，其中，M<0.1N。
可选地，所述第一虚设部与所述第二虚设部之间独立设置，所述间隙位于所述第一虚设部和所述第二虚设部之间。
可选地，所述间隙位于所述第一虚设部和所述第二虚设部之间，所述虚设结构还包括第三虚设部，所述第三虚设部位于所述间隙中并与所述第一虚设部及所述第二虚设部连接，且所述第三虚设部与所述栅线缝隙间隔预设距离；或者所述间隙分别位于所述第一虚设部围成 的区域以及所述第二虚设部围成的区域，所述虚设结构还包括第三虚设部，所述第三虚设部位于所述第一虚设部及所述第二虚设部之间且分别与所述第一虚设部和所述第二虚设部连接，且所述第三虚设部与所述栅线缝隙间隔预设距离；或者所述间隙位于所述第一虚设部和所述第二虚设部之间，所述虚设结构还包括第三虚设部，所述第三虚设部连接于所述第一虚设部远离所述栅线缝隙的一端及所述第二虚设部远离所述栅线缝隙的一端，且所述第三虚设部与所述栅线缝隙间隔预设距离。
可选地，所述三维存储器包括在第一水平方向上由所述栅线缝隙将所述叠层结构进行划分的多个区块，所述区块包括在第二水平方向上依次设置的第一核心区、台阶区及第二核心区，所述第一水平方向与所述第二水平方向相互垂直。
可选地，多个区块包括相邻的第一区块和第二区块，所述栅线缝隙包括位于所述第一区块与所述第二区块之间且分别位于所述第一核心区和所述第二核心区的第一栅线缝隙和第二栅线缝隙，所述第一栅线缝隙朝向所述台阶区的一端连接有一所述虚设结构，所述第二栅线缝隙朝向所述台阶区的一端连接有一所述虚设结构。
可选地，所述间隙位于所述第一虚设部和所述第二虚设部之间，所述虚设结构还包括第三虚设部，所述第三虚设部连接于所述第一虚设部远离所述栅线缝隙的一端及所述第二虚设部远离所述栅线缝隙的一端，且所述第三虚设部与所述栅线缝隙间隔预设距离。
可选地，所述栅线缝隙包括位于所述第一区块远离所述第二区块的一侧的多条间隔的第三栅线缝隙以及位于所述第二区块远离所述第一区块的一侧的多条间隔的第四栅线缝隙，相邻两条所述第三栅线缝隙之间通过所述虚设结构连接；相邻两条所述第四栅线缝隙之间通过所述虚设结构连接。
可选地，所述第一虚设部与所述第二虚设部之间独立设置，所述间隙位于所述第一虚设部和所述第二虚设部之间；或者所述间隙位于所述第一虚设部和所述第二虚设部之间，所述虚设结构还包括第三虚设部，所述第三虚设部位于所述间隙中并与所述第一虚设部及所述第二虚设部连接，且所述第三虚设部与所述栅线缝隙间隔预设距离；或者所述间隙分别位于所述第一虚设部围成的区域以及所述第二虚设部围成的区域，所述虚设结构还包括第三虚设部，所述第三虚设部位于所述第一虚设部及所述第二虚设部之间且分别与所述第一虚设部和所述第二虚设部连接，且所述第三虚设部与所述栅线缝隙间隔预设距离。
可选地，所述第一区块在远离所述第二区块的边缘区域设有位于所述台阶区的第一挡墙结构，所述第二区块在远离所述第一区块的边缘区域设有位于所述台阶区的第二挡墙结构，所述第三栅线缝隙位于所述第一挡墙结构远离所述第二挡墙结构的一侧，所述第四栅线缝隙位于所述第二挡墙结构远离所述第一挡墙结构的一侧，所述第一挡墙结构及所述第二挡墙结 构均包括在垂直方向上交替堆叠的所述栅线牺牲层与所述电介质层。
可选地，所述衬底自下而上依次包括底部多晶硅层、第一间隔层、中部多晶硅层、第二间隔层及顶部多晶硅层，所述虚设结构的底部至少延伸至所述第二间隔层表面，所述栅线缝隙的底部至少延伸至所述顶部多晶硅层表面。
如上所述，本发明的三维存储器中，虚设结构包括第一虚设部与第二虚设部，所述第一虚设部与所述第二虚设部之间设有间隙，栅线缝隙的一端伸入所述间隙中，所述第一虚设部与所述第二虚设部中的至少一个与所述栅线缝隙在水平面上的投影部分重叠，以实现所述虚设结构与所述栅线缝隙的连接。这种将栅线缝隙端部包裹住，但又不完全重叠的虚设结构设计可以有效改善虚设结构与栅线缝隙交界处栅线缝隙刻蚀的工艺窗口问题，有效减少/消除虚设结构与栅线缝隙交界处的脆弱点，有助于提高器件可靠性。
附图说明
图1显示为本发明的三维存储器的一种剖面图。
图2显示为本发明的三维存储器的一种局部俯视图。
图3显示为虚设结构与栅线缝隙连接的第一种平面图。
图4显示为虚设结构与栅线缝隙连接的的第二种平面图。
图5显示为虚设结构与栅线缝隙连接的的第三种平面图。
图6显示为虚设结构与栅线缝隙连接的的第四种平面图。
图7显示为本发明的三维存储器的一种平面布局图。
图8显示为本发明的三维存储器的制作方法的工艺流程图。
图9显示为本发明的三维存储器的制作方法形成叠层结构于衬底上的示意图。
图10显示为本发明的三维存储器的制作方法形成虚设结构的示意图。
图11显示为本发明的三维存储器的制作方法形成栅线缝隙的示意图。
图12显示为本发明的三维存储器的制作方法步骤S3所获得结构的局部俯视图。
元件标号说明
1、1a、1b、1c、1d      虚设结构
101                    第一虚设部
102                    第二虚设部
103                    第三虚设部
2                      栅线缝隙
3                      栅线层
4                      隔离层
5                      绝缘材料
6                      底部多晶硅层
7                      第一间隔层
8                      中部多晶硅层
9                      第二间隔层
10                     顶部多晶硅层
11                     基底层
12                     保护层
13                     氮化硅层
14                     氧化硅层
15                     第一区块
15a                    第一指状结构
15b                    第二指状结构
15c                    第三指状结构
16                     第二区块
16a                    第四指状结构
16b                    第五指状结构
16c                    第六指状结构
17                     第一栅线缝隙
18                     第二栅线缝隙
19                     台阶结构
20                     触点
21                     顶部选择栅切口
22                     第一挡墙结构
23                     第二挡墙结构
24                     第三栅线缝隙
25                     第四栅线缝隙
26                     栅线牺牲层
S1～S3                 步骤
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
请参阅图1至图12。需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
在一种两边为存储阵列区、中间为台阶连接区的三维存储器中，为了防止栅线缝隙太长太密导致结构坍塌，两个区块(block)之间栅线缝隙的中间部分拿掉了，利用栅线牺牲层(氮化硅)去除后留下的氮化硅/氧化硅实现区块与区块之间的隔离。但栅线缝隙头的地方需要利用虚设结构辅助实现区块与区块之间的隔离。为了实现所有区块与区块之间的加固，挡墙结构(great wall)上的栅线缝隙设计成了断断续续的，利用虚设结构，实现区块与区块之间的隔离。但是，栅线缝隙与虚设结构交界的地方会存在脆弱点(weak point)。因为栅线缝隙刻蚀需要停在顶层多晶硅上，但是由于材料差异导致的刻蚀速率不一致，在栅线缝隙与虚设结构交界处，虚设结构吃掉了一部分的多晶硅，降低了栅线缝隙刻蚀停在多晶硅上的工艺窗口。因此，本发明通过新的虚设结构设计来改善上述问题，具体参见下述实施例。
实施例一
本实施例中提供一种三维存储器，请参阅图1，显示为所述三维存储器的一种剖面图，包括叠层结构、虚设结构1及栅线缝隙2，其中，所述叠层结构包括在垂直方向上交替堆叠的栅线层3与隔离层4，所述虚设结构1及所述栅线缝隙2均沿垂直方向贯穿所述叠层结构。
作为示例，所述栅线层3包括但不限于钨层，所述隔离层4包括但不限于氧化硅层，所述虚设结构1及所述栅线缝隙中均填充有绝缘材料5。
作为示例，所述三维存储器还包括多晶硅层，所述叠层结构设于所述多晶硅层上，所述栅线缝隙2的底部至少延伸至所述多晶硅层表面。本实施例中，所述多晶硅层自下而上依次包括底部多晶硅层6、第一间隔层7、中部多晶硅层8、第二间隔层9及顶部多晶硅层10。所述栅线缝隙2与虚设结构1的底部均高于所述中部多晶硅层8的顶面。本实施例中，所述栅线缝隙2的底部到达所述顶部多晶硅层10表面，所述虚设结构1的底面低于所述栅线缝隙2 的底面，并到达所述第二间隔层9表面，所述第一间隔层7或所述第二间隔层9的材质包括但不限于氮氧化硅。
作为示例，所述多晶硅层下方还自下而上依次设有基底层11、保护层12、氮化硅层13、氧化硅层14，所述基底层11包括但不限于Si基底、Ge基底、SiGe基底、绝缘体上硅(Silicon On Insulator，SOI)基底或绝缘体上锗(Germanium On Insulator，GOI)基底等，且所述基底层11可以为P型掺杂或N型掺杂。所述保护层12的材质包括但不限于氧化硅。
需要指出的是，此处仅为示例，在其它实施例中，所述叠层结构下方的结构层可以根据需要进行调整，此处不应过分限制本发明的保护范围。
作为示例，请参阅图2，显示为所述三维存储器的一种局部俯视图，其中，前述图1呈现的为图2的A-A’向剖面。
具体的，如图2所示，所述虚设结构1包括第一虚设部101与第二虚设部102，所述栅线缝隙2的一端伸入由所述第一虚设部101与/或所述第二虚设部102形成的间隙中，所述第一虚设部101与所述第二虚设部102中的至少一个与所述栅线缝隙2在水平面上的投影部分重叠。
具体的，所述第一虚设部101与/或所述第二虚设部102形成的间隙宽度小于所述栅线缝隙2的宽度，以保证所述虚设结构1与所述栅线缝隙2在水平面上的投影有重叠部分，从而实现所述虚设结构1与所述栅线缝隙2的连接。其中，在理想状况下，所述栅线缝隙2位于所述第一虚设部101与所述第二虚设部102形成的间隙的正中间，所述第一虚设部101及所述第二虚设部102均与所述栅线缝隙2在水平面上的投影有重叠部分；或者所述栅线缝隙2位于所述第一虚设部101或所述第二虚设部102形成的间隙的正中间，所述第一虚设部101或所述第二虚设部102与所述栅线缝隙2的两侧均有重叠部分；而在非理想状况下，所述栅线缝隙2偏离间隙的正中间，但因为间隙宽度小于所述栅线缝隙2的宽度，无论所述栅线缝隙2往哪一侧偏移，都能够保证所述虚设结构1与所述栅线缝隙2在水平面上的投影有重叠部分。
作为示例，在垂直于所述栅线缝隙2的延伸方向上，所述虚设结构1与所述栅线缝隙2在水平面上的投影的重叠部分的宽度为M，所述栅线缝隙2的宽度为N，其中，M<0.1N。也就是说，重叠部分的宽度占栅线缝隙2的总宽度的比例非常少，从而可以有效减少/消除虚设结构1与栅线缝隙2交界处的脆弱点，有助于提高器件可靠性。
具体的，在满足上述原则的前提下，所述虚设结构1可以有多种形态。
作为示例，请参阅图3，显示为所述虚设结构1与栅线缝隙2连接的第一种平面图，其中，所述虚设结构1的所述第一虚设部101与所述第二虚设部102之间独立设置，所述间隙 位于所述第一虚设部101和所述第二虚设部102之间。本实施例中，所述第一虚设部101及所述第二虚设部102沿所述栅线缝隙2的延伸方向平行设置，且为直线型。
作为示例，请参阅图4，显示为所述虚设结构1与栅线缝隙2连接的第二种平面图，其中，所述间隙位于所述第一虚设部101和所述第二虚设部102之间，所述虚设结构1的还包括第三虚设部103，所述第三虚设部103位于所述间隙中并与所述第一虚设部101及所述第二虚设部102连接，且所述第三虚设部103与所述栅线缝隙2间隔预设距离。
作为示例，请参阅图5，显示为所述虚设结构1与栅线缝隙2连接的第三种平面图，其中，所述间隙分别位于所述第一虚设部101围成的区域以及所述第二虚设部102围成的区域，所述虚设结构还包括第三虚设部103，所述第三虚设部103位于所述第一虚设部101及所述第二虚设部之间102且分别与所述第一虚设部101和所述第二虚设部102连接，且所述第三虚设部103与所述栅线缝隙2间隔预设距离。
作为示例，请参阅图6，显示为所述虚设结构1与栅线缝隙2连接的第四种平面图，其中，所述间隙位于所述第一虚设部101和所述第二虚设部102之间，所述虚设结构1的所述第一虚设部101与所述第二虚设部102之间通过第三虚设部103连接，具体的，所述第三虚设部103连接于所述第一虚设部101远离所述栅线缝隙2的一端及所述第二虚设部102远离所述栅线缝隙2的一端，且所述第三虚设部103与所述栅线缝隙2间隔预设距离。
在上述不同形态的虚设结构中，图3、图4及图5所示形态的虚设结构更适用于两根栅线缝隙之间的连接，图6所示形态的虚设结构更适用于连接单根栅线缝隙。
需要指出的是，在其它实施例中，所述虚设结构还可以采用其它包裹栅线缝隙端部的形态，此处不应过分限制本发明的保护范围。
作为示例，请参阅图7，显示为所述三维存储器的一种平面布局图，所述三维存储器包括在第一水平方向Y上由所述栅线缝隙将所述叠层结构进行划分的多个区块，所述区块包括在第二水平方向X上依次设置的第一核心区、台阶区及第二核心区，所述第一水平方向Y与所述第二水平方向X相互垂直，所述台阶区设有台阶结构19，所述台阶结构19作为连接区，其包括多级台阶，所述台阶的台面上设有多个与栅线层连接的触点20。
作为示例，多个区块包括相邻的第一区块15与第二区块16，所述栅线缝隙包括位于所述第一区块15与所述第二区块16之间且分别位于所述第一核心区和所述第二核心区的第一栅线缝隙17和第二栅线缝隙18，所述第一栅线缝隙17朝向所述台阶区的一端连接有一虚设结构1a，所述第二栅线缝隙18朝向所述台阶区的一端连接有一虚设结构1b。本实施例中，与所述第一栅线缝隙17连接的虚设结构1a、与所述第二栅线缝隙17连接的虚设结构1b均呈前述图6所示的形状。所述第一栅线缝隙17、所述虚设结构1a、所述第一区块15与所述 第二区块16之间在栅线牺牲层刻蚀之后残留的绝缘材料(未图示)、所述虚设结构1b及所述第二栅线缝隙18依次连接，实现所述第一区块15与所述第二区块16之间的隔离。
作为示例，所述第一区块15与所述第二区块16均包括多个指状结构，例如2-10个指状结构。本实施例中，在所述第一区块15指向所述第二区块的方向上，所述第一区块15依次包括第一指状结构15a、第二指状结构15b及第三指状结构15c，所述第二区块16依次包括第四指状结构16a、第五指状结构16b及第六指状结构16c，其中，每个区块中，相邻指状结构之间通过断续设置的栅线缝隙划分，采用断续设置的栅线缝隙的目的是为了使相邻指状结构的栅线层仍然相连。
作为示例，所述指状结构的存储区域的中间设有顶部选择栅切口21，所述顶部选择栅切口21将所述存储区域的顶部选择栅层划分为两部分，以将存储区域划分为两个独立可编程(读/写)的页。
作为示例，为了实现所有区块与区块之间的加固，所述栅线缝隙还包括位于所述第一区块15远离所述第二区块16的一侧的多条间隔的第三栅线缝隙24以及位于所述第二区块16远离所述第一区块15的一侧的多条间隔的第四栅线缝隙25，所述第三栅线缝隙24和所述第四栅线缝隙24位于所述台阶区，相邻两条所述第三栅线缝隙24之间通过虚设结构1c连接；相邻两条所述第四栅线缝隙25之间通过虚设结构1d连接。所述虚设结构1c及所述虚设结构1d优选采用图3、图4、图5所示的虚设结构形态。
作为示例，所述第一区块15远离所述第二区块16的边缘区域(本实施例中为所述第一指状结构15a的边缘区域)设有第一挡墙结构22，所述第二区块16远离所述第一区块15的边缘区域(本实施例中为第六指状结构16c的边缘区域)中设有第二挡墙结构23，所述第三栅线缝隙1c位于所述第一挡墙结构22远离所述第二挡墙结构23的一侧，所述第四栅线缝隙1d位于所述第二挡墙结构23远离所述第一挡墙结构23的一侧，所述第一挡墙结构22及所述第二挡墙结构23均包括在垂直方向上交替堆叠的导电层(例如钨层)及绝缘层(例如氧化硅层)，其中，所述第一挡墙结构22与所述第二挡墙结构23用于区块结构两端的电连接。所述第一挡墙结构22与所述第二挡墙结构23的横截面积自上而下可以逐渐增大，其中，所述第一指状结构15a中的虚线框区域显示为所述第一导电墙22在水平面上的投影区域，其面积大于所述第一导电墙22的顶面积，所述第六指状结构16c中的虚线框区域显示为所述第二导电墙23在水平面上的投影区域，其面积大于所述第二导电墙23的顶面积。
本实施例的三维存储器中，虚设结构包括第一虚设部与第二虚设部，所述第一虚设部与所述第二虚设部之间设有间隙，栅线缝隙的一端伸入所述间隙中，所述第一虚设部与所述第二虚设部中的至少一个与所述栅线缝隙在水平面上的投影部分重叠，以实现所述虚设结构与 所述栅线缝隙的连接。这种将栅线缝隙端部包裹住，但又不完全重叠的虚设结构设计可以有效改善虚设结构与栅线缝隙交界处栅线缝隙刻蚀的工艺窗口问题，有效减少/消除虚设结构与栅线缝隙交界处的脆弱点，有助于提高器件可靠性。
实施例二
本实施例中提供一种三维存储器的制作方法，请参阅图8，显示为该方法的工艺流程图，包括以下步骤：
S1：提供一衬底，形成叠层结构于所述衬底上，所述叠层结构包括在垂直方向上交替堆叠的栅线牺牲层与隔离层；
S2：形成虚设结构，所述虚设结构沿垂直方向贯穿所述叠层结构，所述虚设结构包括第一虚设部与第二虚设部；
S3：形成栅线缝隙，所述栅线缝隙垂直方向贯穿所述叠层结构，所述栅线缝隙的一端伸入由所述第一虚设部和/或所述第二虚设部形成的间隙中，所述第一虚设部与所述第二虚设部中的至少一个与所述栅线缝隙在水平面上的投影部分重叠。
首先请参阅图9，执行步骤S1：提供一衬底，形成叠层结构于所述衬底上，所述叠层结构包括在垂直方向上交替堆叠的栅线牺牲层26与隔离层4。所述栅线牺牲层26包括但不限于氮化硅层，所述隔离层4包括但不限于氧化硅层。所述栅线牺牲层在后续工艺过程中将被去除，并再次填充栅线材料，例如钨，得到栅线。
作为示例，所述衬底自下而上依次包括基底层11、保护层12、氮化硅层13、氧化硅层14、底部多晶硅层6、第一间隔层7、中部多晶硅层8、第二间隔层9及顶部多晶硅层10，所述基底层11包括但不限于Si基底、Ge基底、SiGe基底、绝缘体上硅(Silicon On Insulator，SOI)基底或绝缘体上锗(Germanium On Insulator，GOI)基底等，且所述基底层11可以为P型掺杂或N型掺杂。所述保护层12的材质包括但不限于氧化硅。所述第一间隔层7或所述第二间隔层9的材质包括但不限于氮氧化硅。所述中部多晶硅层8作为牺牲层，后续将被去除并再次填充。需要指出的是，此处仅为示例，在其它实施例中，所述衬底中的结构层可以根据需要进行调整，此处不应过分限制本发明的保护范围。
然后请参阅图10，执行步骤S2：通过一个或多个湿法蚀刻和/或干法蚀刻工艺(例如深反应离子蚀刻(DRIE))形成虚设结构1，并填充绝缘材料5于所述虚设结构1中，其中，所述虚设结构1沿垂直方向贯穿所述叠层结构。本实施例中，所述虚设结构1的底部到达所述第二间隔层9表面。
再请参阅图11，执行步骤S3：通过一个或多个湿法蚀刻和/或干法蚀刻工艺形成栅线缝 隙2，所述栅线缝隙2沿垂直方向贯穿所述叠层结构。本实施例中，所述栅线缝隙2的底部到达所述顶部多晶硅层10表面。
作为示例，请参阅图12，显示为本步骤所获得结构的局部俯视图，可见，所述虚设结构1包括第一虚设部101与第二虚设部102，所述栅线缝隙2的一端伸入由所述第一虚设部101与/或所述第二虚设部102形成的间隙中，所述第一虚设部101与所述第二虚设部102中的至少一个与所述栅线缝隙2在水平面上的投影部分重叠。
具体的，所述第一虚设部101与/或所述第二虚设部102形成的间隙宽度小于所述栅线缝隙2的宽度，以保证所述虚设结构1与所述栅线缝隙2在水平面上的投影有重叠部分，从而实现所述虚设结构1与所述栅线缝隙2的连接。其中，在理想状况下，所述栅线缝隙2位于所述第一虚设部101与所述第二虚设部102形成的间隙的正中间，所述第一虚设部101及所述第二虚设部102均与所述栅线缝隙2在水平面上的投影有重叠部分；或者所述栅线缝隙2位于所述第一虚设部101或所述第二虚设部102形成的间隙的正中间，所述第一虚设部101或所述第二虚设部102与所述栅线缝隙2的两侧均有重叠部分；而在非理想状况下，所述栅线缝隙2偏离间隙的正中间，但因为间隙宽度小于所述栅线缝隙2的宽度，无论所述栅线缝隙2往哪一侧偏移，都能够保证所述虚设结构1与所述栅线缝隙2在水平面上的投影有重叠部分。
作为示例，在垂直于所述栅线缝隙2的延伸方向上，所述虚设结构1与所述栅线缝隙2在水平面上的投影的重叠部分的宽度为M，所述栅线缝隙2的宽度为N，其中，M<0.1N。也就是说，重叠部分的宽度占栅线缝隙2的总宽度的比例非常少，从而可以有效减少/消除虚设沟结构1与栅线缝隙2交界处的脆弱点，有助于提高器件可靠性。
具体的，在满足上述原则的前提下，所述虚设结构1可以有多种形态。
作为示例，请参阅图3，显示为所述虚设结构1与栅线缝隙2连接的第一种平面图，其中，所述虚设结构1的所述第一虚设部101与所述第二虚设部102之间独立设置，所述间隙位于所述第一虚设部101和所述第二虚设部102之间。本实施例中，所述第一虚设部101及所述第二虚设部102沿所述栅线缝隙2的延伸方向平行设置，且为直线型。
作为示例，请参阅图4，显示为所述虚设结构1与栅线缝隙2连接的第二种平面图，其中，所述间隙位于所述第一虚设部101和所述第二虚设部102之间，所述虚设结构1的还包括第三虚设部103，所述第三虚设部103位于所述间隙中并与所述第一虚设部101及所述第二虚设部102连接，且所述第三虚设部103与所述栅线缝隙2间隔预设距离。
作为示例，请参阅图5，显示为所述虚设结构1与栅线缝隙2连接的第三种平面图，其中，所述间隙分别位于所述第一虚设部101围成的区域以及所述第二虚设部102围成的区域， 所述虚设结构还包括第三虚设部103，所述第三虚设部103位于所述第一虚设部101及所述第二虚设部之间102且分别与所述第一虚设部101和所述第二虚设部102连接，且所述第三虚设部103与所述栅线缝隙2间隔预设距离。
作为示例，请参阅图6，显示为所述虚设结构1与栅线缝隙2连接的第四种平面图，其中，所述间隙位于所述第一虚设部101和所述第二虚设部102之间，所述虚设结构1的所述第一虚设部101与所述第二虚设部102之间通过第三虚设部103连接，具体的，所述第三虚设部103连接于所述第一虚设部101远离所述栅线缝隙2的一端及所述第二虚设部102远离所述栅线缝隙2的一端，且所述第三虚设部103与所述栅线缝隙2间隔预设距离。
需要指出的是，上述图12中同时呈现了三种不同形态的虚设结构，但在实际应用中，可根据需要灵活选择相同或不同形态的虚设结构，此处不应过分限制本发明的保护范围。其中，图3、图4及图5所示形态的虚设结构更适用于两根栅线缝隙之间的连接，图6所示形态的虚设结构更适用于连接单根栅线缝隙。
需要指出的是，在其它实施例中，所述虚设结构还可以采用其它包裹栅线缝隙端部的形态，此处不应过分限制本发明的保护范围。
具体的，后续可去除所述栅线牺牲层，得到横向凹槽，并在所述横向凹槽中沉积栅线层。
本实施例的三维存储器的制作方法中，虚设结构与栅线缝隙的交界面积非常小，相互间影响较小，从而可以扩大虚设结构与栅线缝隙交界处栅线缝隙刻蚀的工艺窗口，有效减少/消除虚设结构与栅线缝隙交界处的脆弱点，有助于提高器件可靠性。
综上所述，本发明的三维存储器中，虚设结构包括第一虚设部与第二虚设部，所述第一虚设部与所述第二虚设部之间设有间隙，栅线缝隙的一端伸入所述间隙中，所述第一虚设部与所述第二虚设部中的至少一个与所述栅线缝隙在水平面上的投影部分重叠，以实现所述虚设结构与所述栅线缝隙的连接。这种将栅线缝隙端部包裹住，但又不完全重叠的虚设结构设计可以有效改善虚设结构与栅线缝隙交界处栅线缝隙刻蚀的工艺窗口问题，有效减少/消除虚设结构与栅线缝隙交界处的脆弱点，有助于提高器件可靠性。所以，本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (29)

  1. 一种三维存储器，其特征在于，包括：
    叠层结构，包括在垂直方向上交替堆叠的栅线层与电介质层；
    虚设结构，沿垂直方向贯穿所述叠层结构，所述虚设结构包括第一虚设部与第二虚设部；
    栅线缝隙，沿垂直方向贯穿所述叠层结构，所述栅线缝隙的一端伸入由所述第一虚设部与/或所述第二虚设部形成的间隙中。
  2. 根据权利要求1所述的三维存储器，其特征在于：所述第一虚设部与所述第二虚设部中的至少一个与所述栅线缝隙在水平面上的投影部分重叠，在垂直于所述栅线缝隙的延伸方向上，所述虚设结构与所述栅线缝隙在水平面上的投影的重叠部分的宽度为M，所述栅线缝隙的宽度为N，其中，M<0.1N。
  3. 根据权利要求1所述的三维存储器，其特征在于：所述第一虚设部与所述第二虚设部之间独立设置，所述间隙位于所述第一虚设部和所述第二虚设部之间。
  4. 根据权利要求3所述的三维存储器，其特征在于：所述第一虚设部及所述第二虚设部沿所述栅线缝隙的延伸方向平行设置。
  5. 根据权利要求1所述的三维存储器，其特征在于：所述间隙位于所述第一虚设部和所述第二虚设部之间，所述虚设结构还包括第三虚设部，所述第三虚设部位于所述间隙中并与所述第一虚设部及所述第二虚设部连接，且所述第三虚设部与所述栅线缝隙间隔预设距离。
  6. 根据权利要求1所述的三维存储器，其特征在于：所述间隙分别位于所述第一虚设部围成的区域以及所述第二虚设部围成的区域，所述虚设结构还包括第三虚设部，所述第三虚设部位于所述第一虚设部及所述第二虚设部之间且分别与所述第一虚设部和所述第二虚设部连接，且所述第三虚设部与所述栅线缝隙间隔预设距离。
  7. 根据权利要求1所述的三维存储器，其特征在于：所述间隙位于所述第一虚设部和所述第二虚设部之间，所述虚设结构还包括第三虚设部，所述第三虚设部连接于所述第一虚设部远离所述栅线缝隙的一端及所述第二虚设部远离所述栅线缝隙的一端，且所述第三虚设部与所述栅线缝隙间隔预设距离。
  8. 根据权利要求1-7任一项所述的三维存储器，其特征在于：所述三维存储器包括在第二水平方向上依次设置的核心区和台阶区，所述栅线缝隙包括位于所述核心区的第一栅线缝隙，所述第一栅线缝隙朝向所述台阶区的一端连接有一所述虚设结构。
  9. 根据权利要求1-7任一项所述的三维存储器，其特征在于：所述三维存储器包括在第一水平方向上由所述栅线缝隙将所述叠层结构进行划分的多个区块，所述区块包括在第二水平方向上依次设置的第一核心区、台阶区及第二核心区，所述第一水平方向与所述第二水平方向相互垂直。
  10. 根据权利要求9所述的三维存储器，其特征在于：多个区块包括相邻的第一区块和第二区块，所述栅线缝隙包括位于所述第一区块与所述第二区块之间且位于所述第一核心区的第一栅线缝隙，所述栅线缝隙包括位于所述第一区块与所述第二区块之间且位于所述第二核心区的第二栅线缝隙，所述第一栅线缝隙朝向所述台阶区的一端连接有一所述虚设结构，所述第二栅线缝隙朝向所述台阶区的一端连接有一所述虚设结构。
  11. 根据权利要求10所述的三维存储器，其特征在于：所述间隙位于所述第一虚设部和所述第二虚设部之间，所述虚设结构还包括第三虚设部，所述第三虚设部连接于所述第一虚设部远离所述栅线缝隙的一端及所述第二虚设部远离所述栅线缝隙的一端，且所述第三虚设部与所述栅线缝隙间隔预设距离。
  12. 根据权利要求10所述的三维存储器，其特征在于：所述栅线缝隙包括位于所述第一区块远离所述第二区块的一侧的多条间隔的第三栅线缝隙以及位于所述第二区块远离所述第一区块的一侧的多条间隔的第四栅线缝隙，所述第三栅线缝隙和所述第四栅线缝隙位于所述台阶区，相邻两条所述第三栅线缝隙之间通过所述虚设结构连接；相邻两条所述第四栅线缝隙之间通过所述虚设结构连接。
  13. 根据权利要求12所述的三维存储器，其特征在于：所述第一虚设部与所述第二虚设部之间独立设置，所述间隙位于所述第一虚设部和所述第二虚设部之间；或者所述间隙位于所述第一虚设部和所述第二虚设部之间，所述虚设结构还包括第三虚设部，所述第三虚设部位于所述间隙中并与所述第一虚设部及所述第二虚设部连接，且所述第三虚设部与所述栅线缝隙间隔预设距离；或者所述间隙分别位于所述第一虚设部围成的区域以及所述第二虚设部围成的区域，所述虚设结构还包括第三虚设部，所述第三虚设部位于所述第一虚设部 及所述第二虚设部之间且分别与所述第一虚设部和所述第二虚设部连接，且所述第三虚设部与所述栅线缝隙间隔预设距离。
  14. 根据权利要求12所述的三维存储器，其特征在于：所述第一区块在远离所述第二区块的边缘区域设有位于所述台阶区的第一挡墙结构，所述第二区块在远离所述第一区块的边缘区域设有位于所述台阶区的第二挡墙结构，所述第三栅线缝隙位于所述第一挡墙结构远离所述第二挡墙结构的一侧，所述第四栅线缝隙位于所述第二挡墙结构远离所述第一挡墙结构的一侧，所述第一挡墙结构及所述第二挡墙结构均包括在垂直方向上交替堆叠的导电层及绝缘层。
  15. 根据权利要求1-7任一项所述的三维存储器，其特征在于：所述虚设结构采用绝缘材料。
  16. 根据权利要求1-7任一项所述的三维存储器，其特征在于：所述虚设结构的底面低于所述栅线缝隙的底面。
  17. 根据权利要求1-7任一项所述的三维存储器，其特征在于：还包括多晶硅层，所述叠层结构设于所述多晶硅上，所述栅线缝隙的底部至少延伸至所述多晶硅层表面。
  18. 一种三维存储器的制作方法，其特征在于，包括以下步骤：
    提供一衬底，形成叠层结构于所述衬底上，所述叠层结构包括在垂直方向上交替堆叠的栅线牺牲层与电介质层；
    形成虚设结构，所述虚设结构沿垂直方向贯穿所述叠层结构，所述虚设结构包括第一虚设部与第二虚设部；
    形成栅线缝隙，所述栅线缝隙沿垂直方向贯穿所述叠层结构，所述栅线缝隙的一端伸入由所述第一虚设部和/或所述第二虚设部形成的间隙中。
  19. 根据权利要求18所述的三维存储器的制作方法，其特征在于：所述第一虚设部与所述第二虚设部中的至少一个与所述栅线缝隙在水平面上的投影部分重叠，在垂直于所述栅线缝隙的延伸方向上，所述虚设结构与所述栅线缝隙在水平面上的投影的重叠部分的宽度为M，所述栅线缝隙的宽度为N，其中，M<0.1N。
  20. 根据权利要求18所述的三维存储器的制作方法，其特征在于：所述第一虚设部与所述第 二虚设部之间独立设置，所述间隙位于所述第一虚设部和所述第二虚设部之间。
  21. 根据权利要求18所述的三维存储器的制作方法，其特征在于：所述间隙位于所述第一虚设部和所述第二虚设部之间，所述虚设结构还包括第三虚设部，所述第三虚设部位于所述间隙中并与所述第一虚设部及所述第二虚设部连接，且所述第三虚设部与所述栅线缝隙间隔预设距离；或者所述间隙分别位于所述第一虚设部围成的区域以及所述第二虚设部围成的区域，所述虚设结构还包括第三虚设部，所述第三虚设部位于所述第一虚设部及所述第二虚设部之间且分别与所述第一虚设部和所述第二虚设部连接，且所述第三虚设部与所述栅线缝隙间隔预设距离；或者所述间隙位于所述第一虚设部和所述第二虚设部之间，所述虚设结构还包括第三虚设部，所述第三虚设部连接于所述第一虚设部远离所述栅线缝隙的一端及所述第二虚设部远离所述栅线缝隙的一端，且所述第三虚设部与所述栅线缝隙间隔预设距离。
  22. 根据权利要求18-21任一项所述的三维存储器的制作方法，其特征在于：所述三维存储器包括在第二水平方向上依次设置的核心区和台阶区，所述栅线缝隙包括位于所述核心区的第一栅线缝隙，所述第一栅线缝隙朝向所述台阶区的一端连接有一所述虚设结构。
  23. 根据权利要求18-21任一项所述的三维存储器的制作方法，其特征在于：所述三维存储器包括在第一水平方向上由所述栅线缝隙将所述叠层结构进行划分的多个区块，所述区块包括在第二水平方向上依次设置的第一核心区、台阶区及第二核心区，所述第一水平方向与所述第二水平方向相互垂直。
  24. 根据权利要求23所述的三维存储器的制作方法，其特征在于：多个区块包括相邻的第一区块和第二区块，所述栅线缝隙包括位于所述第一区块与所述第二区块之间且位于所述第一核心区的第一栅线缝隙，所述栅线缝隙包括位于所述第一区块与所述第二区块之间且位于所述第二核心区的第二栅线缝隙，所述第一栅线缝隙朝向所述台阶区的一端连接有一所述虚设结构，所述第二栅线缝隙朝向所述台阶区的一端连接有一所述虚设结构。
  25. 根据权利要求24所述的三维存储器的制作方法，其特征在于：所述间隙位于所述第一虚设部和所述第二虚设部之间，所述虚设结构还包括第三虚设部，所述第三虚设部连接于所述第一虚设部远离所述栅线缝隙的一端及所述第二虚设部远离所述栅线缝隙的一端，且所述第三虚设部与所述栅线缝隙间隔预设距离。
  26. 根据权利要求24所述的三维存储器的制作方法，其特征在于：所述栅线缝隙包括位于所述第一区块远离所述第二区块的一侧的多条间隔的第三栅线缝隙以及位于所述第二区块远离所述第一区块的一侧的多条间隔的第四栅线缝隙，相邻两条所述第三栅线缝隙之间通过所述虚设结构连接；相邻两条所述第四栅线缝隙之间通过所述虚设结构连接。
  27. 根据权利要求26所述的三维存储器的制作方法，其特征在于：所述第一虚设部与所述第二虚设部之间独立设置，所述间隙位于所述第一虚设部和所述第二虚设部之间；或者所述间隙位于所述第一虚设部和所述第二虚设部之间，所述虚设结构还包括第三虚设部，所述第三虚设部位于所述间隙中并与所述第一虚设部及所述第二虚设部连接，且所述第三虚设部与所述栅线缝隙间隔预设距离；或者所述间隙分别位于所述第一虚设部围成的区域以及所述第二虚设部围成的区域，所述虚设结构还包括第三虚设部，所述第三虚设部位于所述第一虚设部及所述第二虚设部之间且分别与所述第一虚设部和所述第二虚设部连接，且所述第三虚设部与所述栅线缝隙间隔预设距离。
  28. 根据权利要求26所述的三维存储器的制作方法，其特征在于：所述第一区块在远离所述第二区块的边缘区域设有位于所述台阶区的第一挡墙结构，所述第二区块在远离所述第一区块的边缘区域设有位于所述台阶区的第二挡墙结构，所述第三栅线缝隙位于所述第一挡墙结构远离所述第二挡墙结构的一侧，所述第四栅线缝隙位于所述第二挡墙结构远离所述第一挡墙结构的一侧，所述第一挡墙结构及所述第二挡墙结构均包括在垂直方向上交替堆叠的所述栅线牺牲层与所述电介质层。
  29. 根据权利要求18所述的三维存储器的制作方法，其特征在于：所述衬底自下而上依次包括底部多晶硅层、第一间隔层、中部多晶硅层、第二间隔层及顶部多晶硅层，所述虚设结构的底部至少延伸至所述第二间隔层表面，所述栅线缝隙的底部至少延伸至所述顶部多晶硅层表面。
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