WO2022105747A1 - 半导体器件及其制备方法 - Google Patents

半导体器件及其制备方法 Download PDF

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Publication number
WO2022105747A1
WO2022105747A1 PCT/CN2021/130905 CN2021130905W WO2022105747A1 WO 2022105747 A1 WO2022105747 A1 WO 2022105747A1 CN 2021130905 W CN2021130905 W CN 2021130905W WO 2022105747 A1 WO2022105747 A1 WO 2022105747A1
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Prior art keywords
lateral direction
array
channel
semiconductor device
channel pillar
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PCT/CN2021/130905
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English (en)
French (fr)
Inventor
刘思敏
徐伟
许波
郭亚丽
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长江存储科技有限责任公司
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Priority to CN202180006424.7A priority Critical patent/CN114730766A/zh
Publication of WO2022105747A1 publication Critical patent/WO2022105747A1/zh
Priority to US18/087,159 priority patent/US20230125309A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region

Definitions

  • Embodiments of the present disclosure relate to the technical field of semiconductors, and in particular, to a semiconductor device and a method for fabricating the same.
  • Memory is a memory device used to store information in modern information technology. With the increasing demand for integration and data storage density of various electronic devices, it is increasingly difficult for ordinary two-dimensional memory devices to meet the requirements. In this case, three-dimensional (3D) memory emerges as the times require.
  • a stacked structure is formed on the substrate, and the stacked structure is divided into a core region and a staircase region in the direction of the substrate plane.
  • a number of channel holes (CH) will be set and filled with corresponding materials to realize the storage function and the support function.
  • the channel hole in the storage region is first fabricated, and then the channel hole in the step region is fabricated.
  • the channel holes in the storage area are etched and filled first, charges will be stored in the channel holes in the storage area.
  • the channel holes in the stepped area are etched, the The electric charge will have an attractive effect on the channel hole in the step region, thereby causing deformation of the channel hole in the step region, and this deformation will cause leakage current of the semiconductor device and affect the performance of the device.
  • the semiconductor device includes:
  • a stack layer disposed above the substrate and formed by alternately stacking insulating layers and gate layers, the stack layer is divided into a transition channel column region along a first lateral direction parallel to the substrate, and a a dummy channel pillar region next to the transition channel pillar region;
  • transition channel pillars formed in the stack layer and located in the transition channel pillar region, and comprising in the first lateral direction and a second lateral direction parallel to the substrate and perpendicular to the first lateral direction a plurality of transition channel pillars arranged in an array in the lateral direction;
  • a dummy channel column array formed in the stacked layer and located in the dummy channel column region, and comprising a plurality of dummy channel columns arranged in an array in the first lateral direction and the second lateral direction;
  • a gate spacer is formed in the stacked layer and extends along the second lateral direction, and is disposed between the transition channel column array and the dummy channel column array.
  • the dummy channel pillars are disposed in stepped regions formed by the stacked layers.
  • the gate spacers include a plurality of and are spaced along the first lateral direction, and have an arrangement density in a direction from the transition channel pillar array to the dummy channel pillar array. slowing shrieking.
  • the gate spacers include a plurality of and are spaced along the second lateral direction to form a dotted line shape.
  • the semiconductor device further includes a gate line slit extending through the stacked layer in a longitudinal direction perpendicular to the substrate and extending in the first lateral direction.
  • the gate spacers are made of the same material as the gate line slits.
  • a cross-sectional shape of the gate spacer in the first lateral direction includes at least one of a rectangle, a trapezoid, and a semicircle, and the gate spacer faces the dummy channel pillar array one side is a plane.
  • the arrangement density of the transition channel pillars in the transition channel pillar array gradually decreases toward the dummy channel pillar region along the first lateral direction.
  • the transition channel column has a critical dimension, the critical dimension being a distance from a center of the transition channel column to an edge of the transition channel column, the transition channel column The critical dimension gradually increases toward the dummy channel pillar region along the first lateral direction.
  • an embodiment of the present disclosure also provides a method for fabricating a semiconductor device, the fabrication method comprising:
  • a stack layer is provided, the stack layer is disposed above the substrate and is formed by alternately stacking insulating layers and gate layers, and the stack layer is divided into transition channel pillar regions along a first lateral direction parallel to the substrate , and a dummy channel pillar region located next to the transition channel pillar region;
  • transition channel pillars formed in the stack layer and located in the transitional channel pillar region and including in the first lateral direction and in the first lateral direction parallel to the substrate and perpendicular to the substrate a plurality of transition channel pillars arranged in an array on the second lateral direction of the first lateral direction;
  • a dummy channel column array is provided, the dummy channel column array is formed in the stacked layer and located in the dummy channel column region, and includes arrays arranged in the first lateral direction and the second lateral direction a plurality of virtual channel pillars;
  • a gate spacer is provided, the gate spacer is formed in the stack layer, extends along the second lateral direction, and is disposed between the transition channel pillar array and the dummy channel pillar array.
  • the embodiments of the present disclosure provide a semiconductor device, comprising: a substrate, a stack layer disposed above the substrate and formed by alternately stacking insulating layers and gate layers, the stack layer extending along the A first lateral area parallel to the substrate includes a transition channel column region and a dummy channel column region located next to the transition channel column region, formed in the stacked layer and located in the transition channel column region and the dummy channel column region, respectively
  • the transition channel column array and the dummy channel column array respectively comprise a plurality of transitions arranged in an array in a first lateral direction and a second lateral direction perpendicular to the first lateral direction A channel column, a plurality of dummy channel columns, and a gate spacer formed in the stacked layer and extending along the second lateral direction and disposed between the transition channel column array and the dummy channel column array, embodiments of the present disclosure
  • the present disclosure In the provided semiconductor device, by arranging gate spacers between the transition channel column array and
  • FIG. 1 is a schematic top-view structural diagram of a semiconductor device provided by a first embodiment according to an embodiment of the present disclosure.
  • FIG. 2 is a schematic front view of the structure of the semiconductor device provided by the first embodiment according to the embodiment of the present disclosure.
  • FIG. 3 is a schematic flowchart of a method for fabricating a semiconductor device provided by a first embodiment according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic top-view structural diagram of a semiconductor device provided by a second embodiment according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic front view of the structure of the semiconductor device provided by the second embodiment according to the embodiment of the present disclosure.
  • first and second are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implying the number of indicated technical features.
  • features defined as “first”, “second” may expressly or implicitly include one or more of said features.
  • “plurality” means two or more, unless otherwise expressly and specifically defined.
  • the terms “installed”, “connected” and “connected” should be understood in a broad sense, for example, it may be a fixed connection or a Removable connection, or integral connection; can be mechanical connection, can also be electrical connection or can communicate with each other; can be directly connected, can also be indirectly connected through an intermediate medium, can be internal communication between two components or two components. interaction relationship.
  • a first feature "on” or “under” a second feature may include direct contact between the first and second features, or may include the first and second features.
  • the two features are not in direct contact but through another feature between them.
  • the first feature being “above”, “over” and “above” the second feature includes the first feature being directly above and obliquely above the second feature, or simply means that the first feature is level higher than the second feature.
  • the first feature is “below”, “below” and “below” the second feature includes the first feature being directly below and diagonally below the second feature, or simply means that the first feature has a lower level than the second feature.
  • the embodiments of the present disclosure are aimed at the problem of the existing semiconductor device, because the attractive force of the channel column in the storage region causes the deformation of the channel column in the step region, so that the semiconductor device generates leakage current, which affects the performance of the semiconductor device.
  • the present disclosure Embodiments Embodiments are used to solve this problem.
  • FIG. 1 is a schematic top-view structure diagram of a semiconductor device 100 provided by a first embodiment according to an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of the first embodiment according to an embodiment of the present disclosure.
  • a schematic view of the front structure of the semiconductor device 100 the schematic view of the front structure is a schematic cross-sectional view along aa' of the schematic top view structure shown in FIG. components, and their relative positions.
  • the semiconductor device 100 includes a substrate 110 , a stack layer 120 , a channel column array 130 , a dummy channel column array 140 , a gate spacer 150 , and a dielectric layer disposed above the stack layer 120 . 170, of which:
  • the substrate 110 may be a semiconductor substrate, and specifically includes at least one elemental semiconductor material (eg, silicon (Si) substrate, germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material semiconducting material, at least one organic semiconducting material, or other semiconducting material known in the art;
  • elemental semiconductor material eg, silicon (Si) substrate, germanium (Ge) substrate
  • the stacked layer 120 is disposed above the substrate 110 and is formed by alternately stacking insulating layers 121 and gate layers 122 .
  • the insulating layer 121 is made of insulating materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride or a combination of the above materials
  • the gate layer 122 is made of conductive materials, including but not limited to tungsten (W), Cobalt (Co), Copper (Cu), Aluminum (AL), doped silicon, silicide or a combination of the above.
  • the stacked layer 120 is divided into a channel column region A1 along a first lateral direction X1 parallel to the substrate 110, and a dummy channel column region A2 located next to the channel column region A1;
  • the channel pillar array 130 is formed in the stacked layer 120 and located in the channel pillar region A1, and includes a first lateral direction X1 and a second lateral direction X2 parallel to the substrate 110 and perpendicular to the first lateral direction X1.
  • a plurality of transition channel pillars 131 and storage channel pillars 132 are arranged in an array.
  • a functional layer and a channel layer are sequentially formed on the inner wall of the transition channel pillar 131 and the inner wall of the storage channel pillar 132, but the transition channel pillar 131 only plays a supporting role and does not play a storage role.
  • the pillars 132 serve as storage.
  • the storage channel column 132 is connected to the peripheral circuit to receive the control signal from the peripheral circuit to realize the storage function.
  • the functional layer includes a stacked tunneling dielectric layer, a charge storage layer, and a gate dielectric layer.
  • Exemplary materials of the gate dielectric layer and the tunneling dielectric layer are silicon oxide, silicon nitride, an insulating material with high insulation constant, or a combination of the above materials, Exemplary materials for the charge storage layer are silicon nitride, silicon oxynitride, silicon, or combinations thereof.
  • the material filled in the transition channel pillar 131 is not limited in this embodiment of the present application.
  • the material filled in the transition channel pillar 131 may be filled together with the functional layer and the channel layer filled in the storage channel pillar 132 .
  • the functional layer filled with the transition channel pillars 131 and the functional layer filled with the storage channel pillars 132 are completed in the same or the same multiple process steps, and the channel layer filled with the transition channel pillars 131 and the storage channel pillars 132 The filled channel layer is also completed in the same or the same process steps.
  • the material filled in the transition channel column 131 may be different from the material filled in the storage channel column 132, for example, the material filled in the transition channel column 131 may be silicon dioxide or other insulating materials,
  • the filling material in the storage channel pillar 132 is a functional layer and a channel layer.
  • the channel pillar region A1 may include a storage channel pillar 132 , and the storage channel pillar 132 may be adjacent to the gate spacer 150 .
  • the transition channel pillar 131 is located between the storage channel pillar 132 and the dummy channel pillar 141 , and the critical dimension of the transition channel pillar 131 is larger than the critical dimension of the storage channel pillar 132 .
  • the critical dimension of the transition channel pillar 131 may be the distance from the center of the transition channel pillar 131 to the edge of the transition channel pillar 131
  • the critical dimension of the storage channel pillar 132 may be the center of the storage channel pillar 132 to the storage channel pillar 132 edge distance.
  • the transition channel pillar 131 has a larger critical dimension and can provide a larger support area to improve the support for the semiconductor device.
  • the dummy channel column array 140 is formed in the stacked layer 120 and located in the dummy channel column area A2, and includes a plurality of dummy channel columns 141 arranged in an array on the first lateral direction X 1 and the second lateral direction X 2 , specifically , the plurality of dummy channel pillars 141 are disposed in the stepped region formed by the stacked layers 120 .
  • the dummy channel pillars 141 play a supporting role, and specifically, the material filled in the dummy channel pillars 141 may be silicon dioxide or other insulating materials;
  • the gate spacer 150 is formed in the stacked layer 120 and extends along the second lateral direction X 2 , and is disposed between the channel pillar array 130 and the dummy channel pillar array 140 . Specifically, the gate spacer 150 is located in the dummy channel Column area A2.
  • the gate spacers 150 include a plurality of gate spacers 150 and are arranged at intervals along the first lateral direction X 1 , and are arranged in the direction from the channel pillar array 130 to the dummy channel pillar array 140 .
  • the cloth density gradually decreases.
  • the cross-sectional shape of the gate spacer 150 on the first lateral direction X1 includes at least one of a rectangle, a trapezoid, and a semicircle, and the cross-sectional shape is a shape close to the channel pillar region A1, and the gate The side of the gate spacer 150 facing the dummy channel pillar array 140 is a plane.
  • the cross-sectional shape of the gate spacer 150 on the first lateral direction X1 is a rectangle.
  • the semiconductor device 100 further includes a gate line slit 160 , and the gate line slit 160 penetrates the stack layer 120 along the longitudinal direction perpendicular to the substrate 110 and extends along the A lateral direction X1 extends, and the gate spacer 150 and the gate line slit 160 are made of the same material.
  • Exemplary materials of the gate spacer 150 and the gate line slit 160 are polysilicon (Poly) and tungsten (W).
  • the gate spacer 150 separates the channel pillar array 130 from the dummy channel pillar array 140, and the two sides facing the channel pillar array 130 and the dummy channel pillar array 140 are complete planes.
  • Such a design method can better resist the attraction of the charges in the functional layer of the transition channel pillar 131 to the gate spacer 150 and the dummy channel pillar 141 , thereby avoiding the contact between the gate spacer 150 and the dummy channel pillar 141 .
  • the deformation will not cause leakage current of the semiconductor device 100 , thereby improving the performance of the semiconductor device 100 .
  • the arrangement density of the transition channel pillars 131 in the channel pillar array 130 is along the A lateral direction X1 gradually decreases toward the dummy channel column region A2, and the transition channel column 131 has a critical dimension CD (Critical Dimension), which is the center of the transition channel column 131 to the transition channel column 131.
  • the critical dimension CD of the plurality of transition channel pillars 131 gradually increases along the first lateral direction X1 toward the dummy channel pillar region A2.
  • FIG. 3 is a schematic flowchart of a method for fabricating the semiconductor device 100 provided by the first embodiment according to an embodiment of the present disclosure.
  • the preparation method specifically includes:
  • Substrate providing step S101 providing a substrate 110;
  • the stack layer providing step S102 providing the stack layer 120 , the stack layer 120 is disposed above the substrate 110 and is formed by alternately stacking the insulating layer 121 and the gate layer 122 , and the stack layer 120 is parallel to the first lateral direction X 1 of the substrate 110 .
  • a transition channel column region A1 and a dummy channel column region A2 located beside the transition channel column region A1 are distinguished;
  • the transition channel column array providing step S103 providing a transition channel column array 130, the transition channel column array 130 is formed in the stack layer 120 and located in the transition channel column region A1, and includes a first lateral direction X1 and a parallel to the a plurality of transition channel pillars 131 arranged in an array on the substrate 110 and a second lateral direction X2 perpendicular to the first lateral direction X1;
  • Step S104 of providing a dummy channel column array providing a dummy channel column array 140.
  • the dummy channel column array 140 is formed in the stack layer 120 and located in the dummy channel column area A2, and is included in the first lateral direction X1 and the second lateral direction A plurality of dummy channel pillars 141 arranged in an array on X 2 ;
  • Step S105 for providing gate spacers providing gate spacers 150 , which are formed in the stack layer 120 and extend along the second lateral direction X 2 and are disposed in the transition channel pillar array 130 and the dummy channel pillar array between 140.
  • an embodiment of the present disclosure provides a semiconductor device 100, comprising: a substrate 110, a stack layer 120 disposed above the substrate 110 and formed by alternately stacking insulating layers 121 and gate layers 122, the The stacked layer 120 is divided into a channel pillar region A1 along a first lateral direction X1 parallel to the substrate 110, and a dummy channel pillar region A2 located next to the channel pillar region A1, formed in the stacked layer 120 and located in the channel respectively.
  • the channel pillar array 130 and the dummy channel pillar array 140 of the pillar region A1 and the dummy channel pillar region A2, and the channel pillar array 130 and the dummy channel pillar array 140 respectively include the first lateral direction X1 and the vertical direction X1.
  • a plurality of transition channel pillars 131 and a plurality of dummy channel pillars 141 arranged in an array on a second transverse direction X2 of a transverse direction X1, are formed in the stack layer 120 and extend along the second transverse direction X2, and are disposed on
  • the spacer 150 effectively prevents the dummy channel column 141 from being deformed due to the attraction of the charges in the transition channel column 131 to the dummy channel column 141 , resulting in leakage current of the semiconductor device 100 , which affects the performance of the semiconductor device 100 . affecting issues.
  • FIG. 4 is a schematic top view of the semiconductor device 200 according to the second embodiment of the present disclosure
  • FIG. 5 is the second embodiment of the present disclosure.
  • a schematic view of the front structure of the semiconductor device the schematic view of the front structure is a schematic cross-sectional view along bb' of the schematic top view structure shown in FIG.
  • Each component, and the relative positional relationship of each component are schematic cross-sectional view along bb' of the schematic top view structure shown in FIG.
  • the structure of the second embodiment is substantially the same as that of the first embodiment, wherein the function and setting position of the substrate 210 in the second embodiment and the substrate 110 in the first embodiment are the same; Functions of the stacked layer 220 in the second embodiment (including the insulating layers 221 and the gate layers 222 arranged alternately) and the stacked layer 120 in the first embodiment (including the insulating layers 121 and the gate layers 122 arranged alternately) and the setting positions are the same; the channel pillar array 230 (including a plurality of transition channel pillars 231 and a plurality of storage channel pillars 232 ) in the second embodiment is the same as the channel pillar array 130 (including a plurality of storage channel pillars 232 ) in the first embodiment The functions and arrangement positions of the transition channel pillars 131 and the plurality of storage channel pillars 132 are the same; the dummy channel pillar array 240 (including the plurality of dummy channel pillars 241 ) in the second embodiment
  • the functions and arrangement positions of the dummy channel pillar array 140 are the same; the functions and arrangement of the gate line slits 260 in the second embodiment and the gate line slits 160 in the first embodiment The positions are the same; the function and setting position of the dielectric layer 270 in the second embodiment are the same as those of the dielectric layer 170 in the first embodiment.
  • the difference is that the arrangement of the gate spacers 250 in this embodiment is different from the arrangement of the gate spacers 150 in the first embodiment.
  • the gate spacers The grooves 250 include a plurality of grooves and are arranged at intervals along the second lateral direction X 2 to form a dotted line.
  • an embodiment of the present disclosure provides a semiconductor device 200, including: a substrate 210, a stack layer 220 disposed above the substrate 210 and formed by alternately stacking insulating layers 221 and gate layers 222, the The stacked layer 220 is divided into a channel pillar region B1 along a first lateral direction X1 parallel to the substrate 210, and a dummy channel pillar region B2 located next to the channel pillar region B1, formed in the stacked layer 220 and respectively located in the channel
  • the channel pillar array 230 and the dummy channel pillar array 240 in the pillar region B1 and the dummy channel pillar region B2, and the channel pillar array 230 and the dummy channel pillar array 240 respectively include a first lateral X1 and a vertical
  • a plurality of transition channel pillars 231 and a plurality of dummy channel pillars 241 are arranged in an array on a second transverse direction X2 of a transverse direction X1, and are formed in the
  • the embodiments of the present disclosure may also have other implementations. All technical solutions formed by using equivalent replacements or equivalent replacements fall within the protection scope required by the embodiments of the present disclosure.

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Abstract

本公开实施例提供了一种半导体器件，包括：衬底；设置于衬底上方且由绝缘层和栅极层交替层叠的堆叠层，堆叠层沿平行于衬底的第一横向区分有过渡沟道柱区、以及位于过渡沟道柱区旁边的虚拟沟道柱区；形成于堆叠层中且分别位于过渡沟道柱区与虚拟沟道柱区的过渡沟道柱阵列以及虚拟沟道柱阵列，过渡沟道柱阵列以及虚拟沟道柱阵列分别包括在第一横向与在垂直于第一横向的第二横向上呈阵列排列的多个过渡沟道柱以及多个虚拟沟道柱；形成于堆叠层中并沿第二横向延伸，且设置于过渡沟道柱阵列与虚拟沟道柱阵列之间的栅极隔槽。

Description

半导体器件及其制备方法
相关申请的交叉引用
本公开基于申请号为202011294003.2、申请日为2020年11月18日、申请名称为“半导体器件及其制备方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此以全文引入的方式引入本公开。
技术领域
本公开实施例涉及半导体技术领域，尤其涉及一种半导体器件及其制备方法。
背景技术
存储器(Memory)是现代信息技术中用于保存信息的记忆设备。随着各类电子设备对集成度和数据存储密度的需求的不断提高，普通的二维存储器件越来越难以满足要求，在这种情况下，三维(3D)存储器应运而生。
在三维存储器的制备中，主要是通过在衬底上形成堆叠结构，并在衬底平面方向上将堆叠结构划分为存储区(core region)以及台阶区(stair-step region)，在存储区以及台阶区，会设置若干沟道孔(Channel Hole，CH)，并分别填充对应的材料以实现存储功能和支撑功能。
现有技术下，为了降低工艺难度，会先制作存储区的沟道孔，然后再制作台阶区的沟道孔。但是，由于存储区的沟道孔先刻蚀成形并填实，此时会有电荷储存在存储区的沟道孔中，当进行台阶区的沟道孔刻蚀时，存储区沟道孔中的电荷对台阶区的沟道孔会产生吸引力的作用，从而导致台阶区的沟道孔变形，这种变形会使得半导体器件产生漏电流，对器件的性 能造成影响。
发明内容
为了解决上述问题，本公开实施例提供了一种半导体器件，所述半导体器件包括：
衬底；
堆叠层，设置于所述衬底上方且由绝缘层和栅极层交替层叠而成，所述堆叠层沿平行于所述衬底的第一横向区分有过渡沟道柱区、以及位于所述过渡沟道柱区旁边的虚拟沟道柱区；
过渡沟道柱阵列，形成于所述堆叠层中且位于所述过渡沟道柱区，并包括在所述第一横向与在平行于所述衬底且垂直于所述第一横向的第二横向上呈阵列排列的多个过渡沟道柱；
虚拟沟道柱阵列，形成于所述堆叠层中且位于所述虚拟沟道柱区，并包括在所述第一横向与所述第二横向上呈阵列排列的多个虚拟沟道柱；
栅极隔槽，形成于所述堆叠层中并沿所述第二横向延伸，且设置于所述过渡沟道柱阵列与所述虚拟沟道柱阵列之间。
在一些实施例中，所述虚拟沟道柱设置于所述堆叠层所形成的阶梯区。
在一些实施例中，所述栅极隔槽包括多个且沿所述第一横向间隔排布，并由所述过渡沟道柱阵列向所述虚拟沟道柱阵列的方向上的排布密度逐渐减小。
在一些实施例中，所述栅极隔槽包括多个且沿所述第二横向间隔排布而呈虚线形。
在一些实施例中，所述半导体器件还包括栅线狭缝，所述栅线狭缝沿垂直于所述衬底的纵向贯穿所述堆叠层，且沿所述第一横向延伸。
在一些实施例中，所述栅极隔槽与所述栅线狭缝的材料相同。
在一些实施例中，所述栅极隔槽在所述第一横向上的截面形状包括矩 形、梯形、半圆形其中至少之一，且所述栅极隔槽面向所述虚拟沟道柱阵列的一侧为一平面。
在一些实施例中，所述过渡沟道柱阵列中的所述过渡沟道柱的排布密度沿所述第一横向向所述虚拟沟道柱区逐渐减小。
在一些实施例中，所述过渡沟道柱具有关键尺寸，所述关键尺寸为所述过渡沟道柱的中心到所述过渡沟道柱的边缘的距离，所述多个过渡沟道柱的所述关键尺寸沿所述第一横向向所述虚拟沟道柱区逐渐增大。
另一方面，本公开实施例还提供了一种半导体器件的制备方法，所述制备方法包括：
提供衬底；
提供堆叠层，所述堆叠层设置于所述衬底上方且由绝缘层和栅极层交替层叠而成，所述堆叠层沿平行于所述衬底的第一横向区分有过渡沟道柱区、以及位于所述过渡沟道柱区旁边的虚拟沟道柱区；
提供过渡沟道柱阵列，所述过渡沟道柱阵列形成于所述堆叠层中且位于所述过渡沟道柱区，并包括在所述第一横向与在平行于所述衬底且垂直于所述第一横向的第二横向上呈阵列排列的多个过渡沟道柱；
提供虚拟沟道柱阵列，所述虚拟沟道柱阵列形成于所述堆叠层中且位于所述虚拟沟道柱区，并包括在所述第一横向与所述第二横向上呈阵列排列的多个虚拟沟道柱；
提供栅极隔槽，所述栅极隔槽形成于所述堆叠层中并沿所述第二横向延伸，且设置于所述过渡沟道柱阵列与所述虚拟沟道柱阵列之间。
本公开实施例的有益效果为：本公开实施例提供了一种半导体器件，包括：衬底，设置于衬底上方且由绝缘层和栅极层交替层叠而成的堆叠层，该堆叠层沿平行于衬底的第一横向区分有过渡沟道柱区、以及位于过渡沟道柱区旁边的虚拟沟道柱区，形成于堆叠层中且分别位于过渡沟道柱区与 虚拟沟道柱区的过渡沟道柱阵列以及虚拟沟道柱阵列，且过渡沟道柱阵列以及虚拟沟道柱阵列分别包括在第一横向与在垂直于第一横向的第二横向上呈阵列排列的多个过渡沟道柱以及多个虚拟沟道柱，以及形成于堆叠层中并沿第二横向延伸，且设置于过渡沟道柱阵列与虚拟沟道柱阵列之间的栅极隔槽，本公开实施例提供的半导体器件，通过在过渡沟道柱阵列与虚拟沟道柱阵列之间设置栅极隔槽，有效地避免了因过渡沟道柱中的电荷对虚拟沟道柱的吸引力，而使虚拟沟道柱变形，导致半导体器件产生漏电流，对半导体器件的性能造成影响的问题。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对根据本公开实施例而成的各实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开实施例的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是根据本公开实施例而成的第一实施例所提供的半导体器件的俯视结构示意图。
图2是根据本公开实施例而成的第一实施例所提供的半导体器件的正视结构示意图。
图3是根据本公开实施例而成的第一实施例所提供的半导体器件的制备方法的流程示意图。
图4是根据本公开实施例而成的第二实施例所提供的半导体器件的俯视结构示意图。
图5是根据本公开实施例而成的第二实施例所提供的半导体器件的正视结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本公开实施例一部分实施例，而不是全部的实施例。基于本公开实施例中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本公开实施例保护的范围。
在本公开实施例的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开实施例和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开实施例的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本公开实施例的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本公开实施例的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接或可以相互通讯；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本公开实施例中的具体含义。
在本公开实施例中，除非另有明确的规定和限定，第一特征在第二特 征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。
下文的公开提供了许多不同的实施方式或例子用来实现本公开实施例的不同结构。为了简化本公开实施例的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本公开实施例。此外，本公开实施例可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本公开实施例提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
本公开实施例针对现有的半导体器件，因为其存储区沟道柱的吸引力造成其台阶区沟道柱变形，而使得半导体器件产生漏电流，对半导体器件的性能造成影响的问题，本公开实施例实施例用以解决该问题。
请参阅图1以及图2，图1是根据本公开实施例而成的第一实施例所提供的半导体器件100的俯视结构示意图，图2是根据本公开实施例而成的第一实施例所提供的半导体器件100的正视结构示意图，该正视结构示意图为如图1所示的俯视结构示意图沿aa’的截面示意图，从图中可以很直观的看到根据本公开实施例而成的实施例的各组成部分，以及各组成部分的相对位置关系。
如图1以及图2所示，该半导体器件100包括衬底110、堆叠层120、沟道柱阵列130、虚拟沟道柱阵列140、栅极隔槽150以及设置于堆叠层120 上方的介质层170，其中：
衬底110可以为半导体衬底，具体包括至少一个单质半导体材料(例如：为硅(Si)衬底、锗(Ge)衬底)、至少一个III-V化合物半导体材料、至少一个II-VI化合物半导体材料、至少一个有机半导体材料或者在本领域已知的其他半导体材料；
堆叠层120设置于衬底110上方，且由绝缘层121和栅极层122交替层叠而成。其中，绝缘层121由绝缘材料制成，包括但不限于氧化硅、氮化硅、氮氧化硅或以上材料的组合，栅极层122由导电材料制成，包括但不限于钨(W)、钴(Co)、铜(Cu)、铝(AL)、掺杂硅、硅化物或以上材料的组合。在一些实施例中，堆叠层120沿平行于衬底110的第一横向X 1区分有沟道柱区A1、以及位于沟道柱区A1旁边的虚拟沟道柱区A2；
沟道柱阵列130形成于堆叠层120中且位于沟道柱区A1，并包括在第一横向X 1与在平行于衬底110且垂直于第一横向X 1的第二横向X 2上呈阵列排列的多个过渡沟道柱131和存储沟道柱132。
在一些实施例中，在过渡沟道柱131内壁和存储沟道柱132的内壁依次形成有功能层和沟道层，但该过渡沟道柱131只起支撑作用而不起存储作用，存储沟道柱132起到存储作用。例如存储沟道柱132与外围电路连接，以接收来自外围电路的控制信号实现存储功能。功能层包括堆叠的隧穿介质层、电荷储存层和栅介质层，栅介质层和隧穿介质层的示例性材料为氧化硅、氮化硅、高绝缘常数的绝缘材料或以上材料的组合，电荷储存层的示例性材料为氮化硅、氮氧化硅、硅或以上材料的组合。
本申请实施例对过渡沟道柱131中填充的材料不做限定。在一些实施例中，过渡沟道柱131中填充的材料可以是和存储沟道柱132中填充的功能层、沟道层一起填充。例如，过渡沟道柱131填充的功能层与存储沟道柱132填充的功能层是在同一道或同多道工艺步骤中完成，过渡沟道柱131 填充的沟道层与存储沟道柱132填充的沟道层也是在同一道或同多道工艺步骤中完成。在另一些实施例中，过渡沟道柱131中填充的材料可以是和存储沟道柱132中填充的材料不同，例如过渡沟道柱131中填充的材料可以是二氧化硅或其它绝缘材料，存储沟道柱132中填充材料为功能层、沟道层。
在本申请的另一些实施例中，沟道柱区A1中可包含存储沟道柱132，存储沟道柱132可以和栅极隔槽150相邻。
在一些实施例中，过渡沟道柱131位于存储沟道柱132和虚拟沟道柱141之间，过渡沟道柱131的关键尺寸大于存储沟道柱132的关键尺寸。过渡沟道柱131的关键尺寸可以是过渡沟道柱131的中心到过渡沟道柱131的边缘的距离，存储沟道柱132的关键尺寸可以是存储沟道柱132的中心到存储沟道柱132的边缘的距离。过渡沟道柱131具有较大的关键尺寸，可以提供较大的支撑面积，来提高对半导体器件的支撑作用。
虚拟沟道柱阵列140形成于堆叠层120中且位于虚拟沟道柱区A2，并包括在第一横向X 1与第二横向X 2上呈阵列排列的多个虚拟沟道柱141，具体地，该多个虚拟沟道柱141设置于堆叠层120所形成的阶梯区。在一些实施例中，虚拟沟道柱141起支撑作用，具体地，虚拟沟道柱141中填充的材料可以是二氧化硅或其它绝缘材料；
栅极隔槽150形成于堆叠层120中并沿第二横向X 2延伸，且设置于沟道柱阵列130与虚拟沟道柱阵列140之间，具体地，栅极隔槽150位于虚拟沟道柱区A2。
在一些实施例中，如图2所示，栅极隔槽150包括多个且沿第一横向X 1间隔排布，并由沟道柱阵列130向虚拟沟道柱阵列140的方向上的排布密度逐渐减小。
在一些实施例中，栅极隔槽150在第一横向X 1上的截面形状包括矩形、 梯形、半圆形其中至少之一，且该截面形状为靠近沟道柱区A1的形状，且栅极隔槽150面向虚拟沟道柱阵列140的一侧为一平面，在本实施例中，如图1所示，栅极隔槽150在第一横向X 1上的截面形状为矩形。
在一些实施例中，请继续参阅图1，如图1所示，半导体器件100还包括栅线狭缝160，栅线狭缝160沿垂直于衬底110的纵向贯穿堆叠层120，且沿第一横向X 1延伸，且栅极隔槽150与该栅线狭缝160的材料相同，栅极隔槽150与栅线狭缝160的示例性材料为多晶硅(Poly)以及钨(W)。
在本实施例中，因为栅极隔槽150将沟道柱阵列130与虚拟沟道柱阵列140隔开，且面向沟道柱阵列130与虚拟沟道柱阵列140的两侧是完整的平面，这样的设计方式可以较好地抵抗过渡沟道柱131功能层中的电荷对栅极隔槽150与虚拟沟道柱141的吸引力，从而避免了栅极隔槽150与虚拟沟道柱141的变形，不会使半导体器件100产生漏电流，提高了半导体器件100的性能。
在一些实施例中，为了防止过渡沟道柱131功能层中的电荷的吸引力的突变，在本实施例中，沟道柱阵列130中的过渡沟道柱131的排布密度沿所述第一横向X 1向虚拟沟道柱区A2逐渐减小，且过渡沟道柱131具有关键尺寸CD(Critical Dimension)，该关键尺寸CD为过渡沟道柱131的中心到所述过渡沟道柱131的边缘的距离，多个过渡沟道柱131的关键尺寸CD沿第一横向X 1向虚拟沟道柱区A2逐渐增大。
请参阅图3，图3是根据本公开实施例而成的第一实施例所提供的半导体器件100的制备方法的流程示意图。
如图3所示，并请参考图1以及图2中对构成半导体器件100的各部件的标号，该制备方法具体包括：
衬底提供步骤S101：提供衬底110；
堆叠层提供步骤S102：提供堆叠层120，堆叠层120设置于衬底110 上方且由绝缘层121和栅极层122交替层叠而成，堆叠层120沿平行于衬底110的第一横向X 1区分有过渡沟道柱区A1、以及位于过渡沟道柱区A1旁边的虚拟沟道柱区A2；
过渡沟道柱阵列提供步骤S103：提供过渡沟道柱阵列130，过渡沟道柱阵列130形成于堆叠层120中且位于过渡沟道柱区A1，并包括在第一横向X 1与在平行于衬底110且垂直于第一横向X 1的第二横向X 2上呈阵列排列的多个过渡沟道柱131；
虚拟沟道柱阵列提供步骤S104：提供虚拟沟道柱阵列140，虚拟沟道柱阵列140形成于堆叠层120中且位于虚拟沟道柱区A2，并包括在第一横向X 1与第二横向X 2上呈阵列排列的多个虚拟沟道柱141；
栅极隔槽提供步骤S105：提供栅极隔槽150，栅极隔槽150形成于堆叠层120中并沿第二横向X 2延伸，且设置于过渡沟道柱阵列130与虚拟沟道柱阵列140之间。
区别于现有技术，本公开实施例提供了一种半导体器件100，包括：衬底110，设置于衬底110上方且由绝缘层121和栅极层122交替层叠而成的堆叠层120，该堆叠层120沿平行于衬底110的第一横向X 1区分有沟道柱区A1、以及位于沟道柱区A1旁边的虚拟沟道柱区A2，形成于堆叠层120中且分别位于沟道柱区A1与虚拟沟道柱区A2的沟道柱阵列130以及虚拟沟道柱阵列140，且沟道柱阵列130以及虚拟沟道柱阵列140分别包括在第一横向X 1与在垂直于第一横向X 1的第二横向X 2上呈阵列排列的多个过渡沟道柱131以及多个虚拟沟道柱141，以及形成于堆叠层120中并沿第二横向X 2延伸，且设置于沟道柱阵列130与虚拟沟道柱阵列140之间的栅极隔槽150，本公开实施例提供的半导体器件100，通过在沟道柱阵列130与虚拟沟道柱阵列140之间设置栅极隔槽150，有效地避免了因过渡沟道柱131中的电荷对虚拟沟道柱141的吸引力，而使虚拟沟道柱141变形，导致半 导体器件100产生漏电流，对半导体器件100的性能造成影响的问题。
请参阅图4以及图5，图4是根据本公开实施例而成的第二实施例所提供的半导体器件200的俯视结构示意图，图5是根据本公开实施例而成的第二实施例所提供的半导体器件的正视结构示意图，该正视结构示意图为如图4所示的俯视结构示意图沿bb’的截面示意图，从图中可以很直观的看到根据本公开实施例而成的实施例的各组成部分，以及各组成部分的相对位置关系。
如图4所示，该第二实施例与第一实施例的结构大致相同，其中，第二实施例中的衬底210与第一实施例中的衬底110的作用以及设置位置相同；第二实施例中的堆叠层220(包括交替层叠设置的绝缘层221和栅极层222)与第一实施例中的堆叠层120(包括交替层叠设置的绝缘层121和栅极层122)的作用以及设置位置相同；第二实施例中的沟道柱阵列230(包括多个过渡沟道柱231和多个存储沟道柱232)与第一实施例中的沟道柱阵列130(包括多个过渡沟道柱131和多个存储沟道柱132)的作用以及设置位置相同；第二实施例中的虚拟沟道柱阵列240(包括多个虚拟沟道柱241)与第一实施例中的虚拟沟道柱阵列140(包括多个虚拟沟道柱141)的作用以及设置位置相同；第二实施例中的栅线狭缝260与第一实施例中的栅线狭缝160的作用以及设置位置相同；第二实施例中的介质层270与第一实施例中的介质层170的作用以及设置位置相同。其不同之处在于本实施例中的栅极隔槽250的设置方式与第一实施例中的栅极隔槽150的设置方式不同，在本实施例中，如图4所示，栅极隔槽250包括多个且沿第二横向X 2间隔排布而呈虚线形。
区别于现有技术，本公开实施例提供了一种半导体器件200，包括：衬底210，设置于衬底210上方且由绝缘层221和栅极层222交替层叠而成的堆叠层220，该堆叠层220沿平行于衬底210的第一横向X 1区分有沟道柱 区B1、以及位于沟道柱区B1旁边的虚拟沟道柱区B2，形成于堆叠层220中且分别位于沟道柱区B1与虚拟沟道柱区B2的沟道柱阵列230以及虚拟沟道柱阵列240，且沟道柱阵列230以及虚拟沟道柱阵列240分别包括在第一横向X 1与在垂直于第一横向X 1的第二横向X 2上呈阵列排列的多个过渡沟道柱231以及多个虚拟沟道柱241，以及形成于堆叠层220中并沿第二横向X 2延伸，且设置于沟道柱阵列230与虚拟沟道柱阵列240之间的栅极隔槽250，本公开实施例提供的半导体器件200，通过在沟道柱阵列230与虚拟沟道柱阵列240之间设置栅极隔槽250，有效地避免了因过渡沟道柱231中的电荷对虚拟沟道柱241的吸引力，而使虚拟沟道柱241变形，导致半导体器件200产生漏电流，对半导体器件200的性能造成影响的问题。
除上述实施例外，本公开实施例还可以有其他实施方式。凡采用等同替换或等效替换形成的技术方案，均落在本公开实施例要求的保护范围。
综上所述，虽然本公开实施例已将优选实施例揭露如上，但上述优选实施例并非用以限制本公开实施例，本领域的普通技术人员，在不脱离本公开实施例的精神和范围内，均可作各种更动与润饰，因此本公开实施例的保护范围以权利要求界定的范围为准。

Claims (11)

  1. 一种半导体器件，所述半导体器件包括：
    堆叠层，由绝缘层和栅极层交替层叠而成，所述堆叠层沿垂直于所述堆叠方向的第一横向及垂直于所述堆叠方向的第二横向延伸，所述第一横向和所述第二横向垂直；
    沟道柱阵列，形成于所述堆叠层，并包括在所述第一横向与所述第二横向上呈阵列排列的多个沟道柱；
    虚拟沟道柱阵列，形成于所述堆叠层中，并包括在所述第一横向与所述第二横向上呈阵列排列的多个虚拟沟道柱；
    栅极隔槽，形成于所述堆叠层中并沿所述第二横向延伸，且设置于所述沟道柱阵列与所述虚拟沟道柱阵列之间。
  2. 根据权利要求1所述的半导体器件，其中，所述沟道柱阵列包括沿所述第一横向排布的过渡沟道柱和存储沟道柱，所述过渡沟道柱位于所述存储沟道柱和所述虚拟沟道柱之间，所述过渡沟道柱的关键尺寸大于所述存储沟道柱的关键尺寸。
  3. 根据权利要求1所述的半导体器件，其中，所述虚拟沟道柱设置于所述堆叠层所形成的阶梯区。
  4. 根据权利要求1所述的半导体器件，其中，所述栅极隔槽包括多个且沿所述第一横向间隔排布，所述栅极隔槽的排布密度由所述沟道柱阵列向所述虚拟沟道柱阵列的方向上逐渐减小。
  5. 根据权利要求1所述的半导体器件，其中，所述栅极隔槽包括多个且沿所述第二横向间隔排布而呈虚线形。
  6. 根据权利要求1所述的半导体器件，其中，所述半导体器件还包括栅线狭缝，所述栅线狭缝沿垂直于所述衬底的纵向贯穿所述堆叠层，且沿所述第一横向延伸。
  7. 根据权利要求6所述的半导体器件，其中，所述栅极隔槽与所述栅线狭缝的材料相同。
  8. 根据权利要求1所述的半导体器件，其中，所述栅极隔槽在所述第一横向上的截面形状包括矩形、梯形、半圆形其中至少之一，且所述栅极隔槽面向所述虚拟沟道柱阵列的一侧为一平面。
  9. 根据权利要求2所述的半导体器件，其中，所述沟道柱阵列中的所述过渡沟道柱的排布密度沿所述第一横向向所述虚拟沟道柱阵列逐渐减小。
  10. 根据权利要求9所述的半导体器件，其中，所述过渡沟道柱具有关键尺寸，所述关键尺寸为所述过渡沟道柱的中心到所述过渡沟道柱的边缘的距离，所述多个过渡沟道柱的所述关键尺寸沿所述第一横向向所述虚拟沟道柱阵列逐渐增大。
  11. 一种半导体器件的制备方法，所述制备方法包括：
    提供衬底；
    形成堆叠层，所述堆叠层设置于所述衬底上方且由绝缘层和栅极层交替层叠而成，所述堆叠层沿垂直于所述堆叠方向的第一横向及垂直于所述堆叠方向的第二横向延伸，所述第一横向和所述第二横向垂直；
    形成沟道柱阵列，所述沟道柱阵列形成于所述堆叠层中，并包括在所述第一横向与所述第二横向上呈阵列排列的多个沟道柱；
    形成虚拟沟道柱阵列，所述虚拟沟道柱阵列形成于所述堆叠层中，并包括在所述第一横向与所述第二横向上呈阵列排列的多个虚拟沟道柱；
    形成栅极隔槽，所述栅极隔槽形成于所述堆叠层中并沿所述第二横向延伸，且设置于所述沟道柱阵列与所述虚拟沟道柱阵列之间。
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