CN114730766A - 半导体器件及其制备方法 - Google Patents

半导体器件及其制备方法 Download PDF

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Publication number
CN114730766A
CN114730766A CN202180006424.7A CN202180006424A CN114730766A CN 114730766 A CN114730766 A CN 114730766A CN 202180006424 A CN202180006424 A CN 202180006424A CN 114730766 A CN114730766 A CN 114730766A
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China
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array
lateral direction
channel
semiconductor device
channel pillar
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CN202180006424.7A
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English (en)
Inventor
刘思敏
徐伟
许波
郭亚丽
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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Publication of CN114730766A publication Critical patent/CN114730766A/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region

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  • Semiconductor Memories (AREA)
  • Element Separation (AREA)

Abstract

本公开实施例提供了一种半导体器件，包括：衬底；设置于衬底上方且由绝缘层和栅极层交替层叠的堆叠层，堆叠层沿平行于衬底的第一横向区分有过渡沟道柱区、以及位于过渡沟道柱区旁边的虚拟沟道柱区；形成于堆叠层中且分别位于过渡沟道柱区与虚拟沟道柱区的过渡沟道柱阵列以及虚拟沟道柱阵列，过渡沟道柱阵列以及虚拟沟道柱阵列分别包括在第一横向与在垂直于第一横向的第二横向上呈阵列排列的多个过渡沟道柱以及多个虚拟沟道柱；形成于堆叠层中并沿第二横向延伸，且设置于过渡沟道柱阵列与虚拟沟道柱阵列之间的栅极隔槽。

Description

PCT国内申请，说明书已公开。

Claims (11)

  1. PCT国内申请，权利要求书已公开。
CN202180006424.7A 2020-11-18 2021-11-16 半导体器件及其制备方法 Pending CN114730766A (zh)

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Application Number Priority Date Filing Date Title
CN202011294003.2 2020-11-18
CN202011294003.2A CN112420724B (zh) 2020-11-18 2020-11-18 半导体器件及其制备方法
PCT/CN2021/130905 WO2022105747A1 (zh) 2020-11-18 2021-11-16 半导体器件及其制备方法

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CN114730766A true CN114730766A (zh) 2022-07-08

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CN112420724B (zh) * 2020-11-18 2021-09-28 长江存储科技有限责任公司 半导体器件及其制备方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9478561B2 (en) * 2015-01-30 2016-10-25 Samsung Electronics Co., Ltd. Semiconductor memory device and method of fabricating the same
KR102307057B1 (ko) * 2017-07-27 2021-10-01 삼성전자주식회사 수직형 메모리 장치
US10600800B2 (en) * 2018-06-27 2020-03-24 Sandisk Technologies Llc Three-dimensional memory device containing multilevel drain select gate isolation and methods of making the same
CN108878437B (zh) * 2018-07-02 2020-04-21 长江存储科技有限责任公司 形成三维存储器的方法以及三维存储器
US11075283B2 (en) * 2018-10-30 2021-07-27 Taiwan Semiconductor Manufacturing Co., Ltd. Dielectric constant reduction of gate spacer
KR102546653B1 (ko) * 2018-12-11 2023-06-22 삼성전자주식회사 콘택 플러그를 갖는 반도체 소자
CN112802854B (zh) * 2019-03-27 2021-11-05 长江存储科技有限责任公司 3d nand存储器及其形成方法
CN110137177B (zh) * 2019-06-18 2021-07-20 长江存储科技有限责任公司 存储器及其形成方法
CN110197830B (zh) * 2019-06-28 2021-06-08 长江存储科技有限责任公司 3d nand存储器及其形成方法
CN110676259B (zh) * 2019-08-22 2022-04-01 长江存储科技有限责任公司 三维存储结构及其制作方法
CN110808252B (zh) * 2019-10-10 2023-01-10 长江存储科技有限责任公司 3d存储器件及其制造方法
CN111146209A (zh) * 2019-12-25 2020-05-12 长江存储科技有限责任公司 3d存储器件及其制造方法
CN111627918B (zh) * 2020-04-30 2021-05-07 长江存储科技有限责任公司 一种3d nand存储器及其制造方法
CN112420724B (zh) * 2020-11-18 2021-09-28 长江存储科技有限责任公司 半导体器件及其制备方法

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CN112420724B (zh) 2021-09-28
WO2022105747A1 (zh) 2022-05-27
CN112420724A (zh) 2021-02-26
US20230125309A1 (en) 2023-04-27

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