WO2022042100A1 - 存储器的调节方法、调节系统以及半导体器件 - Google Patents

存储器的调节方法、调节系统以及半导体器件 Download PDF

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Publication number
WO2022042100A1
WO2022042100A1 PCT/CN2021/106093 CN2021106093W WO2022042100A1 WO 2022042100 A1 WO2022042100 A1 WO 2022042100A1 CN 2021106093 W CN2021106093 W CN 2021106093W WO 2022042100 A1 WO2022042100 A1 WO 2022042100A1
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memory
transistor
temperature
gate voltage
mapping relationship
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PCT/CN2021/106093
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English (en)
French (fr)
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寗树梁
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长鑫存储技术有限公司
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Priority to US17/452,339 priority Critical patent/US11886721B2/en
Publication of WO2022042100A1 publication Critical patent/WO2022042100A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629—Configuration or reconfiguration of storage systems
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/021—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in voltage or current generators
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0653—Monitoring storage devices or systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects

Definitions

  • the present application relates to the field of semiconductors, and in particular, to a memory regulation method, regulation system and semiconductor device.
  • memory is one of the key devices that determines system performance. It is like a temporary warehouse, responsible for the transfer and temporary storage of data.
  • the key performance indicator of the memory is the time for the memory to read/write data.
  • the data writing of the memory does not write the storage capacitor immediately, because the charging of the gate transistor and the capacitor must take a period of time, that is, the data writing of the memory requires a certain amount of time. In order to ensure the accuracy of data writing, sufficient data writing time will be reserved.
  • the actual data writing time of the memory will be affected by the temperature, which will cause the actual data writing time of the memory to be longer than the sufficient data writing time reserved, so that the data is not completely written to the storage capacitor.
  • Embodiments of the present application provide a memory adjustment method, an adjustment system, and a semiconductor device, by adjusting the actual data writing time of the memory to ensure that the actual data writing time is within a preset time, thereby ensuring that data is completely written to the storage capacitor .
  • the memory includes a transistor, a gate of the transistor is electrically connected to a word line of the memory, and one end of a source/drain of the transistor is connected to a bit line of the memory.
  • the other end is electrically connected to the storage capacitor of the memory, including: obtaining the mapping relationship between the temperature of the transistor, the gate voltage of the transistor and the actual data writing time of the memory; obtaining the current temperature of the transistor; adjusting the gate based on the current temperature and the mapping relationship voltage, so that the actual data writing time corresponding to the adjusted gate voltage is within the preset writing time.
  • the mapping relationship between the temperature of the transistor, the gate voltage of the transistor and the actual data writing time is first obtained, and the actual data writing time is obtained according to the current temperature of the transistor.
  • the input time is adjusted by adjusting the gate voltage of the transistor to adjust the actual data writing time of the transistor at the current temperature, so that the adjusted data writing time is within the preset time to ensure that the data is written to the storage capacitor.
  • An embodiment of the present application further provides a memory adjustment system, including: a first acquisition module, used to acquire the mapping relationship between the temperature of the transistor, the gate voltage of the transistor, and the actual data writing time of the memory; the second acquisition module, used It is used to obtain the current temperature of the transistor; the processing module is used to obtain the adjustment method of the gate voltage based on the current temperature and the mapping relationship; the adjustment module is used to adjust the gate voltage based on the adjustment method, so that the adjusted gate voltage corresponds to the memory.
  • the actual data writing time is within the preset writing time.
  • Embodiments of the present application further provide a semiconductor device, including a memory, and the above-mentioned memory adjustment system.
  • the memory adjustment system adjusts the gate voltage of the transistor based on the temperature of the transistor in the memory, so that the adjusted gate voltage corresponds to the actual data of the memory.
  • the write time is within the preset write time.
  • the first acquisition module obtains the mapping relationship between the temperature of the transistor, the gate voltage of the transistor and the actual data writing time of the memory
  • the second obtaining module obtains the actual data writing time of the memory according to the current temperature of the transistor, obtains the gate voltage adjustment mode of the transistor through the processing module, and then adjusts the gate voltage of the transistor through the adjustment module to adjust the actual data writing of the memory at the current temperature of the transistor input time, so that the data writing time of the adjusted memory is within the preset time to ensure that the data is completely written to the storage capacitor.
  • FIG. 1 is a schematic diagram of a connection structure of a memory transistor according to a first embodiment of the present application
  • FIG. 2 is a schematic structural diagram of a write sequence of a memory provided by the first embodiment of the present application
  • FIG. 3 is a schematic flowchart of a method for adjusting a memory provided by the first embodiment of the present application
  • FIG. 4 is a schematic flowchart of a method for adjusting a memory according to a second embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a memory adjustment system provided by a third embodiment of the present application.
  • the actual data writing time of the memory will be affected by temperature, which will cause the actual data writing time of the memory to be longer than the sufficient data writing time reserved, so that the data is not completely written to the storage capacitor.
  • the first embodiment of the present application provides a method for adjusting a memory, including: obtaining a mapping relationship between the temperature of the transistor, the gate voltage of the transistor, and the actual data writing time of the memory; obtaining the current temperature of the transistor; The gate voltage is adjusted by the current temperature and the mapping relationship, so that the actual data writing time of the memory corresponding to the adjusted gate voltage is within the preset writing time.
  • FIG. 3 is a schematic flowchart corresponding to a method for adjusting a memory provided by an embodiment of the present application, and the method for adjusting a memory in this embodiment is specifically described below.
  • FIG. 1 is a schematic diagram of the structure of a single storage unit in the memory.
  • the selection of the target storage capacitor is realized by a bit line structure (Bit Line, BL) and a word line structure (Word Line, WL)
  • the word line structure is connected to the gate of the transistor, the bit line structure is connected to one end of the source/drain of the transistor, and the other end of the source/drain of the transistor is connected to the storage capacitor.
  • the transistor functions as a switch.
  • the gate voltage input to the transistor in the word line structure is greater than the threshold voltage of the transistor, the transistor is turned on, and an electrical connection is formed between the storage capacitor and the bit line structure.
  • the storage capacitor When the voltage of the storage capacitor is lower than the voltage of the bit line structure, the storage capacitor is discharged, that is, the process of data reading; when the voltage of the storage capacitor is greater than the voltage of the bit line structure, the storage capacitor is charged, that is, the process of data writing.
  • the data read/write of the memory is realized by charging/discharging the storage capacitor in the memory.
  • charging requires a certain amount of time to ensure the execution of the charging process, that is, a certain amount of time needs to be reserved for writing data in the memory to ensure complete writing of the data.
  • FIG. 2 is a timing diagram of data writing in the memory. It should be noted that FIG. 2 is only a schematic diagram of the writing timing of a section of storage area, and does not constitute a limitation to the embodiments of the present application. The technical personnel understand the realization purpose of this scheme.
  • the command to execute data writing is received at time T0; since the storage contains many storage capacitors, it is necessary to find the target storage capacitor before executing data writing, that is, T1 ⁇ T9 are the addressing time; find the target storage capacitor
  • T9 ⁇ T11 is the execution of the write process
  • T11 ⁇ T23 is the time to ensure the complete execution of the write, that is, the write recovery delay (Write Recovery Time, tWR); after T23 and precharge
  • T9 to T23 are the data write time of the memory.
  • a preset write time is set for the memory for data writing of the memory.
  • the actual data writing time of the memory will be affected due to the influence of factors such as the temperature of the transistor and the gate voltage of the transistor.
  • the temperature of the transistor refers to the temperature of the transistor itself.
  • the adjustment method of the memory includes the following steps:
  • the embodiments of the present application mainly compensate the influence of temperature on the actual data writing time of the memory by regulating the gate voltage of the transistor, which does not mean that other conditions do not affect the actual data writing time of the memory.
  • other conditions affecting the actual data writing time of the memory are kept unchanged by default.
  • Step 101 Obtain a first mapping relationship between temperature and actual data writing time.
  • the contact resistance R of the transistor increases, and the decrease in the temperature of the transistor increases the threshold voltage Vth of the transistor. Accordingly, an increase in the temperature of the transistor causes the contact resistance R of the transistor to decrease, and an increase in the temperature of the transistor causes the threshold voltage Vth of the transistor to decrease.
  • the electrical connection between the bit line structure and the storage capacitor is formed when the transistor is turned on.
  • the transistor is turned on, that is, the gate voltage Vgs of the transistor is greater than Vth, and the difference between Vgs and Vth is Vgs-Vth.
  • Vgs-Vth the gate voltage of the transistor
  • Ids the source-drain current of the transistor
  • the threshold voltage Vth increases, the source-drain current Ids of the transistor decreases, and the actual data writing time of the memory increases; when the temperature of the transistor increases, the threshold voltage Vth decreases, and the source-drain current Ids of the transistor increases. larger, the actual data writing time of the memory becomes shorter.
  • the method for obtaining the first mapping relationship includes: keeping the gate voltage of the transistor unchanged, changing the temperature of the transistor, and obtaining a first mapping relationship between the temperature of the transistor and the actual data writing time of the memory, where the first mapping relationship is: Two-dimensional mapping relationship, the independent variable is the temperature of the transistor, and the dependent variable is the actual data writing time of the memory. Then, change the gate voltage of the transistor, keep the gate voltage of the transistor unchanged after changing the gate voltage of the transistor, change the temperature of the transistor, and obtain the first mapping relationship between the temperature of the transistor and the actual data writing time of the memory, thereby obtaining different gate voltages A first mapping relationship in which the actual data writing time of the lower memory varies with the temperature of the transistor.
  • Step 102 obtaining a second mapping relationship between the gate voltage and the actual data writing time.
  • the gate voltage Vgs of the transistor when the transistor is turned on, the gate voltage Vgs of the transistor is increased to increase Vgs-Vth, so that the source-drain current Ids of the transistor increases, thereby reducing the data writing time of the storage capacitor;
  • the gate voltage Vgs of the small transistor is reduced to reduce Vgs-Vth, so that the source-drain current Ids of the transistor is reduced, so that the data writing time of the storage capacitor becomes longer.
  • the method for obtaining the second mapping relationship includes: keeping the temperature of the transistor unchanged, changing the gate voltage of the transistor, and obtaining a second mapping relationship between the gate voltage of the transistor and the actual data writing time of the memory, wherein the second mapping relationship is a two-dimensional mapping relationship, the independent variable is the gate voltage of the transistor, and the dependent variable is the actual data writing time of the memory. Then, change the temperature of the transistor, keep the temperature of the transistor unchanged after changing the temperature of the transistor, change the gate voltage of the transistor, and obtain the second mapping relationship between the gate voltage of the transistor and the actual data writing time of the memory, so as to obtain the memory at different temperatures.
  • a second mapping relationship in which the actual data writing time varies with the gate voltage of the transistor.
  • Step 103 Obtain the mapping relationship between temperature, gate voltage and actual data writing time.
  • mapping relationship between the temperature of the transistor, the gate voltage of the transistor, and the actual data writing time of the memory is obtained, and the mapping relationship is a three-dimensional mapping relationship.
  • steps 101, 102 and 103 provide a specific method for obtaining the mapping relationship between the temperature of the transistor, the gate voltage of the transistor, and the actual data writing time of the memory, and the data corresponds one-to-one. , to ensure the accuracy of the regulation of the actual data writing time of the memory.
  • the above-mentioned mapping relationship can be obtained by directly regulating the relationship between the three.
  • Step 104 obtaining the current temperature of the transistor.
  • the current temperature of the transistor is acquired through a temperature sensor provided in the memory.
  • the current temperature of the transistor is directly obtained through the temperature sensor, and the obtained temperature is accurate and the error is small.
  • the current temperature of the transistor can also be obtained by obtaining the ambient temperature in which the memory operates.
  • Step 105 Obtain a preset temperature and a temperature difference between the current temperature and the preset temperature.
  • Step 106 adjusting the gate voltage according to the temperature difference and the mapping relationship.
  • the method of adjusting the gate voltage according to the temperature difference value and the mapping relationship includes the following steps:
  • Step 116 Obtain the time difference between the actual data writing time corresponding to the current temperature and the preset writing time.
  • the preset temperature of the transistor, the preset gate voltage of the transistor, and the preset writing time of the transistor are set.
  • the preset temperature, the preset gate voltage and the preset writing time can also satisfy The above mapping relationship.
  • the time difference between the actual data writing time of the memory and the preset writing time under the current gate voltage of the transistor is obtained. That is, the change in the actual data writing time of the memory caused by the temperature change is obtained.
  • Step 126 Adjust the gate voltage according to the mapping relationship and the time difference value to offset the time difference value.
  • the actual data writing time of the memory changes, but this change is not conducive to the use of the memory, so it is necessary to regulate the gate voltage of the transistor to stabilize the actual data writing time of the memory. That is, by adjusting the gate voltage to offset the time difference, the actual data writing time of the memory is stabilized.
  • the temperature will affect the actual data writing time of the memory, first obtain the mapping relationship between the temperature of the transistor, the gate voltage of the transistor and the actual data writing time of the memory, and obtain the data according to the current temperature of the transistor.
  • the actual data writing time of the memory is adjusted by adjusting the gate voltage of the transistor to adjust the actual data writing time of the transistor at the current temperature, so that the adjusted data writing time is within the preset time to ensure that the data is written to the storage capacitor.
  • the second embodiment of the present application relates to a method for adjusting a memory.
  • the difference from the first embodiment is that in this embodiment, before adjusting the gate voltage according to the temperature difference, it is judged whether the temperature difference exceeds a preset range.
  • the actual data writing time of the memory is adjusted only when the value exceeds the preset range, which reduces unnecessary adjustment operations and saves adjustment costs.
  • FIG. 4 is a schematic flowchart corresponding to a method for adjusting a memory provided by an embodiment of the present application, and the method for adjusting a memory in this embodiment is specifically described below.
  • the adjustment method of the memory includes the following steps:
  • Step 201 Obtain a first mapping relationship between temperature and actual data writing time.
  • Step 202 obtaining a second mapping relationship between the gate voltage and the actual data writing time.
  • Step 203 Obtain the mapping relationship between temperature, gate voltage and actual writing time.
  • Step 204 obtaining the current temperature of the transistor.
  • Step 205 Obtain a preset temperature and a temperature difference between the current temperature and the preset temperature.
  • steps 201 to 205 are the same as steps 101 to 105 in the first embodiment, and details are not repeated in this embodiment.
  • Step 206 whether the temperature difference exceeds a preset range.
  • This embodiment is also used to determine whether the temperature difference between the current temperature of the transistor and the preset temperature exceeds a preset range before adjusting the gate voltage of the transistor.
  • step 207 the gate voltage of the transistor is adjusted according to the temperature difference and the mapping relationship, that is, step 207 is performed.
  • Step 207 Adjust the gate voltage according to the temperature difference and the mapping relationship.
  • the adjustment method is to increase the gate voltage; if the current temperature is less than the preset temperature and exceeds the preset range, and the N-type transistor of the transistor is adjusted The method is to reduce the gate voltage; if the current temperature is greater than the preset temperature and exceeds the preset range, and the transistor is a P-type transistor, the adjustment method is to reduce the gate voltage; if the current temperature is less than the preset temperature and exceeds the preset range, and the transistor P type transistor, the adjustment method is to increase the gate voltage.
  • this embodiment further divides the preset range, the preset range includes at least a first preset range and a second preset range, and the second preset range is larger than the first preset range.
  • the temperature difference exceeds the first preset range and does not exceed the second preset range, increase or decrease the gate voltage, and the amount of increase or decrease is the first preset value; if the temperature difference exceeds the second preset range , increase or decrease the gate voltage, the amount of increase or decrease is a second preset value, the second preset value is greater than the first preset value, and the first preset value and the second preset value are fixed values .
  • the preset range is divided into at least three sub-preset ranges, and by dividing into more sub-preset ranges, the accuracy of adjusting the actual data writing time to the memory is further improved.
  • the temperature will affect the actual data writing time of the memory, first obtain the mapping relationship between the temperature of the transistor, the gate voltage of the transistor and the actual data writing time of the memory, and obtain the data according to the current temperature of the transistor.
  • the actual data writing time of the memory is adjusted by adjusting the gate voltage of the transistor to adjust the actual data writing time of the transistor at the current temperature, so that the adjusted data writing time is within the preset time to ensure that the data is written to the storage capacitor.
  • the third embodiment of the present application relates to a memory adjustment system.
  • the memory adjustment system 300 includes:
  • the first acquisition module 301 is configured to acquire the mapping relationship between the temperature of the transistor, the gate voltage of the transistor, and the actual data writing time of the memory, wherein the mapping relationship is a three-dimensional mapping relationship.
  • the second obtaining module 302 is configured to obtain the current temperature of the transistor.
  • the current temperature of the transistor is acquired through a temperature sensor provided in the memory.
  • the current temperature of the transistor is directly obtained through the temperature sensor, and the obtained temperature is accurate and the error is small.
  • the current temperature of the transistor can also be obtained by obtaining the ambient temperature in which the memory operates.
  • the processing module 303 is configured to obtain the adjustment mode of the gate voltage based on the current temperature and the mapping relationship.
  • the processing module includes: a comparison unit 313 and a processing unit 333 .
  • the comparison unit 313 is configured to acquire the preset temperature corresponding to the preset writing time, and acquire the temperature difference between the current temperature and the preset temperature.
  • the processing unit 333 is configured to obtain the adjustment mode of the gate voltage according to the temperature difference value and the mapping relationship.
  • the preset temperature of the transistor, the preset gate voltage of the transistor, and the preset writing time of the transistor are set, wherein the preset temperature, the preset gate voltage and the preset writing time are set.
  • the above mapping relationship can also be satisfied.
  • the processing unit 333 obtains the time difference between the actual data writing time of the memory and the preset writing time under the current gate voltage of the transistor according to the temperature difference between the current temperature and the preset temperature, that is, obtains the time difference of the memory caused by the temperature change. Variation in actual data write time.
  • the gate voltage of the transistor needs to be regulated by the processing unit 333 to stabilize the actual data writing time of the memory . That is, according to the mapping relationship and the time difference, the gate voltage is adjusted to offset the time difference, thereby stabilizing the actual data writing time of the memory.
  • the adjustment module 304 is configured to adjust the gate voltage based on the adjustment method, so that the actual data writing time of the memory corresponding to the adjusted gate voltage is within the preset writing time.
  • the first obtaining module 301 includes: a first obtaining sub-module 311 , a second obtaining sub-module 321 and a third obtaining sub-module 331 .
  • the first obtaining sub-module 311 is configured to obtain a first mapping relationship between the temperature of the transistor and the actual data writing time of the memory. Specifically, keeping the gate voltage of the transistor unchanged, a first mapping relationship between the temperature of the transistor and the actual data writing time of the memory is obtained, where the independent variable is the temperature of the transistor, the dependent variable is the actual data writing time of the memory, and the first The mapping relationship is a two-dimensional mapping relationship.
  • the second obtaining sub-module 321 is configured to obtain a second mapping relationship between the gate voltage of the transistor and the actual data writing time of the memory. Specifically, keeping the temperature of the transistor unchanged, a second mapping relationship between the gate voltage of the transistor and the actual data writing time of the memory is obtained, where the independent variable is the gate voltage of the transistor, the dependent variable is the actual data writing time of the memory, and the first The two-mapping relationship is a two-dimensional mapping relationship.
  • the third obtaining sub-module 331 obtains, based on the first mapping relationship and the second mapping relationship, the mapping relationship between the temperature of the transistor, the gate voltage of the transistor, and the actual data writing time of the memory.
  • the processing module 303 further includes: a judging unit 323 for judging whether the temperature difference exceeds a preset range, and when the temperature difference exceeds the preset range, the processing unit 333 is used for obtaining according to the temperature difference and the mapping relationship The way the gate voltage is adjusted.
  • the judging unit 323 includes at least a first judging sub-unit 305 and a second judging sub-unit 306 .
  • the judging unit 323 includes at least a first judging sub-unit 305 and a second judging sub-unit 306 .
  • the first judging subunit 305 is used for judging whether the temperature difference exceeds the first preset range.
  • the second determination subunit 306 is configured to determine whether the temperature difference exceeds a second preset range, and the second preset range is greater than the first preset range.
  • the judging unit includes at least three judging sub-units.
  • the first acquisition module obtains the mapping relationship between the temperature of the transistor, the gate voltage of the transistor and the actual data writing time of the memory
  • the second obtaining module obtains the actual data writing time of the memory according to the current temperature of the transistor, obtains the gate voltage adjustment mode of the transistor through the processing module, and then adjusts the gate voltage of the transistor through the adjustment module to adjust the actual data writing of the memory at the current temperature of the transistor input time, so that the adjusted data writing time is within the preset time to ensure that the data is completely written to the storage capacitor.
  • a logical unit may be a physical unit, a part of a physical unit, or multiple physical units.
  • a composite implementation of the unit in order to highlight the innovative part of the present application, this embodiment does not introduce units that are not closely related to solving the technical problem raised by the present application, but this does not mean that there are no other units in this embodiment.
  • first embodiment and the second embodiment correspond to this embodiment, this embodiment can be implemented in cooperation with the first embodiment and the second embodiment.
  • the relevant technical details mentioned in the first embodiment and the second embodiment are still valid in this embodiment, and the technical effects that can be achieved in the first embodiment and the second embodiment can also be realized in this embodiment. , in order to reduce repetition, no further details are given here.
  • the relevant technical details mentioned in this embodiment can also be applied to the first embodiment and the second embodiment.
  • the fourth embodiment of the present application relates to a semiconductor device.
  • a semiconductor device including: a memory, and the memory adjustment system provided in the third embodiment, the memory adjustment system adjusts the gate voltage of the transistor based on the temperature of the transistor in the memory, so that the adjusted gate voltage corresponds to the actual data writing time of the memory within the preset write time.
  • first embodiment and the second embodiment correspond to this embodiment, this embodiment can be implemented in cooperation with the first embodiment and the second embodiment.
  • the relevant technical details mentioned in the first embodiment and the second embodiment are still valid in this embodiment, and the technical effects that can be achieved in the first embodiment and the second embodiment can also be realized in this embodiment. , in order to reduce repetition, no further description will be given here.
  • the related technical details mentioned in this embodiment can also be applied to the first embodiment and the second embodiment.
  • the method for adjusting the memory includes: acquiring a mapping relationship between the temperature of the transistor, the gate voltage of the transistor, and the actual data writing time; acquiring the current temperature of the transistor; and adjusting the gate voltage based on the current temperature and the mapping relationship to make The actual data writing time corresponding to the adjusted gate voltage is within the preset writing time.
  • the gate voltage of the transistor is used to adjust the actual data writing time of the transistor at the current temperature, so that the adjusted data writing time is within the preset time to ensure that the data is completely written to the storage capacitor.

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Abstract

本申请实施例提供一种存储器的调节方法、调节系统以及半导体器件，其中，存储器的调节方法包括：获取晶体管的温度、晶体管的栅电压以及存储器的实际数据写入时间的映射关系；获取晶体管的当前温度；基于当前温度以及映射关系调整栅电压，以使调整后的栅电压对应的实际数据写入时间在预设写入时间内。

Description

存储器的调节方法、调节系统以及半导体器件
相关申请的交叉引用
本申请要求在2020年08月27日提交中国专利局、申请号为202010879440.4、申请名称为“存储器的调节方法、调节系统以及半导体器件”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体领域，特别涉及一种存储器的调节方法、调节系统以及半导体器件。
背景技术
存储器作为计算机必不可少的三大件之一，存储器是决定系统性能的关键设备之一，它就像一个临时的仓库，负责数据的中转、暂存。
存储器的关键性能指标即存储器读/写数据的时间，存储器的数据写入并不是即时地写入存储电容，因为选通三极管与电容的充电必须要有一段时间，即存储器的数据写入需要一定的写入周期，为了保证数据的写入的准确性，都会预留出足够的数据写入时间。
然而，存储器的实际数据写入时间会受到温度的影响，会导致存储器的实际数据写入时间大于预留出足够的数据写入时间，从而导致数据并未完全写入到存储电容。
发明内容
本申请实施例提供一种存储器的调节方法、调节系统以及半导体器件，通过调节存储器的实际数据写入时间，以保证实际数据写入时间在预设时间内，从而保证数据完全写入到存储电容。
为解决上述技术问题，本申请的实施例提供了一种存储器的调节方法，存 储器包括晶体管，晶体管的栅极与存储器的字线电连接，晶体管的源极/漏极的一端与存储器的位线电连接，另一端与存储器的存储电容电连接，包括：获取晶体管的温度、晶体管的栅电压以及存储器的实际数据写入时间的映射关系；获取晶体管的当前温度；基于当前温度以及映射关系调整栅电压，以使调整后的栅电压对应的实际数据写入时间在预设写入时间内。
与现有技术相比，由于温度会影响存储器的实际数据写入时间，首先获取晶体管的温度、晶体管的栅电压以及实际数据写入时间之间的映射关系，根据晶体管的当前温度获取实际数据写入时间，通过调整晶体管的栅电压以调整晶体管在当前温度下的实际数据写入时间，以使调整后的数据写入时间在预设时间内，保证数据完成写入到存储电容。
本申请实施例还提供了一种存储器的调节系统，包括：第一获取模块，用于获取晶体管的温度、晶体管的栅电压以及存储器的实际数据写入时间的映射关系；第二获取模块，用于获取晶体管的当前温度；处理模块，用于基于当前温度以及映射关系，获取栅电压的调节方式；调节模块，用于基于调节方式，调整栅电压，以使调整后的栅电压对应的存储器的实际数据写入时间在预设写入时间内。
本申请实施例还提供了一种半导体器件，包括存储器，以及上述存储器调节系统，存储器调节系统基于存储器中晶体管的温度，调节晶体管的栅电压，以使调整后的栅电压对应的存储器的实际数据写入时间在预设写入时间内。
相比于现有技术而言，由于温度会影响存储器的实际数据写入时间，通过第一获取模块获取晶体管的温度、晶体管的栅电压以及存储器的实际数据写入时间之间的映射关系，通过第二获取模块根据晶体管的当前温度获取存储器的实际数据写入时间，通过处理模块获取晶体管的栅电压调节方式，然后通过调节模块调整晶体管的栅电压以调整晶体管在当前温度下存储器的实际数据写入时间，以使调整后的存储器的数据写入时间在预设时间内，保证数据完成写入到存储电容。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，除非有特别申明，附图中的图不构成比例限制。
图1为本申请第一实施例提供的存储器晶体管的连接结构示意图；
图2为本申请第一实施例提供的存储器的写入时序的结构示意图；
图3为本申请第一实施例提供的存储器的调节方法的流程示意图；
图4为本申请第二实施例提供的存储器的调节方法的流程示意图；
图5为本申请第三实施例提供的存储器的调节系统的结构示意图。
具体实施方式
存储器的实际数据写入时间会受到温度的影响，会导致存储器的实际数据写入时间大于预留出足够的数据写入时间，从而导致数据并未完全写入到存储电容。
为解决上述问题，本申请第一实施例提供了一种存储器的调节方法，包括：获取晶体管的温度、晶体管的栅电压以及存储器的实际数据写入时间的映射关系；获取晶体管的当前温度；基于当前温度以及映射关系调整栅电压，以使调整后的栅电压对应的存储器的实际数据写入时间在预设写入时间内。
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。以下各个实施例的划分是为了描述方便，不应对本申请的具体实现方式构成任何限定，各个实施例在不矛盾的前提下可以相互结合，相互引用。
图3为本申请实施例提供的存储器的调节方法对应的流程示意图，下面对本实施例的存储器的调节方法进行具体说明。
参考图1，图1为存储器中单个存储单元的结构示意图，存储器中具有多 个存储电容，选取目标存储电容是通过位线结构(Bit Line，BL)以及字线结构(Word Line，WL)实现的，字线结构连接晶体管的栅极，位线结构连接晶体管的源极/漏极的其中一端，晶体管的源极/漏极的另一端连接存储电容。以此种方式形成的连接结构中，晶体管起到开关的作用。当字线结构中输入到晶体管的栅电压大于晶体管的阈值电压时，晶体管导通，存储电容与位线结构之间形成电连接。当存储电容的电压小于位线结构的电压，存储电容放电，即数据读取的过程；当存储电容的电压大于位线结构的电压，存储电容充电，即数据写入的过程。由上述内容可知存储器的数据读取/写入是通过对存储器中对存储电容的充/放电实现的。而充电需要一定的时间来保证充电过程的执行，即存储器中对数据的写入需要预留出一定的时间来保证数据的完全写入。
参考图2，图2为存储器中进行数据写入的时序图，需要说明的是，图2仅为一段存储区写入时序的示意图，并不构成对本申请实施例的限定，目的在于使本领域技术人员了解本方案的实现目的。如图所示，T0时刻接收到执行数据写入的命令；由于存储中包含很多存储电容，因此在执行数据写入前需要找到目标存储电容，即T1～T9为寻址时间；寻找到目标存储电容后即开始执行写入操作，T9～T11为写入过程的执行；T11～T23为保证写入的完整执行空余的时间，即写回延迟(Write Recovery Time，tWR)；T23之后与预充电过程，数据写入后，需要对位线结构进行预充电，才能使得存储器能够正常执行下一个操作命令，其中T9～T23都为存储器的数据写入时间。
在存储器工作之前，会对存储器设定一个预设写入时间，用于存储器的数据写入。存储器在实际工作过程中，由于晶体管的温度、晶体管的栅电压等因素的影响，会影响存储器的实际数据写入时间。当存储器的实际数据写入时间小于等于预设写入时间，存储器的数据写入正常执行，此时存在空余时间；当存储器的实际数据写入时间大于预设写入时间，存储的数据写入无法正常执行；且预设写入时间若设置过大，会导致存储器的读写效率较低。需要说明的是，在本申请实施例中，晶体管的温度指晶体管的本身温度。
参考图3，存储器的调节方法，包括以下步骤：
需要说明的是，本申请实施例主要通过调控晶体管的栅电压，来补偿温度对存储器的实际数据写入时间带来的影响，并不代表其他条件并不影响存储器的实际数据写入时间，在本申请实施例中，除了晶体管的温度以及晶体管的栅电压，其他影响存储器的实际数据写入时间的条件，默认为保持不变的状态。
步骤101，获取温度与实际数据写入时间的第一映射关系。
由于晶体管的温度降低会导致晶体管的接触电阻R变大，且晶体管的温度降低会导致会晶体管的阈值电压Vth变大。相应地，晶体管的温度升高会导致会晶体管的接触电阻R变小，且晶体管的温度升高会导致会晶体管的阈值电压Vth变小。
由前文的结构描述可知，当晶体管导通时，位线结构才与存储电容之间形成电连接，晶体管导通即晶体管的栅电压Vgs大于Vth，且Vgs与Vth之间的差值Vgs-Vth与晶体管的源漏电流Ids呈正相关，即Vgs与Vth的差值Vgs-Vth越大，Ids越大，Ids为存储电容的充电电流，Ids越大，存储器的实际数据写入时间越短。
即晶体管的温度降低，阈值电压Vth变大，晶体管的源漏电流Ids减小，存储器的实际数据写入时间变长；晶体管的温度升高，阈值电压Vth变小，晶体管的源漏电流Ids增大，存储器的实际数据写入时间变短。
具体地，获取第一映射关系的方法包括：保持晶体管的栅电压不变，改变晶体管的温度，获取晶体管的温度与存储器的实际数据写入时间的第一映射关系，其中，第一映射关系为二维映射关系，自变量为晶体管的温度，因变量为存储器的实际数据写入时间。然后，改变晶体管的栅电压，改变晶体管的栅电压后保持晶体管的栅电压不变，改变晶体管的温度，获取晶体管的温度与存储器的实际数据写入时间的第一映射关系，从而获取不同栅电压下存储器的实际数据写入时间随晶体管的温度变化的第一映射关系。
步骤102，获取栅电压与实际数据写入时间的第二映射关系。
由前文的描述可知，当晶体管导通时，增大晶体管的栅电压Vgs，以增大Vgs-Vth，使得晶体管的源漏电流Ids增大，从而使得存储电容的数据写入时间 变小；减小晶体管的栅电压Vgs，以减小Vgs-Vth，使得晶体管的源漏电流Ids减小，从而使得存储电容的数据写入时间变长。
具体地，获取第二映射关系的方法包括：保持晶体管的温度不变，改变晶体管的栅电压，获取晶体管的栅电压与存储器的实际数据写入时间的第二映射关系，其中，第二映射关系为二维映射关系，自变量为晶体管的栅电压，因变量为存储器的实际数据写入时间。然后，改变晶体管的温度，改变晶体管的温度后保持晶体管的温度不变，改变晶体管的栅电压，获取晶体管的栅电压与存储器的实际数据写入时间的第二映射关系，从而获取不同温度下存储器的实际数据写入时间随晶体管的栅电压变化的第二映射关系。
步骤103，获取温度、栅电压以及实际数据写入时间的映射关系。
具体地，基于第一映射关系以及以及第二映射关系，获取晶体管的温度、晶体管的栅电压以及存储器的实际数据写入时间的映射关系，映射关系为三维映射关系。
需要说明的是，本实施例中步骤101、步骤102以及步骤103给出了一种获取晶体管的温度、晶体管的栅电压以及存储器的实际数据写入时间的映射关系的具体方法，数据一一对应，确保存储器的实际数据写入时间调控的准确性，在其他实施例中可以直接通过调控三者之间的关系，以获取上述映射关系。
步骤104，获取晶体管的当前温度。
具体地，在本实施例中通过设置在存储器中的温度传感器获取晶体管的当前温度。通过温度传感器直接获取晶体管的当前温度，获取的温度准确，误差较小。在其他实施例中，还可以通过获取存储器工作的环境温度以获取晶体管的当前温度。
步骤105，获取预设温度，以及当前温度与预设温度的温度差值。
步骤106，根据温度差值与映射关系，调整栅电压。在本实施例中，根据温度差值与映射关系调整栅电压的方式包括以下步骤：
步骤116，获取当前温度对应的实际数据写入时间与预设写入时间的时间差值。
存储器在上电工作之前会设置有晶体管的预设温度，晶体管的预设栅电压，以及晶体管的预设写入时间，其中，预设温度，预设栅电压以及预设写入时间也可以满足上述映射关系。
根据当前温度与预设温度的温度差值，获取晶体管在当前栅电压下，存储器的实际数据写入时间与预设写入时间的时间差值。即获取因温度变化导致的存储器的实际数据写入时间的变化。
步骤126，根据映射关系以及时间差值，调整栅电压，以抵消时间差值。
由于晶体管的温度变化，导致了存储器的实际数据写入时间发生变化，但这一改变并不是有利于存储器使用的，因此需要通过调控晶体管的栅电压以稳定存储器的实际数据写入时间。即通过调整栅电压，以抵消时间差值，从而稳定存储器的实际数据写入时间。
相对于现有技术而言，由于温度会影响存储器的实际数据写入时间，首先获取晶体管的温度、晶体管的栅电压以及存储器的实际数据写入时间之间的映射关系，根据晶体管的当前温度获取存储器的实际数据写入时间，通过调整晶体管的栅电压以调整晶体管在当前温度下存储器的实际数据写入时间，以使调整后的数据写入时间在预设时间内，保证数据完成写入到存储电容。
上面各种步骤划分，只是为了描述清楚，实现时可以合并为一个步骤或者对某些步骤进行拆分，分解为多个步骤，只要包括相同的逻辑关系，都在本专利的保护范围内；对流程中添加无关紧要的修改或者引入无关紧要的设计，但不改变其流程的核心设计都在该专利的保护范围内。
本申请第二实施例涉及一种存储器的调节方法，与第一实施例不同的是本实施里在根据温度差值调控栅电压之前会判断温度差值是否超过预设范围，当温度差值超值超过预设范围时才对存储器的实际数据写入时间进行调节，减少了不必要的调节操作，节约了调节成本。
图4为本申请实施例提供的存储器的调节方法对应的流程示意图，下面对本实施例的存储器的调节方法进行具体说明。
参考图4，存储器的调节方法，包括以下步骤：
步骤201，获取温度与实际数据写入时间的第一映射关系。
步骤202，获取栅电压与实际数据写入时间的第二映射关系。
步骤203，获取温度、栅电压以及实际写入时间的映射关系。
步骤204，获取晶体管的当前温度。
步骤205，获取预设温度，以及当前温度与预设温度的温度差值。
其中，步骤201～步骤205同第一实施例中的步骤101～步骤105，本实施例不再赘述。
步骤206，温度差值是否超过预设范围。
本实施例在对晶体管的栅电压进行调整前还用于判断晶体管的当前温度与预设温度的温度差值是否超过预设范围。
若温度差值超过预设范围，则执行根据温度差值与映射关系，调整晶体管的栅电压，即执行步骤207。
步骤207，根据温度差值与映射关系，调整栅电压。
具体地，若当前温度大于预设温度超过预设范围，且晶体管的N型晶体管，调节方式为增大栅电压；若当前温度小于预设温度超过预设范围，且晶体管的N型晶体管，调节方式为减小栅电压；若当前温度大于预设温度超过预设范围，且晶体管的P型晶体管，调节方式为减小栅电压；若当前温度小于预设温度超过预设范围，且晶体管的P型晶体管，调节方式为增大栅电压。
进一步地，本实施例还对预设范围进行了划分，预设范围至少包括第一预设范围和第二预设范围，第二预设范围大于第一预设范围。
若温度差值超过第一预设范围且不超过第二预设范围，增大或减少栅电压，增大或减小的量为第一预设值；若温度差值超过第二预设范围，增大或减小栅电压，增大或减小的量为第二预设值，第二预设值大于第一预设值，且第一预设值和第二预设值为定值。通过对预设分为进行分段调控，在节约调节成本的基础上，提高了对存储器的实际数据写入时间调节的准确性。
需要说明的是，在其他实施例中，预设范围被划分为至少三个子预设范围，通过划分为更多的子预设范围，进一步提高对存储器的实际数据写入时间调节 的准确性。
相对于现有技术而言，由于温度会影响存储器的实际数据写入时间，首先获取晶体管的温度、晶体管的栅电压以及存储器的实际数据写入时间之间的映射关系，根据晶体管的当前温度获取存储器的实际数据写入时间，通过调整晶体管的栅电压以调整晶体管在当前温度下存储器的实际数据写入时间，以使调整后的数据写入时间在预设时间内，保证数据完成写入到存储电容。
上面各种步骤划分，只是为了描述清楚，实现时可以合并为一个步骤或者对某些步骤进行拆分，分解为多个步骤，只要包括相同的逻辑关系，都在本申请的保护范围内；对流程中添加无关紧要的修改或者引入无关紧要的设计，但不改变其流程的核心设计都在该申请的保护范围内。
本申请第三实施例涉及一种存储器的调节系统。
参考图5，以下将结合附图对本实施例提供的存储器的调节系统进行详细说明，与第一实施例和第二实施例相同或相应的部分，以下将不做详细赘述。
存储器的调节系统300，包括：
第一获取模块301，用于获取晶体管的温度、晶体管的栅电压以及存储器的实际数据写入时间的映射关系，其中，映射关系为三维映射关系。
第二获取模块302，用于获取晶体管的当前温度。
具体地，在本实施例中通过设置在存储器中的温度传感器获取晶体管的当前温度。通过温度传感器直接获取晶体管的当前温度，获取的温度准确，误差较小。在其他实施例中，还可以通过获取存储器工作的环境温度以获取晶体管的当前温度。
处理模块303，用于基于当前温度以及映射关系，获取栅电压的调节方式。
在本实施例中，处理模块包括：比较单元313和处理单元333。
比较单元313，用于获取预设写入时间对应的预设温度，并获取当前温度与预设温度的温度差值。
处理单元333，用于根据温度差值与映射关系，获取栅电压的调节方式。
具体地，存储器在上电工作之前会设置有晶体管的预设温度，晶体管的预 设栅电压，以及晶体管的预设写入时间，其中，预设温度，预设栅电压以及预设写入时间也可以满足上述映射关系。处理单元333根据当前温度与预设温度的温度差值，获取晶体管在当前栅电压下，存储器的实际数据写入时间与预设写入时间的时间差值，即获取因温度变化导致的存储器的实际数据写入时间的变化。由于晶体管的温度变化，导致了存储器的实际数据写入时间发生变化，但这一改变并不是有利于存储器使用的，因此需要通过处理单元333调控晶体管的栅电压以稳定存储器的实际数据写入时间。即根据映射关系以及时间差值，调整栅电压，以抵消时间差值，从而稳定存储器的实际数据写入时间。
调节模块304，用于基于调节方式，调整栅电压，以使调整后的栅电压对应的存储器的实际数据写入时间在预设写入时间内。
在一个例子中，第一获取模块301包括：第一获取子模块311、第二获取子模块321和第三获取子模块331。
第一获取子模块311，用于获取晶体管的温度与存储器的实际数据写入时间的第一映射关系。具体地，保持晶体管的栅电压不变，获取晶体管的温度与存储器的实际数据写入时间的第一映射关系，其中自变量为晶体管的温度，因变量为存储器的实际数据写入时间，第一映射关系为二维映射关系。
第二获取子模块321，用于获取晶体管的栅电压与存储器的实际数据写入时间的第二映射关系。具体地，保持晶体管的温度不变，获取晶体管的栅电压与存储器的实际数据写入时间的第二映射关系，其中自变量为晶体管的栅电压，因变量为存储器的实际数据写入时间，第二映射关系为二维映射关系。
第三获取子模块331，基于第一映射关系以及第二映射关系，获取晶体管的温度、晶体管的栅电压以及存储器的实际数据写入时间的映射关系。
在一个例子中，处理模块303还包括：判断单元323，用于判断温度差值是否超过预设范围，当温度差值超过预设范围，处理单元333用于根据温度差值与映射关系，获取栅电压的调节方式。
具体地，判断单元323至少包括第一判断子单元305和第二判断子单元306。通过对预设分为进行分段调控，在节约调节成本的基础上，提高了对存储 器的实际数据写入时间调节的准确性。
第一判断子单元305，用于判断温度差值是否超过第一预设范围。
第二判断子单元306，用于判断温度差值是否超过第二预设范围，第二预设范围大于第一预设范围。
需要说明的是，在其他实施例中，判断单元包括至少三个判断子单元，通过将预设范围划分为至少三个子预设范围，通过划分为更多的子预设范围，进一步提高对存储器的实际数据写入时间调节的准确性。
相比于现有技术而言，由于温度会影响存储器的实际数据写入时间，通过第一获取模块获取晶体管的温度、晶体管的栅电压以及存储器的实际数据写入时间之间的映射关系，通过第二获取模块根据晶体管的当前温度获取存储器的实际数据写入时间，通过处理模块获取晶体管的栅电压调节方式，然后通过调节模块调整晶体管的栅电压以调整晶体管在当前温度下存储器的实际数据写入时间，以使调整后的数据写入时间在预设时间内，保证数据完成写入到存储电容。
值得一提的是，本实施例中所涉及到的各模块均为逻辑模块，在实际应用中，一个逻辑单元可以是一个物理单元，也可以是一个物理单元的一部分，还可以以多个物理单元的组合实现。此外，为了突出本申请的创新部分，本实施例中并没有将与解决本申请所提出的技术问题关系不太密切的单元引入，但这并不表明本实施例中不存在其它的单元。
由于第一实施例和第二实施例与本实施例相互对应，因此本实施例可与第一实施例和第二实施例互相配合实施。第一实施例和第二实施例中提到的相关技术细节在本实施例中依然有效，在第一实施例和第二实施例中所能达到的技术效果在本实施例中也同样可以实现，为了减少重复，这里不再赘述。相应地，本实施例中提到的相关技术细节也可应用在第一实施例和第二实施例中。
本申请第四实施例涉及一种半导体器件。
半导体器件，包括：存储器，以及第三实施例提供的存储器调节系统，存储器调节系统基于存储器中晶体管的温度，调节晶体管的栅电压，以使调整后 的栅电压对应的存储器的实际数据写入时间在预设写入时间内。
由于第一实施例和第二实施例与本实施例相互对应，因此本实施例可与第一实施例和第二实施例互相配合实施。第一实施例和第二实施例中提到的相关技术细节在本实施例中依然有效，在第一实施例和第二实施例中所能达到的技术效果在本实施例中也同样可以实现，为了减少重复，这里不再赘述。相应地，本实施例中提到的相关技术细节也可应用在第一实施例和第二实施例中。
本领域的普通技术人员可以理解，上述各实施例是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。
工业实用性
在本申请实施例中，存储器的调节方法包括：获取晶体管的温度、晶体管的栅电压以及实际数据写入时间的映射关系；获取晶体管的当前温度；基于当前温度以及映射关系调整栅电压，以使调整后的栅电压对应的实际数据写入时间在预设写入时间内。这样，由于温度会影响存储器的实际数据写入时间，首先获取晶体管的温度、晶体管的栅电压以及实际数据写入时间之间的映射关系，根据晶体管的当前温度获取实际数据写入时间，通过调整晶体管的栅电压以调整晶体管在当前温度下的实际数据写入时间，以使调整后的数据写入时间在预设时间内，保证数据完成写入到存储电容。

Claims (13)

  1. 一种存储器的调节方法，所述存储器包括晶体管，所述晶体管的栅极与存储器的字线电连接，所述晶体管的源极/漏极的一端与存储器的位线电连接，另一端与存储器的存储电容电连接，包括：
    获取所述晶体管的温度、所述晶体管的栅电压以及存储器的实际数据写入时间的映射关系；
    获取所述晶体管的当前温度；
    基于所述当前温度以及所述映射关系调整所述栅电压，以使调整后的所述栅电压对应的所述实际数据写入时间在预设写入时间内。
  2. 根据权利要求1所述的存储器的调节方法，其中，基于所述当前温度以及所述映射关系调整所述栅电压的方法包括：
    获取预设写入时间对应的预设温度；
    获取所述当前温度与所述预设温度的温度差值；
    根据所述温度差值与所述映射关系，调整所述栅电压。
  3. 根据权利要求2所述的存储器的调节方法，其中，根据所述温度差值与所述映射关系，调整所述栅电压之前，还包括以下步骤：
    判断所述温度差值是否超过预设范围；
    若所述温度差值超过所述预设范围，则执行所述根据所述温度差值与所述映射关系，调整所述栅电压。
  4. 根据权利要求2或3所述的存储器的调节方法，其中，根据所述温度差值与所述映射关系，调整所述栅电压的方法，包括：
    根据所述映射关系，获取所述当前温度对应的所述实际数据写入时间与所述预设写入时间的时间差值；
    根据所述映射关系以及所述时间差值，调整所述栅电压，以抵消所述时间差值。
  5. 根据权利要求3所述的存储器的调节方法，其中，所述预设范围至少包 括第一预设范围和第二预设范围，所述第二预设范围大于所述第一预设范围；
    若所述温度差值超过所述第一预设范围且不超过所述第二预设范围，增大或减少所述栅电压，增大或者减少的量为第一预设值；
    若所述温度差值超过所述第二预设范围，增大或减小所述栅电压，增大或者减少的量为第二预设值，所述第二预设值大于所述第一预设值。
  6. 根据权利要求1所述的存储器的调节方法，其中，获取所述晶体管的温度、所述晶体管的栅电压以及存储器的实际数据写入时间的映射关系的方法包括：
    获取所述晶体管的温度与所述存储器的实际数据写入时间的第一映射关系；
    获取所述晶体管的栅电压与所述存储器的实际数据写入时间的第二映射关系；
    基于所述第一映射关系以及所述第二映射关系，获取所述晶体管的温度、所述晶体管的栅电压以及所述存储器的实际数据写入时间的映射关系。
  7. 一种存储器的调节系统，应用于存储器，包括：
    第一获取模块，用于获取晶体管的温度、晶体管的栅电压以及存储器的实际数据写入时间的映射关系；
    第二获取模块，用于获取所述晶体管的当前温度；
    处理模块，用于基于所述当前温度以及所述映射关系，获取所述栅电压的调节方式；
    调节模块，用于基于所述调节方式，调整所述栅电压，以使调整后的所述栅电压对应的所述存储器的实际数据写入时间在预设写入时间内。
  8. 根据权利要求7所述的存储器的调节系统，其中，所述第二获取模块包括设置在所述存储器中的温度传感器。
  9. 根据权利要求7所述的存储器的调节系统，其中，所述处理模块包括：
    比较单元，用于获取所述预设写入时间对应的预设温度，并获取所述当前温度与所述预设温度的温度差值；
    处理单元，用于根据所述温度差值与所述映射关系，获取所述栅电压的调节方式。
  10. 根据权利要求9所述的存储器的调节系统，其中，所述处理模块还包括：判断单元，用于判断所述温度差值是否超过预设范围，当所述温度差值超过所述预设范围，所述处理单元用于根据所述温度差值与所述映射关系，获取所述栅电压的调节方式。
  11. 根据权利要求10所述的存储器的调节系统，其中，所述判断单元至少包括第一判断子单元和第二判断子单元；
    所述第一判断子单元用于，判断所述温度差值是否超过第一预设范围；
    所述第二判断子单元用于，判断所述温度差值是否超过第二预设范围；
    所述第二预设范围大于所述第一预设范围。
  12. 根据权利要求7所述的存储器的调节系统，其中，所述第一获取模块包括：
    第一获取子模块，用于获取所述晶体管的温度与所述存储器的实际数据写入时间的第一映射关系；
    第二获取子模块，用于获取所述晶体管的栅电压与所述存储器的实际数据写入时间的第二映射关系；
    第三获取子模块，基于所述第一映射关系以及所述第二映射关系，获取所述晶体管的温度、所述晶体管的栅电压以及存储器的实际数据写入时间的映射关系。
  13. 一种半导体器件，包括存储器，以及权利要求7～12任一项所述的存储器调节系统，其中，所述存储器调节系统基于所述存储器中晶体管的温度，调节所述晶体管的栅电压，以使调整后的所述栅电压对应的所述存储器的实际数据写入时间在预设写入时间内。
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