WO2022017032A1 - 显示基板及显示装置 - Google Patents

显示基板及显示装置 Download PDF

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Publication number
WO2022017032A1
WO2022017032A1 PCT/CN2021/099017 CN2021099017W WO2022017032A1 WO 2022017032 A1 WO2022017032 A1 WO 2022017032A1 CN 2021099017 W CN2021099017 W CN 2021099017W WO 2022017032 A1 WO2022017032 A1 WO 2022017032A1
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Prior art keywords
pull
light
gate
circuit
pixels
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PCT/CN2021/099017
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English (en)
French (fr)
Inventor
袁志东
李永谦
袁粲
徐攀
Original Assignee
京东方科技集团股份有限公司
合肥京东方卓印科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥京东方卓印科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to JP2022523694A priority Critical patent/JP2023534324A/ja
Priority to KR1020227013391A priority patent/KR20230041644A/ko
Priority to CN202180004610.7A priority patent/CN114258563A/zh
Priority to EP21846073.1A priority patent/EP4044169A4/en
Publication of WO2022017032A1 publication Critical patent/WO2022017032A1/zh
Priority to US17/680,956 priority patent/US11955089B2/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0804—Sub-multiplexed active matrix panel, i.e. wherein one active driving circuit is used at pixel level for multiple image producing elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display substrate and a display device.
  • Organic light emitting diode organic light emitting diode, OLED
  • OLED organic light emitting diode
  • an OLED display substrate includes a base substrate, and a plurality of pixels located on the base substrate, and each pixel includes a light-emitting control circuit, a light-emitting driving circuit and a light-emitting element.
  • the light-emitting control circuit can provide a DC power signal to the light-emitting drive circuit in response to the light-emitting control signal provided by the light-emitting control line to which it is connected, and the light-emitting drive circuit can respond to the gate drive signal provided by the connected gate line and receive The received DC power signal provides a light-emitting drive signal to the light-emitting element.
  • different pixels are connected to different light emission control circuits.
  • Embodiments of the present disclosure provide a display substrate and a display device.
  • the technical solution is as follows:
  • a display substrate comprising:
  • each of the pixels includes a light-emitting control circuit, a light-emitting driving circuit and a light-emitting element, and at least two of the pixels multiplex the same light-emitting control circuit circuit;
  • the gate driving circuit is respectively connected with the plurality of driving signal lines, the plurality of driving signal lines, the A plurality of light-emitting control lines are connected to the plurality of gate lines, the plurality of light-emitting control lines are connected to the light-emitting control circuit included in each of the pixels, and the plurality of gate lines are connected to the light-emitting control circuit included in each of the pixels.
  • a light-emitting driving circuit is connected, and the gate driving circuit is configured to output light-emitting control signals to the plurality of light-emitting control lines and output gates to the plurality of gate lines in response to driving signals provided by the plurality of driving signal lines pole drive signal.
  • At least two of the pixels multiplexing the same light-emitting control circuit are located in the same column.
  • At least two of the pixels multiplexed in the same light-emitting control circuit are adjacent to each other.
  • every two of the pixels in the same column multiplex the same light-emitting control circuit.
  • the two pixels of the same light-emitting control circuit are multiplexed, and are symmetrically arranged on both sides of the light-emitting control line connected to the light-emitting control circuit.
  • each of the driving signal lines is located between two adjacent columns of the pixels.
  • At most two of the driving signal lines are disposed between every two adjacent columns of the pixels.
  • the gate drive circuit includes: a plurality of shift register units in cascade;
  • At least two of the cascaded shift register units are located between two adjacent rows of pixels.
  • At least two cascaded shift register units are located between two adjacent rows of target pixels;
  • the light-emitting control circuits connected to the target pixels in one row are different from the light-emitting control circuits connected to the target pixels in the other row.
  • two cascaded shift register units are provided between each adjacent two rows of the target pixels;
  • One of the shift register units is connected to the target pixels in one row, and the other shift register unit is connected to the target pixels in another row.
  • the two cascaded shift register units are symmetrically arranged between the two rows of target pixels.
  • the shift register unit includes: an input sub-circuit, a pull-down control sub-circuit, a pull-down sub-circuit and an output sub-circuit;
  • the input sub-circuit is respectively connected with the first input terminal, the second input terminal, the first control signal terminal, the second control signal terminal and the pull-up node, and the input sub-circuit is used for providing a response to the first input terminal.
  • the first input signal output the first control signal provided by the first control signal terminal to the pull-up node, and output to the pull-up node in response to the second input signal provided by the second input terminal a second control signal provided by the second control signal terminal;
  • the pull-down control sub-circuit is respectively connected with the first clock signal terminal, the pull-up node, the pull-down power supply terminal, the pull-down node and the output terminal, and the pull-down control sub-circuit is used for responding to the signal provided by the first clock signal terminal.
  • a first clock signal outputting the first clock signal to the pull-down node, and outputting the pull-down power supply terminal to the pull-down node in response to the potential of the pull-up node and the output signal provided by the output terminal pull-down power signal;
  • the pull-down sub-circuit is respectively connected to the reset signal terminal, the pull-down node, the pull-down power terminal, the pull-up node and the output end, and the pull-down sub-circuit is used for responding to the potential of the pull-down node, outputting the pull-down power supply signal to the pull-up node and the output terminal, and outputting the pull-down power supply signal to the pull-up node in response to a reset signal provided by the reset signal terminal;
  • the output sub-circuit is respectively connected to the pull-up node, the second clock signal terminal and the output terminal, and the output sub-circuit is used for outputting the output terminal to the output terminal in response to the potential of the pull-up node The second clock signal provided by the second clock signal terminal.
  • the display substrate further includes: a plurality of data lines on the base substrate;
  • the plurality of gate lines include: a plurality of first gate lines, a plurality of second gate lines and a plurality of third gate lines;
  • the light-emitting control circuit includes: a light-emitting control transistor;
  • the light-emitting driving circuit includes: data writing transistors, reset transistors, drive transistors, compensation transistors and storage capacitors;
  • the gate of the data writing transistor is connected to one of the first gate lines, the first electrode is connected to the gate of the driving transistor, and the second electrode is connected to one of the data lines;
  • the first gate of the driving transistor The pole is connected to the first pole of the light-emitting control transistor, and the second pole is connected to the light-emitting element;
  • the gate of the light-emitting control transistor is connected to one of the light-emitting control lines, and the second pole is connected to the DC power supply terminal;
  • the gate of the reset transistor is connected to one of the second gate lines, the first pole is connected to the first initial signal terminal, and the second pole is connected to the second pole of the driving transistor;
  • the gate of the compensation transistor is connected to a
  • the third gate line is connected, the first electrode is connected to the second initial signal terminal, and the second electrode is connected to the gate of the driving transistor.
  • a display device comprising: a source driving circuit and the display substrate according to the above aspect;
  • the source driving circuit is connected to a plurality of data lines in the display substrate, and the source driving circuit is used for providing data signals for each of the data lines.
  • FIG. 1 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of another display substrate provided by an embodiment of the present disclosure.
  • FIG. 3 is a schematic structural diagram of another display substrate provided by an embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of a circuit structure of two adjacent pixels provided by an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of still another display substrate provided by an embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram of still another display substrate provided by an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of a shift register unit provided by an embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram of another shift register unit provided by an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of still another display substrate provided by an embodiment of the present disclosure.
  • FIG. 11 is a timing diagram of a pixel operation provided by an embodiment of the present disclosure.
  • FIG. 12 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure.
  • the transistors used in all the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics, and the transistors used in the embodiments of the present disclosure are mainly switching transistors according to their functions in the circuit. Since the source and drain of the switching transistor used here are symmetrical, the source and drain are interchangeable. In the embodiments of the present disclosure, the source electrode is referred to as the first electrode, and the drain electrode is referred to as the second electrode. Or the drain is called the first electrode and the source is called the second electrode. According to the form in the drawings, the middle end of the transistor is the gate, the signal input end is the source electrode, and the signal output end is the drain electrode.
  • the switching transistor used in the embodiments of the present disclosure may be any one of a P-type switching transistor and an N-type switching transistor, wherein the P-type switching transistor is turned on when the gate is at a low level, and turned off when the gate is at a high level , the N-type switching transistor is turned on when the gate is high and turned off when the gate is low.
  • FIG. 1 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure.
  • the display substrate may include: a base substrate 01 , and a plurality of pixels 02 arranged on the base substrate 01 and arranged in an array.
  • FIG. 2 is a schematic structural diagram of another display substrate provided by an embodiment of the present disclosure. It can be seen in conjunction with FIG. 1 and FIG. 2 that each pixel 02 may include a light-emitting control circuit 021 , a light-emitting driving circuit 022 and a light-emitting element 023 . And at least two pixels 02 can multiplex the same light-emitting control circuit 021 , that is, at least two pixels 02 can work under the driving of the same light-emitting control circuit 021 .
  • the display substrate may further include: a gate driving circuit 03 on the base substrate 01, a plurality of light-emitting control lines (eg, EM1 to EMn shown in FIG. 2), a plurality of gate lines ( For example, G1 to Gm shown in FIG. 2 ) and a plurality of driving signal lines (L1 to Li shown in FIG. 2 ).
  • a gate driving circuit 03 on the base substrate 01
  • EM1 to EMn shown in FIG. 2 e.g, EM1 to EMn shown in FIG. 2
  • gate lines e.g, G1 to Gm shown in FIG. 2
  • driving signal lines L1 to Li shown in FIG. 2
  • the gate driving circuit 03 can be respectively connected with a plurality of driving signal lines, a plurality of light emission control lines and a plurality of gate lines.
  • a plurality of light-emitting control lines may be connected to the light-emitting control circuit 021 included in each pixel 02
  • a plurality of gate lines may be connected to the light-emitting driving circuit 022 included in each pixel 02 .
  • the gate driving circuit 03 may be configured to output light-emitting control signals to a plurality of light-emitting control lines and output gate driving signals to a plurality of gate lines in response to driving signals provided by the plurality of driving signal lines. That is, the gate driving circuit 03 can operate under the driving of driving signals provided by a plurality of driving signal lines.
  • multiple rows of pixels 02 and multiple gate lines may be connected in one-to-one correspondence, and multiple rows of pixels 02 may also be connected with multiple light-emitting control lines in one-to-one correspondence. That is, in a plurality of pixels 02 located in the same row, the lighting control circuit 021 included in each pixel 02 can be connected to the same lighting control line, and the lighting driving circuit 022 included in each pixel 02 can be connected to the same gate line.
  • the number of gate lines included in the display substrate is the same as the number of rows of pixels.
  • At least two pixels 02 can multiplex the same light-emitting control circuit 021, if the at least two pixels 02 are located in the same row, the number of light-emitting control circuits 021 to be set can be reduced accordingly; If the pixels 02 are located in the same column, the number of lighting control circuits 021 that need to be set can be reduced accordingly, and the number of lighting control lines that need to be set can be reduced accordingly. In this way, the effect of optimizing the pixel space can be achieved without affecting the normal display of the pixels 02 , that is, the area occupied by the pixels 02 on the base substrate 01 is reduced compared to the related art.
  • the area of the remaining space on the base substrate 01 is increased, and the remaining space can be used to reliably set the gate driving circuit 03 and the driving signal lines to be connected to the gate driving circuit 03 .
  • a display substrate in which the gate drive circuit 03 is arranged in a substrate gate drive in array, GIA
  • GIA gate drive in array
  • the lighting control circuit 021 can also be connected to the lighting driving circuit 022, and the lighting driving circuit 022 can also be connected to the lighting element 023.
  • the lighting control circuit 021 may be configured to output a DC power signal to the connected lighting driving circuit 022 in response to the lighting control signal provided by the connected lighting control line.
  • the light-emitting driving circuit 022 can be used to output a driving signal to the connected light-emitting element 023 in response to the gate driving signal provided by the connected gate line and the received DC power signal, so as to drive the light-emitting element 023 to emit light.
  • the embodiments of the present disclosure provide a display substrate. Since in the display substrate, at least two pixels located on the base substrate can reuse the same light-emitting control circuit connected to the light-emitting control line, the number of light-emitting control circuits to be set in the display substrate can be reduced, or further reduced The number of light-emitting control lines that need to be arranged on the display substrate ultimately reduces the area of the substrate that each pixel needs to occupy. Furthermore, the gate driving circuit for providing signals to the signal lines connected to the pixels and the driving signals connected to the gate driving circuit can be arranged on the base substrate.
  • the display substrate provided by the embodiment of the present disclosure has higher resolution.
  • At least two pixels 02 multiplexing the same light-emitting control circuit 021 may be located in the same column.
  • the number of light-emitting control circuits 021 required to be provided on the base substrate 01 can be reduced, but also the number of light-emitting control lines required to be provided on the base substrate 01 can be reduced.
  • the display substrate includes m rows of pixels 02 in total
  • the number of light-emitting control lines set on the substrate 01 is less than the number of rows of pixels 02 . That is, n is less than m in FIG. 2 , where both m and n may be integers greater than 1.
  • At least two pixels 02 multiplexing the same light-emitting control circuit 021 are not only located in the same column, but also adjacent to each other. In this way, layout layout and signal routing can be facilitated.
  • FIG. 3 takes as an example that every two adjacent pixels 02 located in the same column multiplex the same light-emitting control circuit 021 as another display substrate.
  • FIG. 3 only schematically shows that the pixels 02 of the adjacent nth row and the pixels 02 of the n+1th row are multiplexed with the same light-emitting control circuit 021, and the adjacent pixels 02 of the n+2th row and the n+3th row of pixels 02 are adjacent to each other.
  • the row pixels 02 are multiplexed with the same light emission control circuit 021 .
  • two adjacent pixels 02 can also multiplex the same light-emitting control line (eg, EMn and EM(n). +1)).
  • FIG. 4 shows an optional circuit diagram of the two pixels 02
  • FIG. 5 Alternative circuit layouts for the two pixels 02 are shown. 3 to 5 , in the embodiment of the present disclosure, two pixels 02 multiplexed by the same light-emitting control circuit 021 may be symmetrically arranged on two sides of the light-emitting control line EMn connected to the light-emitting control circuit 021 multiplexed by the light-emitting control circuit 021 . side.
  • each transistor included in one pixel 02 and each connected signal line can be symmetrically arranged on the light-emitting control line with each transistor included in the other pixel 02 and each connected signal line Both sides of EMn.
  • Such a design not only further facilitates the layout and signal routing, but also enables centralized arrangement of the signal lines, further optimizing the pixel space.
  • the display substrate may further include: a plurality of data lines located on the base substrate 01 .
  • the plurality of gate lines may include a plurality of first gate lines, a plurality of second gate lines, and a plurality of third gate lines.
  • the number of data lines may be the same as the number of pixel columns, and the number of first grid lines, the number of second grid lines and the number of third grid lines may be the same as the number of pixel rows. 4 and 5 only show one data line D1, two first gate lines G1n and G1(n+1), two second gate lines G2n and G2(n+1), and two third gate lines G3n and G3(n+1).
  • the light-emitting control circuit 021 may include: a light-emitting control transistor T1 .
  • the light-emitting driving circuit 022 may include: a data writing transistor T2, a reset transistor T3, a driving transistor T4, a compensation transistor T5 and a storage capacitor C1.
  • the gate of the data writing transistor T2 may be connected to a first gate line, the first electrode may be connected to the gate of the driving transistor T4, and the second electrode may be connected to a data line D1.
  • the gate of the data writing transistor T2 in the pixel 02 in the nth row is connected to the first gate line G1n, and the gate of the data writing transistor T2 in the pixel 02 in the n+1th row is connected to the first gate line G1(n +1) Connect.
  • the first electrode of the driving transistor T4 can be connected to the first electrode of the light emitting control transistor T1, the second electrode can be connected to the light emitting element 023, and the light emitting element 023 can also be connected to the power supply terminal VSS.
  • the gate of the light-emitting control transistor T1 may be connected to a light-emitting control line EMn, and the second pole of the light-emitting control transistor T1 may be connected to the DC power supply terminal VDD.
  • the gate of the reset transistor T3 may be connected to a second gate line, the first electrode may be connected to the first initial signal terminal Vin1, and the second electrode may be connected to the second electrode of the driving transistor T4.
  • the gate of the reset transistor T3 in the pixel 02 in the nth row is connected to the second gate line G2n, and the gate of the reset transistor T3 in the pixel 02 in the n+1th row is connected to the second gate line G2(n+1) connect.
  • the gate of the compensation transistor T5 may be connected to a third gate line, the first electrode may be connected to the second initial signal terminal Vin2, and the second electrode may be connected to the gate of the driving transistor T4.
  • the gate of the compensation transistor T5 in the pixel 02 in the nth row is connected to the third gate line G3n, and the gate of the compensation transistor T5 in the pixel 02 in the n+1th row is connected with the third gate line G3(n+1) .
  • the above only schematically shows an optional structure of the pixel 02, which is a 5T1C (ie, five transistors and one capacitor) structure.
  • the embodiment of the present disclosure does not limit the structure of the pixel 02, which may also be other structures, such as a 7T1C structure.
  • the optional structure of the display substrate is illustrated by taking as an example that the same light-emitting control circuit 021 is multiplexed for every two adjacent pixels 02 located in the same column:
  • each driving signal line connected to the gate driving circuit 03 may be located between two adjacent columns of pixels 02 .
  • FIG. 6 which shows yet another display substrate, since it is located in the same column and multiplexes the same light-emitting control circuit 021 for every two adjacent pixels 02 , so that between every two adjacent columns of pixels 02 can be Additional areas are reserved, such as area 5 and area 6 as shown in FIG. 6 .
  • the driving signal lines connected to the gate driving circuit 03 may be arranged in the regions 5 and 6 .
  • the driving signal lines since the area between every two adjacent columns of pixels 02 is limited, in order to ensure reliable arrangement of the driving signal lines, at most two driving signal lines may be arranged between every two adjacent columns of pixels 02 .
  • the gate driving circuit 03 may include: a plurality of shift register units 031 in cascade. At least two cascaded shift register units 031 may be located between two adjacent rows of pixels 02 .
  • FIG. 6 since they are located in the same column and multiplex the same light-emitting control circuit 021 for every two adjacent pixels 02, an extra area can also be reserved between every two adjacent rows of pixels 02, as shown in FIG. 6 shows area 1, area 2, area 3 and area 4.
  • at least two cascaded shift register units 031 may be disposed in the regions 1 to 4 between every two adjacent rows of pixels 02 .
  • At least two cascaded shift register units 031 may be located between two adjacent rows of target pixels 02 .
  • the light emission control circuit connected to one row of target pixels 02 is different from the light emission control circuit connected to the other row of target pixels 02 . That is, two less cascaded shift register units 031 may be located between two rows of pixels 02 that are not multiplexed with the light emission control circuit 021 .
  • FIG. 7 is a schematic structural diagram of still another display substrate provided by an embodiment of the present disclosure. As shown in FIG. 7 , only two cascaded shift register units 031 may be disposed between every two adjacent rows of target pixels 02 . Wherein, one shift register unit 031 may be connected with a row of target pixels 02, and another shift register unit 031 may be connected with another row of target pixels 02 (not shown in FIG. 7).
  • the two cascaded shift register units 031 may be symmetrically arranged between the two rows of target pixels. That is, the transistors included in one shift register unit 031 are arranged symmetrically with the transistors included in the other shift register unit 031 . In this way, some driving signal lines (eg, power supply signals for providing DC signals) can be shared, which further optimizes the GIA space, that is, reduces the area of the base substrate 01 occupied by the shift register unit 031 .
  • driving signal lines eg, power supply signals for providing DC signals
  • FIG. 8 is a schematic structural diagram of a shift register unit provided by an embodiment of the present disclosure.
  • the shift register unit 031 may include: an input sub-circuit 0311 , a pull-down control sub-circuit 0312 , a pull-down sub-circuit 0313 and an output sub-circuit 0314 .
  • the input sub-circuit 0311 can be respectively connected to the first input terminal IN1, the second input terminal IN2, the first control signal terminal CN, the second control signal terminal CNB and the pull-up node PU.
  • the input sub-circuit 0311 can be configured to output the first control signal provided by the first control signal terminal CN to the pull-up node PU in response to the first input signal provided by the first input terminal IN1, and the first control signal provided by the second input terminal IN2 in response to the pull-up node PU.
  • the input sub-circuit 0311 may output the first control signal provided by the first control signal terminal CN to the pull-up node PU when the potential of the first input signal provided by the first input terminal IN1 is the first potential. And, when the potential of the second input signal provided by the second input terminal IN2 is the first potential, the second control signal provided by the second control signal terminal CNB may be output to the pull-up node PU.
  • the first input terminal IN1 may be connected to the output terminal of the shift register unit 031 of the previous stage, and the second input terminal IN2 may be connected to the output terminal of the shift register unit 031 of the next stage.
  • the potential of the first control signal and the potential of the second control signal may be complementary. That is, when the potential of the first control signal is the first potential, the potential of the second control signal is the second potential; when the potential of the first control signal is the second potential, the potential of the second control signal is the first potential.
  • the first potential may be an effective potential, and the second potential may be an inactive potential.
  • the transistor is an N-type transistor, the first potential may be a high potential relative to the second potential; when the transistor is a P-type transistor, the first potential may be a low potential relative to the second potential.
  • the first stage shift register unit 031 and the last stage shift register unit 031 can be connected to the initial signal terminal, and the initial signal terminal can be used to shift to the first stage.
  • the first input terminal IN1 connected to the bit register unit 031 provides the initial signal at the first potential, and can be used to provide the initial signal at the first potential to the second input terminal IN2 connected to the last stage shift register unit 031 , so as to ensure the normal operation of the first-stage shift register unit 031 and the last-stage shift register unit 031 .
  • the pull-down control sub-circuit 0312 may be connected to the first clock signal terminal CK, the pull-up node PU, the pull-down power supply terminal VGL, the pull-down node PD and the output terminal OUT, respectively.
  • the pull-down control sub-circuit 0312 can be used for outputting the first clock signal to the pull-down node PD in response to the first clock signal provided by the first clock signal terminal CK, and in response to the potential of the pull-up node PU and the output signal provided by the output terminal OUT , the pull-down node PD outputs the pull-down power signal provided by the pull-down power terminal VGL.
  • the pull-down control sub-circuit 0312 may output the first clock signal to the pull-down node PD when the potential of the first clock signal provided by the first clock signal terminal CK is the first potential, so as to charge the pull-down node PD.
  • the pull-down control sub-circuit 0312 can output the pull-down power signal provided by the pull-down power terminal VGL to the pull-down node PD when the potential of the pull-up node PU is the first potential, and the potential of the pull-down power signal can be the second potential to realize the pull-down Noise reduction of node PD.
  • the pull-down control sub-circuit 0312 can output the pull-down power signal to the pull-down node PD when the potential of the output signal provided by the output terminal OUT is the first potential, so as to realize noise reduction of the pull-down node PD.
  • the pull-down sub-circuit 0313 may be respectively connected to the reset signal terminal RST, the pull-down node PD, the pull-down power source terminal VGL, the pull-up node PU and the output terminal OUT.
  • the pull-down subcircuit 0313 can be used to output a pull-down power signal to the pull-up node PU and the output terminal OUT in response to the potential of the pull-down node PD, and to output a pull-down power signal to the pull-up node PU in response to the reset signal provided by the reset signal terminal RST.
  • the pull-down subcircuit 0313 can output a pull-down power signal to the pull-up node PU and the output terminal OUT when the potential of the pull-down node PD is the first potential, so as to realize noise reduction on the pull-up node PU and the output terminal OUT.
  • the pull-up node PU can output a pull-down power supply signal, so as to realize noise reduction of the pull-up node PU.
  • the output sub-circuit 0314 may be connected to the pull-up node PU, the second clock signal terminal CKB and the output terminal OUT, respectively.
  • the output sub-circuit 0314 may be configured to output the second clock signal provided by the second clock signal terminal CKB to the output terminal OUT in response to the potential of the pull-up node PU.
  • the output sub-circuit 0314 may output the second clock signal provided by the second clock signal terminal CKB to the output terminal OUT when the potential of the pull-up node PU is the first potential.
  • the second clock signal may be provided to the gate line as a gate driving signal, or may be provided to the light emission control line as a light emission control signal.
  • FIG. 9 is a schematic structural diagram of another shift register unit provided by an embodiment of the present disclosure.
  • the input sub-circuit 0311 may include: a first input transistor M1 and a second input transistor M2.
  • the pull-down control sub-circuit 0312 may include: a first pull-down control transistor M3, a second pull-down control transistor M4 and a third pull-down control transistor M5.
  • the pull-down sub-circuit 0313 may include: a first pull-down transistor M6, a second pull-down transistor M7, a third pull-down transistor M8 and a pull-down capacitor C2.
  • the output sub-circuit 0314 may include: an output transistor M9 and an output capacitor C3.
  • the gate of the first input transistor M1 may be connected to the first input terminal IN1, the first pole may be connected to the first control signal terminal CN, and the second pole may be connected to the pull-up node PU.
  • the first input transistor M1 can output the first control signal provided by the first control signal terminal CN to the pull-up node PU when the potential of the first input signal provided by the first input terminal IN1 is the first potential, so as to realize the pull-up node PU. Pull the charging of the node PU.
  • the gate of the second input transistor M2 may be connected to the second input terminal IN2, the first pole may be connected to the second control signal terminal CNB, and the second pole may be connected to the pull-up node PU.
  • the second input transistor M2 can output the second control signal provided by the second control signal terminal CNB to the pull-up node PU, so as to realize the pull-up node PU. Pull the reset of the node PU.
  • Both the gate and the first pole of the first pull-down control transistor M3 may be connected to the first clock signal terminal CK, and the second pole may be connected to the pull-down node PD.
  • the first pull-down control transistor M3 can output the first clock signal to the pull-down node PD when the potential of the first clock signal provided by the first clock signal terminal CK is the first potential to charge the pull-down node PD.
  • the gate of the second pull-down control transistor M4 may be connected to the pull-up node PU, the first electrode may be connected to the pull-down power supply terminal VGL, and the second electrode may be connected to the pull-down node PD.
  • the second pull-down control transistor M4 can output a pull-down power signal to the pull-down node PD when the potential of the pull-up node PU is the first potential, so as to realize noise reduction of the pull-down node PD.
  • the gate of the third pull-down control transistor M5 may be connected to the output terminal OUT, the first electrode may be connected to the pull-down power supply terminal VGL, and the second electrode may be connected to the pull-down node PD.
  • the third pull-down control transistor M5 can output a pull-down power signal to the pull-down node PD when the potential of the output signal provided by the output terminal OUT is the first potential, so as to realize noise reduction of the pull-down node PD.
  • the gate of the first pull-down transistor M6 may be connected to the reset signal terminal RST, the first pole may be connected to the pull-down power supply terminal VGL, and the second pole may be connected to the pull-up node PU.
  • the first pull-down transistor M6 can output the pull-down power supply signal provided by the pull-down power supply terminal VGL to the pull-up node PU when the potential of the reset signal provided by the reset signal terminal RST is the first potential, so as to realize the drop-down of the pull-up node PU. noise.
  • Both the gate of the second pull-down transistor M7 and the gate of the third pull-down transistor M8 may be connected to the pull-down node PD, and both the first pole of the second pull-down transistor M7 and the first pole of the third pull-down transistor M8 may be connected to the pull-down power supply terminal VGL is connected, the second pole of the second pull-down transistor M7 may be connected to the pull-up node PU, and the second pole of the third pull-down transistor M8 may be connected to the output terminal OUT.
  • the second pull-down transistor M7 can output a pull-down power signal to the pull-up node PU when the potential of the pull-down node PD is the first potential, so as to realize noise reduction of the pull-up node PU.
  • the third pull-down transistor M8 can output a pull-down power signal to the output terminal OUT when the potential of the pull-down node PD is the first potential, so as to realize noise reduction of the output terminal OUT.
  • One end of the pull-down capacitor C2 may be connected to the pull-down node PD, and the other end may be connected to the pull-down power supply terminal VGL.
  • the pull-down capacitor C2 can be used to maintain the potential of the pull-down node PD.
  • One end of the output capacitor C3 may be connected to the pull-up node PU, and the other end may be connected to the output end OUT.
  • the output capacitor C3 can be used to maintain the potential of the pull-up node PU.
  • the gate of the output transistor M9 may be connected to the pull-up node PU, the first pole may be connected to the second clock signal terminal CKB, and the second pole may be connected to the output terminal OUT.
  • the driving signal line connected to the gate driving circuit 03 includes: the first control signal terminal CN is connected to a signal line, a signal line connected to the second control signal terminal CNB, a signal line connected to the reset signal terminal RST, a signal line connected to the first clock signal terminal CK, a signal line connected to the second clock signal terminal CKB, and Pull down the signal line connected to the power supply terminal VGL and the signal line connected to the initial signal terminal.
  • the initial signal terminal is respectively connected to the first input terminal IN1 connected to the first stage shift register unit 031 and the second input terminal IN2 connected to the last stage shift register unit 031 . In this way, if the two shift register units 031 are symmetrically arranged between the two rows of target pixels 02, the two shift register units 031 can share a signal line connected to the pull-down power supply terminal VGL.
  • the shift register unit 031 shown in FIG. 8 shows the circuit structure of the shift register unit 031 located between two adjacent rows of pixels 02, and the driving signal lines (eg, the initial signal terminal Optional setting position for the connected signal line (STV).
  • the driving signal lines eg, the initial signal terminal Optional setting position for the connected signal line (STV).
  • the relatively large transistors in the shift register unit 031 can be arranged in the relatively large area 1 and the area 2, and the relatively large size of the shift register unit 031 can be arranged. Small transistors are arranged in regions 3 and 4 which are relatively small in area.
  • two transistors may be connected in series to form one transistor (eg, two transistors M7 shown in FIG.
  • the substrate and substrate 01 are separated from the same light-emitting control circuit 021 . Areas other than the area where the pixel 02 is located are larger. Therefore, effective technical support is provided for the gate driving circuit 03 to be disposed on the base substrate 01, that is, technical support is provided for a high-resolution (per pixel inch, PPI) GIA display substrate.
  • the second gate line G2n connected to the reset transistor T3 provides a gate driving signal at the first potential, and the reset transistor T3 is turned on.
  • the third gate line G3n connected to the compensation transistor T5 also provides a gate driving signal at the first potential, and the compensation transistor T5 is turned on.
  • the first initial signal terminal Vin1 can output the first initial signal at the second potential to the second pole of the driving transistor T4 in the pixel 02 in the nth row through the reset transistor T3, so as to realize the second initial signal of the driving transistor T4. Extreme reset.
  • the second initial signal terminal Vin2 can output a second initial signal to the gate of the driving transistor T4 in the nth row of pixels 02 through the compensation transistor T5, and the second initial signal can be used as the compensation data Vref1.
  • the t1 phase can also be referred to as a reset phase when driving the nth row of pixels 02 .
  • the third gate line G3n connected to the compensation transistor T5 continues to provide the gate driving signal at the first potential.
  • the compensation transistor T5 remains on.
  • the second initial signal terminal Vin2 can continue to output the second initial signal to the gate of the driving transistor T4 in the nth row of pixels 02 through the compensation transistor T5.
  • the potential of the gate of the driving transistor T4 can change with the potential of the second electrode of the driving transistor T4 until it becomes Vref1-Vth1, where Vth1 is the threshold voltage of the driving transistor T4.
  • the t2 stage may be referred to as a compensation stage when driving the nth row of pixels 02 .
  • stage t3 in the pixel 02 in the nth row, the first gate line G1n connected to the data writing transistor T2 starts to provide a gate driving signal at the first potential, and the data writing transistor T2 is turned on.
  • the data line D1 outputs a data signal to the gate of the driving transistor T4 through the data writing transistor T2.
  • the t3 stage may be referred to as a data writing stage when driving the n-th row of pixels 02 .
  • the second gate line G2(n+1) connected to the reset transistor T3 provides a gate driving signal at the first potential, and the reset transistor T3 is turned on.
  • the third gate line G3(n+1) to which the compensation transistor T5 is connected also provides the gate drive signal at the first potential, and the compensation transistor T5 is turned on.
  • the first initial signal terminal Vin1 can output the first initial signal at the second potential to the second pole of the driving transistor T4 in the pixel 02 in the n+1th row through the reset transistor T3, thereby realizing the driving transistor. Reset of the second pole of T4.
  • the second initial signal terminal Vin2 can output a second initial signal to the gate of the driving transistor T4 in the pixel 02 in the n+1 th row through the compensation transistor T5, and the second initial signal can be used as the compensation data Vref2 when the pixel of this row is driven.
  • the t4 stage may be referred to as a reset stage when the pixel 02 in the n+1 th row is driven.
  • the third gate line G3(n+1) connected to the compensation transistor T5 continues to provide the gate driving signal at the first potential.
  • the compensation transistor T5 remains on.
  • the second initial signal terminal Vin2 can continue to output the second initial signal to the gate of the driving transistor T4 in the pixel 02 in the n+1 th row through the compensation transistor T5.
  • the potential of the gate of the driving transistor T4 of the row of pixels 02 can change with the potential of the second pole until it becomes Vref2-Vth2, where Vth2 is the driving transistor Threshold voltage of T4.
  • the t5 stage can be referred to as a compensation stage when driving the pixels 02 in the n+1 th row.
  • stage t6 in the pixel 02 in the n+1th row, the first gate line G1(n+1) connected to the data writing transistor T2 starts to provide the gate driving signal at the first potential, and the data writing transistor T2 is turned on.
  • the data line D1 can output a data signal to the gate of the driving transistor T4 in the row of pixels 02 through the data writing transistor T2.
  • the t6 stage may be referred to as a data writing stage when the pixel 02 in the n+1 th row is driven.
  • the light-emitting control line EMn connected to the light-emitting control transistor T1 multiplexed by the pixels 02 in the n-th row and the pixels 02 in the n+1-th row is always A lighting control signal at a first potential is provided.
  • the DC power supply terminal VDD can output a DC power supply signal to the first pole of the driving transistor T4 included in each row of pixels 02 in the two rows of pixels 02 through the light-emitting control transistor T1.
  • the drive transistor T4 can output a drive signal to the connected light-emitting element 023 based on the DC power signal and the data signal to drive the nth row of the light-emitting element 023 to emit light.
  • the driving transistor T4 can output a driving signal to the connected light-emitting element 023 based on the DC power signal and the data signal, so as to drive the light-emitting element 023 in the n+1th row to emit light.
  • the embodiments of the present disclosure provide a display substrate. Since in the display substrate, at least two pixels located on the base substrate can reuse the same light-emitting control circuit connected to the light-emitting control line, the number of light-emitting control circuits to be set in the display substrate can be reduced, or further reduced The number of light-emitting control lines that need to be arranged on the display substrate ultimately reduces the area of the substrate that each pixel needs to occupy. Furthermore, the gate driving circuit for providing signals to the signal lines connected to the pixels and the driving signals connected to the gate driving circuit can be arranged on the base substrate.
  • the display substrate provided by the embodiment of the present disclosure has higher resolution.
  • FIG. 12 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure.
  • the display device may include: a source driving circuit 100 and a display substrate 000 as shown in any one of FIGS. 1 to 3 , 6 , 7 and 10 .
  • the source driving circuit 100 may be connected to a plurality of data lines D1 to Dm in the display substrate 000, and the source driving circuit 100 may be used to provide data signals for each data line.
  • FIG. 12 also shows a gate driving circuit 03, a plurality of first gate lines G11 to G1m, a plurality of second gate lines G21 to G2m, a plurality of third gate lines G3 to G3m, and A plurality of light emission control lines EM1 to EMn.
  • the gate driving circuit 03 may be connected to a plurality of first gate lines G11 to G1m, a plurality of second gate lines G21 to G2m, a plurality of third gate lines G3 to G3m, and a plurality of emission control lines EM1 to EMn.
  • the gate driving circuit 03 can be used to provide gate driving signals for a plurality of first gate lines G11 to G1m, a plurality of second gate lines G21 to G2m and a plurality of third gate lines G3 to G3m, and to control the light emission of a plurality of The lines EM1 to EMn provide light emission control driving signals.
  • the gate driving circuit 03 may actually include: a gate driving circuit for providing a gate driving signal to the first gate line, a gate driving circuit for providing a gate driving signal to the second gate line There are four gate driving circuits in total, including a gate driving circuit for providing a gate driving signal to the third gate line, and a gate driving circuit for providing a light-emitting control driving signal to the light-emitting control line.
  • each gate driving circuit may be composed of at least two cascaded shift register units 031, and each shift register unit 031 may be associated with a corresponding signal line (eg, the first gate line) connect.
  • the display device may be: OLED display device, electronic paper, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, and any other product or component with display function.

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Abstract

一种显示基板（000）及显示装置，属于显示技术领域。由于显示基板（000）中，位于衬底基板（01）上的至少两个像素（02）可以复用同一个连接发光控制线（EM1,…,EM（n+1））的发光控制电路（021），因此可以减少显示基板（000）中所需设置的发光控制电路（021）的数量，或是再减少显示基板（000）上所需设置的发光控制线（EM1,…,EM（n+1））的数量，最终使得每个像素（02）所需占用衬底基板（01）的面积较小。进而，可以使得为像素（02）所连接的信号线提供信号的栅极驱动电路（03），以及栅极驱动电路（03）所连接的驱动信号线（L1,…,Li）均能够设置于衬底基板（01）上。显示基板（000）的分辨率较高。

Description

显示基板及显示装置
本公开要求于2020年7月21日提交的申请号为202010707527.3、发明名称为“显示基板及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板及显示装置。
背景技术
有机发光二极管(organic light emitting diode，OLED)显示基板因其自发光、宽视角及响应速度快等优点被广泛应用于显示领域中。
相关技术中，OLED显示基板包括衬底基板，以及位于衬底基板上的多个像素，每个像素均包括：发光控制电路、发光驱动电路和发光元件。其中，发光控制电路能够响应于其所连接的发光控制线提供的发光控制信号，向发光驱动电路提供直流电源信号，发光驱动电路能够响应于其所连接的栅线提供的栅极驱动信号以及接收到的直流电源信号，向发光元件提供发光驱动信号。且，不同的像素连接的发光控制电路不同。
由于不同的像素连接的发光控制电路不同，因此导致显示基板中需要设置较多数量的发光控制线，该多条发光控制线会占用衬底基板的较大面积，不利于高分辨率的实现。
发明内容
本公开实施例提供了一种显示基板及显示装置。所述技术方案如下：
一方面，提供了一种显示基板，所述显示基板包括：
衬底基板；
位于所述衬底基板上且阵列排布的多个像素，每个所述像素均包括：发光控制电路、发光驱动电路和发光元件，且至少两个所述像素复用同一个所述发光控制电路；
以及，位于所述衬底基板上的栅极驱动电路、多条发光控制线、多条栅线和多条驱动信号线，所述栅极驱动电路分别与所述多条驱动信号线、所述多条发光控制线和所述多条栅线连接，所述多条发光控制线与各个所述像素包括的所述发光控制电路连接，所述多条栅线与各个所述像素包括的所述发光驱动电路连接，所述栅极驱动电路用于响应于所述多条驱动信号线提供的驱动信号，向所述多条发光控制线输出发光控制信号，并向所述多条栅线输出栅极驱动信号。
可选的，复用同一个所述发光控制电路的至少两个所述像素位于同一列。
可选的，复用同一个所述发光控制电路的至少两个所述像素相邻。
可选的，位于同一列的每两个所述像素复用同一个所述发光控制电路。
可选的，复用同一个所述发光控制电路的两个所述像素，对称排布于所述发光控制电路连接的所述发光控制线的两侧。
可选的，每条所述驱动信号线均位于相邻两列所述像素之间。
可选的，每相邻两列所述像素之间，设置有至多两条所述驱动信号线。
可选的，所述栅极驱动电路包括：级联的多个移位寄存器单元；
至少两个级联的所述移位寄存器单元位于相邻两行像素之间。
可选的，至少两个级联的所述移位寄存器单元位于相邻两行目标像素之间；
所述两行目标像素中，一行所述目标像素所连接的发光控制电路，与另一行所述目标像素所连接的发光控制电路不同。
可选的，每相邻两行所述目标像素之间设置有两个级联的所述移位寄存器单元；
其中，一个所述移位寄存器单元与一行所述目标像素连接，另一个所述移位寄存器单元与另一行所述目标像素连接。
可选的，两个级联的所述移位寄存器单元对称排布于所述两行目标像素之间。
可选的，所述移位寄存器单元包括：输入子电路、下拉控制子电路、下拉子电路和输出子电路；
所述输入子电路分别与第一输入端、第二输入端、第一控制信号端、第二控制信号端和上拉节点连接，所述输入子电路用于响应于所述第一输入端提供的第一输入信号，向所述上拉节点输出所述第一控制信号端提供的第一控制信 号，以及响应于所述第二输入端提供的第二输入信号，向所述上拉节点输出所述第二控制信号端提供的第二控制信号；
所述下拉控制子电路分别与第一时钟信号端、所述上拉节点、下拉电源端、下拉节点和输出端连接，所述下拉控制子电路用于响应于所述第一时钟信号端提供的第一时钟信号，向所述下拉节点输出所述第一时钟信号，以及响应于所述上拉节点的电位和所述输出端提供的输出信号，向所述下拉节点输出所述下拉电源端提供的下拉电源信号；
所述下拉子电路分别与复位信号端、所述下拉节点、所述下拉电源端、所述上拉节点和所述输出端连接，所述下拉子电路用于响应于所述下拉节点的电位，向所述上拉节点和所述输出端输出所述下拉电源信号，以及响应于所述复位信号端提供的复位信号，向所述上拉节点输出所述下拉电源信号；
所述输出子电路分别与所述上拉节点、第二时钟信号端和所述输出端连接，所述输出子电路用于响应于所述上拉节点的电位，向所述输出端输出所述第二时钟信号端提供的第二时钟信号。
可选的，所述显示基板还包括：位于所述衬底基板上的多条数据线；
所述多条栅线包括：多条第一栅线、多条第二栅线和多条第三栅线；所述发光控制电路包括：发光控制晶体管；所述发光驱动电路包括：数据写入晶体管、复位晶体管、驱动晶体管、补偿晶体管和存储电容；
所述数据写入晶体管的栅极与一条所述第一栅线连接，第一极与所述驱动晶体管的栅极连接，第二极与一条所述数据线连接；所述驱动晶体管的第一极与所述发光控制晶体管的第一极连接，第二极与所述发光元件连接；所述发光控制晶体管的栅极与一条所述发光控制线连接，第二极与直流电源端连接；所述复位晶体管的栅极与一条所述第二栅线连接，第一极与第一初始信号端连接，第二极与所述驱动晶体管的第二极连接；所述补偿晶体管的栅极与一条所述第三栅线连接，第一极与所述第二初始信号端连接，第二极与所述驱动晶体管的栅极连接。
另一方面，提供了一种显示装置，所述显示装置包括：源极驱动电路以及如上述方面所述的显示基板；
所述源极驱动电路与所述显示基板中的多条数据线连接，所述源极驱动电路用于为每条所述数据线提供数据信号。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开实施例提供的一种显示基板的结构示意图；
图2是本公开实施例提供的另一种显示基板的结构示意图；
图3是本公开实施例提供的又一种显示基板的结构示意图；
图4是本公开实施例提供的一种相邻两个像素的电路结构示意图；
图5是本公开实施例提供的一种相邻两个像素的可选结构版图；
图6是本公开实施例提供的再一种显示基板的结构示意图；
图7是本公开实施例提供的再一种显示基板的结构示意图；
图8是本公开实施例提供的一种移位寄存器单元的结构示意图；
图9是本公开实施例提供的另一种移位寄存器单元的结构示意图；
图10是本公开实施例提供的再一种显示基板的结构示意图；
图11是本公开实施例提供的一种像素工作时序图；
图12是本公开实施例提供的一种显示装置的结构示意图。
具体实施方式
为使本公开实施例的发明构思的目的、技术方案和优点更加清楚，下面将结合附图和一些实施例对本公开实施例保护的发明构思做详细描述。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件，根据在电路中的作用本公开的实施例所采用的晶体管主要为开关晶体管。由于这里采用的开关晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本公开实施例中，将其中源极称为第一极，漏极称为第二极。或将其中漏极称为第一极，源极称为第二极按附图中的形态规定晶体管的中间端为栅极、信号输入端为源极、信号输出端为漏极。此外，本公开实施例所采用的开关晶体管可以为P型开关晶体管和N型开关晶体管中的任一种，其中，P型开关晶体管在栅极为低电平时导通，在栅极为高电平时截止，N型开关晶体管在栅极为高电平时导通，在栅极为低电平时截止。
图1是本公开实施例提供的一种显示基板的结构示意图。如图1所示，该显示基板可以包括：衬底基板01，以及位于衬底基板01上且阵列排布的多个像素02。图2是本公开实施例提供的另一种显示基板的结构示意图。结合图1和图2可以看出：每个像素02均可以包括：发光控制电路021、发光驱动电路022和发光元件023。且至少两个像素02可以复用同一个发光控制电路021，即至少两个像素02可以在同一个发光控制电路021的驱动下工作。
继续参考图2可以看出，显示基板还可以包括：位于衬底基板01上的栅极驱动电路03、多条发光控制线(如，图2示出的EM1至EMn)、多条栅线(如，图2示出的G1至Gm)和多条驱动信号线(如图2示出的L1至Li)。
其中，栅极驱动电路03可以分别与多条驱动信号线、多条发光控制线和多条栅线连接。多条发光控制线可以与各个像素02包括的发光控制电路021连接，多条栅线可以与各个像素02包括的发光驱动电路022连接。栅极驱动电路03可以用于响应于多条驱动信号线提供的驱动信号，向多条发光控制线输出发光控制信号，并向多条栅线输出栅极驱动信号。即，栅极驱动电路03可以在多条驱动信号线提供的驱动信号的驱动下工作。
可选的，一般多行像素02与多条栅线可以一一对应连接，且多行像素02与多条发光控制线也可以一一对应连接。即位于同一行的多个像素02中，每个像素02包括的发光控制电路021可以与同一条发光控制线连接，每个像素02包括的发光驱动电路022可以与同一条栅线连接。相应的，在本公开实施例中，显示基板包括的栅线的条数和像素的行数相同。且由于至少两个像素02可以复用同一个发光控制电路021，因此若该至少两个像素02位于同一行，则相应的可以减少所需设置的发光控制电路021的数量；若该至少两个像素02位于同一列，则相应的既可以减少所需设置的发光控制电路021的数量，且可以减少所需设置的发光控制线的数量。如此，均可以在不影响像素02正常显示的前提下，达到优化像素空间的效果，即相对于相关技术减小像素02在衬底基板01上所占用的面积。进而，即增大了衬底基板01上剩余空间的面积，该剩余空间可以用于可靠设置栅极驱动电路03和栅极驱动电路03所需连接的驱动信号线。由此，即得到了将栅极驱动电路03设置于基板内(gate drive in array，GIA)的显示基板，即GIA显示基板。
另外，继续参考图2可以看出，每个像素02中，发光控制电路021还可以与发光驱动电路022连接，发光驱动电路022还可以与发光元件023连接。发光控制电路021可以用于响应于所连接的发光控制线提供的发光控制信号，向所连接的发光驱动电路022输出直流电源信号。发光驱动电路022可以用于响应于所连接的栅线提供的栅极驱动信号和接收到的直流电源信号，向所连接的发光元件023输出驱动信号，以驱动发光元件023发光。
综上所述，本公开实施例提供了一种显示基板。由于该显示基板中，位于衬底基板上的至少两个像素可以复用同一个连接发光控制线的发光控制电路，因此可以减少显示基板中所需设置的发光控制电路的数量，或是再减少显示基板上所需设置的发光控制线的数量，即最终使得每个像素所需占用衬底基板的面积较小。进而，可以使得为像素所连接的信号线提供信号的栅极驱动电路，以及栅极驱动电路所连接的驱动信号均能够设置于衬底基板上。本公开实施例提供的显示基板的分辨率较高。
可选的，结合图2可以看出，在本公开实施例中，复用同一个发光控制电路021的至少两个像素02可以位于同一列。如此，结合上述实施例记载，相对于相关技术，不仅可以减少衬底基板01上所需设置的发光控制电路021的数量，而且可以减少衬底基板01上所需设置的发光控制线的数量。
例如，假设显示基板共包括m行像素02，若位于同一列的至少两个像素02复用同一个发光控制电路021，则衬底基板上01设置的发光控制线的数量小于像素02的行数。即，图2中n小于m，其中m和n均可以为大于1的整数。
可选的，复用同一个发光控制电路021的至少两个像素02不仅位于同一列，且可以相邻。如此，可以便于版图布局，以及信号走线。
例如，图3以位于同一列且相邻的每两个像素02复用同一个发光控制电路021为例示出又一种显示基板。且，图3仅示意性示出相邻的第n行像素02和第n+1行像素02复用同一个发光控制电路021，以及相邻的第n+2行像素02和第n+3行像素02复用同一个发光控制电路021。结合图3可以进一步看出，在复用同一个发光控制电路021的两个像素02位于同一列时，相邻两个像素02也可以复用同一条发光控制线(如，EMn和EM(n+1))。
可选的，结合图3，以位于第一列且相邻的第n行像素02和第n+1行像素 02为例，图4示出了该两个像素02的可选电路图，图5示出了该两个像素02的可选电路版图。结合图3至图5，在本公开实施例中，复用同一个发光控制电路021的两个像素02，可以对称排布于其所复用的发光控制电路021连接的发光控制线EMn的两侧。即，该两个像素02中，一个像素02包括的各晶体管和所连接的各条信号线，与另一个像素02包括的各晶体管和所连接的各条信号线均可以对称设置于发光控制线EMn的两侧。如此设计，不仅可以进一步便于版图布局，信号走线，且可以使得信号线集中设置，进一步优化了像素空间。
再结合图4和图5，在本公开实施例中，为了可靠驱动像素02包括的发光元件023发光，该显示基板还可以包括：位于衬底基板01上的多条数据线。多条栅线可以包括：多条第一栅线、多条第二栅线和多条第三栅线。
其中，数据线的条数与像素列数可以相同，第一栅线的条数、第二栅线的条数和第三栅线的条数均可以与像素行数相同。图4和图5仅示出一条数据线D1，两条第一栅线G1n和G1(n+1)，两条第二栅线G2n和G2(n+1)，以及两条第三栅线G3n和G3(n+1)。
继续参考图4和图5，每个像素02中，发光控制电路021可以包括：发光控制晶体管T1。发光驱动电路022可以包括：数据写入晶体管T2、复位晶体管T3、驱动晶体管T4、补偿晶体管T5和存储电容C1。
数据写入晶体管T2的栅极可以与一条第一栅线连接，第一极可以与驱动晶体管T4的栅极连接，第二极可以与一条数据线D1连接。其中，第n行像素02中的数据写入晶体管T2的栅极与第一栅线G1n连接，第n+1行像素02中的数据写入晶体管T2的栅极与第一栅线G1(n+1)连接。
驱动晶体管T4的第一极可以与发光控制晶体管T1的第一极连接，第二极可以与发光元件023连接，发光元件023还可以与电源端VSS连接。
发光控制晶体管T1的栅极可以与一条发光控制线EMn连接，发光控制晶体管T1的第二极可以与直流电源端VDD连接。
复位晶体管T3的栅极可以与一条第二栅线连接，第一极可以与第一初始信号端Vin1连接，第二极可以与驱动晶体管T4的第二极连接。其中，第n行像素02中的复位晶体管T3的的栅极与第二栅线G2n连接，第n+1行像素02中的复位晶体管T3的栅极与第二栅线G2(n+1)连接。
补偿晶体管T5的栅极可以与一条第三栅线连接，第一极可以与第二初始信 号端Vin2连接，第二极可以与驱动晶体管T4的栅极连接。其中，第n行像素02中的补偿晶体管T5的的栅极与第三栅线G3n连接，第n+1行像素02中的补偿晶体管T5栅极与第三栅线G3(n+1)连接。
需要说明的是，以上仅是示意性示出一种像素02的可选结构，为5T1C(即，五个晶体管和一个电容)结构。当然，本公开实施例对像素02的结构不做限定，其还可以是其他结构，如7T1C结构。
下述实施例均以位于同一列且每相邻两个像素02复用同一个发光控制电路021为例示出显示基板的可选结构：
可选的，在本公开实施例中，栅极驱动电路03所连接的每条驱动信号线可以均位于相邻两列像素02之间。例如，参考图6，其示出了再一种显示基板，由于位于同一列且每相邻两个像素02复用同一个发光控制电路021，因此使得在每相邻两列像素02之间可以预留有额外区域，如图6示出的区域5和区域6。相应的，栅极驱动电路03所连接的驱动信号线可以设置于该区域5和6中。
可选的，由于每相邻两列像素02之间的区域有限，因此为了确保驱动信号线的可靠设置，每相邻两列像素02之间，可以设置有至多两条驱动信号线。
在本公开实施例中，栅极驱动电路03可以包括：级联的多个移位寄存器单元031。至少两个级联的移位寄存器单元031可以位于相邻两行像素02之间。
例如，再结合图6，由于位于同一列且每相邻两个像素02复用同一个发光控制电路021，因此使得在每相邻两行像素02之间也可以预留有额外区域，如图6示出的区域1、区域2、区域3和区域4。相应的，至少两个级联的移位寄存器单元031可以设置于每相邻两行像素02之间的区域1至区域4中。
并且，为了便于信号走线，结合图6，至少两个级联的移位寄存器单元031可以位于相邻两行目标像素02之间。该两行目标像素02中，一行目标像素02所连接的发光控制电路，与另一行目标像素02所连接的发光控制电路不同。即，少两个级联的移位寄存器单元031可以位于为未复用发光控制电路021的两行像素02之间。
可选的，图7是本公开实施例提供的再一种显示基板的结构示意图。如图7所示，每相邻两行目标像素02之间可以仅设置有两个级联的移位寄存器单元031。其中，一个移位寄存器单元031可以与一行目标像素02连接，另一个移位寄存器单元031可以与另一行目标像素02连接(图7未示出)。
可选的，该两个级联的移位寄存器单元031可以对称排布于该两行目标像素之间。即一个移位寄存器单元031包括的各晶体管，与另一个移位寄存器单元031包括的各晶体管均对称设置。如此，可以使得一些驱动信号线(如，提供直流信号的电源信号)可以被共用，进一步优化了GIA空间，即减少了移位寄存器单元031所需占用衬底基板01的面积。
图8是本公开实施例提供的一种移位寄存器单元的结构示意图。如图8所示，移位寄存器单元031可以包括：输入子电路0311、下拉控制子电路0312、下拉子电路0313和输出子电路0314。
输入子电路0311可以分别与第一输入端IN1、第二输入端IN2、第一控制信号端CN、第二控制信号端CNB和上拉节点PU连接。输入子电路0311可以用于响应于第一输入端IN1提供的第一输入信号，向上拉节点PU输出第一控制信号端CN提供的第一控制信号，以及响应于第二输入端IN2提供的第二输入信号，向上拉节点PU输出第二控制信号端CNB提供的第二控制信号。
示例的，输入子电路0311可以在第一输入端IN1提供的第一输入信号的电位为第一电位时，向上拉节点PU输出第一控制信号端CN提供的第一控制信号。以及，可以在第二输入端IN2提供的第二输入信号的电位为第一电位时，向上拉节点PU输出第二控制信号端CNB提供的第二控制信号。
可选的，第一输入端IN1可以与上一级移位寄存器单元031的输出端连接，第二输入端IN2可以与下一级移位寄存器单元031的输出端连接。第一控制信号的电位和第二控制信号的电位可以互补。即在第一控制信号的电位为第一电位时，第二控制信号的电位为第二电位；在第一控制信号的电位为第二电位时，第二控制信号的电位为第一电位。其中，第一电位可以为有效电位，第二电位可以为无效电位。在晶体管为N型晶体管时，第一电位相对于第二电位可以为高电位；在晶体管为P型晶体管时，第一电位相对于第二电位可以为低电位。
另，对于第一级移位寄存器单元031而言，因其不具有上一级移位寄存器单元031，对于最后一级移位寄存器单元031而言，因其不具有下一级移位寄存器单元031，故为了保证栅极驱动电路03的正常工作，第一级移位寄存器单元031和最后一级移位寄存器单元031可以与初始信号端连接，该初始信号端可以用于向第一级移位寄存器单元031所连接的第一输入端IN1提供处于第一电位的初始信号，且可以用于向最后一级移位寄存器单元031所连接的第二输入端 IN2提供处于第一电位的初始信号，从而确保第一级移位寄存器单元031和最后一级移位寄存器单元031的正常工作。
下拉控制子电路0312可以分别与第一时钟信号端CK、上拉节点PU、下拉电源端VGL、下拉节点PD和输出端OUT连接。下拉控制子电路0312可以用于响应于第一时钟信号端CK提供的第一时钟信号，向下拉节点PD输出第一时钟信号，以及响应于上拉节点PU的电位和输出端OUT提供的输出信号，向下拉节点PD输出下拉电源端VGL提供的下拉电源信号。
示例的，下拉控制子电路0312可以在第一时钟信号端CK提供的第一时钟信号的电位为第一电位时，向下拉节点PD输出第一时钟信号，以实现对下拉节点PD的充电。下拉控制子电路0312可以在上拉节点PU的电位为第一电位时，向下拉节点PD输出下拉电源端VGL提供的下拉电源信号，该下拉电源信号的电位可以为第二电位，以实现对下拉节点PD的降噪。以及，下拉控制子电路0312可以在输出端OUT提供的输出信号的电位为第一电位时，向下拉节点PD输出下拉电源信号，以实现对下拉节点PD的降噪。
下拉子电路0313可以分别与复位信号端RST、下拉节点PD、下拉电源端VGL、上拉节点PU和输出端OUT连接。下拉子电路0313可以用于响应于下拉节点PD的电位，向上拉节点PU和输出端OUT输出下拉电源信号，以及响应于复位信号端RST提供的复位信号，向上拉节点PU输出下拉电源信号。
示例的，下拉子电路0313可以在下拉节点PD的电位为第一电位时，向上拉节点PU和输出端OUT输出下拉电源信号，以实现对上拉节点PU和输出端OUT的降噪。以及，可以在复位信号端RST提供的复位信号的电位为第一电位时，向上拉节点PU输出下拉电源信号，以实现对上拉节点PU的降噪。
输出子电路0314可以分别与上拉节点PU、第二时钟信号端CKB和输出端OUT连接。输出子电路0314可以用于响应于上拉节点PU的电位，向输出端OUT输出第二时钟信号端CKB提供的第二时钟信号。
示例的，输出子电路0314可以在上拉节点PU的电位为第一电位时，向输出端OUT输出第二时钟信号端CKB提供的第二时钟信号。该第二时钟信号可以作为栅极驱动信号提供至栅线，或，作为发光控制信号提供至发光控制线。
图9是本公开实施例提供的另一种移位寄存器单元的结构示意图。如图9所示，输入子电路0311可以包括：第一输入晶体管M1和第二输入晶体管M2。 下拉控制子电路0312可以包括：第一下拉控制晶体管M3、第二下拉控制晶体管M4和第三下拉控制晶体管M5。下拉子电路0313可以包括：第一下拉晶体管M6、第二下拉晶体管M7、第三下拉晶体管M8和下拉电容C2。输出子电路0314可以包括：输出晶体管M9和输出电容C3。
其中，第一输入晶体管M1的栅极可以与第一输入端IN1连接，第一极可以与第一控制信号端CN连接，第二极可以与上拉节点PU连接。相应的，第一输入晶体管M1可以在第一输入端IN1提供的第一输入信号的电位为第一电位时，向上拉节点PU输出第一控制信号端CN提供的第一控制信号，实现对上拉节点PU的充电。
第二输入晶体管M2的栅极可以与第二输入端IN2连接，第一极可以与第二控制信号端CNB连接，第二极可以与上拉节点PU连接。相应的，第二输入晶体管M2可以在第二输入端IN2提供的第二输入信号的电位为第一电位时，向上拉节点PU输出第二控制信号端CNB提供的第二控制信号，实现对上拉节点PU的复位。
第一下拉控制晶体管M3的栅极和第一极可以均与第一时钟信号端CK连接，第二极可以与下拉节点PD连接。相应的，第一下拉控制晶体管M3可以在第一时钟信号端CK提供的第一时钟信号的电位为第一电位时，向下拉节点PD输出第一时钟信号，实现对下拉节点PD的充电。
第二下拉控制晶体管M4的栅极可以与上拉节点PU连接，第一极可以与下拉电源端VGL连接，第二极可以与下拉节点PD连接。相应的，第二下拉控制晶体管M4可以在上拉节点PU的电位为第一电位时，向下拉节点PD输出下拉电源信号，实现对下拉节点PD的降噪。
第三下拉控制晶体管M5的栅极可以与输出端OUT连接，第一极可以与下拉电源端VGL连接，第二极可以与下拉节点PD连接。相应的，第三下拉控制晶体管M5可以在输出端OUT提供的输出信号的电位为第一电位时，向下拉节点PD输出下拉电源信号，实现对下拉节点PD的降噪。
第一下拉晶体管M6的栅极可以与复位信号端RST连接，第一极可以与下拉电源端VGL连接，第二极可以与上拉节点PU连接。相应的，第一下拉晶体管M6可以在复位信号端RST提供的复位信号的电位为第一电位时，向上拉节点PU输出下拉电源端VGL提供的下拉电源信号，实现对上拉节点PU的降噪。
第二下拉晶体管M7的栅极和第三下拉晶体管M8的栅极均可以与下拉节点PD连接，第二下拉晶体管M7的第一极和第三下拉晶体管M8的第一极均可以与下拉电源端VGL连接，第二下拉晶体管M7的第二极可以与上拉节点PU连接，第三下拉晶体管M8的第二极可以与输出端OUT连接。相应的，第二下拉晶体管M7可以在下拉节点PD的电位为第一电位时，向上拉节点PU输出下拉电源信号，实现对上拉节点PU的降噪。第三下拉晶体管M8可以在下拉节点PD的电位为第一电位时，向输出端OUT输出下拉电源信号，实现对输出端OUT的降噪。
下拉电容C2的一端可以与下拉节点PD连接，另一端可以与下拉电源端VGL连接。下拉电容C2可以用于保持下拉节点PD的电位。
输出电容C3的一端可以与上拉节点PU连接，另一端可以与输出端OUT连接。输出电容C3可以用于保持上拉节点PU的电位。
输出晶体管M9的栅极可以与上拉节点PU连接，第一极可以与第二时钟信号端CKB连接，第二极可以与输出端OUT连接。
相应的，对于图7和图8示出的移位寄存器单元031所属栅极驱动电路03而言，该栅极驱动电路03所连接的驱动信号线即包括：第一控制信号端CN所连接的信号线，第二控制信号端CNB所连接的信号线，复位信号端RST所连接的信号线，第一时钟信号端CK所连接的信号线，第二时钟信号端CKB所连接的信号线，以及下拉电源端VGL所连接的信号线，以及初始信号端所连接的信号线。结合图8实施例的记载，该初始信号端分别与第一级移位寄存器单元031所连接的第一输入端IN1，和最后一级移位寄存器单元031所连接的第二输入端IN2连接。如此，若两个移位寄存器单元031对称排布于两行目标像素02之间，则两个移位寄存器单元031可以共用一条下拉电源端VGL所连接的信号线。
再结合图10，其以图8示出的移位寄存器单元031，示出了位于相邻两行像素02之间的移位寄存器单元031的电路结构，以及驱动信号线(如，初始信号端所连接的信号线STV)的可选设置位置。结合图6至图9可知，在布局时，可以将移位寄存器单元031中尺寸相对较大的晶体管设置于面积相对较大的区域1和区域2中，将移位寄存器单元031中尺寸相对较小的晶体管设置于面积相对较小的区域3和区域4中。另，再参考图10，还可以将两个晶体管串联形成一个晶体管(如，图10示出的两个晶体管M7)，或，将两个电容串联形成 一个电容(如，图10示出的两个电容C2，和两个电容C3)，从而使得可以在衬底基板01有限的空间内，可靠设置下移位寄存器单元031中的所有晶体管。
在衬底基板01面积确定的情况下，对比未复用发光控制电路021的相关技术，本公开实施例通过设置至少两个像素02复用同一个发光控制电路021，使得衬底基板01中除像素02所在区域之外的其他区域面积较大。由此，为栅极驱动电路03设置于衬底基板01上提供了有效的技术支持，即为高分辨率(per pixel inch，PPI)的GIA显示基板提供了技术支持。
假设像素02中的晶体管均为N型晶体管，结合图4示出的复用同一个发光控制电路021的相邻两个像素02，对本公开实施例提供的像素工作原理进行介绍：图11是本公开实施例提供的一种像素工作时序图。
参考图11，在t1阶段，第n行像素02中，复位晶体管T3连接的第二栅线G2n提供处于第一电位的栅极驱动信号，复位晶体管T3开启。补偿晶体管T5连接的第三栅线G3n也提供处于第一电位的栅极驱动信号，补偿晶体管T5开启。相应的，第一初始信号端Vin1可以通过复位晶体管T3，向第n行像素02中的驱动晶体管T4的第二极输出处于第二电位的第一初始信号，从而实现对驱动晶体管T4的第二极的复位。第二初始信号端Vin2可以通过补偿晶体管T5，向第n行像素02中的驱动晶体管T4的栅极输出第二初始信号，第二初始信号可以作为补偿数据Vref1。t1阶段也可以称为驱动第n行像素02时的复位阶段。
在t2阶段，第n行像素02中，补偿晶体管T5连接的第三栅线G3n持续提供处于第一电位的栅极驱动信号。补偿晶体管T5保持开启。第二初始信号端Vin2可以通过补偿晶体管T5，继续向第n行像素02中的驱动晶体管T4的栅极输出第二初始信号。在存储电容C1耦合作用下，驱动晶体管T4的栅极的电位可以随着驱动晶体管T4的第二极电位变化，直至变为Vref1-Vth1，Vth1为该驱动晶体管T4的阈值电压。t2阶段可以称为驱动第n行像素02时的补偿阶段。
在t3阶段，第n行像素02中，数据写入晶体管T2连接的第一栅线G1n开始提供处于第一电位的栅极驱动信号，数据写入晶体管T2开启。数据线D1通过该数据写入晶体管T2向驱动晶体管T4的栅极输出数据信号。t3阶段可以称为驱动第n行像素02时的数据写入阶段。
在t4阶段，第n+1行像素02中，复位晶体管T3连接的第二栅线G2(n+1)提供处于第一电位的栅极驱动信号，该复位晶体管T3开启。补偿晶体管T5连 接的第三栅线G3(n+1)也提供处于第一电位的栅极驱动信号，该补偿晶体管T5开启。相应的，第一初始信号端Vin1可以通过该复位晶体管T3，向第n+1行像素02中的驱动晶体管T4的第二极输出处于第二电位的第一初始信号，从而实现对该驱动晶体管T4的第二极的复位。第二初始信号端Vin2可以通过补偿晶体管T5，向第n+1行像素02中的驱动晶体管T4的栅极输出第二初始信号，第二初始信号可以作为该行像素驱动时的补偿数据Vref2。t4阶段可以称为驱动第n+1行像素02时的复位阶段。
在t5阶段，第n+1行像素02中，补偿晶体管T5连接的第三栅线G3(n+1)持续提供处于第一电位的栅极驱动信号。补偿晶体管T5保持开启。第二初始信号端Vin2可以通过补偿晶体管T5，继续向第n+1行像素02中的驱动晶体管T4的栅极输出第二初始信号。在该行像素02中存储电容C1的耦合作用下，该行像素02的驱动晶体管T4的栅极的电位可以随着其第二极的电位变化，直至变为Vref2-Vth2，Vth2为该驱动晶体管T4的阈值电压。t5阶段可以称为驱动第n+1行像素02时的补偿阶段。
在t6阶段，第n+1行像素02中，数据写入晶体管T2连接的第一栅线G1(n+1)开始提供处于第一电位的栅极驱动信号，该数据写入晶体管T2开启。数据线D1可以通过该数据写入晶体管T2，向该行像素02中驱动晶体管T4的栅极输出数据信号。t6阶段可以称为驱动第n+1行像素02时的数据写入阶段。
需要说明的是，参考图10，在阶段t1、阶段t2、阶段t4和阶段t5中，第n行像素02和第n+1行像素02复用的发光控制晶体管T1连接的发光控制线EMn一直提供处于第一电位的发光控制信号。直流电源端VDD可以通过该发光控制晶体管T1向该两行像素02中，每行像素02包括的驱动晶体管T4的第一极输出直流电源信号。在t3阶段之后，第n行像素02中，驱动晶体管T4即可以基于该直流电源信号和数据信号，向所连接的发光元件023输出驱动信号，以驱动第n行发光元件023发光。在t6阶段之后，第n+1行像素02中，驱动晶体管T4即可以基于该直流电源信号和数据信号，向所连接的发光元件023输出驱动信号，以驱动第n+1行发光元件023发光。
综上所述，本公开实施例提供了一种显示基板。由于该显示基板中，位于衬底基板上的至少两个像素可以复用同一个连接发光控制线的发光控制电路，因此可以减少显示基板中所需设置的发光控制电路的数量，或是再减少显示基 板上所需设置的发光控制线的数量，即最终使得每个像素所需占用衬底基板的面积较小。进而，可以使得为像素所连接的信号线提供信号的栅极驱动电路，以及栅极驱动电路所连接的驱动信号均能够设置于衬底基板上。本公开实施例提供的显示基板的分辨率较高。
图12是本公开实施例提供的一种显示装置的结构示意图。如图12所示，该显示装置可以包括：源极驱动电路100以及如图1至图3、图6、图7和图10任一所示的显示基板000。
其中，该源极驱动电路100可以与显示基板000中的多条数据线D1至Dm连接，该源极驱动电路100可以用于为每条数据线提供数据信号。
另，图12还示出了显示基板000中包括的栅极驱动电路03、多条第一栅线G11至G1m、多条第二栅线G21至G2m、多条第三栅线G3至G3m和多条发光控制线EM1至EMn。栅极驱动电路03可以与多条第一栅线G11至G1m、多条第二栅线G21至G2m、多条第三栅线G3至G3m和多条发光控制线EM1至EMn连接。栅极驱动电路03可以用于为多条第一栅线G11至G1m、多条第二栅线G21至G2m和多条第三栅线G3至G3m提供栅极驱动信号，并为多条发光控制线EM1至EMn提供发光控制驱动信号。
可选的，在本公开实施例中，为了实现向多条第一栅线G11至G1m、多条第二栅线G21至G2m、多条第三栅线G3至G3m和多条发光控制线EM1至EMn可靠提供驱动信号，栅极驱动电路03其实可以包括：用于向第一栅线提供栅极驱动信号的栅极驱动电路，用于向第二栅线提供栅极驱动信号的栅极驱动电路，用于向第三栅线提供栅极驱动信号的栅极驱动电路，以及用于向发光控制线提供发光控制驱动信号的栅极驱动电路共四个栅极驱动电路。且，结合图7，每个栅极驱动电路均可以由至少两个级联的移位寄存器单元031组成，每个移位寄存器单元031可以与对应的一条信号线(如，第一栅线)连接。
可选的，该显示装置可以为：OLED显示装置、电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框等任何具有显示功能的产品或部件。
应当理解的是，在本文中提及的“多个”是指两个或两个以上。以上所述仅为本公开的可选实施例，并不用以限制本公开，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (15)

  1. 一种显示基板，其中，所述显示基板包括：
    衬底基板；
    位于所述衬底基板上且阵列排布的多个像素，每个所述像素均包括：发光控制电路、发光驱动电路和发光元件，且至少两个所述像素复用同一个所述发光控制电路；
    以及，位于所述衬底基板上的栅极驱动电路、多条发光控制线、多条栅线和多条驱动信号线，所述栅极驱动电路分别与所述多条驱动信号线、所述多条发光控制线和所述多条栅线连接，所述多条发光控制线与各个所述像素包括的所述发光控制电路连接，所述多条栅线与各个所述像素包括的所述发光驱动电路连接，所述栅极驱动电路用于响应于所述多条驱动信号线提供的驱动信号，向所述多条发光控制线输出发光控制信号，并向所述多条栅线输出栅极驱动信号。
  2. 根据权利要求1所述的显示基板，其中，复用同一个所述发光控制电路的至少两个所述像素位于同一列。
  3. 根据权利要求2所述的显示基板，其中，复用同一个所述发光控制电路的至少两个所述像素相邻。
  4. 根据权利要求3所述的显示基板，其中，位于同一列的每两个所述像素复用同一个所述发光控制电路。
  5. 根据权利要求4所述的显示基板，其中，复用同一个所述发光控制电路的两个所述像素，对称排布于所述发光控制电路连接的所述发光控制线的两侧。
  6. 根据权利要求1至5任一所述的显示基板，其中，每条所述驱动信号线均位于相邻两列所述像素之间。
  7. 根据权利要求6所述的显示基板，其中，每相邻两列所述像素之间，设置有至多两条所述驱动信号线。
  8. 根据权利要求1至7任一所述的显示基板，其中，所述栅极驱动电路包括：级联的多个移位寄存器单元；
    至少两个级联的所述移位寄存器单元位于相邻两行像素之间。
  9. 根据权利要求8所述的显示基板，其中，至少两个级联的所述移位寄存器单元位于相邻两行目标像素之间；
    所述两行目标像素中，一行所述目标像素所连接的发光控制电路，与另一行所述目标像素所连接的发光控制电路不同。
  10. 根据权利要求9所述的显示基板，其中，每相邻两行所述目标像素之间设置有两个级联的所述移位寄存器单元；
    其中，一个所述移位寄存器单元与一行所述目标像素连接，另一个所述移位寄存器单元与另一行所述目标像素连接。
  11. 根据权利要求10所述的显示基板，其中，两个级联的所述移位寄存器单元对称排布于所述两行目标像素之间。
  12. 根据权利要求8所述的显示基板，其中，所述移位寄存器单元包括：输入子电路、下拉控制子电路、下拉子电路和输出子电路；
    所述输入子电路分别与第一输入端、第二输入端、第一控制信号端、第二控制信号端和上拉节点连接，所述输入子电路用于响应于所述第一输入端提供的第一输入信号，向所述上拉节点输出所述第一控制信号端提供的第一控制信号，以及响应于所述第二输入端提供的第二输入信号，向所述上拉节点输出所述第二控制信号端提供的第二控制信号；
    所述下拉控制子电路分别与第一时钟信号端、所述上拉节点、下拉电源端、下拉节点和输出端连接，所述下拉控制子电路用于响应于所述第一时钟信号端提供的第一时钟信号，向所述下拉节点输出所述第一时钟信号，以及响应于所 述上拉节点的电位和所述输出端提供的输出信号，向所述下拉节点输出所述下拉电源端提供的下拉电源信号；
    所述下拉子电路分别与复位信号端、所述下拉节点、所述下拉电源端、所述上拉节点和所述输出端连接，所述下拉子电路用于响应于所述下拉节点的电位，向所述上拉节点和所述输出端输出所述下拉电源信号，以及响应于所述复位信号端提供的复位信号，向所述上拉节点输出所述下拉电源信号；
    所述输出子电路分别与所述上拉节点、第二时钟信号端和所述输出端连接，所述输出子电路用于响应于所述上拉节点的电位，向所述输出端输出所述第二时钟信号端提供的第二时钟信号。
  13. 根据权利要求1至12任一所述的显示基板，其中，所述显示基板还包括：位于所述衬底基板上的多条数据线；
    所述多条栅线包括：多条第一栅线、多条第二栅线和多条第三栅线；所述发光控制电路包括：发光控制晶体管；所述发光驱动电路包括：数据写入晶体管、复位晶体管、驱动晶体管、补偿晶体管和存储电容；
    所述数据写入晶体管的栅极与一条所述第一栅线连接，第一极与所述驱动晶体管的栅极连接，第二极与一条所述数据线连接；所述驱动晶体管的第一极与所述发光控制晶体管的第一极连接，第二极与所述发光元件连接；所述发光控制晶体管的栅极与一条所述发光控制线连接，第二极与直流电源端连接；所述复位晶体管的栅极与一条所述第二栅线连接，第一极与第一初始信号端连接，第二极与所述驱动晶体管的第二极连接；所述补偿晶体管的栅极与一条所述第三栅线连接，第一极与所述第二初始信号端连接，第二极与所述驱动晶体管的栅极连接。
  14. 根据权利要求12所述的显示基板，其中，每条所述驱动信号线均位于相邻两列所述像素之间，且每相邻两列所述像素之间，设置有至多两条所述驱动信号线；
    每相邻两行所述目标像素之间设置有两个级联的所述移位寄存器单元，且两个级联的所述移位寄存器单元对称排布于所述两行目标像素之间；其中，一个所述移位寄存器单元与一行所述目标像素连接，另一个所述移位寄存器单元 与另一行所述目标像素连接；所述两行目标像素中，一行所述目标像素所连接的发光控制电路，与另一行所述目标像素所连接的发光控制电路不同；
    所述显示基板还包括：位于所述衬底基板上的多条数据线；所述多条栅线包括：多条第一栅线、多条第二栅线和多条第三栅线；所述发光控制电路包括：发光控制晶体管；所述发光驱动电路包括：数据写入晶体管、复位晶体管、驱动晶体管、补偿晶体管和存储电容；
    所述数据写入晶体管的栅极与一条所述第一栅线连接，第一极与所述驱动晶体管的栅极连接，第二极与一条所述数据线连接；所述驱动晶体管的第一极与所述发光控制晶体管的第一极连接，第二极与所述发光元件连接；所述发光控制晶体管的栅极与一条所述发光控制线连接，第二极与直流电源端连接；所述复位晶体管的栅极与一条所述第二栅线连接，第一极与第一初始信号端连接，第二极与所述驱动晶体管的第二极连接；所述补偿晶体管的栅极与一条所述第三栅线连接，第一极与所述第二初始信号端连接，第二极与所述驱动晶体管的栅极连接。
  15. 一种显示装置，其中，所述显示装置包括：源极驱动电路以及如权利要求1至14任一所述的显示基板；
    所述源极驱动电路与所述显示基板中的多条数据线连接，所述源极驱动电路用于为每条所述数据线提供数据信号。
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