WO2022246642A1 - 驱动电路、驱动方法、驱动模组和显示装置 - Google Patents

驱动电路、驱动方法、驱动模组和显示装置 Download PDF

Info

Publication number
WO2022246642A1
WO2022246642A1 PCT/CN2021/095775 CN2021095775W WO2022246642A1 WO 2022246642 A1 WO2022246642 A1 WO 2022246642A1 CN 2021095775 W CN2021095775 W CN 2021095775W WO 2022246642 A1 WO2022246642 A1 WO 2022246642A1
Authority
WO
WIPO (PCT)
Prior art keywords
node
control
electrically connected
transistor
terminal
Prior art date
Application number
PCT/CN2021/095775
Other languages
English (en)
French (fr)
Inventor
王志冲
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202180001260.9A priority Critical patent/CN115699146A/zh
Priority to PCT/CN2021/095775 priority patent/WO2022246642A1/zh
Priority to US17/772,052 priority patent/US20240144851A1/en
Publication of WO2022246642A1 publication Critical patent/WO2022246642A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G09G2310/062—Waveforms for resetting a plurality of scan lines at a time
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a driving circuit, a driving method, a driving module and a display device.
  • two driving circuits need to be used to generate the light-emitting control signal and the gate driving signal respectively, which cannot simplify the driving scheme and is not conducive to narrowing the frame.
  • an embodiment of the present disclosure provides a drive circuit, including a light emission control signal generation circuit and a gate drive circuit; the light emission control signal generation circuit includes a first node control circuit, a second node control circuit, a third Node control circuit and light emission control output circuit;
  • the first node control circuit is used to control the potential of the first node
  • the second node control circuit is used to control the potential of the second node
  • the third node control circuit is used to control the potential of the third node
  • the light emission control output circuit is used to control the light emission control signal output end to output the light emission control signal according to the potential of the second node and the potential of the third node;
  • the gate drive circuit is configured to control the potential of the first node, the first input signal provided by the first input terminal and the reset signal provided by the reset terminal, according to the first clock signal provided by the first clock signal terminal and the second
  • the first voltage signal provided by the first voltage terminal controls the gate drive signal output terminal to output the gate drive signal.
  • the gate drive circuit includes a fourth node control circuit and a gate output circuit
  • the fourth node control circuit is used to control the connection or disconnection between the fourth node and the reset terminal under the control of the potential of the first node, and the first input provided at the first input terminal Under the control of the input signal, control the connection or disconnection between the fourth node and the first voltage terminal;
  • the gate output circuit is used to control the connection or disconnection between the gate drive signal output terminal and the first clock signal terminal under the control of the potential of the fourth node.
  • the gate drive signal output terminal is controlled to be connected or disconnected from the first voltage terminal, and is used to control the gate drive signal provided by the gate drive signal output terminal according to the potential of the fourth node.
  • the driving circuit described in at least one embodiment of the present disclosure further includes a gate reset circuit
  • the gate reset circuit is used to control the connection or disconnection between the gate drive signal output terminal and the first voltage terminal under the control of the potential of the first node.
  • the fourth node control circuit includes a first transistor and a second transistor
  • the control electrode of the first transistor is electrically connected to the first node, the first electrode of the first transistor is electrically connected to the reset terminal, and the second electrode of the first transistor is electrically connected to the fourth node. connect;
  • the control pole of the second transistor is electrically connected to the first input terminal, the first pole of the second transistor is electrically connected to the fourth node, and the second pole of the second transistor is electrically connected to the first The voltage terminal is electrically connected.
  • the gate output circuit includes a third transistor, a fourth transistor and a first capacitor
  • the control electrode of the third transistor is electrically connected to the fourth node, the first electrode of the third transistor is electrically connected to the first clock signal terminal, and the second electrode of the third transistor is electrically connected to the gate driver The signal output terminal is electrically connected;
  • the control electrode of the fourth transistor is electrically connected to the first input terminal, the first electrode of the fourth transistor is electrically connected to the gate drive signal output end, and the second electrode of the fourth transistor is electrically connected to the The first voltage terminal is electrically connected;
  • a first end of the first capacitor is electrically connected to the fourth node, and a second end of the first capacitor is electrically connected to the gate drive signal output end.
  • the gate reset circuit includes a fifth transistor
  • the control electrode of the fifth transistor is electrically connected to the first node, the first electrode of the fifth transistor is electrically connected to the gate drive signal output end, and the second electrode of the fifth transistor is electrically connected to the The first voltage end is electrically connected.
  • the first node control circuit includes a fifth node control subcircuit and a first node control subcircuit;
  • the fifth node control subcircuit is used to control the connection or disconnection between the fifth node and the second voltage terminal under the control of the first clock signal provided by the first clock signal terminal, and control the potential of the third node Next, control the connection or disconnection between the fifth node and the first clock signal terminal;
  • the first node control subcircuit is used for controlling the potential of the first node according to the potential of the fifth node and the second clock signal provided by the second clock signal terminal.
  • the fifth node control subcircuit includes a sixth transistor and a seventh transistor;
  • the control electrode of the sixth transistor is electrically connected to the first clock signal terminal, the first electrode of the sixth transistor is electrically connected to the second voltage end, and the second electrode of the sixth transistor is electrically connected to the fifth node;
  • the control electrode of the seventh transistor is electrically connected to the third node, the first electrode of the seventh transistor is electrically connected to the first clock signal terminal, and the second electrode of the seventh transistor is electrically connected to the fifth node.
  • the first node control subcircuit is used to control the connection or disconnection between the first node and the second clock signal terminal under the control of the potential of the fifth node, and is used to The potential of the node controls the potential of the first node.
  • the first node control subcircuit includes an eighth transistor and a second capacitor;
  • the control electrode of the eighth transistor is electrically connected to the fifth node, the first electrode of the eighth transistor is electrically connected to the second clock signal terminal, and the second electrode of the eighth transistor is electrically connected to the first node;
  • the first end of the second capacitor is electrically connected to the fifth node, and the second end of the second capacitor is electrically connected to the first node.
  • the drive circuit further includes a conduction control circuit; the conduction control circuit is configured to control the fifth node and the second voltage signal under the control of the second voltage signal provided by the second voltage terminal.
  • the sixth node is connected or disconnected;
  • the first node control subcircuit is used to control the connection or disconnection between the first node and the second clock signal terminal under the control of the potential of the sixth node, and is used to, according to the potential of the sixth node, controlling the potential of the first node.
  • the first node control subcircuit includes an eighth transistor and a second capacitor, and the conduction control circuit includes a first conduction control transistor;
  • the control pole of the first conduction control transistor is electrically connected to the second voltage terminal, the first pole of the first conduction control transistor is electrically connected to the fifth node, and the second pole of the first conduction control transistor electrically connected to the sixth node;
  • the control pole of the eighth transistor is electrically connected to the sixth node, the first pole of the eighth transistor is electrically connected to the second clock signal terminal, and the second pole of the eighth transistor is electrically connected to the first node;
  • the first end of the second capacitor is electrically connected to the sixth node, and the second end of the second capacitor is electrically connected to the first node.
  • the second node control circuit is used to control the connection or disconnection between the first node and the second node under the control of the second clock signal provided by the second clock signal terminal, and is used to Under the control of the potential of the third node, control the connection or disconnection between the second node and the first voltage terminal, and maintain the potential of the second node.
  • the second node control circuit includes a ninth transistor, a tenth transistor, and a control capacitor;
  • the control pole of the ninth transistor is electrically connected to the second clock signal terminal, the first pole of the ninth transistor is electrically connected to the first node, and the second pole of the ninth transistor is electrically connected to the second node;
  • the control pole of the tenth transistor is electrically connected to the third node, the first pole of the tenth transistor is electrically connected to the first voltage terminal, and the second pole of the tenth transistor is electrically connected to the second node;
  • the first end of the control capacitor is electrically connected to the second node, and the second end of the control capacitor is connected to the first voltage end.
  • the third node control circuit is configured to control the connection or disconnection between the third node and the second input end under the control of the first clock signal provided by the first clock signal end, and the fifth node Under the control of the potential and the second clock signal, control the connection or disconnection between the third node and the first voltage terminal, and control the potential of the third node according to the second clock signal.
  • the third node control circuit includes an eleventh transistor, a twelfth transistor, a thirteenth transistor, and a third capacitor;
  • the control electrode of the eleventh transistor is electrically connected to the first clock signal terminal, the first electrode of the eleventh transistor is electrically connected to the second input end, and the second electrode of the eleventh transistor is electrically connected to the third node;
  • the control electrode of the twelfth transistor is electrically connected to the fifth node, and the first electrode of the twelfth transistor is electrically connected to the first voltage terminal;
  • the control pole of the thirteenth transistor is electrically connected to the second clock signal terminal, the first pole of the thirteenth transistor is electrically connected to the second pole of the twelfth transistor, and the second pole of the thirteenth transistor is electrically connected to the third node ;
  • the first end of the third capacitor is electrically connected to the second clock signal end, and the second end of the third capacitor is electrically connected to the third node.
  • the third node control circuit includes a seventh node control subcircuit and a third node control subcircuit;
  • the seventh node control subcircuit is used to control the connection or disconnection between the seventh node and the first voltage terminal under the control of the potential of the fifth node, and control the connection or disconnection between the seventh node and the first voltage terminal under the control of the potential of the third node.
  • the third node control subcircuit is used to control the potential of the third node according to the potential of the seventh node, and control the connection between the third node and the third node under the control of the first clock signal provided by the first clock signal terminal.
  • the second input terminals are connected or disconnected.
  • the third node control subcircuit includes an eleventh transistor and a third capacitor;
  • the seventh node control subcircuit includes a twelfth transistor and a thirteenth transistor;
  • the control electrode of the eleventh transistor is electrically connected to the first clock signal terminal, the first electrode of the eleventh transistor is electrically connected to the second input end, and the second electrode of the eleventh transistor is electrically connected to the third node;
  • the control pole of the twelfth transistor is electrically connected to the fifth node, the first pole of the twelfth transistor is electrically connected to the first voltage terminal, and the second pole of the twelfth transistor is electrically connected to the seventh node;
  • the control pole of the thirteenth transistor is electrically connected to the third node, the first pole of the thirteenth transistor is electrically connected to the second clock signal terminal, and the second pole of the thirteenth transistor is electrically connected to the seventh node;
  • the first end of the third capacitor is electrically connected to the seventh node, and the second end of the third capacitor is electrically connected to the third node.
  • the light emission control output circuit includes a conduction subcircuit;
  • the third node control circuit includes a third node control subcircuit, a seventh node control subcircuit and an eighth node control subcircuit;
  • the conduction subcircuit is used to control the connection or disconnection between the third node and the eighth node under the control of the second voltage signal provided by the second voltage terminal;
  • the third node control subcircuit is used to control the connection or disconnection between the third node and the second input terminal under the control of the first clock signal provided by the first clock signal terminal;
  • the seventh node control subcircuit is used to control the connection or disconnection between the seventh node and the first voltage terminal under the control of the potential of the fifth node, and control the connection or disconnection between the seventh node and the first voltage terminal under the control of the potential of the eighth node.
  • the eighth node control subcircuit is used to control the potential of the eighth node according to the potential of the seventh node.
  • the conduction subcircuit includes a second conduction control transistor, the third node control subcircuit includes an eleventh transistor, and the seventh node control subcircuit includes a twelfth transistor and a thirteenth transistor ;
  • the eighth node control subcircuit includes a third capacitor;
  • the control pole of the second conduction control transistor is electrically connected to the second voltage terminal, the first pole of the second conduction control transistor is electrically connected to the third node, and the second pole of the second conduction control transistor electrically connected to the eighth node;
  • the control electrode of the eleventh transistor is electrically connected to the first clock signal terminal, the first electrode of the eleventh transistor is electrically connected to the second input end, and the second electrode of the eleventh transistor is electrically connected to the third node;
  • the control pole of the twelfth transistor is electrically connected to the fifth node, the first pole of the twelfth transistor is electrically connected to the first voltage terminal, and the second pole of the twelfth transistor is electrically connected to the seventh node;
  • the control pole of the thirteenth transistor is electrically connected to the eighth node, the first pole of the thirteenth transistor is electrically connected to the second clock signal terminal, and the second pole of the thirteenth transistor is electrically connected to the seventh node;
  • the first end of the third capacitor is electrically connected to the seventh node, and the second end of the third capacitor is electrically connected to the eighth node.
  • the light emission control output circuit includes a first output transistor and a second output transistor
  • the control pole of the first output transistor is electrically connected to the third node, the first pole of the first output transistor is electrically connected to the second voltage terminal, and the second pole of the first output transistor is electrically connected to the light emission control signal output terminal;
  • the control electrode of the second output transistor is electrically connected to the second node, the first electrode of the second output transistor is electrically connected to the output end of the light emission control signal, and the second electrode of the second output transistor is electrically connected to the first voltage end.
  • the light emission control output circuit includes a second conduction control transistor, a first output transistor and a second output transistor;
  • the control pole of the second conduction control transistor is electrically connected to the second voltage terminal, the first pole of the second conduction control transistor is electrically connected to the third node, and the second pole of the second conduction control transistor electrically connected to the eighth node;
  • the control pole of the first output transistor is electrically connected to the eighth node, the first pole of the first output transistor is electrically connected to the second voltage terminal, and the second pole of the first output transistor is electrically connected to the light emission control signal output terminal;
  • the control electrode of the second output transistor is electrically connected to the second node, the first electrode of the second output transistor is electrically connected to the output end of the light emission control signal, and the second electrode of the second output transistor is electrically connected to the first voltage end.
  • the present disclosure also provides a driving method applied to the above-mentioned driving circuit, the driving method comprising:
  • the gate drive circuit Under the control of the potential of the first node, the first input signal provided by the first input terminal and the reset signal provided by the reset terminal, the gate drive circuit provides the first clock signal provided by the first clock signal terminal and the first voltage terminal provided The first voltage signal controls the gate drive signal output end to output the gate drive signal.
  • the driving cycle includes a first input phase, a second input phase, a third input phase, and a first reset phase set in sequence; the driving method includes:
  • the fourth node control circuit controls the disconnection between the fourth node and the reset terminal under the control of the potential of the first node, and controls the disconnection between the fourth node and the first terminal under the control of the first input signal.
  • the voltage terminals are disconnected; under the control of the potential of the fourth node, the gate output circuit controls the disconnection between the gate drive signal output terminal and the first clock signal terminal, and controls the gate drive signal under the control of the first input signal.
  • the signal output terminal is disconnected from the first voltage terminal, so that the gate drive signal output terminal maintains outputting the first voltage signal;
  • the fourth node control circuit controls the communication between the fourth node and the reset terminal under the control of the potential of the first node;
  • the pole drive signal output end is connected to the first clock signal end, so that the gate drive signal output end outputs a first voltage signal;
  • the fourth node control circuit controls the disconnection between the fourth node and the reset terminal; under the control of the potential of the fourth node, the gate output circuit controls the gate
  • the pole drive signal output end is connected to the first clock signal end, so that the gate drive signal output end outputs a second voltage signal;
  • the fourth node control circuit controls the communication between the fourth node and the reset terminal under the control of the potential of the first node, and controls the communication between the fourth node and the first terminal under the control of the first input signal.
  • the voltage terminals are connected; under the control of the potential of the fourth node, the gate output circuit controls the disconnection between the gate drive signal output terminal and the first clock signal terminal, and controls the gate drive signal under the control of the first input signal.
  • the signal output end communicates with the first voltage end, so that the gate drive signal output end outputs the first voltage signal.
  • the driving circuit further includes a gate reset circuit; the driving method further includes:
  • the gate reset circuit controls the disconnection between the gate drive signal output terminal and the first voltage terminal under the control of the potential of the first node
  • the gate reset circuit controls the communication between the gate drive signal output terminal and the first voltage terminal under the control of the potential of the first node
  • the gate reset circuit controls the disconnection between the gate drive signal output terminal and the first voltage terminal under the control of the potential of the first node
  • the gate reset circuit controls the communication between the gate driving signal output terminal and the first voltage terminal under the control of the potential of the first node.
  • the present disclosure also provides a driving module, comprising multiple stages of the above-mentioned driving circuits.
  • the second input end of the driving circuit is electrically connected to the light emission control signal output end of an adjacent upper level driving circuit.
  • the first input end of the drive circuit is electrically connected to the light emission control signal output end of the adjacent upper stage drive circuit; or, the first input end of the drive circuit is connected to the light emission control signal output end of the drive circuit electrical connection.
  • the reset terminal of the drive circuit is electrically connected to the light emission control signal output terminal of the adjacent next-level drive circuit; or, the reset terminal is electrically connected to the gate drive signal output terminal of the adjacent upper-level drive circuit. connect.
  • an embodiment of the present disclosure provides a display device, including the above-mentioned driving module.
  • FIG. 1 is a structural diagram of a driving circuit described in an embodiment of the present disclosure
  • Fig. 2 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure
  • Fig. 3 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • Fig. 4 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG. 5 is a working timing diagram of at least one embodiment of the driving circuit shown in FIG. 4;
  • Fig. 6 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • Fig. 7 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • Fig. 8 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • Fig. 9 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • Fig. 10 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG. 11 is a working timing diagram of at least one embodiment of the driving circuit shown in FIG. 10 of the present disclosure.
  • FIG. 12A is a schematic diagram of the working state of at least one embodiment of the driving circuit as shown in FIG. 10 in the first preparation stage t01 of the present disclosure
  • FIG. 12B is a schematic diagram of the working state of at least one embodiment of the driving circuit as shown in FIG. 10 in the second preparation stage t02 of the present disclosure
  • FIG. 12C is a schematic diagram of the working state of at least one embodiment of the driving circuit as shown in FIG. 10 in the first input stage t1 of the present disclosure
  • FIG. 12D is a schematic diagram of the working state of at least one embodiment of the driving circuit as shown in FIG. 10 in the second input stage t2 of the present disclosure
  • FIG. 12E is a schematic diagram of the working state of at least one embodiment of the driving circuit as shown in FIG. 10 in the third input stage t3 of the present disclosure
  • FIG. 12F is a schematic diagram of the working state of at least one embodiment of the driving circuit as shown in FIG. 10 in the first reset phase t4 of the present disclosure
  • FIG. 12G is a schematic diagram of the working state of at least one embodiment of the driving circuit as shown in FIG. 10 in the second reset phase t5 of the present disclosure
  • FIG. 12H is a schematic diagram of the working state of at least one embodiment of the driving circuit as shown in FIG. 10 in the third reset phase t6 of the present disclosure
  • Fig. 13 is a waveform diagram of a light emission control signal and a gate drive signal provided by the drive circuit according to at least one embodiment of the present disclosure
  • Fig. 14 is a waveform diagram of a light emission control signal and a gate drive signal provided by the drive circuit according to at least one embodiment of the present disclosure
  • Fig. 15 is a waveform diagram of a light emission control signal and a gate drive signal provided by the drive circuit according to at least one embodiment of the present disclosure
  • Fig. 16 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG. 17 is a working timing diagram of at least one embodiment of the driving circuit as shown in FIG. 16 of the present disclosure.
  • FIG. 18 is a structural diagram of a gate drive circuit provided by at least one embodiment of the present disclosure.
  • Fig. 19 is a structural diagram of at least one embodiment of the gate drive circuit
  • Fig. 20 is a structural diagram of at least one embodiment of the gate drive circuit
  • Figure 21 is a circuit diagram of at least one embodiment of the gate drive circuit
  • Fig. 22 is a working timing diagram of at least one embodiment of the gate driving circuit.
  • the transistors used in all the embodiments of the present disclosure may be triodes, thin film transistors or field effect transistors or other devices with the same characteristics.
  • one pole is called the first pole, and the other pole is called the second pole.
  • the control electrode when the transistor is a triode, can be a base, the first electrode can be a collector, and the second electrode can be an emitter; or, the control electrode can be a base pole, the first pole may be an emitter, and the second pole may be a collector.
  • the control electrode when the transistor is a thin film transistor or a field effect transistor, the control electrode may be a gate, the first electrode may be a drain, and the second electrode may be a source; or, the The control electrode may be a gate, the first electrode may be a source, and the second electrode may be a drain.
  • the drive circuit described in the embodiment of the present disclosure includes a light emission control signal generation circuit and a gate drive circuit 10;
  • the light emission control signal generation circuit includes a first node control circuit 11, a second node control circuit 12, The third node control circuit 13 and the light emission control output circuit 14;
  • the first node control circuit 11 is electrically connected to the first node PU1 for controlling the potential of the first node PU1;
  • the second node control circuit 12 is electrically connected to the second node PU for controlling the potential of the second node PU;
  • the third node control circuit 13 is electrically connected to the third node PD1 for controlling the potential of the third node PD1;
  • the light emission control output circuit 14 is electrically connected to the second node PU, the third node PD1 and the light emission control signal output terminal E1 respectively, and is used to control the The light emission control signal output terminal E1 outputs the light emission control signal;
  • the gate drive circuit 10 is electrically connected to the first node PU1, the first input terminal I1, the reset terminal R1, the first clock signal terminal K1, the first voltage terminal V1 and the gate drive signal output terminal G1 respectively, for Under the control of the potential of the first node PU1, the first input signal provided by the first input terminal I1 and the reset signal provided by the reset terminal R1, according to the first clock signal provided by the first clock signal terminal K1 and the first voltage terminal V1 provided The first voltage signal controls the gate drive signal output terminal G1 to output the gate drive signal.
  • a gate driving circuit for generating a gate driving signal is added, and the signal obtained by ORing the reset signal provided by the reset terminal R1 with the voltage signal of the first node PU1 of the bank is used as Input/reset function, that is, when the reset signal and the voltage signal of the first node PU1 of the bank are effective voltage signals at the same time, the input function is realized.
  • the voltage signal of the first node PU1 of the bank is an effective voltage signal
  • the reset signal is When the voltage signal is invalid, the reset function is realized.
  • the noise is denoised for G1, so that the driving circuit described in the embodiment of the present disclosure can generate the light emission control signal while generating the gate signal.
  • the driving signal can simplify the driving scheme, reduce the number of signals, and narrow the frame.
  • the drive circuit described in the embodiment of the present disclosure includes a light emission control signal generation circuit and a gate drive circuit;
  • the light emission control signal generation circuit includes a first node control circuit 11, a second node control circuit 12, a second node control circuit Three-node control circuit 13 and light-emitting control output circuit 14;
  • the gate drive circuit includes a fourth node control circuit 21 and a gate output circuit 23;
  • the first node control circuit 11 is electrically connected to the first node PU1 for controlling the potential of the first node PU1;
  • the second node control circuit 12 is electrically connected to the second node PU for controlling the potential of the second node PU;
  • the third node control circuit 13 is electrically connected to the third node PD1, and is used to control the potential of the third node PD1;
  • the light emission control output circuit 14 is electrically connected to the second node PU, the third node PD1 and the light emission control signal output terminal E1 respectively, and is used to control the The light emission control signal output terminal E1 outputs the light emission control signal;
  • the fourth node control circuit 21 is electrically connected to the first node PU1, the fourth node PPU, the reset terminal R1, the first input terminal I1 and the first voltage terminal V1 respectively, and is used to control the potential of the first node PU1. Under the control, control the connection or disconnection between the fourth node PPU and the reset terminal R1, and control the connection between the fourth node PPU and the reset terminal R1 under the control of the first input signal provided by the first input terminal I1. connecting or disconnecting the first voltage terminals V1;
  • the gate output circuit 23 is electrically connected to the fourth node PPU, the gate drive signal output terminal G1, the first clock signal terminal K1, the first input terminal I1 and the first voltage terminal V1, for Under the control of the potential of the node PPU, the connection or disconnection between the gate driving signal output terminal G1 and the first clock signal terminal K1 is controlled, and under the control of the first input signal provided by the first input terminal I1, all
  • the gate driving signal output terminal G1 is connected or disconnected from the first voltage terminal V1, and is used to control the gate driving signal provided by the gate driving signal output terminal G1 according to the potential of the fourth node PPU.
  • a gate driving circuit for generating a gate driving signal is added, and the signal obtained by ORing the reset signal provided by the reset terminal R1 with the voltage signal of the first node PU1 of the bank is used as Input/reset function, that is, when the reset signal and the voltage signal of the first node PU1 of the bank are effective voltage signals at the same time, the input function is realized (input for the fourth node PPU), when the voltage signal of the first node PU1 of the bank is Effective voltage signal, and the reset function is realized when the reset signal is an invalid voltage signal (for the fourth node PPU reset), when the first input signal provided by I1 is a valid voltage signal, it is the fourth node PPU and G1 denoising, so that
  • the driving circuit described in the embodiments of the present disclosure can generate the gate driving signal while generating the light-emitting control signal, which can simplify the driving scheme, reduce the number of signals, and narrow the frame.
  • the effective voltage signal when each transistor included in the driving circuit is a p-type transistor, the effective voltage signal may be a low voltage signal, and the invalid voltage signal may be a high voltage signal; when each transistor included in the driving circuit When the transistor is an n-type transistor, the valid voltage signal can be a high voltage signal, and the invalid voltage signal can be a low voltage signal.
  • the pulse width of the generated light-emitting control signal can be adjusted, and the light-emitting control signal can be a low-voltage effective signal, and the generated gate drive signal can be low-voltage effective.
  • the time for which the potential of the light emission control signal is at a high voltage may be greater than or equal to 2H (the pulse width of the light emission control signal is adjustable), and the time for which the gate drive signal is at a low voltage may be less than or equal to 1H .
  • the first voltage terminal may be a high voltage terminal.
  • the driving cycle may include a first input phase, a second input phase, a third input phase and a first reset phase set in sequence;
  • the fourth node control circuit 21 controls the disconnection between the fourth node PPU and the reset terminal R1 under the control of the potential of the first node PU1, and controls the fourth node PPU under the control of the first input signal.
  • the node PPU is disconnected from the first voltage terminal V1; under the control of the potential of the fourth node PPU, the gate output circuit 23 controls the disconnection between the gate drive signal output terminal G1 and the first clock signal terminal K1, and at the first Under the control of the input signal, the gate driving signal output terminal G1 is controlled to be disconnected from the first voltage terminal V1, so that the gate driving signal output terminal G1 maintains outputting the first voltage signal;
  • the fourth node control circuit 21 controls the connection between the fourth node PPU and the reset terminal R1 under the control of the potential of the first node PU1;
  • the gate output circuit 23 is at the potential of the fourth node PPU Under the control of the control, the connection between the gate drive signal output terminal G1 and the first clock signal terminal K1 is controlled, so that the gate drive signal output terminal G1 outputs the first voltage signal;
  • the fourth node control circuit 21 controls the disconnection between the fourth node PPU and the reset terminal R1 under the control of the potential of the first node PU1;
  • the gate output circuit 23 is at the potential of the fourth node PPU Under the control of the gate drive signal output terminal G1 is controlled to communicate with the first clock signal terminal K1, so that the gate drive signal output terminal G1 outputs a second voltage signal;
  • the fourth node control circuit 21 controls the connection between the fourth node PPU and the reset terminal R1 under the control of the potential of the first node PU1, and controls the connection between the fourth node PPU and the reset terminal R1 under the control of the first input signal.
  • the node PPU is connected to the first voltage terminal V1; under the control of the potential of the fourth node PPU, the gate output circuit 23 controls the disconnection between the gate drive signal output terminal G1 and the first clock signal terminal K1, and the first Under the control of the input signal, the gate driving signal output terminal G1 is controlled to communicate with the first voltage terminal V1, so that the gate driving signal output terminal G1 outputs the first voltage signal.
  • the first voltage signal may be a high voltage signal
  • the second voltage signal may be a low voltage signal
  • the first input end may be electrically connected to the light emission control signal output end of the adjacent upper stage driving circuit; or, the first input end of the driving circuit is electrically connected to the light emission control signal output end of the driving circuit. connect.
  • the reset terminal of the drive circuit is electrically connected to the light emission control signal output terminal of the adjacent next-level drive circuit; or, the reset terminal is electrically connected to the gate drive signal output terminal of the adjacent upper-level drive circuit. connect.
  • the driving circuit described in at least one embodiment of the present disclosure may further include a gate reset circuit 24 ;
  • the gate reset circuit 24 is electrically connected to the first node PU1, the gate drive signal output terminal G1 and the first voltage terminal V1, and is used to control the gate voltage under the control of the potential of the first node PU1.
  • the drive signal output terminal G1 is connected or disconnected from the first voltage terminal V1.
  • the gate reset circuit 24 is added to control the potential of the first node PU1 Next, control the gate driving signal output terminal to output the first voltage signal to reset G1.
  • the gate reset circuit 24 controls the disconnection between the gate driving signal output terminal G1 and the first voltage terminal V1 under the control of the potential of the first node PU1;
  • the gate reset circuit 24 controls the connection between the gate driving signal output terminal G1 and the first voltage terminal V1 under the control of the potential of the first node PU1;
  • the gate reset circuit 24 controls the disconnection between the gate driving signal output terminal G1 and the first voltage terminal V1 under the control of the potential of the first node PU1;
  • the gate reset circuit 24 controls the communication between the gate drive signal output terminal G1 and the first voltage terminal V1 to reset G1.
  • the fourth node control circuit includes a first transistor and a second transistor
  • the control electrode of the first transistor is electrically connected to the first node, the first electrode of the first transistor is electrically connected to the reset terminal, and the second electrode of the first transistor is electrically connected to the fourth node. connect;
  • the control pole of the second transistor is electrically connected to the first input terminal, the first pole of the second transistor is electrically connected to the fourth node, and the second pole of the second transistor is electrically connected to the first The voltage terminal is electrically connected.
  • the gate output circuit includes a third transistor, a fourth transistor and a first capacitor
  • the control electrode of the third transistor is electrically connected to the fourth node, the first electrode of the third transistor is electrically connected to the first clock signal terminal, and the second electrode of the third transistor is electrically connected to the gate driver The signal output terminal is electrically connected;
  • the control electrode of the fourth transistor is electrically connected to the first input terminal, the first electrode of the fourth transistor is electrically connected to the gate drive signal output end, and the second electrode of the fourth transistor is electrically connected to the The first voltage terminal is electrically connected;
  • a first end of the first capacitor is electrically connected to the fourth node, and a second end of the first capacitor is electrically connected to the gate drive signal output end.
  • the first capacitor is used to couple the fourth node, so that the transistor whose control electrode is electrically connected to the fourth node is more fully turned on, so as to output a waveform to the gate drive signal output terminal.
  • the gate reset circuit includes a fifth transistor
  • the control electrode of the fifth transistor is electrically connected to the first node, the first electrode of the fifth transistor is electrically connected to the gate drive signal output end, and the second electrode of the fifth transistor is electrically connected to the The first voltage end is electrically connected.
  • the fourth node control circuit 21 includes a first transistor M1 and a second transistor M2;
  • the gate of the first transistor M1 is electrically connected to the first node PU1, the first pole of the first transistor M1 is electrically connected to the reset terminal R1, and the second pole of the first transistor M1 is electrically connected to the reset terminal R1.
  • the fourth node PPU is electrically connected;
  • the gate of the second transistor M2 is electrically connected to the first input terminal I1, the first pole of the second transistor M2 is electrically connected to the fourth node PPU, and the second pole of the second transistor M2 Electrically connected to the high voltage terminal V01;
  • the gate output circuit 23 includes a third transistor M3, a fourth transistor M4 and a first capacitor C1;
  • the gate of the third transistor M3 is electrically connected to the fourth node PPU, the first pole of the third transistor M3 is electrically connected to the first clock signal terminal K1, and the second pole of the third transistor M3 is electrically connected to the first clock signal terminal K1.
  • the gate drive signal output terminal G1 is electrically connected;
  • the gate of the fourth transistor M4 is electrically connected to the first input terminal I1, the first pole of the fourth transistor M4 is electrically connected to the gate drive signal output terminal G1, and the gate of the fourth transistor M4 The second pole is electrically connected to the high voltage terminal V01;
  • the gate reset circuit 24 includes a fifth transistor M5;
  • the gate of the fifth transistor M5 is electrically connected to the first node PU1, the first pole of the fifth transistor M5 is electrically connected to the gate drive signal output terminal G1, and the first electrode of the fifth transistor M5 The two poles are electrically connected to the high voltage terminal V01;
  • a first end of the first capacitor C1 is electrically connected to the fourth node PPU, and a second end of the first capacitor C1 is electrically connected to the gate drive signal output end G1.
  • each transistor is a p-type transistor.
  • K1 provides a low voltage signal
  • I1 provides a low voltage signal
  • R1 provides a low voltage signal
  • the potential of PU1 is high voltage
  • the potential of PPU is high voltage
  • M1 is turned off
  • M2 is turned on
  • M3 is turned off
  • M4 is turned on
  • M5 is turned off
  • G1 outputs a high voltage signal
  • K1 provides a high voltage signal
  • I1 provides a low voltage signal
  • R1 provides a low voltage signal
  • the potential of PU1 is high voltage
  • the potential of PPU is high voltage
  • M1 is turned off
  • M2 is turned on
  • M3 is turned off
  • M4 is turned on
  • M5 is turned off
  • G1 outputs a high voltage signal
  • K1 provides a low voltage signal
  • I1 provides a high voltage signal
  • R1 provides a low voltage signal
  • the potential of PU1 is high voltage
  • the potential of PPU is high voltage
  • M1, M2, M3, M4 and M5 are all closed off
  • G1 continues to output high-voltage signals
  • K1 provides a high voltage signal
  • I1 provides a high voltage signal
  • R1 provides a low voltage signal
  • the potential of PU1 is low voltage
  • the potential of PPU is pulled down
  • M1 is turned on
  • M2 is turned off
  • M3 is turned on
  • M4 Turn off
  • M5 is on
  • G1 provides a high voltage signal
  • K1 provides a low-voltage signal
  • I1 provides a high-voltage signal
  • R1 provides a high-voltage signal
  • the potential of PU1 is a high voltage
  • the potential of PPU is further pulled down
  • M1 and M2 are turned off
  • M3 is turned on
  • M4 Shut down
  • M5 is turned off
  • G1 provides a low voltage signal
  • K1 provides a high voltage signal
  • I1 provides a low voltage signal
  • R1 provides a high voltage signal
  • the potential of PU1 is low voltage
  • the potential of PPU is high voltage
  • M1 and M2 are turned on
  • M3 is turned off
  • M4 is turned on
  • M5 is turned on
  • G1 provides a high voltage signal to reset G1;
  • K1 provides a low voltage signal
  • I1 provides a low voltage signal
  • R1 provides a high voltage signal
  • the potential of PU1 is high voltage
  • the potential of PPU is high voltage
  • M1 is turned off
  • M2 is turned on
  • M3 is turned off
  • M4 is turned on
  • M5 is turned off
  • G1 provides a high voltage signal
  • K1 provides a high voltage signal
  • I1 provides a low voltage signal
  • R1 provides a low voltage signal
  • the potential of PU1 is high voltage
  • the potential of PPU is high voltage
  • M1 is turned off
  • M2 is turned on
  • M3 is turned off
  • M4 is turned on
  • M5 is turned off
  • G1 provides a high voltage signal.
  • the potential of the light emission control signal provided by E1 lasts at a high voltage for 3H, and the potential of the gate drive signal provided by G1 stays at a low voltage for 1H.
  • the light emission control signal and the gate driving signal shown in FIG. 5 are driving signals in practical applications, and the duty cycle is less than 50%.
  • the effective width is less than 1H, and the period is 2H, so the duty cycle is less than 50%, resulting in gaps separated by dotted lines between stages in the figure.
  • the first node control circuit may include a fifth node control sub-circuit 51 and a a node control sub-circuit 52;
  • the fifth node control sub-circuit 51 is electrically connected to the first clock signal terminal K1, the fifth node PD2, the second voltage terminal V2 and the third node PD1 respectively, and is used for the first clock provided at the first clock signal terminal K1 Under the control of the signal, the connection or disconnection between the fifth node PD2 and the second voltage terminal V2 is controlled, and under the control of the potential of the third node PD1, the connection between the fifth node PD2 and the first clock signal terminal K1 is controlled. connected or disconnected;
  • the first node control sub-circuit 52 is electrically connected to the fifth node PD2, the second clock signal terminal K2 and the first node PU1 respectively, and is used for the second node provided by the potential of the fifth node PD2 and the second clock signal terminal K2
  • the clock signal controls the potential of the first node PU1.
  • the first node control subcircuit 52 can be used to control the communication between the first node PU1 and the second clock signal terminal K2 or is disconnected, and is used to control the potential of the first node PU1 according to the potential of the fifth node PD2.
  • the fifth node control subcircuit includes a sixth transistor and a seventh transistor;
  • the control electrode of the sixth transistor is electrically connected to the first clock signal terminal, the first electrode of the sixth transistor is electrically connected to the second voltage end, and the second electrode of the sixth transistor is electrically connected to the fifth node;
  • the control electrode of the seventh transistor is electrically connected to the third node, the first electrode of the seventh transistor is electrically connected to the first clock signal terminal, and the second electrode of the seventh transistor is electrically connected to the fifth node.
  • the first node control subcircuit includes an eighth transistor and a second capacitor;
  • the control electrode of the eighth transistor is electrically connected to the fifth node, the first electrode of the eighth transistor is electrically connected to the second clock signal terminal, and the second electrode of the eighth transistor is electrically connected to the first node;
  • the first end of the second capacitor is electrically connected to the fifth node, and the second end of the second capacitor is electrically connected to the first node.
  • the drive circuit may further include a conduction control circuit; the conduction control circuit is used to control the fifth node and the sixth node under the control of the second voltage signal provided by the second voltage terminal connected or disconnected;
  • the first node control subcircuit is used to control the connection or disconnection between the first node and the second clock signal terminal under the control of the potential of the sixth node, and is used to, according to the potential of the sixth node, controlling the potential of the first node.
  • the drive circuit described in at least one embodiment of the present disclosure may include a conduction control circuit, the conduction control circuit controls the connection or disconnection between the fifth node and the sixth node, and the first node controls the sub-circuit The potential of the first node is controlled under the control of the potential of the six nodes.
  • the driving circuit described in at least one embodiment of the present disclosure may further include a conduction control circuit 60;
  • the first node control circuit May include a fifth node control subcircuit 51 and a first node control subcircuit 52;
  • the conduction control circuit 60 is electrically connected to the second voltage terminal V2, the fifth node PD2 and the sixth node PD22 respectively, and is used to control the fifth node PD2 under the control of the second voltage signal provided by the second voltage terminal V2. connected or disconnected with the sixth node PD22;
  • the fifth node control sub-circuit 51 is electrically connected to the first clock signal terminal K1, the fifth node PD2, the second voltage terminal V2 and the third node PD1 respectively, and is used for the first clock provided at the first clock signal terminal K1 Under the control of the signal, the connection or disconnection between the fifth node PD2 and the second voltage terminal V2 is controlled, and under the control of the potential of the third node PD1, the connection between the fifth node PD2 and the first clock signal terminal K1 is controlled. connected or disconnected;
  • the first node control sub-circuit 52 is respectively electrically connected to the sixth node PD22, the first node PU1 and the second clock signal terminal K2, and is used to control the first node PU1 under the control of the potential of the sixth node PD22. It is connected or disconnected with the second clock signal terminal K2, and is used to control the potential of the first node PU1 according to the potential of the sixth node PD22.
  • the conduction control circuit 60 controls the connection or disconnection between PD2 and PD22 under the control of the second voltage signal
  • the fifth node control sub-circuit 51 controls the fifth node The potential of PD2
  • the first node control sub-circuit 52 controls the potential of the first node PU1.
  • the first node control subcircuit includes an eighth transistor and a second capacitor, and the conduction control circuit includes a first conduction control transistor;
  • the control pole of the first conduction control transistor is electrically connected to the second voltage terminal, the first pole of the first conduction control transistor is electrically connected to the fifth node, and the second pole of the first conduction control transistor electrically connected to the sixth node;
  • the control electrode of the eighth transistor is electrically connected to the sixth node, the first electrode of the eighth transistor is electrically connected to the second clock signal terminal, and the second electrode of the eighth transistor is electrically connected to the first node;
  • the first end of the second capacitor is electrically connected to the sixth node, and the second end of the second capacitor is electrically connected to the first node.
  • the second node control circuit is electrically connected to the second clock signal terminal K2, the first node PU1, the second node PU, the third node PD1 and the first voltage terminal V1 respectively, for Under the control of the second clock signal provided by the second clock signal terminal K2, the connection or disconnection between the first node PU1 and the second node PU is controlled, and it is used to control the potential of the third node PD1 Under control, the connection or disconnection between the second node PU and the first voltage terminal V1 is controlled and used to maintain the potential of the second node PU.
  • the second node control circuit includes a ninth transistor, a tenth transistor and a control capacitor;
  • the control pole of the ninth transistor is electrically connected to the second clock signal terminal, the first pole of the ninth transistor is electrically connected to the first node, and the second pole of the ninth transistor is electrically connected to the second node;
  • the control pole of the tenth transistor is electrically connected to the third node, the first pole of the tenth transistor is electrically connected to the first voltage terminal, and the second pole of the tenth transistor is electrically connected to the second node;
  • the first end of the control capacitor is electrically connected to the second node, and the second end of the control capacitor is connected to the first voltage end.
  • the third node control circuit is connected to the first clock signal terminal K1, the third node PD1, the second input terminal I2, the fifth node PD2, and the second clock signal terminal respectively.
  • the signal terminal K2 is electrically connected to the first voltage terminal V1, and is used to control the connection or disconnection between the third node PD1 and the second input terminal I2 under the control of the first clock signal provided by the first clock signal terminal K1.
  • the connection or disconnection between the third node PD1 and the first voltage terminal V1 is controlled, and is used to The potential of the third node PD1 is controlled.
  • the third node control circuit includes an eleventh transistor, a twelfth transistor, a thirteenth transistor, and a third capacitor;
  • the control electrode of the eleventh transistor is electrically connected to the first clock signal terminal, the first electrode of the eleventh transistor is electrically connected to the second input end, and the second electrode of the eleventh transistor is electrically connected to the third node;
  • the control electrode of the twelfth transistor is electrically connected to the fifth node, and the first electrode of the twelfth transistor is electrically connected to the first voltage terminal;
  • the control pole of the thirteenth transistor is electrically connected to the second clock signal terminal, the first pole of the thirteenth transistor is electrically connected to the second pole of the twelfth transistor, and the second pole of the thirteenth transistor is electrically connected to the third node ;
  • the first end of the third capacitor is electrically connected to the second clock signal end, and the second end of the third capacitor is electrically connected to the third node.
  • the second node control circuit 12 is respectively connected to the second clock signal terminal K2, the first node PU1, the second node PU,
  • the third node PD1 is electrically connected to the first voltage terminal V1, and is used to control the communication between the first node PU1 and the second node PU under the control of the second clock signal provided by the second clock signal terminal K2 or is disconnected, and is used to control the connection or disconnection between the second node PU and the first voltage terminal V1 under the control of the potential of the third node PD1;
  • the third node control circuit 13 is respectively electrically connected to the first clock signal terminal K1, the third node PD1, the second input terminal I2, the fifth node PD2, the second clock signal terminal K2 and the first voltage terminal V1, for Under the control of the first clock signal provided by the first clock signal terminal K1, the connection or disconnection between the third node PD1 and the second input terminal I2 is controlled, and the potential of the fifth node PD2 and the second clock signal terminal K2 provide Under the control of the second clock signal, control the connection or disconnection between the third node PD1 and the first voltage terminal V1, and control the potential of the third node PD1 according to the second clock signal.
  • the second node control circuit 12 controls the potential of the second node PU
  • the third node control circuit 13 controls the potential of the third node PD1.
  • the third node control circuit may include a seventh node control subcircuit and a third node control subcircuit;
  • the seventh node control subcircuit is used to control the connection or disconnection between the seventh node and the first voltage terminal under the control of the potential of the fifth node, and control the connection or disconnection between the seventh node and the first voltage terminal under the control of the potential of the third node.
  • the third node control subcircuit is used to control the potential of the third node according to the potential of the seventh node, and control the connection between the third node and the third node under the control of the first clock signal provided by the first clock signal terminal.
  • the second input terminals are connected or disconnected.
  • the third node control subcircuit includes an eleventh transistor and a third capacitor
  • the seventh node control subcircuit includes a twelfth transistor and a thirteenth transistor
  • the control electrode of the eleventh transistor is electrically connected to the first clock signal terminal, the first electrode of the eleventh transistor is electrically connected to the second input end, and the second electrode of the eleventh transistor is electrically connected to the third node;
  • the control pole of the twelfth transistor is electrically connected to the fifth node, the first pole of the twelfth transistor is electrically connected to the first voltage terminal, and the second pole of the twelfth transistor is electrically connected to the seventh node;
  • the control pole of the thirteenth transistor is electrically connected to the third node, the first pole of the thirteenth transistor is electrically connected to the second clock signal terminal, and the second pole of the thirteenth transistor is electrically connected to the seventh node;
  • the first end of the third capacitor is electrically connected to the seventh node, and the second end of the third capacitor is electrically connected to the third node.
  • the light emission control output circuit includes a first output transistor and a second output transistor
  • the control pole of the first output transistor is electrically connected to the third node, the first pole of the first output transistor is electrically connected to the second voltage terminal, and the second pole of the first output transistor is electrically connected to the light emission control signal output terminal;
  • the control electrode of the second output transistor is electrically connected to the second node, the first electrode of the second output transistor is electrically connected to the output end of the light emission control signal, and the second electrode of the second output transistor is electrically connected to the first voltage end.
  • the light emission control output circuit may include a conduction subcircuit 70 and a light emission control output subcircuit 71;
  • the circuit includes a third node control subcircuit 80, a seventh node control subcircuit 81 and an eighth node control subcircuit 82;
  • the conduction sub-circuit 70 is electrically connected to the first voltage terminal V2, the third node PD1 and the eighth node PD11 respectively, and is used to control the third node PD1 under the control of the second voltage signal provided by the first voltage terminal V2. connected to or disconnected from the eighth node PD11;
  • the light emission control output sub-circuit 71 is electrically connected to the second node PU, the eighth node PD11, the light emission control signal output terminal E1, the high voltage terminal V01 and the low voltage terminal V02, and is used for controlling the potential of the eighth node PD11. Next, control the connection or disconnection between the light emission control signal output terminal E1 and the low voltage terminal V02, and control the connection or disconnection between the light emission control signal output terminal E1 and the high voltage terminal V01 under the control of the potential of the second node PU ;
  • the third node control subcircuit 80 is electrically connected to the first clock signal terminal K1, the second input terminal I2 and the third node PD1 respectively, and is used to control the first clock signal provided by the first clock signal terminal K1, Controlling the connection or disconnection between the second input terminal I2 and the third node PD1;
  • the seventh node control sub-circuit 81 is respectively electrically connected to the fifth node PD2, the eighth node PD11, the seventh node N1, the first voltage terminal V1 and the second clock signal terminal K2, and is used to control the potential of the fifth node PD2. Under the control of the seventh node N1 and the first voltage terminal V1 to connect or disconnect, under the control of the potential of the eighth node PD11, control the connection between the seventh node N1 and the second clock signal terminal K2 connected or disconnected;
  • the eighth node control subcircuit 82 is electrically connected to the seventh node N1 and the eighth node PD11 respectively, and is used for controlling the potential of the eighth node PD11 according to the potential of the seventh node N1 .
  • the conduction subcircuit 70 controls the connection or disconnection between PD1 and PD11 under the control of the second voltage signal
  • the third node control subcircuit 81 controls the third The potential of the node PD1
  • the seventh node control subcircuit 81 controls the potential of the seventh node N1
  • the eighth node control subcircuit 82 controls the potential of the eighth node PD11.
  • the conduction subcircuit includes a second conduction control transistor
  • the third node control subcircuit includes an eleventh transistor
  • the seventh node control subcircuit includes a twelfth transistor and a thirteenth transistor
  • the eighth node control subcircuit includes a third capacitor
  • the control pole of the second conduction control transistor is electrically connected to the second voltage terminal, the first pole of the second conduction control transistor is electrically connected to the third node, and the second pole of the second conduction control transistor electrically connected to the eighth node;
  • the control electrode of the eleventh transistor is electrically connected to the first clock signal terminal, the first electrode of the eleventh transistor is electrically connected to the second input end, and the second electrode of the eleventh transistor is electrically connected to the third node;
  • the control pole of the twelfth transistor is electrically connected to the fifth node, the first pole of the twelfth transistor is electrically connected to the first voltage terminal, and the second pole of the twelfth transistor is electrically connected to the seventh node;
  • the control pole of the thirteenth transistor is electrically connected to the eighth node, the first pole of the thirteenth transistor is electrically connected to the second clock signal terminal, and the second pole of the thirteenth transistor is electrically connected to the seventh node;
  • the first end of the third capacitor is electrically connected to the seventh node, and the second end of the third capacitor is electrically connected to the eighth node.
  • the light emission control output circuit includes a second conduction control transistor, a first output transistor and a second output transistor;
  • the control pole of the second conduction control transistor is electrically connected to the second voltage terminal, the first pole of the second conduction control transistor is electrically connected to the third node, and the second pole of the second conduction control transistor electrically connected to the eighth node;
  • the control pole of the first output transistor is electrically connected to the eighth node, the first pole of the first output transistor is electrically connected to the second voltage terminal, and the second pole of the first output transistor is electrically connected to the light emission control signal output terminal;
  • the control electrode of the second output transistor is electrically connected to the second node, the first electrode of the second output transistor is electrically connected to the output end of the light emission control signal, and the second electrode of the second output transistor is electrically connected to the first voltage end.
  • the fifth node control subcircuit 51 includes a sixth transistor M6 and a seventh transistor M7;
  • the gate of the sixth transistor M6 is electrically connected to the first clock signal terminal K1, the first pole of the sixth transistor M6 is electrically connected to the low voltage terminal V02, and the second pole of the sixth transistor M6 is electrically connected to the fifth Node PD2 is electrically connected;
  • the gate of the seventh transistor M7 is electrically connected to the third node PD1, the first pole of the seventh transistor M7 is electrically connected to the first clock signal terminal K1, and the second pole of the seventh transistor M7 is electrically connected to the fifth node PD1.
  • Node PD2 is electrically connected;
  • the first node control subcircuit 52 includes an eighth transistor M8 and a second capacitor C2;
  • the gate of the eighth transistor M8 is electrically connected to the fifth node PD2, the first pole of the eighth transistor M8 is electrically connected to the second clock signal terminal K2, and the second pole of the eighth transistor M8 is electrically connected to the first node PU1 ;
  • the first end of the second capacitor C2 is electrically connected to the fifth node PD2, and the second end of the second capacitor C2 is electrically connected to the first node PU1;
  • the second node control circuit 12 includes a ninth transistor M9, a tenth transistor M10 and a control capacitor C0;
  • the gate of the ninth transistor M9 is electrically connected to the second clock signal terminal K2, the first pole of the ninth transistor M9 is electrically connected to the first node PU1, and the second pole of the ninth transistor M9 is electrically connected to the second node PU;
  • the gate of the tenth transistor M10 is electrically connected to the third node PD1, the first pole of the tenth transistor M10 is electrically connected to the high voltage terminal V01, and the second pole of the tenth transistor M10 is electrically connected to the second node PU;
  • the first end of the control capacitor C0 is electrically connected to the second node PU, and the second end of the control capacitor C0 is electrically connected to the high voltage end V01;
  • the third node control circuit 13 includes an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13 and a third capacitor C3;
  • the gate of the eleventh transistor M11 is electrically connected to the first clock signal terminal K1, the first pole of the eleventh transistor M11 is electrically connected to the second input terminal I2, and the second pole of the eleventh transistor M11 is electrically connected to the third node PD1. electrical connection;
  • the gate of the twelfth transistor M12 is electrically connected to the fifth node PD2, and the first pole of the twelfth transistor M12 is electrically connected to the high voltage terminal V01;
  • the gate of the thirteenth transistor M13 is electrically connected to the second clock signal terminal K2, the first pole of the thirteenth transistor M13 is electrically connected to the second pole of the twelfth transistor M12, and the second pole of the thirteenth transistor M13 is electrically connected to the second pole of the twelfth transistor M13.
  • the third node PD1 is electrically connected;
  • the first terminal of the third capacitor C3 is electrically connected to the second clock signal terminal K2, and the second terminal of the third capacitor C3 is electrically connected to the third node PD1;
  • the light emission control output circuit 14 includes a first output transistor M01 and a second output transistor M02;
  • the gate of the first output transistor M01 is electrically connected to the third node PD1, the first pole of the first output transistor M01 is electrically connected to the low voltage terminal V02, and the second pole of the first output transistor M01 is electrically connected to the light emission control signal output terminal E1. connect;
  • the gate of the second output transistor M02 is electrically connected to the second node PU, the first pole of the second output transistor M02 is electrically connected to the light emission control signal output terminal E1, and the second pole of the second output transistor M02 is electrically connected to the high voltage terminal V02. connect.
  • both I1 and I2 are electrically connected to the light-emitting control signal output end of the adjacent upper-level driving circuit, and R1 is electrically connected to the light-emitting control signal output terminal of the adjacent next-level driving circuit. electrical connection.
  • I1 may be replaced by being electrically connected to the output end of the light emission control signal of the driving circuit.
  • R1 may be replaced by being electrically connected to the gate drive signal output terminal of the adjacent upper stage drive circuit.
  • all transistors are p-type transistors, but not limited thereto.
  • the driving cycle when at least one embodiment of the driving circuit shown in FIG. 10 is in operation, the driving cycle includes a first preparation stage t01, a second preparation stage t02, a first input stage t1, and a second input stage. t2, the third input phase t3, the first reset phase t4, the second reset phase t5 and the third reset phase t6;
  • K1 provides a low-voltage signal
  • K2 provides a high-voltage signal
  • I1 and I2 provide a low-voltage signal
  • R1 provides a low-voltage signal
  • M11 is turned on
  • M6 is turned on
  • M13 is turned off
  • PD1 The potential of M7 is low voltage
  • M7 is turned on
  • the potential of PD2 is low voltage
  • M8 is turned on
  • the potential of PU1 is high voltage
  • M9 is turned off
  • M6 is turned on
  • the potential of PU is high voltage
  • M01 is turned on
  • M02 is turned off
  • E1 output is low Voltage signal
  • M1 is turned off
  • M2 is turned on
  • M3 is turned off
  • M4 is turned on
  • M5 is turned off
  • the potential of the PPU is maintained at a high voltage
  • G1 outputs a high voltage signal
  • K1 provides a high voltage signal
  • K2 provides a low voltage signal
  • I1 and I2 provide a low voltage signal
  • R1 provides a low voltage signal
  • M11 is turned off
  • M6 is turned off
  • K2 provides The potential of the second clock signal decreases, so the potential of PD1 is further reduced due to coupling
  • M7 is turned on
  • the potential of PD2 is a high voltage
  • M12 is turned off
  • M8 turned off
  • the potential of PU1 is a high voltage
  • M9 is turned on
  • M10 is turned on
  • the potential of PU is high voltage
  • M01 is turned on
  • M02 is turned off
  • E1 outputs a low voltage signal
  • M1 is turned off
  • M2 is turned on
  • M3 is turned off
  • M4 is turned on
  • M5 is turned off
  • the potential of PPU is high voltage
  • G1 outputs a high voltage signal ;
  • K1 provides a low voltage signal
  • K2 provides a high voltage signal
  • I1 and I2 provide a high voltage signal
  • R1 provides a low voltage signal
  • M11 is turned on
  • M6 is turned on
  • M13 is turned off
  • PD1 The potential of M7 is high voltage
  • M7 is turned off
  • the potential of PD2 is low voltage
  • M8 is turned on
  • the potential of PU1 is high voltage
  • M9 is turned off
  • M10 is turned off
  • the potential of PU is maintained at high voltage
  • M01 and M02 are both turned off
  • E1 keeps outputting low voltage signal
  • M1 is turned off
  • M2 is turned off
  • M3 is turned off
  • M4 is turned off
  • M5 is turned off
  • the potential of PPU is maintained at high voltage
  • G1 continues to output high voltage signal
  • K1 provides a high-voltage signal
  • K2 provides a low-voltage signal
  • I1 and I2 provide a high-voltage signal
  • R1 provides a low-voltage signal
  • M11 and M6 are turned off, and the potential of PD2 is maintained at Low voltage
  • M13 and M12 are turned on, the potential of PD1 is high voltage
  • M8 is turned on
  • the potential of PU1 is low voltage
  • M9 turned on
  • the potential of PU low voltage
  • M01 is turned off
  • M02 is turned on
  • E1 outputs a high voltage signal
  • M1 is turned on
  • M2 is turned off
  • M3 is turned on
  • M4 is turned off
  • M5 is turned on
  • the potential of the PPU is low voltage
  • G1 outputs a high voltage signal
  • K1 provides a low voltage signal
  • K2 provides a high voltage signal
  • I1 and I2 provide a high voltage signal
  • R1 provides a high voltage signal
  • M11 and M6 are turned on, and the potential of PD1 is a high voltage
  • M7 is turned off
  • the potential of PD2 is low voltage
  • M13 is turned off
  • M8 is turned on
  • the potential of PU1 is a high voltage signal
  • M9 turned off
  • M10 is turned off
  • the potential of PU is maintained at low voltage
  • M01 is turned off
  • M02 is turned on
  • E1 outputs a high voltage signal
  • M1 is turned off
  • M2 is turned off
  • M3 is turned on
  • M4 is turned off
  • M5 is turned off
  • G1 outputs a low voltage signal
  • the potential of the PPU is reduced to a lower voltage due to coupling
  • K1 provides a high voltage signal
  • K2 provides a low voltage signal
  • I1 and I2 provide a low voltage signal
  • R1 provides a high voltage signal
  • M11 and M6 are turned off, and the potential of PD2 is maintained at Low voltage
  • M12 and M13 are turned on, the potential of PD1 is high voltage
  • M8 is turned on
  • the potential of PU1 is low voltage
  • M10 is turned off
  • the potential of PU low voltage
  • M01 is turned off
  • M02 is turned on
  • E1 outputs a high voltage signal
  • M1 is turned on
  • M2 is turned on
  • M3 is turned off
  • M4 is turned on
  • M5 is turned on
  • the potential of the PPU is high voltage
  • G1 outputs a high voltage signal
  • K1 provides a low-voltage signal
  • K2 provides a high-voltage signal
  • I1 and I2 provide a low-voltage signal
  • R1 provides a high-voltage signal
  • M11 and M6 are turned on, M11 is turned off, and PD1
  • the potential is low voltage
  • M10 is turned on
  • M9 is turned off
  • the potential of PU is high voltage
  • M7 is turned on
  • the potential of PD2 is low voltage
  • M8 is turned on
  • the potential of PU1 is high voltage
  • M01 is turned on
  • M02 is turned off
  • E1 outputs low voltage Signal
  • M1 is turned off
  • M2 is turned on
  • M3 is turned off
  • M4 is turned on
  • M5 is turned off
  • the potential of the PPU is high voltage
  • G1 outputs a high voltage signal
  • K1 provides a high-voltage signal
  • K2 provides a low-voltage signal
  • I1 and I2 provide a low-voltage signal
  • R1 provides a low-voltage signal
  • M11 and M6 are turned off, due to the first
  • the potential of the second clock signal is reduced from high voltage to low voltage, then the potential of PD1 is further reduced due to coupling, M7 is turned on, the potential of PD2 is high voltage, M12 is turned off, M8 is turned off, the potential of PU1 is maintained at high voltage, M9
  • M10 is on, the potential of PU is high voltage, M01 is on, M02 is off, E1 outputs a low voltage signal; M1 is off, M2 is on, M3 is off, M4 is on, M5 is off, the potential of PPU is high voltage, G1 outputs a high voltage signal.
  • the driving circuit described in at least one embodiment of the present disclosure can simultaneously output a light-emitting control signal and a gate drive signal during operation, and the pulse width of the light-emitting control signal can be adjusted.
  • the time for which the potential of the light emission control signal output by the driving circuit according to at least one embodiment of the present disclosure remains at a high voltage is 7H.
  • the time for which the potential of the light-emitting control signal output by the driving circuit according to at least one embodiment of the present disclosure remains at a high voltage is 5H.
  • the time for which the potential of the light emission control signal output by the driving circuit according to at least one embodiment of the present disclosure remains at a high voltage is 3H.
  • the fifth node control subcircuit 51 includes a sixth transistor M6 and a seventh transistor M7;
  • the gate of the sixth transistor M6 is electrically connected to the first clock signal terminal K1, the first pole of the sixth transistor M6 is electrically connected to the low voltage terminal V02, and the second pole of the sixth transistor M6 is electrically connected to the fifth Node PD2 is electrically connected;
  • the gate of the seventh transistor M7 is electrically connected to the third node PD1, the first pole of the seventh transistor M7 is electrically connected to the first clock signal terminal K1, and the second pole of the seventh transistor M7 is electrically connected to the fifth node PD1.
  • Node PD2 is electrically connected;
  • the first node control sub-circuit 52 includes an eighth transistor M8 and a second capacitor C2, and the conduction control circuit 60 includes a first conduction control transistor M21;
  • the gate of the first conduction control transistor M21 is electrically connected to the low voltage terminal V02, the first pole of the first conduction control transistor M21 is electrically connected to the fifth node PD2, and the first conduction control transistor M21 The second pole of is electrically connected to the sixth node PD22;
  • the gate of the eighth transistor M8 is electrically connected to the sixth node PD22, the first pole of the eighth transistor M8 is electrically connected to the second clock signal terminal K2, and the second pole of the eighth transistor M8 is electrically connected to the first node PU1 electrical connection;
  • the first end of the second capacitor C2 is electrically connected to the sixth node PD22, and the second end of the second capacitor C2 is electrically connected to the first node PU1;
  • the second node control circuit 12 includes a ninth transistor M9, a tenth transistor M10 and a control capacitor C0;
  • the gate of the ninth transistor M9 is electrically connected to the second clock signal terminal K2, the first pole of the ninth transistor M9 is electrically connected to the first node PU1, and the second pole of the ninth transistor M9 is electrically connected to the second node PU;
  • the gate of the tenth transistor M10 is electrically connected to the third node PD1, the first pole of the tenth transistor M10 is electrically connected to the high voltage terminal V01, and the second pole of the tenth transistor M10 is electrically connected to the second node PU;
  • the first end of the control capacitor C0 is electrically connected to the second node PU, and the second end of the control capacitor C0 is electrically connected to the high voltage end V01;
  • the conduction subcircuit 70 includes a second conduction control transistor M22, the third node control subcircuit 80 includes an eleventh transistor M11; the seventh node control subcircuit 81 includes a twelfth transistor M12 and a tenth transistor M11. Three transistors M13; the eighth node control subcircuit 82 includes a third capacitor C3;
  • the gate of the second conduction control transistor M22 is electrically connected to the low voltage terminal V02, the first pole of the second conduction control transistor M22 is electrically connected to the third node PD1, and the second conduction control transistor M22 The second pole of is electrically connected to the eighth node PD11;
  • the gate of the eleventh transistor M11 is electrically connected to the first clock signal terminal K1, the first pole of the eleventh transistor M11 is electrically connected to the second input terminal I2, and the second pole of the eleventh transistor M11 is electrically connected to the third node PD1. electrical connection;
  • the gate of the twelfth transistor M12 is electrically connected to the fifth node PD2, the first pole of the twelfth transistor M12 is electrically connected to the high voltage terminal V01, and the second pole of the twelfth transistor M12 is electrically connected to the seventh node N1;
  • the gate of the thirteenth transistor M13 is electrically connected to the eighth node PD11, the first pole of the thirteenth transistor M13 is electrically connected to the second clock signal terminal K2, and the second pole of the thirteenth transistor M13 is electrically connected to the seventh node N1. connect;
  • the first end of the third capacitor C3 is electrically connected to the seventh node N1, and the second end of the third capacitor C3 is electrically connected to the eighth node PD11;
  • the light emission control output sub-circuit 71 includes a first output transistor M01 and a second output transistor M02;
  • the gate of the first output transistor M01 is electrically connected to the eighth node PD11, the first pole of the first output transistor M01 is electrically connected to the low voltage terminal V02, and the second pole of the first output transistor M01 is electrically connected to the light emission control signal output terminal E1. connect;
  • the gate of the second output transistor M02 is electrically connected to the second node PU, the first pole of the second output transistor M02 is electrically connected to the light emission control signal output terminal E1, and the second pole of the second output transistor M02 is electrically connected to the high voltage terminal V02. connect.
  • both I1 and I2 are electrically connected to the light-emitting control signal output end of the adjacent upper-level driving circuit, and R1 is electrically connected to the light-emitting control signal output terminal of the adjacent next-level driving circuit. electrical connection.
  • all transistors are p-type transistors, but not limited thereto.
  • M21 and M22 may not be provided.
  • the benefits of adding M21 are as follows: to stabilize the potential of PD22, reduce the influence of M7 leakage, and thus stabilize the control of M8;
  • the benefits of adding M22 are as follows: it can stabilize the low potential of PD11 and reduce the influence of the leakage of M11 on the potential of PD11.
  • K1 provides a low voltage signal
  • K2 provides a high voltage signal
  • I1 and I2 provide a high voltage signal
  • M11 and M6 are turned on
  • the potential of PD1 is a high voltage
  • M22 is turned on
  • the potential of PD11 is a high voltage
  • PD2 The potential of M21 is low voltage
  • M21 is turned on
  • the potential of PD22 is low voltage
  • M8 is turned on
  • the potential of PU1 is high voltage
  • M9 is turned off
  • the potential of PU is maintained at high voltage
  • M10 is turned off
  • M13 is turned off
  • M12 is turned on
  • N1 The potential is high voltage, both M01 and M02 are turned off, and E1 continues to output low voltage signals;
  • K1 provides a high voltage signal
  • K2 provides a low voltage signal
  • I1 and I2 provide a high voltage signal
  • M11 and M6 are turned off
  • M7 is turned off
  • the potential of PD2 is maintained at a low voltage
  • M12 is turned on
  • N1's The potential is high voltage
  • the potential of PD11 is high voltage
  • the potential of PD1 is high voltage
  • M21 and M22 are turned on
  • the potential of PD22 is coupled to a lower voltage
  • M8 is turned on
  • the potential of PU1 is low voltage
  • M9 is turned on
  • the potential of PU When the voltage is low, M01 is turned off, M02 is turned on, and E1 outputs a high voltage signal;
  • K1 provides a low voltage signal
  • K2 provides a high voltage signal
  • I1 and I2 provide a high voltage signal
  • M11 and M6 are turned on
  • M22 is turned on
  • the potential of PD1 and the potential of PD11 are both high voltage
  • the potential of PD2 For low voltage, M21 is turned on, the potential of PD22 is low voltage, M12 is turned on, M13 is turned off, the potential of N1 is high voltage, M8 is turned on, the potential of PU1 is high voltage, M9 is turned off, M10 is turned off, and the potential of PU is maintained When the voltage is low, M01 is turned off, M02 is turned on, and E1 outputs a high voltage signal;
  • K1 provides a high voltage signal
  • K2 provides a low voltage signal
  • I1 and I2 provide a low voltage signal
  • M11 and M6 are turned off
  • the potential of PD1 is high voltage
  • M7 is turned off
  • the potential of PD2 is maintained at low Voltage
  • M21 is turned on
  • the potential of PD22 is further pulled down
  • M8 is turned on
  • the potential of PU1 is low voltage
  • M9 is turned on
  • the potential of PU is low voltage
  • M12 is turned on
  • M13 is turned off
  • the potential of N1 is high voltage
  • the potential of PD11 For high voltage, M01 is turned off, M02 is turned on, and E1 outputs a high voltage signal;
  • K1 provides a low voltage signal
  • K2 provides a high voltage signal
  • I1 and I2 provide a low voltage signal
  • M11 and M6 are turned on
  • the potential of PD1 is low voltage
  • M7 is turned on
  • the potential of PD2 is low voltage
  • M12 Open M22 is open
  • the potential of PD11 is low voltage
  • M13 is open
  • the potential of N1 is high voltage
  • M21 is open
  • the potential of PD22 is low voltage
  • M8 is open
  • the potential of PU1 is high voltage
  • M9 is closed
  • M10 is open
  • PU The potential is high voltage
  • M01 is turned on
  • M02 is turned off
  • E1 outputs a low voltage signal
  • K1 provides a high voltage signal
  • K2 provides a low voltage signal
  • I1 and I2 provide a low voltage signal
  • M11 and M6 are turned off
  • the potential of PD1 is low voltage
  • M7 is turned on
  • the potential of PD2 is high voltage
  • M12 is turned off
  • M22 is turned on
  • the potential of PD11 is low voltage
  • M13 is turned on
  • the potential of N1 is low voltage
  • the potential of PD11 is further pulled down
  • M10 is turned on
  • the potential of PU is high voltage
  • M01 is turned on
  • M02 is turned off
  • E1 Provides a low voltage signal.
  • a gate drive circuit 10 is provided, and the gate drive circuit 10 is respectively connected to the control node L1, the first input terminal I1, the reset terminal R1, the first clock
  • the signal terminal K1, the first voltage terminal V1 and the gate drive signal output terminal G1 are electrically connected to control the potential of the control node L1, the first input signal provided by the first input terminal I1 and the reset signal provided by the reset terminal R1
  • the gate drive signal output terminal G1 is controlled to output the gate drive signal.
  • the reset signal provided by the reset terminal R1 and the voltage signal of the first node PU1 of the bank are used as the signal obtained by "OR" operation as the input/reset function, that is, when the reset signal When the voltage signal of the first node PU1 of the bank is a valid voltage signal at the same time, the input function is realized.
  • the reset signal When the voltage signal of the first node PU1 of the bank is a valid voltage signal, and the reset signal is an invalid voltage signal, the reset function is realized.
  • I1 provides When the first input signal of is an effective voltage signal, denoising is performed for G1, so that the gate driving circuit 10 provided by at least one embodiment of the present disclosure can generate a gate driving signal.
  • control node L1 may be the first node in the light emission control signal generation circuit; the structure of the light emission control signal generation circuit may not be limited to the circuit structure provided in the embodiments of the present disclosure.
  • At least one embodiment of the gate drive circuit may include a fourth node control circuit 21 and a gate output circuit 23 ;
  • the fourth node control circuit 21 is electrically connected to the control node L1, the fourth node PPU, the reset terminal R1, the first input terminal I1, and the first voltage terminal V1 respectively, for controlling the potential of the control node L1 Controlling the connection or disconnection between the fourth node PPU and the reset terminal R1, and controlling the connection between the fourth node PPU and the reset terminal R1 under the control of the first input signal provided by the first input terminal I1 A voltage terminal V1 is connected or disconnected;
  • the gate output circuit 23 is electrically connected to the fourth node PPU, the gate drive signal output terminal G1, the first clock signal terminal K1, the first input terminal I1 and the first voltage terminal V1, for Under the control of the potential of the node PPU, the connection or disconnection between the gate driving signal output terminal G1 and the first clock signal terminal K1 is controlled, and under the control of the first input signal provided by the first input terminal I1, all
  • the gate driving signal output terminal G1 is connected or disconnected from the first voltage terminal V1, and is used to control the gate driving signal provided by the gate driving signal output terminal G1 according to the potential of the fourth node PPU.
  • the driving cycle may include a first input phase, a second input phase, a third input phase and a first reset phase arranged in sequence;
  • the fourth node control circuit 21 controls the disconnection between the fourth node PPU and the reset terminal R1 under the control of the potential of the control node L1, and controls the fourth node PPU under the control of the first input signal.
  • the PPU is disconnected from the first voltage terminal V1; under the control of the potential of the fourth node PPU, the gate output circuit 23 controls the disconnection between the gate drive signal output terminal G1 and the first clock signal terminal K1, and the first input Under the control of the signal, the gate drive signal output terminal G1 is controlled to be disconnected from the first voltage terminal V1, so that the gate drive signal output terminal G1 maintains outputting the first voltage signal;
  • the fourth node control circuit 21 controls the connection between the fourth node PPU and the reset terminal R1 under the control of the potential of the control node L1; Under control, the connection between the gate drive signal output terminal G1 and the first clock signal terminal K1 is controlled, so that the gate drive signal output terminal G1 outputs a first voltage signal;
  • the fourth node control circuit 21 controls the disconnection between the fourth node PPU and the reset terminal R1 under the control of the potential of the control node L1; Under control, the connection between the gate drive signal output terminal G1 and the first clock signal terminal K1 is controlled, so that the gate drive signal output terminal G1 outputs a second voltage signal;
  • the fourth node control circuit 21 controls the communication between the fourth node PPU and the reset terminal R1 under the control of the potential of the control node L1, and controls the connection between the fourth node PPU and the reset terminal R1 under the control of the first input signal.
  • the PPU is connected to the first voltage terminal V1; under the control of the potential of the fourth node PPU, the gate output circuit 23 controls the disconnection between the gate drive signal output terminal G1 and the first clock signal terminal K1, and the first input Under the control of the signal, the gate driving signal output terminal G1 is controlled to communicate with the first voltage terminal V1, so that the gate driving signal output terminal G1 outputs the first voltage signal.
  • the driving circuit described in at least one embodiment of the present disclosure may further include a gate reset circuit 24;
  • the gate reset circuit 24 is electrically connected to the control node L1, the gate drive signal output terminal G1, and the first voltage terminal V1, and is used to control the gate drive signal under the control of the potential of the control node L1.
  • the output terminal G1 is connected or disconnected from the first voltage terminal V1.
  • the gate reset circuit 24 is added to control the potential of the control node L11 and controlling the gate drive signal output terminal to output a first voltage signal to reset G1.
  • the gate reset circuit 24 controls the disconnection between the gate drive signal output terminal G1 and the first voltage terminal V1 under the control of the potential of the control node L1;
  • the gate reset circuit 24 controls the connection between the gate driving signal output terminal G1 and the first voltage terminal V1 under the control of the potential of the control node L1;
  • the gate reset circuit 24 controls the disconnection between the gate drive signal output terminal G1 and the first voltage terminal V1 under the control of the potential of the control node L1;
  • the gate reset circuit 24 controls the connection between the gate driving signal output terminal G1 and the first voltage terminal V1 under the control of the potential of the control node L1 to reset G1.
  • the fourth node control circuit 21 includes a first transistor M1 and a second transistor M2;
  • the gate of the first transistor M1 is electrically connected to the control node L1, the first pole of the first transistor M1 is electrically connected to the reset terminal R1, and the second pole of the first transistor M1 is electrically connected to the
  • the fourth node PPU is electrically connected;
  • the gate of the second transistor M2 is electrically connected to the first input terminal I1, the first pole of the second transistor M2 is electrically connected to the fourth node PPU, and the second pole of the second transistor M2 Electrically connected to the high voltage terminal V01;
  • the gate output circuit 23 includes a third transistor M3, a fourth transistor M4 and a first capacitor C1;
  • the gate of the third transistor M3 is electrically connected to the fourth node PPU, the first pole of the third transistor M3 is electrically connected to the first clock signal terminal K1, and the second pole of the third transistor M3 is electrically connected to the first clock signal terminal K1.
  • the gate drive signal output terminal G1 is electrically connected;
  • the gate of the fourth transistor M4 is electrically connected to the first input terminal I1, the first pole of the fourth transistor M4 is electrically connected to the gate drive signal output terminal G1, and the gate of the fourth transistor M4 The second pole is electrically connected to the high voltage terminal V01;
  • a first end of the first capacitor C1 is electrically connected to the fourth node PPU, and a second end of the first capacitor C1 is electrically connected to the gate drive signal output end G1.
  • each transistor is a p-type transistor.
  • control node L1 may be the first node in the light emitting control signal generating circuit.
  • K1 provides a low voltage signal
  • I1 provides a low voltage signal
  • R1 provides a low voltage signal
  • the potential of L1 is high voltage
  • the potential of PPU is high voltage
  • M1 is turned off
  • M2 is turned on
  • M3 is turned off
  • M4 is turned on
  • M5 is turned off
  • G1 outputs a high voltage signal
  • K1 provides a high voltage signal
  • I1 provides a low voltage signal
  • R1 provides a low voltage signal
  • the potential of L1 is high voltage
  • the potential of PPU is high voltage
  • M1 is turned off
  • M2 is turned on
  • M3 is turned off
  • M4 is turned on
  • M5 is turned off
  • G1 outputs a high voltage signal
  • K1 provides a low voltage signal
  • I1 provides a high voltage signal
  • R1 provides a low voltage signal
  • the potential of L1 is high voltage
  • the potential of PPU is high voltage
  • M1, M2, M3, M4 and M5 are all closed off
  • G1 continues to output high-voltage signals
  • K1 provides a high voltage signal
  • I1 provides a high voltage signal
  • R1 provides a low voltage signal
  • the potential of L1 is low voltage
  • the potential of PPU is pulled down
  • M1 is turned on
  • M2 is turned off
  • M3 is turned on
  • M4 Turn off
  • M5 is on
  • G1 provides a high voltage signal
  • K1 provides a low-voltage signal
  • I1 provides a high-voltage signal
  • R1 provides a high-voltage signal
  • the potential of L1 is a high voltage
  • the potential of the PPU is further pulled down
  • M1 and M2 are turned off
  • M3 is turned on
  • M4 Shut down
  • M5 is turned off
  • G1 provides a low voltage signal
  • K1 provides a high voltage signal
  • I1 provides a low voltage signal
  • R1 provides a high voltage signal
  • the potential of L1 is low voltage
  • the potential of PPU is high voltage
  • M1 and M2 are turned on
  • M3 is turned off
  • M4 is turned on
  • M5 is turned on
  • G1 provides a high voltage signal to reset G1;
  • K1 provides a low voltage signal
  • I1 provides a low voltage signal
  • R1 provides a high voltage signal
  • the potential of L1 is high voltage
  • the potential of PPU is high voltage
  • M1 is turned off
  • M2 is turned on
  • M3 is turned off
  • M4 is turned on
  • M5 is turned off
  • G1 provides a high voltage signal
  • K1 provides a high voltage signal
  • I1 provides a low voltage signal
  • R1 provides a low voltage signal
  • the potential of L1 is high voltage
  • the potential of PPU is high voltage
  • M1 is turned off
  • M2 is turned on
  • M3 is turned off
  • M4 is turned on
  • M5 is turned off
  • G1 provides a high voltage signal.
  • the gate drive circuit Under the control of the potential of the first node, the first input signal provided by the first input terminal and the reset signal provided by the reset terminal, the gate drive circuit provides the first clock signal provided by the first clock signal terminal and the first voltage terminal provided The first voltage signal controls the gate drive signal output end to output the gate drive signal.
  • the driving circuit can generate the gate driving signal while generating the light-emitting control signal, which can simplify the driving scheme, reduce the number of signals, and narrow the frame.
  • the driving method described in at least one embodiment of the present disclosure is applied to the above-mentioned driving circuit, and the driving cycle includes a first input phase, a second input phase, a third input phase and a first reset phase arranged in sequence; the driving method includes :
  • the fourth node control circuit controls the disconnection between the fourth node and the reset terminal under the control of the potential of the first node, and controls the disconnection between the fourth node and the first terminal under the control of the first input signal.
  • the voltage terminals are disconnected; under the control of the potential of the fourth node, the gate output circuit controls the disconnection between the gate drive signal output terminal and the first clock signal terminal, and controls the gate drive signal under the control of the first input signal.
  • the signal output terminal is disconnected from the first voltage terminal, so that the gate drive signal output terminal maintains outputting the first voltage signal;
  • the fourth node control circuit controls the communication between the fourth node and the reset terminal under the control of the potential of the first node;
  • the pole drive signal output end is connected to the first clock signal end, so that the gate drive signal output end outputs a first voltage signal;
  • the fourth node control circuit controls the disconnection between the fourth node and the reset terminal; under the control of the potential of the fourth node, the gate output circuit controls the gate
  • the pole drive signal output end is connected to the first clock signal end, so that the gate drive signal output end outputs a second voltage signal;
  • the fourth node control circuit controls the communication between the fourth node and the reset terminal under the control of the potential of the first node, and controls the communication between the fourth node and the first terminal under the control of the first input signal.
  • the voltage terminals are connected; under the control of the potential of the fourth node, the gate output circuit controls the disconnection between the gate drive signal output terminal and the first clock signal terminal, and controls the gate drive signal under the control of the first input signal.
  • the signal output end communicates with the first voltage end, so that the gate drive signal output end outputs the first voltage signal.
  • the driving circuit further includes a gate reset circuit; the driving method further includes:
  • the gate reset circuit controls the disconnection between the gate drive signal output terminal and the first voltage terminal under the control of the potential of the first node
  • the gate reset circuit controls the communication between the gate drive signal output terminal and the first voltage terminal under the control of the potential of the first node
  • the gate reset circuit controls the disconnection between the gate drive signal output terminal and the first voltage terminal under the control of the potential of the first node
  • the gate reset circuit controls the communication between the gate drive signal output terminal and the first voltage terminal under the control of the potential of the first node.
  • the gate reset circuit in order to prevent the potential of the first input signal provided by the first input terminal from continuing to be an invalid voltage for too long and fail to reset the output terminal of the gate drive signal in time, the gate reset circuit is added to Under the control of the potential of a node, the gate drive signal output terminal is controlled to output a first voltage signal, so as to reset the gate drive signal output terminal.
  • the driving module described in the embodiment of the present disclosure includes multiple stages of the above-mentioned driving circuits.
  • the second input end of the driving circuit may be electrically connected to the light emission control signal output end of an adjacent upper level driving circuit.
  • the first input end of the drive circuit is electrically connected to the light emission control signal output end of the adjacent upper stage drive circuit; or, the first input end of the drive circuit is connected to the light emission control signal output end of the drive circuit electrical connection.
  • the reset terminal of the drive circuit is electrically connected to the light emission control signal output terminal of the adjacent next-level drive circuit; or, the reset terminal is electrically connected to the gate drive signal output terminal of the adjacent upper-level drive circuit. connect.
  • the display device described in the embodiment of the present disclosure includes the above-mentioned driving module.
  • the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • the display device provided by at least one embodiment of the present disclosure may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Electronic Switches (AREA)

Abstract

本公开提供一种驱动电路、驱动方法、驱动模组和显示装置。驱动电路包括发光控制信号生成电路和栅极驱动电路；栅极驱动电路用于在第一节点的电位、第一输入端提供的第一输入信号和复位端提供的复位信号的控制下，根据第一时钟信号端提供的第一时钟信号和第一电压端提供的第一电压信号，控制栅极驱动信号输出端输出栅极驱动信号。本公开能够在生成发光控制信号的同时，生成栅极驱动信号，能简化驱动方案，减少信号数量，并窄化边框。

Description

驱动电路、驱动方法、驱动模组和显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种驱动电路、驱动方法、驱动模组和显示装置。
背景技术
在相关技术中，需要采用两个驱动电路分别生成发光控制信号、栅极驱动信号，不能简化驱动方案，不利于窄化边框。
发明内容
在一个方面中，本公开实施例提供了一种驱动电路，包括发光控制信号生成电路和栅极驱动电路；所述发光控制信号生成电路包括第一节点控制电路、第二节点控制电路、第三节点控制电路和发光控制输出电路；
所述第一节点控制电路用于控制第一节点的电位；
所述第二节点控制电路用于控制第二节点的电位；
所述第三节点控制电路用于控制第三节点的电位；
所述发光控制输出电路用于根据所述第二节点的电位和所述第三节点的电位，控制发光控制信号输出端输出发光控制信号；
所述栅极驱动电路用于在第一节点的电位、第一输入端提供的第一输入信号和复位端提供的复位信号的控制下，根据第一时钟信号端提供的第一时钟信号和第一电压端提供的第一电压信号，控制栅极驱动信号输出端输出栅极驱动信号。
可选的，所述栅极驱动电路包括第四节点控制电路和栅极输出电路；
所述第四节点控制电路用于在所述第一节点的电位的控制下，控制所述第四节点与所述复位端之间连通或断开，在所述第一输入端提供的第一输入信号的控制下，控制所述第四节点与所述第一电压端之间连通或断开；
所述栅极输出电路用于在所述第四节点的电位的控制下，控制所述栅极 驱动信号输出端与第一时钟信号端之间连通或断开在所述第一输入信号的控制下，控制所述栅极驱动信号输出端与所述第一电压端连通或断开，并用于根据所述第四节点的电位，控制所述栅极驱动信号输出端提供的栅极驱动信号。
可选的，本公开至少一实施例所述的驱动电路还包括栅极复位电路；
所述栅极复位电路用于在所述第一节点的电位的控制下，控制所述栅极驱动信号输出端与所述第一电压端之间连通或断开。
可选的，所述第四节点控制电路包括第一晶体管和第二晶体管；
所述第一晶体管的控制极与所述第一节点电连接，所述第一晶体管的第一极与所述复位端电连接，所述第一晶体管的第二极与所述第四节点电连接；
所述第二晶体管的控制极与所述第一输入端电连接，所述第二晶体管的第一极与所述第四节点电连接，所述第二晶体管的第二极与所述第一电压端电连接。
可选的，所述栅极输出电路包括第三晶体管、第四晶体管和第一电容；
所述第三晶体管的控制极与所述第四节点电连接，所述第三晶体管的第一极与第一时钟信号端电连接，所述第三晶体管的第二极与所述栅极驱动信号输出端电连接；
所述第四晶体管的控制极与所述第一输入端电连接，所述第四晶体管的第一极与所述栅极驱动信号输出端电连接，所述第四晶体管的第二极与所述第一电压端电连接；
所述第一电容的第一端与所述第四节点电连接，所述第一电容的第二端与所述栅极驱动信号输出端电连接。
可选的，所述栅极复位电路包括第五晶体管；
所述第五晶体管的控制极与所述第一节点电连接，所述第五晶体管的第一极与所述栅极驱动信号输出端电连接，所述第五晶体管的第二极与所述第一电压端电连接。
可选的，所述第一节点控制电路包括第五节点控制子电路和第一节点控制子电路；
所述第五节点控制子电路用于在第一时钟信号端提供的第一时钟信号的 控制下，控制第五节点与第二电压端之间连通或断开，在第三节点的电位的控制下，控制所述第五节点与第一时钟信号端之间连通或断开；
所述第一节点控制子电路用于根据第五节点的电位和第二时钟信号端提供的第二时钟信号，控制第一节点的电位。
可选的，第五节点控制子电路包括第六晶体管和第七晶体管；
所述第六晶体管的控制极与第一时钟信号端电连接，所述第六晶体管的第一极与第二电压端电连接，所述第六晶体管的第二极与第五节点电连接；
所述第七晶体管的控制极与第三节点电连接，所述第七晶体管的第一极与第一时钟信号端电连接，所述第七晶体管的第二极与第五节点电连接。
可选的，所述第一节点控制子电路用于在所述第五节点的电位的控制下，控制第一节点与第二时钟信号端之间连通或断开，并用于根据所述第五节点的电位，控制所述第一节点的电位。
可选的，所述第一节点控制子电路包括第八晶体管和第二电容；
第八晶体管的控制极与所述第五节点电连接，第八晶体管的第一极与第二时钟信号端电连接，第八晶体管的第二极与第一节点电连接；
第二电容的第一端与第五节点电连接，第二电容的第二端与第一节点电连接。
可选的，本公开至少一实施例所述的驱动电路还包括导通控制电路；所述导通控制电路用于在第二电压端提供的第二电压信号的控制下，控制第五节点与第六节点之间连通或断开；
所述第一节点控制子电路用于在所述第六节点的电位的控制下，控制第一节点与第二时钟信号端之间连通或断开，并用于根据所述第六节点的电位，控制所述第一节点的电位。
可选的，第一节点控制子电路包括第八晶体管和第二电容，所述导通控制电路包括第一导通控制晶体管；
所述第一导通控制晶体管的控制极与第二电压端电连接，所述第一导通控制晶体管的第一极与第五节点电连接，所述第一导通控制晶体管的第二极与第六节点电连接；
所述第八晶体管的控制极与所述第六节点电连接，第八晶体管的第一极 与第二时钟信号端电连接，第八晶体管的第二极与第一节点电连接；
第二电容的第一端与第六节点电连接，第二电容的第二端与第一节点电连接。
可选的，所述第二节点控制电路用于在第二时钟信号端提供的第二时钟信号的控制下，控制所述第一节点与所述第二节点之间连通或断开，并用于在所述第三节点的电位的控制下，控制所述第二节点与第一电压端之间连通或断开，并用于维持第二节点的电位。
可选的，所述第二节点控制电路包括第九晶体管、第十晶体管和控制电容；
第九晶体管的控制极与第二时钟信号端电连接，第九晶体管的第一极与第一节点电连接，第九晶体管的第二极与第二节点电连接；
第十晶体管的控制极与第三节点电连接，第十晶体管的第一极与第一电压端电连接，第十晶体管的第二极与第二节点电连接；
所述控制电容的第一端与所述第二节点电连接，所述控制电容的第二端与第一电压端。
可选的，所述第三节点控制电路用于在第一时钟信号端提供的第一时钟信号的控制下，控制第三节点与第二输入端之间连通或断开，在第五节点的电位和第二时钟信号的控制下，控制所述第三节点与第一电压端之间连通或断开，并用于根据第二时钟信号控制第三节点的电位。
可选的，所述第三节点控制电路包括第十一晶体管、第十二晶体管、第十三晶体管和第三电容；
第十一晶体管的控制极与第一时钟信号端电连接，第十一晶体管的第一极与第二输入端电连接，第十一晶体管的第二极与第三节点电连接；
第十二晶体管的控制极与第五节点电连接，第十二晶体管的第一极与第一电压端电连接；
第十三晶体管的控制极与第二时钟信号端电连接，第十三晶体管的第一极与第十二晶体管的第二极电连接，第十三晶体管的第二极与第三节点电连接；
第三电容的第一端与第二时钟信号端电连接，第三电容的第二端与第三 节点电连接。
可选的，所述第三节点控制电路包括第七节点控制子电路和第三节点控制子电路；
所述第七节点控制子电路用于在第五节点的电位的控制下，控制所述第七节点与第一电压端之间连通或断开，在第三节点的电位的控制下，控制所述第七节点与第二时钟信号端之间连通或断开；
所述第三节点控制子电路用于根据所述第七节点的电位，控制所述第三节点的电位，并在第一时钟信号端提供的第一时钟信号的控制下，控制第三节点与第二输入端之间连通或断开。
可选的，第三节点控制子电路包括第十一晶体管和第三电容；第七节点控制子电路包括第十二晶体管和第十三晶体管；
第十一晶体管的控制极与第一时钟信号端电连接，第十一晶体管的第一极与第二输入端电连接，第十一晶体管的第二极与第三节点电连接；
第十二晶体管的控制极与第五节点电连接，第十二晶体管的第一极与第一电压端电连接，第十二晶体管的第二极与第七节点电连接；
第十三晶体管的控制极与第三节点电连接，第十三晶体管的第一极与第二时钟信号端电连接，第十三晶体管的第二极与第七节点电连接；
第三电容的第一端与第七节点电连接，第三电容的第二端与第三节点电连接。
可选的，所述发光控制输出电路包括导通子电路；所述第三节点控制电路包括第三节点控制子电路、第七节点控制子电路和第八节点控制子电路；
所述导通子电路用于在第二电压端提供的第二电压信号的控制下，控制第三节点与第八节点之间连通或断开；
所述第三节点控制子电路用于在第一时钟信号端提供的第一时钟信号的控制下，控制第三节点与第二输入端之间连通或断开；
所述第七节点控制子电路用于在第五节点的电位的控制下，控制所述第七节点与第一电压端之间连通或断开，在第八节点的电位的控制下，控制所述第七节点与第二时钟信号端之间连通或断开；
所述第八节点控制子电路用于根据所述第七节点的电位，控制所述第八 节点的电位。
可选的，所述导通子电路包括第二导通控制晶体管，所述第三节点控制子电路包括第十一晶体管，所述第七节点控制子电路包括第十二晶体管和第十三晶体管；所述第八节点控制子电路包括第三电容；
所述第二导通控制晶体管的控制极与第二电压端电连接，所述第二导通控制晶体管的第一极与第三节点电连接，所述第二导通控制晶体管的第二极与第八节点电连接；
第十一晶体管的控制极与第一时钟信号端电连接，第十一晶体管的第一极与第二输入端电连接，第十一晶体管的第二极与第三节点电连接；
第十二晶体管的控制极与第五节点电连接，第十二晶体管的第一极与第一电压端电连接，第十二晶体管的第二极与第七节点电连接；
第十三晶体管的控制极与第八节点电连接，第十三晶体管的第一极与第二时钟信号端电连接，第十三晶体管的第二极与第七节点电连接；
第三电容的第一端与第七节点电连接，第三电容的第二端与第八节点电连接。
可选的，所述发光控制输出电路包括第一输出晶体管和第二输出晶体管；
第一输出晶体管的控制极与第三节点电连接，第一输出晶体管的第一极与第二电压端电连接，第一输出晶体管的第二极与发光控制信号输出端电连接；
第二输出晶体管的控制极与第二节点电连接，第二输出晶体管的第一极与发光控制信号输出端电连接，第二输出晶体管的第二极与第一电压端电连接。
可选的，所述发光控制输出电路包括第二导通控制晶体管、第一输出晶体管和第二输出晶体管；
所述第二导通控制晶体管的控制极与第二电压端电连接，所述第二导通控制晶体管的第一极与第三节点电连接，所述第二导通控制晶体管的第二极与第八节点电连接；
第一输出晶体管的控制极与第八节点电连接，第一输出晶体管的第一极与第二电压端电连接，第一输出晶体管的第二极与发光控制信号输出端电连 接；
第二输出晶体管的控制极与第二节点电连接，第二输出晶体管的第一极与发光控制信号输出端电连接，第二输出晶体管的第二极与第一电压端电连接。
在第二个方面中，本公开还提供了一种驱动方法，应用于上述的驱动电路，所述驱动方法包括：
栅极驱动电路在第一节点的电位、第一输入端提供的第一输入信号和复位端提供的复位信号的控制下，根据第一时钟信号端提供的第一时钟信号和第一电压端提供的第一电压信号，控制栅极驱动信号输出端输出栅极驱动信号。
可选的，驱动周期包括依次设置的第一输入阶段、第二输入阶段、第三输入阶段和第一复位阶段；所述驱动方法包括：
在第一输入阶段，所述第四节点控制电路在第一节点的电位的控制下，控制第四节点与复位端之间断开，在第一输入信号的控制下，控制第四节点与第一电压端之间断开；栅极输出电路在第四节点的电位的控制下，控制栅极驱动信号输出端与第一时钟信号端之间断开，在第一输入信号的控制下，控制栅极驱动信号输出端与所述第一电压端断开，以使得栅极驱动信号输出端维持输出第一电压信号；
在第二输入阶段，所述第四节点控制电路在第一节点的电位的控制下，控制第四节点与复位端之间连通；栅极输出电路在第四节点的电位的控制下，控制栅极驱动信号输出端与第一时钟信号端之间连通，以使得栅极驱动信号输出端输出第一电压信号；
在第三输入阶段，所述第四节点控制电路在第一节点的电位的控制下，控制第四节点与复位端之间断开；栅极输出电路在第四节点的电位的控制下，控制栅极驱动信号输出端与第一时钟信号端之间连通，以使得栅极驱动信号输出端输出第二电压信号；
在第一复位阶段，所述第四节点控制电路在第一节点的电位的控制下，控制第四节点与复位端之间连通，在第一输入信号的控制下，控制第四节点与第一电压端之间连通；栅极输出电路在第四节点的电位的控制下，控制栅 极驱动信号输出端与第一时钟信号端之间断开，在第一输入信号的控制下，控制栅极驱动信号输出端与所述第一电压端连通，以使得栅极驱动信号输出端输出第一电压信号。
可选的，所述驱动电路还包括栅极复位电路；所述驱动方法还包括：
在第一输入阶段，栅极复位电路在第一节点的电位的控制下，控制所述栅极驱动信号输出端与所述第一电压端之间断开；
在第二输入阶段，栅极复位电路在第一节点的电位的控制下，控制所述栅极驱动信号输出端与所述第一电压端之间连通；
在第三输入阶段，栅极复位电路在第一节点的电位的控制下，控制所述栅极驱动信号输出端与所述第一电压端之间断开；
在第一复位阶段，栅极复位电路在第一节点的电位的控制下，控制所述栅极驱动信号输出端与所述第一电压端之间连通。
在第三个方面中，本公开还提供了一种驱动模组，包括多级上述的驱动电路。
可选的，所述驱动电路的第二输入端与相邻上一级驱动电路的发光控制信号输出端电连接。
可选的，所述驱动电路的第一输入端与相邻上一级驱动电路的发光控制信号输出端电连接；或者，所述驱动电路的第一输入端与该驱动电路的发光控制信号输出端电连接。
可选的，所述驱动电路的复位端与相邻下一级驱动电路的发光控制信号输出端电连接；或者，所述复位端与相邻上一级驱动电路的栅极驱动信号输出端电连接。
在第四个方面中，本公开实施例提供一种显示装置，包括上述的驱动模组。
附图说明
图1是本公开实施例所述的驱动电路的结构图；
图2是本公开至少一实施例所述的驱动电路的结构图；
图3是本公开至少一实施例所述的驱动电路的结构图；
图4是本公开至少一实施例所述的驱动电路的结构图；
图5是图4所示的驱动电路的至少一实施例的工作时序图；
图6是本公开至少一实施例所述的驱动电路的结构图；
图7是本公开至少一实施例所述的驱动电路的结构图；
图8是本公开至少一实施例所述的驱动电路的结构图；
图9是本公开至少一实施例所述的驱动电路的结构图；
图10是本公开至少一实施例所述的驱动电路的电路图；
图11是本公开如图10所述的驱动电路的至少一实施例的工作时序图；
图12A是本公开如图10所述的驱动电路的至少一实施例在第一准备阶段t01的工作状态示意图；
图12B是本公开如图10所述的驱动电路的至少一实施例在第二准备阶段t02的工作状态示意图；
图12C是本公开如图10所述的驱动电路的至少一实施例在第一输入阶段t1的工作状态示意图；
图12D是本公开如图10所述的驱动电路的至少一实施例在第二输入阶段t2的工作状态示意图；
图12E是本公开如图10所述的驱动电路的至少一实施例在第三输入阶段t3的工作状态示意图；
图12F是本公开如图10所述的驱动电路的至少一实施例在第一复位阶段t4的工作状态示意图；
图12G是本公开如图10所述的驱动电路的至少一实施例在第二复位阶段t5的工作状态示意图；
图12H是本公开如图10所述的驱动电路的至少一实施例在第三复位阶段t6的工作状态示意图；
图13是本公开至少一实施例所述的驱动电路提供的发光控制信号和栅极驱动信号的一波形图；
图14是本公开至少一实施例所述的驱动电路提供的发光控制信号和栅极驱动信号的一波形图；
图15是本公开至少一实施例所述的驱动电路提供的发光控制信号和栅 极驱动信号的一波形图；
图16是本公开至少一实施例所述的驱动电路的电路图；
图17是本公开如图16所述的驱动电路的至少一实施例的工作时序图；
图18所示是本公开至少一实施例提供的栅极驱动电路的结构图；
图19是所述栅极驱动电路的至少一实施例的结构图；
图20是所述栅极驱动电路的至少一实施例的结构图；
图21是所述栅极驱动电路的至少一实施例的电路图；
图22是所述栅极驱动电路的至少一实施例的工作时序图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为三极管、薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除控制极之外的两极，将其中一极称为第一极，另一极称为第二极。
在实际操作时，当所述晶体管为三极管时，所述控制极可以为基极，所述第一极可以为集电极，所述第二极可以发射极；或者，所述控制极可以为基极，所述第一极可以为发射极，所述第二极可以集电极。
在实际操作时，当所述晶体管为薄膜晶体管或场效应管时，所述控制极可以为栅极，所述第一极可以为漏极，所述第二极可以为源极；或者，所述控制极可以为栅极，所述第一极可以为源极，所述第二极可以为漏极。
如图1所示，本公开实施例所述的驱动电路包括发光控制信号生成电路和栅极驱动电路10；所述发光控制信号生成电路包括第一节点控制电路11、第二节点控制电路12、第三节点控制电路13和发光控制输出电路14；
所述第一节点控制电路11与第一节点PU1电连接，用于控制第一节点PU1的电位；
所述第二节点控制电路12与第二节点PU电连接，用于控制第二节点PU 的电位；
所述第三节点控制电路13与第三节点PD1电连接，用于控制第三节点PD1的电位；
所述发光控制输出电路14分别与第二节点PU、第三节点PD1和发光控制信号输出端E1电连接，用于根据所述第二节点PU的电位和所述第三节点PD1的电位，控制发光控制信号输出端E1输出发光控制信号；
所述栅极驱动电路10分别与第一节点PU1、第一输入端I1、复位端R1、第一时钟信号端K1、第一电压端V1和栅极驱动信号输出端G1电连接，用于在第一节点PU1的电位、第一输入端I1提供的第一输入信号和复位端R1提供的复位信号的控制下，根据第一时钟信号端K1提供的第一时钟信号和第一电压端V1提供的第一电压信号，控制栅极驱动信号输出端G1输出栅极驱动信号。
在本公开实施例所述的驱动电路中，增加生成栅极驱动信号的栅极驱动电路，以复位端R1提供的复位信号与本行第一节点PU1的电压信号进行“或”运算所得信号作为输入/复位功能，也即，当复位信号与本行第一节点PU1的电压信号同时为有效电压信号时实现输入功能，当本行第一节点PU1的电压信号为有效电压信号，而复位信号为无效电压信号时实现复位功能，当I1提供的第一输入信号为有效电压信号时，为G1去噪，从而使得本公开实施例所述的驱动电路能够在生成发光控制信号的同时，生成栅极驱动信号，能简化驱动方案，减少信号数量，并窄化边框。
如图2所示，本公开实施例所述的驱动电路包括发光控制信号生成电路和栅极驱动电路；所述发光控制信号生成电路包括第一节点控制电路11、第二节点控制电路12、第三节点控制电路13和发光控制输出电路14；所述栅极驱动电路包括第四节点控制电路21和栅极输出电路23；
所述第一节点控制电路11与第一节点PU1电连接，用于控制第一节点PU1的电位；
所述第二节点控制电路12与第二节点PU电连接，用于控制第二节点PU的电位；
所述第三节点控制电路13与第三节点PD1电连接，用于控制第三节点 PD1的电位；
所述发光控制输出电路14分别与第二节点PU、第三节点PD1和发光控制信号输出端E1电连接，用于根据所述第二节点PU的电位和所述第三节点PD1的电位，控制发光控制信号输出端E1输出发光控制信号；
所述第四节点控制电路21分别与第一节点PU1、第四节点PPU、复位端R1、第一输入端I1和第一电压端V1电连接，用于在所述第一节点PU1的电位的控制下，控制所述第四节点PPU与所述复位端R1之间连通或断开，在所述第一输入端I1提供的第一输入信号的控制下，控制所述第四节点PPU与所述第一电压端V1之间连通或断开；
所述栅极输出电路23分别与第四节点PPU、栅极驱动信号输出端G1、第一时钟信号端K1、第一输入端I1和第一电压端V1电连接，用于在所述第四节点PPU的电位的控制下，控制所述栅极驱动信号输出端G1与第一时钟信号端K1之间连通或断开，在第一输入端I1提供的第一输入信号的控制下，控制所述栅极驱动信号输出端G1与所述第一电压端V1连通或断开，并用于根据所述第四节点PPU的电位，控制所述栅极驱动信号输出端G1提供的栅极驱动信号。
在本公开实施例所述的驱动电路中，增加生成栅极驱动信号的栅极驱动电路，以复位端R1提供的复位信号与本行第一节点PU1的电压信号进行“或”运算所得信号作为输入/复位功能，也即，当复位信号与本行第一节点PU1的电压信号同时为有效电压信号时实现输入功能(为第四节点PPU输入)，当本行第一节点PU1的电压信号为有效电压信号，而复位信号为无效电压信号时实现复位功能(为第四节点PPU复位)，当I1提供的第一输入信号为有效电压信号时，为第四节点PPU和G1去噪，从而使得本公开实施例所述的驱动电路能够在生成发光控制信号的同时，生成栅极驱动信号，能简化驱动方案，减少信号数量，并窄化边框。
在本公开至少一实施例中，当所述驱动电路包括的各晶体管为p型晶体管时，有效电压信号可以为低电压信号，无效电压信号可以为高电压信号；当所述驱动电路包括的各晶体管为n型晶体管时，有效电压信号可以为高电 压信号，无效电压信号可以低电压信号。
本公开实施例所述的驱动电路在工作时，生成的发光控制信号的脉宽可调，并所述发光控制信号可以为低电压有效的信号，生成的栅极驱动信号可以为低电压有效的信号。并且，所述发光控制信号的电位持续为高电压的时间可以大于或等于2H(所述发光控制信号的脉宽可调)，所述栅极驱动信号持续为低电压的时间可以小于或等于1H。
其中，1H为理论上一行像素充电时间，1H＝1/帧刷新频率/行数。
可选的，所述第一电压端可以为高电压端。
本公开如图2所示的驱动电路的实施例在工作时，驱动周期可以包括依次设置的第一输入阶段、第二输入阶段、第三输入阶段和第一复位阶段；
在第一输入阶段，所述第四节点控制电路21在第一节点PU1的电位的控制下，控制第四节点PPU与复位端R1之间断开，在第一输入信号的控制下，控制第四节点PPU与第一电压端V1之间断开；栅极输出电路23在第四节点PPU的电位的控制下，控制栅极驱动信号输出端G1与第一时钟信号端K1之间断开，在第一输入信号的控制下，控制栅极驱动信号输出端G1与所述第一电压端V1断开，以使得栅极驱动信号输出端G1维持输出第一电压信号；
在第二输入阶段，所述第四节点控制电路21在第一节点PU1的电位的控制下，控制第四节点PPU与复位端R1之间连通；栅极输出电路23在第四节点PPU的电位的控制下，控制栅极驱动信号输出端G1与第一时钟信号端K1之间连通，以使得栅极驱动信号输出端G1输出第一电压信号；
在第三输入阶段，所述第四节点控制电路21在第一节点PU1的电位的控制下，控制第四节点PPU与复位端R1之间断开；栅极输出电路23在第四节点PPU的电位的控制下，控制栅极驱动信号输出端G1与第一时钟信号端K1之间连通，以使得栅极驱动信号输出端G1输出第二电压信号；
在第一复位阶段，所述第四节点控制电路21在第一节点PU1的电位的控制下，控制第四节点PPU与复位端R1之间连通，在第一输入信号的控制下，控制第四节点PPU与第一电压端V1之间连通；栅极输出电路23在第四节点PPU的电位的控制下，控制栅极驱动信号输出端G1与第一时钟信号端 K1之间断开，在第一输入信号的控制下，控制栅极驱动信号输出端G1与所述第一电压端V1连通，以使得栅极驱动信号输出端G1输出第一电压信号。
在本公开至少一实施例中，所述第一电压信号可以为高电压信号，所述第二电压信号可以为低电压信号。
可选的，所述第一输入端可以与相邻上一级驱动电路的发光控制信号输出端电连接；或者，所述驱动电路的第一输入端与该驱动电路的发光控制信号输出端电连接。
可选的，所述驱动电路的复位端与相邻下一级驱动电路的发光控制信号输出端电连接；或者，所述复位端与相邻上一级驱动电路的栅极驱动信号输出端电连接。
如图3所示，在图2所示的驱动电路的实施例的基础上，本公开至少一实施例所述的驱动电路还可以包括栅极复位电路24；
所述栅极复位电路24分别与第一节点PU1、栅极驱动信号输出端G1和第一电压端V1电连接，用于在所述第一节点PU1的电位的控制下，控制所述栅极驱动信号输出端G1与所述第一电压端V1之间连通或断开。
在具体实施时，为避免I1提供的第一输入信号的电位持续为无效电压的时间过长而无法及时为G1复位，增加所述栅极复位电路24，以在第一节点PU1的电位的控制下，控制所述栅极驱动信号输出端输出第一电压信号，以为G1复位。
本公开如图3所示的驱动电路的至少一实施例在工作时，
在第一输入阶段，栅极复位电路24在第一节点PU1的电位的控制下，控制所述栅极驱动信号输出端G1与所述第一电压端V1之间断开；
在第二输入阶段，栅极复位电路24在第一节点PU1的电位的控制下，控制所述栅极驱动信号输出端G1与所述第一电压端V1之间连通；
在第三输入阶段，栅极复位电路24在第一节点PU1的电位的控制下，控制所述栅极驱动信号输出端G1与所述第一电压端V1之间断开；
在第一复位阶段，栅极复位电路24在第一节点PU1的电位的控制下，控制所述栅极驱动信号输出端G1与所述第一电压端V1之间连通，以对G1复位。
可选的，所述第四节点控制电路包括第一晶体管和第二晶体管；
所述第一晶体管的控制极与所述第一节点电连接，所述第一晶体管的第一极与所述复位端电连接，所述第一晶体管的第二极与所述第四节点电连接；
所述第二晶体管的控制极与所述第一输入端电连接，所述第二晶体管的第一极与所述第四节点电连接，所述第二晶体管的第二极与所述第一电压端电连接。
可选的，所述栅极输出电路包括第三晶体管、第四晶体管和第一电容；
所述第三晶体管的控制极与所述第四节点电连接，所述第三晶体管的第一极与第一时钟信号端电连接，所述第三晶体管的第二极与所述栅极驱动信号输出端电连接；
所述第四晶体管的控制极与所述第一输入端电连接，所述第四晶体管的第一极与所述栅极驱动信号输出端电连接，所述第四晶体管的第二极与所述第一电压端电连接；
所述第一电容的第一端与所述第四节点电连接，所述第一电容的第二端与所述栅极驱动信号输出端电连接。
在本公开至少一实施例中，所述第一电容用于对第四节点进行耦合，使得控制极与第四节点电连接的晶体管开启更充分，从而向栅极驱动信号输出端输出波形。
可选的，所述栅极复位电路包括第五晶体管；
所述第五晶体管的控制极与所述第一节点电连接，所述第五晶体管的第一极与所述栅极驱动信号输出端电连接，所述第五晶体管的第二极与所述第一电压端电连接。
如图4所示，在图3所示的驱动电路的至少一实施例的基础上，所述第四节点控制电路21包括第一晶体管M1和第二晶体管M2；
所述第一晶体管M1的栅极与所述第一节点PU1电连接，所述第一晶体管M1的第一极与所述复位端R1电连接，所述第一晶体管M1的第二极与所述第四节点PPU电连接；
所述第二晶体管M2的栅极与所述第一输入端I1电连接，所述第二晶体管M2的第一极与所述第四节点PPU电连接，所述第二晶体管M2的第二极 与高电压端V01电连接；
所述栅极输出电路23包括第三晶体管M3、第四晶体管M4和第一电容C1；
所述第三晶体管M3的栅极与所述第四节点PPU电连接，所述第三晶体管M3的第一极与第一时钟信号端K1电连接，所述第三晶体管M3的第二极与所述栅极驱动信号输出端G1电连接；
所述第四晶体管M4的栅极与所述第一输入端I1电连接，所述第四晶体管M4的第一极与所述栅极驱动信号输出端G1电连接，所述第四晶体管M4的第二极与所述高电压端V01电连接；
所述栅极复位电路24包括第五晶体管M5；
所述第五晶体管M5的栅极与所述第一节点PU1电连接，所述第五晶体管M5的第一极与所述栅极驱动信号输出端G1电连接，所述第五晶体管M5的第二极与高电压端V01电连接；
所述第一电容C1的第一端与所述第四节点PPU电连接，所述第一电容C1的第二端与所述栅极驱动信号输出端G1电连接。
在图4所示的驱动电路的至少一实施例中，各晶体管都为p型晶体管。
如图5所示，本公开如图4所示的驱动电路的至少一实施例在工作时，驱动周期包括依次设置的第一准备阶段t01、第二准备阶段t02、第一输入阶段t1、第二输入阶段t2、第三输入阶段t3、第一复位阶段t4、第二复位阶段t5和第三复位阶段t6；
在第一准备阶段t01，K1提供低电压信号，I1提供低电压信号，R1提供低电压信号，PU1的电位为高电压，PPU的电位为高电压，M1关断，M2打开，M3关断，M4打开，M5关断，G1输出高电压信号；
在第二准备阶段t01，K1提供高电压信号，I1提供低电压信号，R1提供低电压信号，PU1的电位为高电压，PPU的电位为高电压，M1关断，M2打开，M3关断，M4打开，M5关断，G1输出高电压信号；
在第一输入阶段t1，K1提供低电压信号，I1提供高电压信号，R1提供低电压信号，PU1的电位为高电压，PPU的电位为高电压，M1、M2、M3、M4和M5都关断，G1持续输出高电压信号；
在第二输入阶段t2，K1提供高电压信号，I1提供高电压信号，R1提供低电压信号，PU1的电位为低电压，PPU的电位被拉低，M1打开，M2关断，M3打开，M4关断，M5打开，G1提供高电压信号；
在第三输入阶段t3，K1提供低电压信号，I1提供高电压信号，R1提供高电压信号，PU1的电位为高电压，PPU的电位被进一步拉低，M1和M2关断，M3打开，M4关断，M5关断，G1提供低电压信号；
在第一复位阶段t4，K1提供高电压信号，I1提供低电压信号，R1提供高电压信号，PU1的电位为低电压，PPU的电位为高电压，M1和M2打开，M3关断，M4打开，M5打开，G1提供高电压信号，以对G1复位；
在第二复位阶段t5，K1提供低电压信号，I1提供低电压信号，R1提供高电压信号，PU1的电位为高电压，PPU的电位为高电压，M1关断，M2打开，M3关断，M4打开，M5关断，G1提供高电压信号；
在第三复位阶段t6，K1提供高电压信号，I1提供低电压信号，R1提供低电压信号，PU1的电位为高电压，PPU的电位为高电压，M1关断，M2打开，M3关断，M4打开，M5关断，G1提供高电压信号。
如图5所示，E1提供的发光控制信号的电位持续为高电压的时间为3H，G1提供的栅极驱动信号的电位持续为低电压的时间为1H。
图5中示出的发光控制信号和栅极驱动信号是实际应用情况下的驱动信号，占空比小于50％。有效宽度小于1H，周期为2H，故占空比小于50％，导致图上各阶段间都用虚线隔出空隙。
在本公开至少一实施例中，如图6所示，在图4所示的驱动电路的至少一实施例的基础上，所述第一节点控制电路可以包括第五节点控制子电路51和第一节点控制子电路52；
所述第五节点控制子电路51分别与第一时钟信号端K1、第五节点PD2、第二电压端V2和第三节点PD1电连接，用于在第一时钟信号端K1提供的第一时钟信号的控制下，控制第五节点PD2与第二电压端V2之间连通或断开，在第三节点PD1的电位的控制下，控制所述第五节点PD2与第一时钟信号端K1之间连通或断开；
所述第一节点控制子电路52分别与第五节点PD2、第二时钟信号端K2和第一节点PU1电连接，用于根据第五节点PD2的电位和第二时钟信号端 K2提供的第二时钟信号，控制第一节点PU1的电位。
在本公开至少一实施例中，所述第一节点控制子电路52可以用于在所述第五节点PD2的电位的控制下，控制第一节点PU1与第二时钟信号端K2之间连通或断开，并用于根据所述第五节点PD2的电位，控制所述第一节点PU1的电位。
可选的，第五节点控制子电路包括第六晶体管和第七晶体管；
所述第六晶体管的控制极与第一时钟信号端电连接，所述第六晶体管的第一极与第二电压端电连接，所述第六晶体管的第二极与第五节点电连接；
所述第七晶体管的控制极与第三节点电连接，所述第七晶体管的第一极与第一时钟信号端电连接，所述第七晶体管的第二极与第五节点电连接。
可选的，所述第一节点控制子电路包括第八晶体管和第二电容；
第八晶体管的控制极与所述第五节点电连接，第八晶体管的第一极与第二时钟信号端电连接，第八晶体管的第二极与第一节点电连接；
第二电容的第一端与第五节点电连接，第二电容的第二端与第一节点电连接。
本公开至少一实施例所述的驱动电路还可以包括导通控制电路；所述导通控制电路用于在第二电压端提供的第二电压信号的控制下，控制第五节点与第六节点之间连通或断开；
所述第一节点控制子电路用于在所述第六节点的电位的控制下，控制第一节点与第二时钟信号端之间连通或断开，并用于根据所述第六节点的电位，控制所述第一节点的电位。
在具体实施时，本公开至少一实施例所述的驱动电路可以包括导通控制电路，导通控制电路控制第五节点与第六节点之间连通或断开，第一节点控制子电路在第六节点的电位的控制下控制第一节点的电位。
如图7所示，在图3所示的驱动电路的至少一实施例的基础上，本公开至少一实施例所述的驱动电路还可以包括导通控制电路60；所述第一节点控制电路可以包括第五节点控制子电路51和第一节点控制子电路52；
所述导通控制电路60分别与第二电压端V2、第五节点PD2和第六节点PD22电连接，用于在第二电压端V2提供的第二电压信号的控制下，控制第 五节点PD2与第六节点PD22之间连通或断开；
所述第五节点控制子电路51分别与第一时钟信号端K1、第五节点PD2、第二电压端V2和第三节点PD1电连接，用于在第一时钟信号端K1提供的第一时钟信号的控制下，控制第五节点PD2与第二电压端V2之间连通或断开，在第三节点PD1的电位的控制下，控制所述第五节点PD2与第一时钟信号端K1之间连通或断开；
所述第一节点控制子电路52分别与第六节点PD22、第一节点PU1和第二时钟信号端K2电连接，用于在所述第六节点PD22的电位的控制下，控制第一节点PU1与第二时钟信号端K2之间连通或断开，并用于根据所述第六节点PD22的电位，控制所述第一节点PU1的电位。
在图7所示的驱动电路的至少一实施例中，导通控制电路60在第二电压信号的控制下控制PD2和PD22之间连通或断开，第五节点控制子电路51控制第五节点PD2的电位，第一节点控制子电路52控制第一节点PU1的电位。
可选的，第一节点控制子电路包括第八晶体管和第二电容，所述导通控制电路包括第一导通控制晶体管；
所述第一导通控制晶体管的控制极与第二电压端电连接，所述第一导通控制晶体管的第一极与第五节点电连接，所述第一导通控制晶体管的第二极与第六节点电连接；
所述第八晶体管的控制极与所述第六节点电连接，第八晶体管的第一极与第二时钟信号端电连接，第八晶体管的第二极与第一节点电连接；
第二电容的第一端与第六节点电连接，第二电容的第二端与第一节点电连接。
在本公开至少一实施例中，所述第二节点控制电路分别与第二时钟信号端K2、第一节点PU1、第二节点PU、第三节点PD1和第一电压端V1电连接，用于在第二时钟信号端K2提供的第二时钟信号的控制下，控制所述第一节点PU1与所述第二节点PU之间连通或断开，并用于在所述第三节点PD1的电位的控制下，控制所述第二节点PU与第一电压端V1之间连通或断开，并用于维持第二节点PU的电位。
可选的，所述第二节点控制电路包括第九晶体管、第十晶体管和控制电 容；
第九晶体管的控制极与第二时钟信号端电连接，第九晶体管的第一极与第一节点电连接，第九晶体管的第二极与第二节点电连接；
第十晶体管的控制极与第三节点电连接，第十晶体管的第一极与第一电压端电连接，第十晶体管的第二极与第二节点电连接；
所述控制电容的第一端与所述第二节点电连接，所述控制电容的第二端与第一电压端。
在本公开至少一实施例中，如图7所示，所述第三节点控制电路分别与第一时钟信号端K1、第三节点PD1、第二输入端I2、第五节点PD2、第二时钟信号端K2和第一电压端V1电连接，用于在第一时钟信号端K1提供的第一时钟信号的控制下，控制第三节点PD1与第二输入端I2之间连通或断开，在第五节点PD2的电位和第二时钟信号端K2提供的第二时钟信号的控制下，控制所述第三节点PD1与第一电压端V1之间连通或断开，并用于根据第二时钟信号控制第三节点PD1的电位。
可选的，所述第三节点控制电路包括第十一晶体管、第十二晶体管、第十三晶体管和第三电容；
第十一晶体管的控制极与第一时钟信号端电连接，第十一晶体管的第一极与第二输入端电连接，第十一晶体管的第二极与第三节点电连接；
第十二晶体管的控制极与第五节点电连接，第十二晶体管的第一极与第一电压端电连接；
第十三晶体管的控制极与第二时钟信号端电连接，第十三晶体管的第一极与第十二晶体管的第二极电连接，第十三晶体管的第二极与第三节点电连接；
第三电容的第一端与第二时钟信号端电连接，第三电容的第二端与第三节点电连接。
如图8所示，在图6所示的驱动电路的至少一实施例的基础上，所述第二节点控制电路12分别与第二时钟信号端K2、第一节点PU1、第二节点PU、第三节点PD1和第一电压端V1电连接，用于在第二时钟信号端K2提供的第二时钟信号的控制下，控制所述第一节点PU1与所述第二节点PU之间连 通或断开，并用于在所述第三节点PD1的电位的控制下，控制所述第二节点PU与第一电压端V1之间连通或断开；
所述第三节点控制电路13分别与第一时钟信号端K1、第三节点PD1、第二输入端I2、第五节点PD2、第二时钟信号端K2和第一电压端V1电连接，用于在第一时钟信号端K1提供的第一时钟信号的控制下，控制第三节点PD1与第二输入端I2之间连通或断开，在第五节点PD2的电位和第二时钟信号端K2提供的第二时钟信号的控制下，控制所述第三节点PD1与第一电压端V1之间连通或断开，并用于根据第二时钟信号控制第三节点PD1的电位。
在图8所示的驱动电路的至少一实施例中，第二节点控制电路12控制第二节点PU的电位，第三节点控制电路13控制第三节点PD1的电位。
在本公开至少一实施例中，所述第三节点控制电路可以包括第七节点控制子电路和第三节点控制子电路；
所述第七节点控制子电路用于在第五节点的电位的控制下，控制所述第七节点与第一电压端之间连通或断开，在第三节点的电位的控制下，控制所述第七节点与第二时钟信号端之间连通或断开；
所述第三节点控制子电路用于根据所述第七节点的电位，控制所述第三节点的电位，并在第一时钟信号端提供的第一时钟信号的控制下，控制第三节点与第二输入端之间连通或断开。
可选的，所述第三节点控制子电路包括第十一晶体管和第三电容；
第七节点控制子电路包括第十二晶体管和第十三晶体管；
第十一晶体管的控制极与第一时钟信号端电连接，第十一晶体管的第一极与第二输入端电连接，第十一晶体管的第二极与第三节点电连接；
第十二晶体管的控制极与第五节点电连接，第十二晶体管的第一极与第一电压端电连接，第十二晶体管的第二极与第七节点电连接；
第十三晶体管的控制极与第三节点电连接，第十三晶体管的第一极与第二时钟信号端电连接，第十三晶体管的第二极与第七节点电连接；
第三电容的第一端与第七节点电连接，第三电容的第二端与第三节点电连接。
可选的，所述发光控制输出电路包括第一输出晶体管和第二输出晶体管；
第一输出晶体管的控制极与第三节点电连接，第一输出晶体管的第一极与第二电压端电连接，第一输出晶体管的第二极与发光控制信号输出端电连接；
第二输出晶体管的控制极与第二节点电连接，第二输出晶体管的第一极与发光控制信号输出端电连接，第二输出晶体管的第二极与第一电压端电连接。
如图9所示，在图7所示的驱动电路的至少一实施例的基础上，所述发光控制输出电路可以包括导通子电路70和发光控制输出子电路71；所述第三节点控制电路包括第三节点控制子电路80、第七节点控制子电路81和第八节点控制子电路82；
所述导通子电路70分别与第一电压端V2、第三节点PD1和第八节点PD11电连接，用于在第一电压端V2提供的第二电压信号的控制下，控制第三节点PD1与第八节点PD11之间连通或断开；
所述发光控制输出子电路71分别与第二节点PU、第八节点PD11、发光控制信号输出端E1、高电压端V01和低电压端V02电连接，用于在第八节点PD11的电位的控制下，控制发光控制信号输出端E1与低电压端V02之间连通或断开，在第二节点PU的电位的控制下，控制发光控制信号输出端E1与高电压端V01之间连通或断开；
所述第三节点控制子电路80分别与第一时钟信号端K1、第二输入端I2和第三节点PD1电连接，用于在第一时钟信号端K1提供的第一时钟信号的控制下，控制第二输入端I2与第三节点PD1之间连通或断开；
所述第七节点控制子电路81分别与第五节点PD2、第八节点PD11、第七节点N1、第一电压端V1和第二时钟信号端K2电连接，用于在第五节点PD2的电位的控制下，控制所述第七节点N1与第一电压端V1之间连通或断开，在第八节点PD11的电位的控制下，控制所述第七节点N1与第二时钟信号端K2之间连通或断开；
所述第八节点控制子电路82分别与第七节点N1和第八节点PD11电连接，用于根据所述第七节点N1的电位，控制所述第八节点PD11的电位。
在图9所示的驱动电路的至少一实施例中，导通子电路70在第二电压信 号的控制下，控制PD1与PD11之间连通或断开，第三节点控制子电路81控制第三节点PD1的电位，第七节点控制子电路81控制第七节点N1的电位，第八节点控制子电路82控制第八节点PD11的电位。
可选的，所述导通子电路包括第二导通控制晶体管，所述第三节点控制子电路包括第十一晶体管；所述第七节点控制子电路包括第十二晶体管和第十三晶体管；所述第八节点控制子电路包括第三电容；
所述第二导通控制晶体管的控制极与第二电压端电连接，所述第二导通控制晶体管的第一极与第三节点电连接，所述第二导通控制晶体管的第二极与第八节点电连接；
第十一晶体管的控制极与第一时钟信号端电连接，第十一晶体管的第一极与第二输入端电连接，第十一晶体管的第二极与第三节点电连接；
第十二晶体管的控制极与第五节点电连接，第十二晶体管的第一极与第一电压端电连接，第十二晶体管的第二极与第七节点电连接；
第十三晶体管的控制极与第八节点电连接，第十三晶体管的第一极与第二时钟信号端电连接，第十三晶体管的第二极与第七节点电连接；
第三电容的第一端与第七节点电连接，第三电容的第二端与第八节点电连接。
可选的，所述发光控制输出电路包括第二导通控制晶体管、第一输出晶体管和第二输出晶体管；
所述第二导通控制晶体管的控制极与第二电压端电连接，所述第二导通控制晶体管的第一极与第三节点电连接，所述第二导通控制晶体管的第二极与第八节点电连接；
第一输出晶体管的控制极与第八节点电连接，第一输出晶体管的第一极与第二电压端电连接，第一输出晶体管的第二极与发光控制信号输出端电连接；
第二输出晶体管的控制极与第二节点电连接，第二输出晶体管的第一极与发光控制信号输出端电连接，第二输出晶体管的第二极与第一电压端电连接。
如图10所示，在本公开至少一实施例所述的驱动电路中，在图8所示的 驱动电路的至少一实施例的基础上，
第五节点控制子电路51包括第六晶体管M6和第七晶体管M7；
所述第六晶体管M6的栅极与第一时钟信号端K1电连接，所述第六晶体管M6的第一极与低电压端V02电连接，所述第六晶体管M6的第二极与第五节点PD2电连接；
所述第七晶体管M7的栅极与第三节点PD1电连接，所述第七晶体管M7的第一极与第一时钟信号端K1电连接，所述第七晶体管M7的第二极与第五节点PD2电连接；
所述第一节点控制子电路52包括第八晶体管M8和第二电容C2；
第八晶体管M8的栅极与所述第五节点PD2电连接，第八晶体管M8的第一极与第二时钟信号端K2电连接，第八晶体管M8的第二极与第一节点PU1电连接；
第二电容C2的第一端与第五节点PD2电连接，第二电容C2的第二端与第一节点PU1电连接；
所述第二节点控制电路12包括第九晶体管M9、第十晶体管M10和控制电容C0；
第九晶体管M9的栅极与第二时钟信号端K2电连接，第九晶体管M9的第一极与第一节点PU1电连接，第九晶体管M9的第二极与第二节点PU电连接；
第十晶体管M10的栅极与第三节点PD1电连接，第十晶体管M10的第一极与高电压端V01电连接，第十晶体管M10的第二极与第二节点PU电连接；
控制电容C0的第一端与所述第二节点PU电连接，所述控制电容C0的第二端与高电压端V01电连接；
所述第三节点控制电路13包括第十一晶体管M11、第十二晶体管M12、第十三晶体管M13和第三电容C3；
第十一晶体管M11的栅极与第一时钟信号端K1电连接，第十一晶体管M11的第一极与第二输入端I2电连接，第十一晶体管M11的第二极与第三节点PD1电连接；
第十二晶体管M12的栅极与第五节点PD2电连接，第十二晶体管M12的第一极与高电压端V01电连接；
第十三晶体管M13的栅极与第二时钟信号端K2电连接，第十三晶体管M13的第一极与第十二晶体管M12的第二极电连接，第十三晶体管M13的第二极与第三节点PD1电连接；
第三电容C3的第一端与第二时钟信号端K2电连接，第三电容C3的第二端与第三节点PD1电连接；
所述发光控制输出电路14包括第一输出晶体管M01和第二输出晶体管M02；
第一输出晶体管M01的栅极与第三节点PD1电连接，第一输出晶体管M01的第一极与低电压端V02电连接，第一输出晶体管M01的第二极与发光控制信号输出端E1电连接；
第二输出晶体管M02的栅极与第二节点PU电连接，第二输出晶体管M02的第一极与发光控制信号输出端E1电连接，第二输出晶体管M02的第二极与高电压端V02电连接。
在图10所示的驱动电路的至少一实施例中，I1与I2都与相邻上一级驱动电路的发光控制信号输出端电连接，R1与相邻下一级驱动电路的发光控制信号输出端电连接。
可选的，I1可以替换为与所述驱动电路的发光控制信号输出端电连接。
可选的，R1可以替换为与相邻上一级驱动电路的栅极驱动信号输出端电连接。
在图10所示的驱动电路的至少一实施例中，所有的晶体管都为p型晶体管，但不以此为限。
如图11所示，图10所示的驱动电路的至少一实施例在工作时，驱动周期包括依次设置的第一准备阶段t01、第二准备阶段t02、第一输入阶段t1、第二输入阶段t2、第三输入阶段t3、第一复位阶段t4、第二复位阶段t5和第三复位阶段t6；
在第一准备阶段t01，K1提供低电压信号，K2提供高电压信号，I1和I2提供低电压信号，R1提供低电压信号，如图12A所示，M11打开，M6打开， M13关断，PD1的电位为低电压，M7打开，PD2的电位为低电压，M8打开，PU1的电位为高电压，M9关断，M6打开，PU的电位为高电压，M01打开，M02关断，E1输出低电压信号；M1关断，M2打开，M3关断，M4打开，M5关断，PPU的电位维持为高电压，G1输出高电压信号；
在第二准备阶段t02，K1提供高电压信号，K2提供低电压信号，I1和I2提供低电压信号，R1提供低电压信号，如图12B所示，M11关断，M6关断，由于K2提供的第二时钟信号的电位降低，因此PD1的电位由于耦合而进一步降低，M7打开，PD2的电位为高电压，M12关断，M8关断，PU1的电位为高电压，M9打开，M10打开，PU的电位为高电压，M01打开，M02关断，E1输出低电压信号；M1关断，M2打开，M3关断，M4打开，M5关断，PPU的电位为高电压，G1输出高电压信号；
在第一输入阶段t1，K1提供低电压信号，K2提供高电压信号，I1和I2提供高电压信号，R1提供低电压信号，如图12C所示，M11打开，M6打开，M13关断，PD1的电位为高电压，M7关断，PD2的电位为低电压，M8打开，PU1的电位为高电压，M9关断，M10关断，PU的电位维持为高电压，M01和M02都关断，E1维持输出低电压信号；M1关断，M2关断、M3关断、M4关断、M5关断，PPU的电位维持为高电压，G1持续输出高电压信号；
在第二输入阶段t2，K1提供高电压信号，K2提供低电压信号，I1和I2提供高电压信号，R1提供低电压信号，如图12D所示，M11和M6关断，PD2的电位维持为低电压，M13和M12打开，PD1的电位为高电压，M8打开，PU1的电位为低电压，M9打开，PU的电位为低电压，M01关断，M02打开，E1输出高电压信号；M1打开，M2关断，M3打开，M4关断，M5打开，PPU的电位为低电压，G1输出高电压信号；
在第三输入阶段t3，K1提供低电压信号，K2提供高电压信号，I1和I2提供高电压信号，R1提供高电压信号，如图12E所示，M11和M6打开，PD1的电位为高电压，M7关断，PD2的电位为低电压，M13关断，M8打开，PU1的电位为高电压信号，M9关断，M10关断，PU的电位维持为低电压，M01关断，M02打开，E1输出高电压信号；M1关断，M2关断，M3打开，M4关断，M5关断，G1输出低电压信号，PPU的电位因耦合而降低为更低电压；
在第一复位阶段t4，K1提供高电压信号，K2提供低电压信号，I1和I2提供低电压信号，R1提供高电压信号，如图12F所示，M11和M6关断，PD2的电位维持为低电压，M12和M13都打开，PD1的电位为高电压，M8打开，PU1的电位为低电压，M10关断，PU的电位为低电压，M01关断，M02打开，E1输出高电压信号；M1打开，M2打开，M3关断，M4打开，M5打开，PPU的电位为高电压，G1输出高电压信号；
在第二复位阶段t5，K1提供低电压信号，K2提供高电压信号，I1和I2提供低电压信号，R1提供高电压信号，如图12G所示，M11和M6打开，M11关断，PD1的电位为低电压，M10打开，M9关断，PU的电位为高电压，M7打开，PD2的电位为低电压，M8打开，PU1的电位为高电压，M01打开，M02关断，E1输出低电压信号；M1关断，M2打开，M3关断，M4打开，M5关断，PPU的电位为高电压，G1输出高电压信号；
在第三复位阶段t6，K1提供高电压信号，K2提供低电压信号，I1和I2提供低电压信号，R1提供低电压信号，如图12H所示，M11和M6关断，由于K2提供的第二时钟信号的电位由高电压降低为低电压，则PD1的电位由于耦合而进一步降低，M7打开，PD2的电位为高电压，M12关断，M8关断，PU1的电位维持为高电压，M9打开，M10打开，PU的电位为高电压，M01打开，M02关断，E1输出低电压信号；M1关断，M2打开，M3关断，M4打开，M5关断，PPU的电位为高电压，G1输出高电压信号。
本公开至少一实施例所述的驱动电路在工作时，可以同时输出发光控制信号和栅极驱动信号，并发光控制信号的脉宽可调。
如图13所示，本公开至少一实施例所述的驱动电路输出的发光控制信号的电位持续为高电压的时间(也即所述发光控制信号的脉冲宽度)为7H。
如图14所示，本公开至少一实施例所述的驱动电路输出的发光控制信号的电位持续为高电压的时间(也即所述发光控制信号的脉冲宽度)为5H。
如图15所示，本公开至少一实施例所述的驱动电路输出的发光控制信号的电位持续为高电压的时间(也即所述发光控制信号的脉冲宽度)为3H。
如图16所示，在图9所示的驱动电路的至少一实施例的基础上，
第五节点控制子电路51包括第六晶体管M6和第七晶体管M7；
所述第六晶体管M6的栅极与第一时钟信号端K1电连接，所述第六晶体管M6的第一极与低电压端V02电连接，所述第六晶体管M6的第二极与第五节点PD2电连接；
所述第七晶体管M7的栅极与第三节点PD1电连接，所述第七晶体管M7的第一极与第一时钟信号端K1电连接，所述第七晶体管M7的第二极与第五节点PD2电连接；
第一节点控制子电路52包括第八晶体管M8和第二电容C2，所述导通控制电路60包括第一导通控制晶体管M21；
所述第一导通控制晶体管M21的栅极与低电压端V02电连接，所述第一导通控制晶体管M21的第一极与第五节点PD2电连接，所述第一导通控制晶体管M21的第二极与第六节点PD22电连接；
所述第八晶体管M8的栅极与所述第六节点PD22电连接，第八晶体管M8的第一极与第二时钟信号端K2电连接，第八晶体管M8的第二极与第一节点PU1电连接；
第二电容C2的第一端与第六节点PD22电连接，第二电容C2的第二端与第一节点PU1电连接；
所述第二节点控制电路12包括第九晶体管M9、第十晶体管M10和控制电容C0；
第九晶体管M9的栅极与第二时钟信号端K2电连接，第九晶体管M9的第一极与第一节点PU1电连接，第九晶体管M9的第二极与第二节点PU电连接；
第十晶体管M10的栅极与第三节点PD1电连接，第十晶体管M10的第一极与高电压端V01电连接，第十晶体管M10的第二极与第二节点PU电连接；
控制电容C0的第一端与所述第二节点PU电连接，所述控制电容C0的第二端与高电压端V01电连接；
所述导通子电路70包括第二导通控制晶体管M22，所述第三节点控制子电路80包括第十一晶体管M11；所述第七节点控制子电路81包括第十二晶体管M12和第十三晶体管M13；所述第八节点控制子电路82包括第三电容 C3；
所述第二导通控制晶体管M22的栅极与低电压端V02电连接，所述第二导通控制晶体管M22的第一极与第三节点PD1电连接，所述第二导通控制晶体管M22的第二极与第八节点PD11电连接；
第十一晶体管M11的栅极与第一时钟信号端K1电连接，第十一晶体管M11的第一极与第二输入端I2电连接，第十一晶体管M11的第二极与第三节点PD1电连接；
第十二晶体管M12的栅极与第五节点PD2电连接，第十二晶体管M12的第一极与高电压端V01电连接，第十二晶体管M12的第二极与第七节点N1电连接；
第十三晶体管M13的栅极与第八节点PD11电连接，第十三晶体管M13的第一极与第二时钟信号端K2电连接，第十三晶体管M13的第二极与第七节点N1电连接；
第三电容C3的第一端与第七节点N1电连接，第三电容C3的第二端与第八节点PD11电连接；
所述发光控制输出子电路71包括第一输出晶体管M01和第二输出晶体管M02；
第一输出晶体管M01的栅极与第八节点PD11电连接，第一输出晶体管M01的第一极与低电压端V02电连接，第一输出晶体管M01的第二极与发光控制信号输出端E1电连接；
第二输出晶体管M02的栅极与第二节点PU电连接，第二输出晶体管M02的第一极与发光控制信号输出端E1电连接，第二输出晶体管M02的第二极与高电压端V02电连接。
在图16所示的驱动电路的至少一实施例中，I1与I2都与相邻上一级驱动电路的发光控制信号输出端电连接，R1与相邻下一级驱动电路的发光控制信号输出端电连接。
在图16所示的驱动电路的至少一实施例中，所有的晶体管都为p型晶体管，但不以此为限。
在图16所示的驱动电路的至少一实施例中，也可以不设有M21和M22。
在图16所示的驱动电路的至少一实施例中，增加M21的好处如下：使PD22的电位稳定，减小M7漏电的影响，从而对M8的控制稳定；
增加M22的好处如下：可以稳定PD11的低电位，减小M11的漏电对PD11的电位的影响。
如图17所示，本公开如图16所示的驱动电路的至少一实施例在工作时，驱动周期包括依次设置的第一输入阶段t1、第二输入阶段t2、第三输入阶段t3、第一复位阶段t4、第二复位阶段t4和第三复位阶段t5；
在第一输入阶段t1，K1提供低电压信号，K2提供高电压信号，I1和I2提供高电压信号，M11和M6打开，PD1的电位为高电压，M22打开，PD11的电位为高电压，PD2的电位为低电压，M21打开，PD22的电位为低电压，M8打开，PU1的电位为高电压，M9关断，PU的电位维持为高电压，M10关断，M13关断，M12打开，N1的电位为高电压，M01和M02都关断，E1持续输出低电压信号；
在第二输入阶段t2，K1提供高电压信号，K2提供低电压信号，I1和I2提供高电压信号，M11和M6关断，M7关断，PD2的电位维持为低电压，M12打开，N1的电位为高电压，PD11的电位为高电压，PD1的电位为高电压，M21和M22打开，PD22的电位被耦合至更低电压，M8打开，PU1的电位为低电压，M9打开，PU的电位为低电压，M01关断，M02打开，E1输出高电压信号；
在第三输入阶段t3，K1提供低电压信号，K2提供高电压信号，I1和I2提供高电压信号，M11和M6打开，M22打开，PD1的电位和PD11的电位都为高电压，PD2的电位为低电压，M21打开，PD22的电位为低电压，M12打开，M13关断，N1的电位为高电压，M8打开，PU1的电位为高电压，M9关断，M10关断，PU的电位维持为低电压，M01关断，M02打开，E1输出高电压信号；
在第一复位阶段t4，K1提供高电压信号，K2提供低电压信号，I1和I2提供低电压信号，M11和M6关断，PD1的电位为高电压，M7关断，PD2的电位维持为低电压，M21打开，PD22的电位被进一步拉低，M8打开，PU1的电位为低电压，M9打开，PU的电位为低电压，M12打开，M13关断，N1的电位为高电压，PD11的电位为高电压，M01关断，M02打开，E1输出高 电压信号；
在第二复位阶段t5，K1提供低电压信号，K2提供高电压信号，I1和I2提供低电压信号，M11和M6打开，PD1的电位为低电压，M7打开，PD2的电位为低电压，M12打开，M22打开，PD11的电位为低电压，M13打开，N1的电位为高电压，M21打开，PD22的电位为低电压，M8打开，PU1的电位为高电压，M9关断，M10打开，PU的电位为高电压，M01打开，M02关断，E1输出低电压信号；
在第三复位阶段t6，K1提供高电压信号，K2提供低电压信号，I1和I2提供低电压信号，M11和M6关断，PD1的电位为低电压，M7打开，PD2的电位为高电压，M12关断，M22打开，PD11的电位为低电压，M13打开，N1的电位为低电压，PD11的电位被进一步拉低，M10打开，PU的电位为高电压，M01打开，M02关断，E1提供低电压信号。
在本公开至少一实施例中，如图18所示，提供一种栅极驱动电路10，所述栅极驱动电路10分别与控制节点L1、第一输入端I1、复位端R1、第一时钟信号端K1、第一电压端V1和栅极驱动信号输出端G1电连接，用于在控制节点L1的电位、第一输入端I1提供的第一输入信号和复位端R1提供的复位信号的控制下，根据第一时钟信号端K1提供的第一时钟信号和第一电压端V1提供的第一电压信号，控制栅极驱动信号输出端G1输出栅极驱动信号。
本公开至少一实施例提供的栅极驱动电路，以复位端R1提供的复位信号与本行第一节点PU1的电压信号进行“或”运算所得信号作为输入/复位功能，也即，当复位信号与本行第一节点PU1的电压信号同时为有效电压信号时实现输入功能，当本行第一节点PU1的电压信号为有效电压信号，而复位信号为无效电压信号时实现复位功能，当I1提供的第一输入信号为有效电压信号时，为G1去噪，从而使得本公开至少一实施例提供的栅极驱动电路10能够生成栅极驱动信号。
可选的，所述控制节点L1可以为发光控制信号生成电路中的第一节点；所述发光控制信号生成电路的结构可以不限于本公开实施例提供的电路结构。
如图19所示，在图18所示的栅极驱动电路的至少一实施例的基础上， 所述栅极驱动电路的至少一实施例可以包括第四节点控制电路21和栅极输出电路23；
所述第四节点控制电路21分别与控制节点L1、第四节点PPU、复位端R1、第一输入端I1和第一电压端V1电连接，用于在所述控制节点L1的电位的控制下，控制所述第四节点PPU与所述复位端R1之间连通或断开，在所述第一输入端I1提供的第一输入信号的控制下，控制所述第四节点PPU与所述第一电压端V1之间连通或断开；
所述栅极输出电路23分别与第四节点PPU、栅极驱动信号输出端G1、第一时钟信号端K1、第一输入端I1和第一电压端V1电连接，用于在所述第四节点PPU的电位的控制下，控制所述栅极驱动信号输出端G1与第一时钟信号端K1之间连通或断开，在第一输入端I1提供的第一输入信号的控制下，控制所述栅极驱动信号输出端G1与所述第一电压端V1连通或断开，并用于根据所述第四节点PPU的电位，控制所述栅极驱动信号输出端G1提供的栅极驱动信号。
图19所示的栅极驱动电路的至少一实施例在工作时，驱动周期可以包括依次设置的第一输入阶段、第二输入阶段、第三输入阶段和第一复位阶段；
在第一输入阶段，所述第四节点控制电路21在控制节点L1的电位的控制下，控制第四节点PPU与复位端R1之间断开，在第一输入信号的控制下，控制第四节点PPU与第一电压端V1之间断开；栅极输出电路23在第四节点PPU的电位的控制下，控制栅极驱动信号输出端G1与第一时钟信号端K1之间断开，在第一输入信号的控制下，控制栅极驱动信号输出端G1与所述第一电压端V1断开，以使得栅极驱动信号输出端G1维持输出第一电压信号；
在第二输入阶段，所述第四节点控制电路21在控制节点L1的电位的控制下，控制第四节点PPU与复位端R1之间连通；栅极输出电路23在第四节点PPU的电位的控制下，控制栅极驱动信号输出端G1与第一时钟信号端K1之间连通，以使得栅极驱动信号输出端G1输出第一电压信号；
在第三输入阶段，所述第四节点控制电路21在控制节点L1的电位的控制下，控制第四节点PPU与复位端R1之间断开；栅极输出电路23在第四节点PPU的电位的控制下，控制栅极驱动信号输出端G1与第一时钟信号端K1 之间连通，以使得栅极驱动信号输出端G1输出第二电压信号；
在第一复位阶段，所述第四节点控制电路21在控制节点L1的电位的控制下，控制第四节点PPU与复位端R1之间连通，在第一输入信号的控制下，控制第四节点PPU与第一电压端V1之间连通；栅极输出电路23在第四节点PPU的电位的控制下，控制栅极驱动信号输出端G1与第一时钟信号端K1之间断开，在第一输入信号的控制下，控制栅极驱动信号输出端G1与所述第一电压端V1连通，以使得栅极驱动信号输出端G1输出第一电压信号。
如图20所示，在图19所示的栅极驱动电路的至少一实施例的基础上，本公开至少一实施例所述的驱动电路还可以包括栅极复位电路24；
所述栅极复位电路24分别与控制节点L1、栅极驱动信号输出端G1和第一电压端V1电连接，用于在所述控制节点L1的电位的控制下，控制所述栅极驱动信号输出端G1与所述第一电压端V1之间连通或断开。
在具体实施时，为避免I1提供的第一输入信号的电位持续为无效电压的时间过长而无法及时为G1复位，增加所述栅极复位电路24，以在控制节点L11的电位的控制下，控制所述栅极驱动信号输出端输出第一电压信号，以为G1复位。
本公开如图20所示的驱动电路的至少一实施例在工作时，
在第一输入阶段，栅极复位电路24在控制节点L1的电位的控制下，控制所述栅极驱动信号输出端G1与所述第一电压端V1之间断开；
在第二输入阶段，栅极复位电路24在控制节点L1的电位的控制下，控制所述栅极驱动信号输出端G1与所述第一电压端V1之间连通；
在第三输入阶段，栅极复位电路24在控制节点L1的电位的控制下，控制所述栅极驱动信号输出端G1与所述第一电压端V1之间断开；
在第一复位阶段，栅极复位电路24在控制节点L1的电位的控制下，控制所述栅极驱动信号输出端G1与所述第一电压端V1之间连通，以对G1复位。
如图21所示，在图20所示的栅极驱动电路的至少一实施例的基础上，所述第四节点控制电路21包括第一晶体管M1和第二晶体管M2；
所述第一晶体管M1的栅极与所述控制节点L1电连接，所述第一晶体管 M1的第一极与所述复位端R1电连接，所述第一晶体管M1的第二极与所述第四节点PPU电连接；
所述第二晶体管M2的栅极与所述第一输入端I1电连接，所述第二晶体管M2的第一极与所述第四节点PPU电连接，所述第二晶体管M2的第二极与高电压端V01电连接；
所述栅极输出电路23包括第三晶体管M3、第四晶体管M4和第一电容C1；
所述第三晶体管M3的栅极与所述第四节点PPU电连接，所述第三晶体管M3的第一极与第一时钟信号端K1电连接，所述第三晶体管M3的第二极与所述栅极驱动信号输出端G1电连接；
所述第四晶体管M4的栅极与所述第一输入端I1电连接，所述第四晶体管M4的第一极与所述栅极驱动信号输出端G1电连接，所述第四晶体管M4的第二极与所述高电压端V01电连接；
所述第一电容C1的第一端与所述第四节点PPU电连接，所述第一电容C1的第二端与所述栅极驱动信号输出端G1电连接。
在图21所示的栅极驱动电路的至少一实施例中，各晶体管都为p型晶体管。
在图21所示的栅极驱动电路的至少一实施例中，控制节点L1可以为发光控制信号生成电路中的第一节点。
如图22所示，如图21所示的栅极驱动电路的至少一实施例在工作时，驱动周期包括依次设置的第一准备阶段t01、第二准备阶段t02、第一输入阶段t1、第二输入阶段t2、第三输入阶段t3、第一复位阶段t4、第二复位阶段t5和第三复位阶段t6；
在第一准备阶段t01，K1提供低电压信号，I1提供低电压信号，R1提供低电压信号，L1的电位为高电压，PPU的电位为高电压，M1关断，M2打开，M3关断，M4打开，M5关断，G1输出高电压信号；
在第二准备阶段t01，K1提供高电压信号，I1提供低电压信号，R1提供低电压信号，L1的电位为高电压，PPU的电位为高电压，M1关断，M2打开，M3关断，M4打开，M5关断，G1输出高电压信号；
在第一输入阶段t1，K1提供低电压信号，I1提供高电压信号，R1提供低电压信号，L1的电位为高电压，PPU的电位为高电压，M1、M2、M3、M4和M5都关断，G1持续输出高电压信号；
在第二输入阶段t2，K1提供高电压信号，I1提供高电压信号，R1提供低电压信号，L1的电位为低电压，PPU的电位被拉低，M1打开，M2关断，M3打开，M4关断，M5打开，G1提供高电压信号；
在第三输入阶段t3，K1提供低电压信号，I1提供高电压信号，R1提供高电压信号，L1的电位为高电压，PPU的电位被进一步拉低，M1和M2关断，M3打开，M4关断，M5关断，G1提供低电压信号；
在第一复位阶段t4，K1提供高电压信号，I1提供低电压信号，R1提供高电压信号，L1的电位为低电压，PPU的电位为高电压，M1和M2打开，M3关断，M4打开，M5打开，G1提供高电压信号，以对G1复位；
在第二复位阶段t5，K1提供低电压信号，I1提供低电压信号，R1提供高电压信号，L1的电位为高电压，PPU的电位为高电压，M1关断，M2打开，M3关断，M4打开，M5关断，G1提供高电压信号；
在第三复位阶段t6，K1提供高电压信号，I1提供低电压信号，R1提供低电压信号，L1的电位为高电压，PPU的电位为高电压，M1关断，M2打开，M3关断，M4打开，M5关断，G1提供高电压信号。本公开实施例所述的驱动方法，应用于上述的驱动电路，所述驱动方法包括：
栅极驱动电路在第一节点的电位、第一输入端提供的第一输入信号和复位端提供的复位信号的控制下，根据第一时钟信号端提供的第一时钟信号和第一电压端提供的第一电压信号，控制栅极驱动信号输出端输出栅极驱动信号。
采用本公开实施例所述的驱动方法，能够使得驱动电路在生成发光控制信号的同时，生成栅极驱动信号，能简化驱动方案，减少信号数量，并窄化边框。
本公开至少一实施例所述的驱动方法，应用于上述的驱动电路，驱动周期包括依次设置的第一输入阶段、第二输入阶段、第三输入阶段和第一复位阶段；所述驱动方法包括：
在第一输入阶段，所述第四节点控制电路在第一节点的电位的控制下，控制第四节点与复位端之间断开，在第一输入信号的控制下，控制第四节点与第一电压端之间断开；栅极输出电路在第四节点的电位的控制下，控制栅极驱动信号输出端与第一时钟信号端之间断开，在第一输入信号的控制下，控制栅极驱动信号输出端与所述第一电压端断开，以使得栅极驱动信号输出端维持输出第一电压信号；
在第二输入阶段，所述第四节点控制电路在第一节点的电位的控制下，控制第四节点与复位端之间连通；栅极输出电路在第四节点的电位的控制下，控制栅极驱动信号输出端与第一时钟信号端之间连通，以使得栅极驱动信号输出端输出第一电压信号；
在第三输入阶段，所述第四节点控制电路在第一节点的电位的控制下，控制第四节点与复位端之间断开；栅极输出电路在第四节点的电位的控制下，控制栅极驱动信号输出端与第一时钟信号端之间连通，以使得栅极驱动信号输出端输出第二电压信号；
在第一复位阶段，所述第四节点控制电路在第一节点的电位的控制下，控制第四节点与复位端之间连通，在第一输入信号的控制下，控制第四节点与第一电压端之间连通；栅极输出电路在第四节点的电位的控制下，控制栅极驱动信号输出端与第一时钟信号端之间断开，在第一输入信号的控制下，控制栅极驱动信号输出端与所述第一电压端连通，以使得栅极驱动信号输出端输出第一电压信号。
在本公开至少一实施例中，所述驱动电路还包括栅极复位电路；所述驱动方法还包括：
在第一输入阶段，栅极复位电路在第一节点的电位的控制下，控制所述栅极驱动信号输出端与所述第一电压端之间断开；
在第二输入阶段，栅极复位电路在第一节点的电位的控制下，控制所述栅极驱动信号输出端与所述第一电压端之间连通；
在第三输入阶段，栅极复位电路在第一节点的电位的控制下，控制所述栅极驱动信号输出端与所述第一电压端之间断开；
在第一复位阶段，栅极复位电路在第一节点的电位的控制下，控制所述 栅极驱动信号输出端与所述第一电压端之间连通。
在具体实施时，为避免第一输入端提供的第一输入信号的电位持续为无效电压的时间过长而无法及时为栅极驱动信号输出端复位，增加所述栅极复位电路，以在第一节点的电位的控制下，控制所述栅极驱动信号输出端输出第一电压信号，以为栅极驱动信号输出端复位。
本公开实施例所述的驱动模组包括多级上述的驱动电路。
在具体实施时，所述驱动电路的第二输入端可以与相邻上一级驱动电路的发光控制信号输出端电连接。
可选的，所述驱动电路的第一输入端与相邻上一级驱动电路的发光控制信号输出端电连接；或者，所述驱动电路的第一输入端与该驱动电路的发光控制信号输出端电连接。
可选的，所述驱动电路的复位端与相邻下一级驱动电路的发光控制信号输出端电连接；或者，所述复位端与相邻上一级驱动电路的栅极驱动信号输出端电连接。
本公开实施例所述的显示装置包括上述的驱动模组。
本公开实施例所提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开至少一实施例所提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (30)

  1. 一种驱动电路，包括发光控制信号生成电路和栅极驱动电路；所述发光控制信号生成电路包括第一节点控制电路、第二节点控制电路、第三节点控制电路和发光控制输出电路；
    所述第一节点控制电路用于控制第一节点的电位；
    所述第二节点控制电路用于控制第二节点的电位；
    所述第三节点控制电路用于控制第三节点的电位；
    所述发光控制输出电路用于根据所述第二节点的电位和所述第三节点的电位，控制发光控制信号输出端输出发光控制信号；
    所述栅极驱动电路用于在第一节点的电位、第一输入端提供的第一输入信号和复位端提供的复位信号的控制下，根据第一时钟信号端提供的第一时钟信号和第一电压端提供的第一电压信号，控制栅极驱动信号输出端输出栅极驱动信号。
  2. 如权利要求1所述的驱动电路，其中，所述栅极驱动电路包括第四节点控制电路和栅极输出电路；
    所述第四节点控制电路用于在所述第一节点的电位的控制下，控制所述第四节点与所述复位端之间连通或断开，在所述第一输入端提供的第一输入信号的控制下，控制所述第四节点与所述第一电压端之间连通或断开；
    所述栅极输出电路用于在所述第四节点的电位的控制下，控制所述栅极驱动信号输出端与第一时钟信号端之间连通或断开在所述第一输入信号的控制下，控制所述栅极驱动信号输出端与所述第一电压端连通或断开，并用于根据所述第四节点的电位，控制所述栅极驱动信号输出端提供的栅极驱动信号。
  3. 如权利要求2所述的驱动电路，其中，还包括栅极复位电路；
    所述栅极复位电路用于在所述第一节点的电位的控制下，控制所述栅极驱动信号输出端与所述第一电压端之间连通或断开。
  4. 如权利要求2所述的驱动电路，其中，所述第四节点控制电路包括第一晶体管和第二晶体管；
    所述第一晶体管的控制极与所述第一节点电连接，所述第一晶体管的第一极与所述复位端电连接，所述第一晶体管的第二极与所述第四节点电连接；
    所述第二晶体管的控制极与所述第一输入端电连接，所述第二晶体管的第一极与所述第四节点电连接，所述第二晶体管的第二极与所述第一电压端电连接。
  5. 如权利要求2所述的驱动电路，其中，所述栅极输出电路包括第三晶体管、第四晶体管和第一电容；
    所述第三晶体管的控制极与所述第四节点电连接，所述第三晶体管的第一极与第一时钟信号端电连接，所述第三晶体管的第二极与所述栅极驱动信号输出端电连接；
    所述第四晶体管的控制极与所述第一输入端电连接，所述第四晶体管的第一极与所述栅极驱动信号输出端电连接，所述第四晶体管的第二极与所述第一电压端电连接；
    所述第一电容的第一端与所述第四节点电连接，所述第一电容的第二端与所述栅极驱动信号输出端电连接。
  6. 如权利要求3所述的驱动电路，其中，所述栅极复位电路包括第五晶体管；
    所述第五晶体管的控制极与所述第一节点电连接，所述第五晶体管的第一极与所述栅极驱动信号输出端电连接，所述第五晶体管的第二极与所述第一电压端电连接。
  7. 如权利要求1至6中任一权利要求所述的驱动电路，其中，所述第一节点控制电路包括第五节点控制子电路和第一节点控制子电路；
    所述第五节点控制子电路用于在第一时钟信号端提供的第一时钟信号的控制下，控制第五节点与第二电压端之间连通或断开，在第三节点的电位的控制下，控制所述第五节点与第一时钟信号端之间连通或断开；
    所述第一节点控制子电路用于根据第五节点的电位和第二时钟信号端提供的第二时钟信号，控制第一节点的电位。
  8. 如权利要求7所述的驱动电路，其中，第五节点控制子电路包括第六晶体管和第七晶体管；
    所述第六晶体管的控制极与第一时钟信号端电连接，所述第六晶体管的第一极与第二电压端电连接，所述第六晶体管的第二极与第五节点电连接；
    所述第七晶体管的控制极与第三节点电连接，所述第七晶体管的第一极与第一时钟信号端电连接，所述第七晶体管的第二极与第五节点电连接。
  9. 如权利要求7所述的驱动电路，其中，所述第一节点控制子电路用于在所述第五节点的电位的控制下，控制第一节点与第二时钟信号端之间连通或断开，并用于根据所述第五节点的电位，控制所述第一节点的电位。
  10. 如权利要求9所述的驱动电路，其中，所述第一节点控制子电路包括第八晶体管和第二电容；
    第八晶体管的控制极与所述第五节点电连接，第八晶体管的第一极与第二时钟信号端电连接，第八晶体管的第二极与第一节点电连接；
    第二电容的第一端与第五节点电连接，第二电容的第二端与第一节点电连接。
  11. 如权利要求7所述的驱动电路，其中，还包括导通控制电路；所述导通控制电路用于在第二电压端提供的第二电压信号的控制下，控制第五节点与第六节点之间连通或断开；
    所述第一节点控制子电路用于在所述第六节点的电位的控制下，控制第一节点与第二时钟信号端之间连通或断开，并用于根据所述第六节点的电位，控制所述第一节点的电位。
  12. 如权利要求11所述的驱动电路，其中，第一节点控制子电路包括第八晶体管和第二电容，所述导通控制电路包括第一导通控制晶体管；
    所述第一导通控制晶体管的控制极与第二电压端电连接，所述第一导通控制晶体管的第一极与第五节点电连接，所述第一导通控制晶体管的第二极与第六节点电连接；
    所述第八晶体管的控制极与所述第六节点电连接，第八晶体管的第一极与第二时钟信号端电连接，第八晶体管的第二极与第一节点电连接；
    第二电容的第一端与第六节点电连接，第二电容的第二端与第一节点电连接。
  13. 如权利要求1至6中任一权利要求所述的驱动电路，其中，所述第 二节点控制电路用于在第二时钟信号端提供的第二时钟信号的控制下，控制所述第一节点与所述第二节点之间连通或断开，并用于在所述第三节点的电位的控制下，控制所述第二节点与第一电压端之间连通或断开，并用于维持第二节点的电位。
  14. 如权利要求13所述的驱动电路，其中，所述第二节点控制电路包括第九晶体管、第十晶体管和控制电容；
    第九晶体管的控制极与第二时钟信号端电连接，第九晶体管的第一极与第一节点电连接，第九晶体管的第二极与第二节点电连接；
    第十晶体管的控制极与第三节点电连接，第十晶体管的第一极与第一电压端电连接，第十晶体管的第二极与第二节点电连接；
    所述控制电容的第一端与所述第二节点电连接，所述控制电容的第二端与第一电压端。
  15. 如权利要求7所述的驱动电路，其中，所述第三节点控制电路用于在第一时钟信号端提供的第一时钟信号的控制下，控制第三节点与第二输入端之间连通或断开，在第五节点的电位和第二时钟信号的控制下，控制所述第三节点与第一电压端之间连通或断开，并用于根据第二时钟信号控制第三节点的电位。
  16. 如权利要求15所述的驱动电路，其中，所述第三节点控制电路包括第十一晶体管、第十二晶体管、第十三晶体管和第三电容；
    第十一晶体管的控制极与第一时钟信号端电连接，第十一晶体管的第一极与第二输入端电连接，第十一晶体管的第二极与第三节点电连接；
    第十二晶体管的控制极与第五节点电连接，第十二晶体管的第一极与第一电压端电连接；
    第十三晶体管的控制极与第二时钟信号端电连接，第十三晶体管的第一极与第十二晶体管的第二极电连接，第十三晶体管的第二极与第三节点电连接；
    第三电容的第一端与第二时钟信号端电连接，第三电容的第二端与第三节点电连接。
  17. 如权利要求7所述的驱动电路，其中，所述第三节点控制电路包括 第七节点控制子电路和第三节点控制子电路；
    所述第七节点控制子电路用于在第五节点的电位的控制下，控制所述第七节点与第一电压端之间连通或断开，在第三节点的电位的控制下，控制所述第七节点与第二时钟信号端之间连通或断开；
    所述第三节点控制子电路用于根据所述第七节点的电位，控制所述第三节点的电位，并在第一时钟信号端提供的第一时钟信号的控制下，控制第三节点与第二输入端之间连通或断开。
  18. 如权利要求17所述的驱动电路，其中，第三节点控制子电路包括第十一晶体管和第三电容；第七节点控制子电路包括第十二晶体管和第十三晶体管；
    第十一晶体管的控制极与第一时钟信号端电连接，第十一晶体管的第一极与第二输入端电连接，第十一晶体管的第二极与第三节点电连接；
    第十二晶体管的控制极与第五节点电连接，第十二晶体管的第一极与第一电压端电连接，第十二晶体管的第二极与第七节点电连接；
    第十三晶体管的控制极与第三节点电连接，第十三晶体管的第一极与第二时钟信号端电连接，第十三晶体管的第二极与第七节点电连接；
    第三电容的第一端与第七节点电连接，第三电容的第二端与第三节点电连接。
  19. 如权利要求7所述的驱动电路，其中，所述发光控制输出电路包括导通子电路；所述第三节点控制电路包括第三节点控制子电路、第七节点控制子电路和第八节点控制子电路；
    所述导通子电路用于在第二电压端提供的第二电压信号的控制下，控制第三节点与第八节点之间连通或断开；
    所述第三节点控制子电路用于在第一时钟信号端提供的第一时钟信号的控制下，控制第三节点与第二输入端之间连通或断开；
    所述第七节点控制子电路用于在第五节点的电位的控制下，控制所述第七节点与第一电压端之间连通或断开，在第八节点的电位的控制下，控制所述第七节点与第二时钟信号端之间连通或断开；
    所述第八节点控制子电路用于根据所述第七节点的电位，控制所述第八 节点的电位。
  20. 如权利要求19所述的驱动电路，其中，所述导通子电路包括第二导通控制晶体管，所述第三节点控制子电路包括第十一晶体管，所述第七节点控制子电路包括第十二晶体管和第十三晶体管；所述第八节点控制子电路包括第三电容；
    所述第二导通控制晶体管的控制极与第二电压端电连接，所述第二导通控制晶体管的第一极与第三节点电连接，所述第二导通控制晶体管的第二极与第八节点电连接；
    第十一晶体管的控制极与第一时钟信号端电连接，第十一晶体管的第一极与第二输入端电连接，第十一晶体管的第二极与第三节点电连接；
    第十二晶体管的控制极与第五节点电连接，第十二晶体管的第一极与第一电压端电连接，第十二晶体管的第二极与第七节点电连接；
    第十三晶体管的控制极与第八节点电连接，第十三晶体管的第一极与第二时钟信号端电连接，第十三晶体管的第二极与第七节点电连接；
    第三电容的第一端与第七节点电连接，第三电容的第二端与第八节点电连接。
  21. 如权利要求1至6中任一权利要求所述的驱动电路，其中，所述发光控制输出电路包括第一输出晶体管和第二输出晶体管；
    第一输出晶体管的控制极与第三节点电连接，第一输出晶体管的第一极与第二电压端电连接，第一输出晶体管的第二极与发光控制信号输出端电连接；
    第二输出晶体管的控制极与第二节点电连接，第二输出晶体管的第一极与发光控制信号输出端电连接，第二输出晶体管的第二极与第一电压端电连接。
  22. 如权利要求1至6中任一权利要求所述的驱动电路，其中，所述发光控制输出电路包括第二导通控制晶体管、第一输出晶体管和第二输出晶体管；
    所述第二导通控制晶体管的控制极与第二电压端电连接，所述第二导通控制晶体管的第一极与第三节点电连接，所述第二导通控制晶体管的第二极 与第八节点电连接；
    第一输出晶体管的控制极与第八节点电连接，第一输出晶体管的第一极与第二电压端电连接，第一输出晶体管的第二极与发光控制信号输出端电连接；
    第二输出晶体管的控制极与第二节点电连接，第二输出晶体管的第一极与发光控制信号输出端电连接，第二输出晶体管的第二极与第一电压端电连接。
  23. 一种驱动方法，应用于如权利要求1至22中任一权利要求所述的驱动电路，所述驱动方法包括：
    栅极驱动电路在第一节点的电位、第一输入端提供的第一输入信号和复位端提供的复位信号的控制下，根据第一时钟信号端提供的第一时钟信号和第一电压端提供的第一电压信号，控制栅极驱动信号输出端输出栅极驱动信号。
  24. 如权利要求23所述的驱动方法，其中，驱动周期包括依次设置的第一输入阶段、第二输入阶段、第三输入阶段和第一复位阶段；所述驱动方法包括：
    在第一输入阶段，所述第四节点控制电路在第一节点的电位的控制下，控制第四节点与复位端之间断开，在第一输入信号的控制下，控制第四节点与第一电压端之间断开；栅极输出电路在第四节点的电位的控制下，控制栅极驱动信号输出端与第一时钟信号端之间断开，在第一输入信号的控制下，控制栅极驱动信号输出端与所述第一电压端断开，以使得栅极驱动信号输出端维持输出第一电压信号；
    在第二输入阶段，所述第四节点控制电路在第一节点的电位的控制下，控制第四节点与复位端之间连通；栅极输出电路在第四节点的电位的控制下，控制栅极驱动信号输出端与第一时钟信号端之间连通，以使得栅极驱动信号输出端输出第一电压信号；
    在第三输入阶段，所述第四节点控制电路在第一节点的电位的控制下，控制第四节点与复位端之间断开；栅极输出电路在第四节点的电位的控制下，控制栅极驱动信号输出端与第一时钟信号端之间连通，以使得栅极驱动信号 输出端输出第二电压信号；
    在第一复位阶段，所述第四节点控制电路在第一节点的电位的控制下，控制第四节点与复位端之间连通，在第一输入信号的控制下，控制第四节点与第一电压端之间连通；栅极输出电路在第四节点的电位的控制下，控制栅极驱动信号输出端与第一时钟信号端之间断开，在第一输入信号的控制下，控制栅极驱动信号输出端与所述第一电压端连通，以使得栅极驱动信号输出端输出第一电压信号。
  25. 如权利要求24所述的驱动方法，其中，所述驱动电路还包括栅极复位电路；所述驱动方法还包括：
    在第一输入阶段，栅极复位电路在第一节点的电位的控制下，控制所述栅极驱动信号输出端与所述第一电压端之间断开；
    在第二输入阶段，栅极复位电路在第一节点的电位的控制下，控制所述栅极驱动信号输出端与所述第一电压端之间连通；
    在第三输入阶段，栅极复位电路在第一节点的电位的控制下，控制所述栅极驱动信号输出端与所述第一电压端之间断开；
    在第一复位阶段，栅极复位电路在第一节点的电位的控制下，控制所述栅极驱动信号输出端与所述第一电压端之间连通。
  26. 一种驱动模组，包括多级如权利要求1至22中任一权利要求所述的驱动电路。
  27. 如权利要求26所述的驱动模组，其中，所述驱动电路的第二输入端与相邻上一级驱动电路的发光控制信号输出端电连接。
  28. 如权利要求26或27所述的驱动模组，其中，所述驱动电路的第一输入端与相邻上一级驱动电路的发光控制信号输出端电连接；或者，所述驱动电路的第一输入端与该驱动电路的发光控制信号输出端电连接。
  29. 如权利要求26或27所述的驱动模组，其中，所述驱动电路的复位端与相邻下一级驱动电路的发光控制信号输出端电连接；或者，所述复位端与相邻上一级驱动电路的栅极驱动信号输出端电连接。
  30. 一种显示装置，包括如权利要求26或29所述的驱动模组。
PCT/CN2021/095775 2021-05-25 2021-05-25 驱动电路、驱动方法、驱动模组和显示装置 WO2022246642A1 (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN202180001260.9A CN115699146A (zh) 2021-05-25 2021-05-25 驱动电路、驱动方法、驱动模组和显示装置
PCT/CN2021/095775 WO2022246642A1 (zh) 2021-05-25 2021-05-25 驱动电路、驱动方法、驱动模组和显示装置
US17/772,052 US20240144851A1 (en) 2021-05-25 2021-05-25 Driving circuit, driving method, driving module and display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2021/095775 WO2022246642A1 (zh) 2021-05-25 2021-05-25 驱动电路、驱动方法、驱动模组和显示装置

Publications (1)

Publication Number Publication Date
WO2022246642A1 true WO2022246642A1 (zh) 2022-12-01

Family

ID=84229145

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/095775 WO2022246642A1 (zh) 2021-05-25 2021-05-25 驱动电路、驱动方法、驱动模组和显示装置

Country Status (3)

Country Link
US (1) US20240144851A1 (zh)
CN (1) CN115699146A (zh)
WO (1) WO2022246642A1 (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109903715A (zh) * 2019-04-09 2019-06-18 京东方科技集团股份有限公司 栅极驱动单元、栅极驱动方法、栅极驱动电路和显示装置
CN110211539A (zh) * 2018-08-02 2019-09-06 京东方科技集团股份有限公司 像素驱动电路、像素驱动方法和触控显示装置
CN111292664A (zh) * 2020-02-20 2020-06-16 合肥京东方卓印科技有限公司 栅极驱动电路、显示面板及其显示方法
CN111710293A (zh) * 2020-07-15 2020-09-25 京东方科技集团股份有限公司 移位寄存器及其驱动方法、驱动电路、显示装置
CN111816123A (zh) * 2020-07-21 2020-10-23 合肥京东方卓印科技有限公司 显示基板及显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110211539A (zh) * 2018-08-02 2019-09-06 京东方科技集团股份有限公司 像素驱动电路、像素驱动方法和触控显示装置
CN109903715A (zh) * 2019-04-09 2019-06-18 京东方科技集团股份有限公司 栅极驱动单元、栅极驱动方法、栅极驱动电路和显示装置
CN111292664A (zh) * 2020-02-20 2020-06-16 合肥京东方卓印科技有限公司 栅极驱动电路、显示面板及其显示方法
CN111710293A (zh) * 2020-07-15 2020-09-25 京东方科技集团股份有限公司 移位寄存器及其驱动方法、驱动电路、显示装置
CN111816123A (zh) * 2020-07-21 2020-10-23 合肥京东方卓印科技有限公司 显示基板及显示装置

Also Published As

Publication number Publication date
CN115699146A (zh) 2023-02-03
US20240144851A1 (en) 2024-05-02

Similar Documents

Publication Publication Date Title
US20210166632A1 (en) Pixel unit circuit, pixel circuit, method for driving pixel circuit and display device
WO2021244273A1 (zh) 复位控制信号生成电路、方法、模组和显示装置
CN109545145B (zh) 像素电路及其驱动方法、显示装置
US11763740B2 (en) Signal generation circuit, signal generation method, signal generation module and display device
US20200184872A1 (en) Shift register circuit, gate driving circuit and method for driving the same, and display apparatus
WO2022226765A1 (zh) 驱动电路、驱动方法、移位寄存器和显示装置
CN107369413B (zh) 一种像素补偿电路、其驱动方法、显示面板及显示装置
US11263940B2 (en) Shift register unit, driving method thereof, gate drive circuit and display device
CN111768733B (zh) 发光控制信号生成电路、方法和显示装置
US20200211435A1 (en) Shift register unit, driving method, gate drive circuit and display device
CN109215601B (zh) 电压提供单元、方法、显示驱动电路和显示装置
CN113112955A (zh) 像素电路及其驱动方法、显示基板、显示装置
CN114023264A (zh) 驱动电路、驱动模组、驱动方法和显示装置
WO2022246642A1 (zh) 驱动电路、驱动方法、驱动模组和显示装置
WO2024036897A1 (zh) 像素补偿电路及显示面板
WO2021072734A1 (zh) 移位寄存器单元、驱动方法、栅极驱动电路和显示装置
WO2022193685A1 (zh) 驱动电路、驱动方法和显示装置
CN106057119B (zh) 一种行扫描驱动单元、行扫描驱动系统及其驱动方法
US11600224B2 (en) Gate driving circuit and driving method thereof, display panel
WO2023092304A1 (zh) 驱动电路、驱动模组、驱动方法和显示装置
WO2022048425A1 (zh) 栅极驱动单元、驱动方法、栅极驱动电路和显示装置
US11328651B2 (en) Shift register for compensation for sub-pixle row, driving method thereof, gate driving circuit and display device
WO2023173259A1 (zh) 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
TW202008340A (zh) 雙閘極電晶體電路、畫素電路及其閘極驅動電路
CN215895935U (zh) 扫描电路和显示面板

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 17772052

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21942229

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE