WO2022048425A1 - 栅极驱动单元、驱动方法、栅极驱动电路和显示装置 - Google Patents

栅极驱动单元、驱动方法、栅极驱动电路和显示装置 Download PDF

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Publication number
WO2022048425A1
WO2022048425A1 PCT/CN2021/112322 CN2021112322W WO2022048425A1 WO 2022048425 A1 WO2022048425 A1 WO 2022048425A1 CN 2021112322 W CN2021112322 W CN 2021112322W WO 2022048425 A1 WO2022048425 A1 WO 2022048425A1
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WIPO (PCT)
Prior art keywords
node
electrically connected
control
input
terminal
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PCT/CN2021/112322
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English (en)
French (fr)
Inventor
商广良
张洁
卢江楠
李梅
刘利宾
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/905,620 priority Critical patent/US11798458B2/en
Publication of WO2022048425A1 publication Critical patent/WO2022048425A1/zh
Priority to US18/466,619 priority patent/US20230419878A1/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a gate driving unit, a driving method, a gate driving circuit and a display device.
  • an embodiment of the present disclosure provides a gate driving unit, including a first input node control circuit and a charge pump circuit;
  • the first input node control circuit is respectively electrically connected with the clock signal terminal, the input terminal and the first input node, and is used for turning on or off the input terminal and the first input node under the control of the clock signal provided by the clock signal terminal. connections between the first input nodes;
  • the charge pump circuit is electrically connected to the first input node, the input clock signal terminal and the first node, respectively, and is used for, when the voltage signal of the first input node is the first voltage signal, at the input clock signal Under the control of the input clock signal provided by the terminal, the voltage signal of the first input node is controlled to be converted into the voltage signal of the first node, and the polarity of the voltage signal of the first node is the same as that of the first node.
  • the polarities of the voltage signals of the input nodes are the same, and the absolute value of the voltage value of the voltage signal of the first node is greater than the absolute value of the voltage value of the voltage signal of the first input node.
  • the gate driving unit includes an output circuit, the output circuit includes a first output transistor, the control electrode of the first output transistor is electrically connected to the first node, and the first output transistor is connected to the first node.
  • One pole is electrically connected to the output voltage terminal, and the second pole of the first output transistor is electrically connected to the gate driving signal output terminal.
  • the charge pump circuit includes an input energy storage sub-circuit, an on-off control sub-circuit and a first energy storage sub-circuit;
  • the first end of the input energy storage sub-circuit is electrically connected to the input clock signal terminal, and the second end of the input energy storage sub-circuit is electrically connected to the first input node for storing electrical energy and according to the the potential of the input clock signal controls the potential of the first input node;
  • the on-off control subcircuit is electrically connected to the first input node and the first node respectively, and is used for turning on or off the first input node under the control of the potential of the first input node a connection with the first node;
  • the first energy storage sub-circuit is electrically connected to the first node for storing electrical energy and maintaining the potential of the first node.
  • the charge pump circuit includes an input energy storage sub-circuit, an on-off control sub-circuit, a switch control sub-circuit and a first energy storage sub-circuit;
  • the first end of the input energy storage sub-circuit is electrically connected to the first control node, and the second end of the input energy storage sub-circuit is electrically connected to the first input node for storing electrical energy and according to the first control node The potential of the control the potential of the first input node;
  • the on-off control subcircuit is electrically connected to the first input node and the first node respectively, and is used for turning on or off the first input node under the control of the potential of the first input node a connection with the first node;
  • the first energy storage sub-circuit is electrically connected to the first node for storing electrical energy and maintaining the potential of the first node;
  • the switch control sub-circuit is electrically connected to the first input node, the input clock signal terminal and the first control node, respectively, and is used to turn on or off all the switches under the control of the potential of the first input node. connection between the input clock signal terminal and the first control node.
  • the input energy storage sub-circuit includes an input capacitor
  • the first energy storage sub-circuit includes a first storage capacitor
  • the on-off control sub-circuit includes an on-off control transistor
  • the first end of the input capacitor is electrically connected to the input clock signal end, and the second end of the input capacitor is electrically connected to the first input node;
  • the first end of the first storage capacitor is electrically connected to the first node, and the second end of the first storage capacitor is electrically connected to the second voltage end;
  • control electrode of the on-off control transistor and the first electrode of the on-off control transistor are electrically connected to the first input node, and the second electrode of the on-off control transistor is electrically connected to the first node.
  • the input energy storage sub-circuit includes an input capacitor
  • the first energy storage sub-circuit includes a first storage capacitor
  • the on-off control sub-circuit includes an on-off control transistor
  • a first end of the input capacitor is electrically connected to the first control node, and a second end of the input capacitor is electrically connected to the first input node;
  • the first end of the first storage capacitor is electrically connected to the first node, and the second end of the first storage capacitor is electrically connected to the second voltage end;
  • control electrode of the on-off control transistor and the first electrode of the on-off control transistor are electrically connected to the first input node, and the second electrode of the on-off control transistor is electrically connected to the first node.
  • the ratio between the capacitance value of the input capacitor and the capacitance value of the first storage capacitor is greater than or equal to 1 and less than or equal to 10.
  • the switch control subcircuit includes a switch control transistor
  • the control electrode of the switch control transistor is electrically connected to the first input node, the first electrode of the switch control transistor is electrically connected to the input clock signal terminal, and the second electrode of the switch control transistor is electrically connected to the first input node.
  • a control node is electrically connected.
  • the first input node control circuit includes a first isolation node control sub-circuit and a first isolation sub-circuit;
  • the first isolation node control sub-circuit is electrically connected to the clock signal terminal, the input terminal and the first isolation node respectively, and is used for turning on or off the input terminal under the control of the clock signal provided by the clock signal terminal a connection with the first isolation node;
  • the first isolation sub-circuit is respectively electrically connected to the second voltage terminal, the first isolation node and the first input node, and is used for controlling the second voltage terminal under the control of the second voltage signal provided by the second voltage terminal.
  • the first isolation node communicates with the first input node.
  • the clock signal terminal includes a first clock signal terminal and a second clock signal terminal;
  • the first isolation node control sub-circuit includes a first control transistor and a second control transistor; the control electrode of the first control transistor is the same as the control electrode.
  • the second clock signal terminal is electrically connected, the first pole of the first control transistor is electrically connected to the input terminal; the control pole of the second control transistor is electrically connected to the first clock signal terminal, the The first electrode of the second control transistor is electrically connected to the second electrode of the first control transistor, and the second electrode of the second control transistor is electrically connected to the first isolation node; or,
  • the clock signal terminal includes a second clock signal terminal
  • the first isolated node control sub-circuit includes a first control transistor
  • the control electrode of the first control transistor is electrically connected to the second clock signal terminal
  • the first control transistor is electrically connected to the second clock signal terminal.
  • a first electrode of a control transistor is electrically connected to the input terminal, and a second electrode of the first control transistor is electrically connected to the first isolation node; or,
  • the clock signal terminal includes a first clock signal terminal
  • the first isolation node control sub-circuit includes a second control transistor; the control electrode of the second control transistor is electrically connected to the first clock signal terminal, and the first control transistor is electrically connected to the first clock signal terminal.
  • a first electrode of a control transistor is electrically connected to the input terminal, and a second electrode of the second control transistor is electrically connected to the first isolation node.
  • the first isolation subcircuit includes a first isolation transistor
  • the control electrode of the first isolation transistor is electrically connected to the second voltage terminal, the first electrode of the first isolation transistor is electrically connected to the first isolation node, and the second electrode of the first isolation transistor is electrically connected to the first isolation node.
  • the first input node is electrically connected.
  • the gate driving unit according to at least one embodiment of the present disclosure further includes a first node control circuit
  • the first node control circuit is respectively electrically connected to the second input node, the third voltage terminal and the first node, and is used for controlling the third voltage terminal to input the third voltage terminal under the control of the potential of the second input node. A voltage signal is written to the first node.
  • the first node control circuit includes a first node control transistor
  • a control electrode of the first node control transistor is electrically connected to the second input node, a first electrode of the first node control transistor is electrically connected to a third voltage terminal, and a second electrode of the first node control transistor is electrically connected is electrically connected to the first node.
  • the gate driving unit according to at least one embodiment of the present disclosure further includes a first tank circuit
  • the first energy storage circuit is electrically connected to the second node and the second clock signal terminal respectively, and is used for controlling the potential of the second node according to the second clock signal.
  • the gate driving unit described in at least one embodiment of the present disclosure further includes a gate driving signal output terminal and a first energy storage circuit;
  • the first energy storage circuit is electrically connected to the second node and the gate driving signal output terminal respectively, and is used for controlling the potential of the second node according to the gate driving signal output from the gate driving signal output terminal.
  • the gate driving unit described in at least one embodiment of the present disclosure further includes an output circuit
  • the output circuit is respectively electrically connected with the first node, the second node, the gate drive signal output terminal, the output voltage terminal and the second clock signal output terminal, and is used for controlling the output voltage under the control of the potential of the first node writing a signal into the gate driving signal output terminal, and under the control of the potential of the second node, writing a second clock signal into the gate driving signal output terminal;
  • the output voltage terminal is used for providing an output voltage signal.
  • the output circuit includes a first output transistor and a second output transistor
  • the control electrode of the first output transistor is electrically connected to the first node, the first electrode of the first output transistor is electrically connected to the output voltage terminal, and the second electrode of the first output transistor is electrically connected to the output voltage terminal.
  • the gate drive signal output terminal is electrically connected;
  • the control electrode of the second output transistor is electrically connected to the second node, the first electrode of the second output transistor is electrically connected to the gate driving signal output terminal, and the second electrode of the second output transistor is electrically connected is electrically connected to the second clock signal terminal.
  • the gate driving unit according to at least one embodiment of the present disclosure further includes a second node control circuit
  • the second node control circuit includes a third input node control subcircuit, a second input node control subcircuit and a second node control subcircuit;
  • the third input node control sub-circuit is respectively electrically connected to the first clock signal terminal, the second voltage terminal, the first input node and the third input node, and is used for converting the second voltage signal under the control of the first clock signal writing to the third input node, and for writing the first clock signal into the third input node under the control of the potential of the first input node;
  • the second input node control sub-circuit is respectively electrically connected to the third input node, the second input node and the input clock signal terminal, and is used for writing the input clock signal under the control of the potential of the third input node the second input node for controlling the potential of the second input node according to the potential of the third input node;
  • the second node control sub-circuit is respectively electrically connected to the second input node, the first input node, the second node and the input clock signal terminal, and the second node control sub-circuit is further connected to the second clock signal terminal or the first clock signal terminal.
  • the three-voltage terminals are electrically connected for turning on or off the connection between the second input node and the second node under the control of an input clock signal, and for changing the potential of the first input node Under the control, the second clock signal or the third voltage signal is written into the second node.
  • the third input node control sub-circuit includes a third control transistor and a fourth control transistor, wherein,
  • the control pole of the third control transistor is electrically connected to the first clock signal terminal, the first pole of the third control transistor is electrically connected to the second voltage terminal, and the second pole of the third control transistor is electrically connected to the third input Node electrical connection;
  • the control electrode of the fourth control transistor is electrically connected to the first input node, the first electrode of the fourth control transistor is electrically connected to the first clock signal terminal, and the second electrode of the fourth control transistor is electrically connected is electrically connected to the third input node.
  • the gate driving unit according to at least one embodiment of the present disclosure further includes a second node control circuit
  • the second node control circuit includes a third input node control subcircuit, a second input node control subcircuit and a second node control subcircuit;
  • the third input node control sub-circuit is respectively electrically connected to the first clock signal terminal, the second voltage terminal, the first isolation node and the third input node, and is used for converting the second voltage signal under the control of the first clock signal writing to the third input node, and for writing the first clock signal into the third input node under the control of the potential of the first isolation node;
  • the second input node control sub-circuit is respectively electrically connected to the third input node, the second input node and the input clock signal terminal, and is used for writing the input clock signal under the control of the potential of the third input node the second input node for controlling the potential of the second input node according to the potential of the third input node;
  • the second node control sub-circuit is respectively electrically connected to the second input node, the first isolation node, the second node and the input clock signal terminal, and the second node control sub-circuit is further connected to the second clock signal terminal or the first clock signal terminal.
  • the three-voltage terminals are electrically connected for turning on or off the connection between the second input node and the second node under the control of an input clock signal, and for changing the potential of the first input node Under the control, the second clock signal or the third voltage signal is written into the second node.
  • the third input node control sub-circuit includes a third control transistor and a fourth control transistor, wherein,
  • the control pole of the third control transistor is electrically connected to the first clock signal terminal, the first pole of the third control transistor is electrically connected to the second voltage terminal, and the second pole of the third control transistor is electrically connected to the third input Node electrical connection;
  • the control electrode of the fourth control transistor is electrically connected to the first isolation node, the first electrode of the fourth control transistor is electrically connected to the first clock signal terminal, and the second electrode of the fourth control transistor is electrically connected is electrically connected to the third input node.
  • the third input node control sub-circuit includes a third control transistor, a fourth control transistor and a second isolation transistor;
  • the control electrode of the third control transistor is electrically connected to the first clock signal terminal, the first electrode of the third control transistor is electrically connected to the second voltage terminal, and the second electrode of the third control transistor is isolated from the second voltage terminal Node electrical connection;
  • the control electrode of the fourth control transistor is electrically connected to the first isolation node, the first electrode of the fourth control transistor is electrically connected to the first clock signal terminal, and the second electrode of the fourth control transistor is electrically connected electrically connected to the second isolation node;
  • the control electrode of the second isolation transistor is electrically connected to the second voltage terminal, the first electrode of the second isolation transistor is electrically connected to the second isolation node, and the second electrode of the second isolation transistor is electrically connected to the third input node electrical connection.
  • the second input node control sub-circuit includes a fifth control transistor and a first capacitor
  • the control electrode of the fifth control transistor is electrically connected to the third input node, the first electrode of the fifth control transistor is electrically connected to the second input node, and the second electrode of the fifth control transistor is electrically connected to the second input node.
  • the input clock signal terminal is electrically connected;
  • the first end of the first capacitor is electrically connected to the third input node, and the second end of the first capacitor is electrically connected to the second input node.
  • the second node control sub-circuit includes a sixth control transistor and a seventh control transistor;
  • the control electrode of the sixth control transistor is electrically connected to the input clock signal terminal, the first electrode of the sixth control transistor is electrically connected to the second input node, and the second electrode of the sixth control transistor is electrically connected to the second input node. the second node is electrically connected;
  • the control electrode of the seventh control transistor is electrically connected to the first isolation node, the first electrode of the seventh control transistor is electrically connected to the second clock signal terminal or the third voltage terminal, and the seventh control transistor is electrically connected to the second clock signal terminal or the third voltage terminal.
  • the second pole is electrically connected to the second node.
  • an embodiment of the present disclosure further provides a driving method, which is applied to the above-mentioned gate driving unit, and the driving method includes:
  • the first input node control circuit turns on or off the connection between the input terminal and the first input node under the control of the clock signal provided by the clock signal terminal;
  • the charge pump circuit controls to convert the voltage signal of the first input node into the first voltage signal under the control of the input clock signal provided by the input clock signal terminal.
  • a voltage signal of a node, and the polarity of the voltage signal of the first node is the same as the polarity of the voltage signal of the first input node, and the absolute value of the voltage value of the voltage signal of the first node is greater than all The absolute value of the voltage value of the voltage signal of the first input node.
  • an embodiment of the present disclosure further provides a gate driving circuit, including the above gate driving unit.
  • an embodiment of the present disclosure further provides a display device including the above gate driving circuit.
  • FIG. 1 is a structural diagram of a gate driving unit according to an embodiment of the present disclosure
  • FIG. 2 is a structural diagram of a gate driving unit according to at least one embodiment of the present disclosure
  • FIG. 3 is a structural diagram of a gate driving unit according to at least one embodiment of the present disclosure.
  • FIG. 4 is a structural diagram of a gate driving unit according to at least one embodiment of the present disclosure.
  • FIG. 5 is a structural diagram of a gate driving unit according to at least one embodiment of the present disclosure.
  • FIG. 6 is a structural diagram of a gate driving unit according to at least one embodiment of the present disclosure.
  • FIG. 7 is a structural diagram of a gate driving unit according to at least one embodiment of the present disclosure.
  • FIG. 8 is a structural diagram of a gate driving unit according to at least one embodiment of the present disclosure.
  • FIG. 9 is a structural diagram of a gate driving unit according to at least one embodiment of the present disclosure.
  • FIG. 10 is a structural diagram of a gate driving unit according to at least one embodiment of the present disclosure.
  • FIG. 11 is a structural diagram of a gate driving unit according to at least one embodiment of the present disclosure.
  • FIG. 12 is a structural diagram of a gate driving unit according to at least one embodiment of the present disclosure.
  • FIG. 13 is a structural diagram of a gate driving unit according to at least one embodiment of the present disclosure.
  • FIG. 14 is a circuit diagram of at least one embodiment of the gate driving unit of the present invention.
  • FIG. 15 is a working timing diagram of at least one embodiment of the gate driving unit according to the present invention as shown in FIG. 14;
  • 16 is a circuit diagram of at least one embodiment of the gate driving unit of the present invention.
  • 17 is a circuit diagram of at least one embodiment of the gate driving unit of the present invention.
  • FIG. 18 is a working timing diagram of at least one embodiment of the gate driving unit according to the present invention as shown in FIG. 17 ;
  • 19 is a circuit diagram of at least one specific embodiment of the gate driving unit of the present invention.
  • 20 is a circuit diagram of at least one specific embodiment of the gate driving unit of the present invention.
  • FIG. 21 is a working timing diagram of at least one specific embodiment of the gate driving unit according to the present invention as shown in FIG. 20;
  • 22 is a circuit diagram of at least one embodiment of the gate driving unit of the present invention.
  • FIG. 23 is a circuit diagram of at least one embodiment of the gate driving unit of the present invention.
  • 24 is a circuit diagram of at least one embodiment of the gate driving unit of the present invention.
  • 25 is a circuit diagram of at least one embodiment of the gate driving unit of the present invention.
  • FIG. 26 is a circuit diagram of at least one embodiment of the gate driving unit of the present invention.
  • the transistors used in all the embodiments of the present disclosure may be triodes, thin film transistors, field effect transistors, or other devices with the same characteristics.
  • one pole is called the first pole, and the other pole is called the second pole.
  • control electrode when the transistor is a triode, the control electrode may be the base electrode, the first electrode may be the collector electrode, and the second electrode may be the emitter electrode; or the control electrode may be the base electrode electrode, the first electrode can be an emitter electrode, and the second electrode can be a collector electrode.
  • the control electrode when the transistor is a thin film transistor or a field effect transistor, the control electrode may be a gate electrode, the first electrode may be a drain electrode, and the second electrode may be a source electrode;
  • the control electrode may be a gate electrode, the first electrode may be a source electrode, and the second electrode may be a drain electrode.
  • the gate driving unit includes a first input node control circuit 10 and a charge pump circuit 11 ;
  • the first input node control circuit 10 is electrically connected to the clock signal terminal K0, the input terminal I1 and the first input node P11 respectively, and is used to turn on or off under the control of the clock signal provided by the clock signal terminal K0 the connection between the input terminal I1 and the first input node P11;
  • the charge pump circuit 11 is electrically connected to the first input node P11, the input clock signal terminal KI and the first node P1 respectively, and is used for, when the voltage signal of the first input node P11 is the first voltage signal, Under the control of the input clock signal provided by the input clock signal terminal KI, the voltage signal of the first input node P11 is controlled to be converted into the voltage signal of the first node P1, and the voltage of the first node P1 is controlled to The polarity of the signal is the same as the polarity of the voltage signal of the first input node P11, and the absolute value of the voltage value of the voltage signal of the first node P1 is greater than the voltage value of the voltage signal of the first input node P11. absolute value.
  • the gate driving unit can sufficiently pull down or raise the potential of the first node P1 in the hold phase through the charge pump circuit 11, so that in the hold phase, the first output transistor controlled by P1 remains turned on, and then This makes it possible to make the potential of the output gate driving signal not be affected by noise interference in the hold phase.
  • the polarity of the voltage signal of the first node P1 is the same as the polarity of the voltage signal of the first input node P11 means: when the voltage signal of P1 is a positive voltage signal, the voltage signal of P11 is a positive voltage signal ; When the voltage signal of P1 is a negative voltage signal, the voltage signal of P11 is a negative voltage signal.
  • the absolute value of the voltage value of the voltage signal of the first node P1 being greater than the absolute value of the voltage value of the voltage signal of the first input node P11 means:
  • the voltage value of the voltage signal of P1 is greater than the voltage value of the voltage signal of P11;
  • the voltage value of the voltage signal of P1 is smaller than the voltage value of the voltage signal of P11.
  • the charge pump structure can further lower or raise the potential of the first node in the hold phase.
  • the charge pump circuit can convert P11
  • the potential pump is 2-3 times lower, but not limited to this.
  • the gate driving unit may include an output circuit, the output circuit includes a first output transistor, a control electrode of the first output transistor is electrically connected to the first node, and the first output transistor The first pole of the first output transistor is electrically connected to the output voltage terminal, and the second pole of the first output transistor is electrically connected to the gate driving signal output terminal.
  • the first output transistor is a p-type transistor, and the first voltage signal is a negative voltage signal; or,
  • the first voltage signal is a positive voltage signal.
  • a working cycle of the gate driving unit may include an input stage, an output stage, a reset stage and a hold stage which are arranged in sequence.
  • the input terminal provides an input signal; in the output stage, the gate The drive unit outputs a valid gate drive signal; in the reset stage, the gate drive signal is reset, so that the gate drive unit outputs an invalid gate drive signal; in the hold stage, the gate drive unit needs to keep the output invalid gate drive signal.
  • the potential of the valid gate driving signal is a high voltage
  • the potential of the invalid gate driving signal is low Voltage
  • the potential of the valid gate driving signal is a low voltage
  • the potential of the invalid gate driving signal is a high voltage
  • the charge pump circuit includes an input energy storage sub-circuit 21 , an on-off control sub-circuit 22 and the first energy storage sub-circuit 23;
  • the first end of the input energy storage sub-circuit 21 is electrically connected to the input clock signal terminal KI, and the second end of the input energy storage sub-circuit 21 is electrically connected to the first input node P11 for storing electrical energy and controlling the potential of the first input node P11 according to the potential of the input clock signal;
  • the on-off control sub-circuit 22 is electrically connected to the first input node P11 and the first node P1 respectively, and is used for turning on or off the first input node P11 under the control of the potential of the first input node P11 the connection between the first input node P11 and the first node P1;
  • the first energy storage sub-circuit 23 is electrically connected to the first node P1 for storing electrical energy and maintaining the potential of the first node P1.
  • the input energy storage sub-circuit 21 , the on-off control sub-circuit 22 and the first energy storage sub-circuit 23 form a charge pump circuit.
  • the ratio between the capacitance value of the input capacitor included in the input energy storage sub-circuit 21 and the capacitance value of the first storage capacitor included in the first energy storage sub-circuit may be greater than or equal to 1:1 and less than or equal to 10:1, but not limited thereto.
  • the input energy storage sub-circuit includes an input capacitor
  • the first energy storage sub-circuit includes a first storage capacitor
  • the on-off control sub-circuit includes an on-off control transistor
  • the first end of the input capacitor is electrically connected to the input clock signal end, and the second end of the input capacitor is electrically connected to the first input node;
  • the first end of the first storage capacitor is electrically connected to the first node, and the second end of the first storage capacitor is electrically connected to the second voltage end;
  • control electrode of the on-off control transistor and the first electrode of the on-off control transistor are electrically connected to the first input node, and the second electrode of the on-off control transistor is electrically connected to the first node.
  • the input energy storage sub-circuit 21 and the first energy storage sub-circuit 23 may include capacitors, and the on-off control sub-circuit 22 may include diode-connected transistors, but not limited thereto.
  • the charge pump circuit includes an input energy storage sub-circuit 21 and an on-off control sub-circuit 22 , switch control sub-circuit 20 and first energy storage sub-circuit 23;
  • the first end of the input energy storage sub-circuit 21 is electrically connected to the first control node P21, and the second end of the input energy storage sub-circuit 21 is electrically connected to the first input node P11 for storing electrical energy and according to The potential of the first control node P21 controls the potential of the first input node P11;
  • the on-off control sub-circuit 22 is electrically connected to the first input node P11 and the first node P1 respectively, and is used for turning on or off the first input node P11 under the control of the potential of the first input node P11 the connection between the first input node P11 and the first node P1;
  • the first energy storage sub-circuit 23 is electrically connected to the first node P1 for storing electrical energy and maintaining the potential of the first node P1;
  • the switch control sub-circuit 20 is electrically connected to the first input node P11, the input clock signal terminal KI and the first control node P21, respectively, and is used for conducting a circuit under the control of the potential of the first input node P11. Turn on or off the connection between the input clock signal terminal KI and the first control node P21.
  • the input energy storage sub-circuit 21 , the on-off control sub-circuit 22 , the switch control sub-circuit 20 and the first energy storage sub-circuit Circuit 23 constitutes a charge pump circuit.
  • a switch control sub-circuit 20 is added to the charge pump circuit, and the The switch control subcircuit 20 turns on or off the connection between the input clock signal terminal KI and the first control node P21 under the control of the potential of the first input node P11; the switch control subcircuit 20 can control whether the input clock signal terminal KI is connected to the input energy storage sub-circuit 21, and whether the potential of P11 is controlled by the input clock signal.
  • the input energy storage sub-circuit includes an input capacitor
  • the first energy storage sub-circuit includes a first storage capacitor
  • the on-off control sub-circuit includes an on-off control transistor
  • the first end of the input capacitor is electrically connected to the first control node, and the second end of the input capacitor is electrically connected to the first input node;
  • the first end of the first storage capacitor is electrically connected to the first node, and the second end of the first storage capacitor is electrically connected to the second voltage end;
  • control electrode of the on-off control transistor and the first electrode of the on-off control transistor are electrically connected to the first input node, and the second electrode of the on-off control transistor is electrically connected to the first node.
  • the switch control subcircuit includes a switch control transistor
  • the control electrode of the switch control transistor is electrically connected to the first input node, the first electrode of the switch control transistor is electrically connected to the input clock signal terminal, and the second electrode of the switch control transistor is electrically connected to the first input node.
  • a control node is electrically connected.
  • the ratio between the capacitance value of the input capacitor and the capacitance value of the first storage capacitor is greater than or equal to 1 and less than or equal to 10, but not limited thereto.
  • the first input node control circuit may include a first isolation node control sub-circuit 41 and a first isolation node subcircuit 42;
  • the first isolation node control sub-circuit 41 is electrically connected to the clock signal terminal K0, the input terminal I1 and the first isolation node P31 respectively, and is used to turn on or off under the control of the clock signal provided by the clock signal terminal K0. Open the connection between the input terminal I1 and the first isolation node P31;
  • the first isolation sub-circuit 42 is electrically connected to the second voltage terminal V2, the first isolation node P31 and the first input node P11 respectively, and is used for controlling the second voltage signal provided at the second voltage terminal V2 Next, the communication between the first isolation node P31 and the first input node P11 is controlled.
  • the first isolation sub-circuit 42 controls the communication between the first isolation node P31 and the first input node P11, and the first isolation node
  • the control sub-circuit 41 controls whether to write the input signal into the first isolation node P31 under the control of the clock signal provided by K0.
  • the clock signal terminal may include a first clock signal terminal and a second clock signal terminal;
  • the first isolated node control sub-circuit includes a first control transistor and a second control transistor; the first control transistor The control electrode of the first control transistor is electrically connected to the second clock signal terminal, the first electrode of the first control transistor is electrically connected to the input terminal, and the control electrode of the second control transistor is electrically connected to the first clock signal terminal.
  • a first electrode of the second control transistor is electrically connected to a second electrode of the first control transistor, and a second electrode of the second control transistor is electrically connected to the first isolation node.
  • the clock signal terminal may include a second clock signal terminal
  • the first isolation node control sub-circuit may include a first control transistor; the control electrode of the first control transistor is connected to the first control transistor.
  • the two clock signal terminals are electrically connected, the first pole of the first control transistor is electrically connected to the input terminal, and the second pole of the first control transistor is electrically connected to the first isolation node.
  • the clock signal terminal may include a first clock signal terminal
  • the first isolation node control sub-circuit may include a second control transistor; the control electrode of the second control transistor is connected to the first A clock signal terminal is electrically connected, the first pole of the first control transistor is electrically connected to the input terminal, and the second pole of the second control transistor is electrically connected to the first isolation node.
  • the first isolation node control sub-circuit may only include a first control transistor, and the control electrode of the first control transistor is electrically connected to the second clock signal terminal, provided that the rising edge of the second clock signal not earlier than the falling edge of the input signal provided at the input; or,
  • the first isolated node control sub-circuit may only include a second control transistor, and the control electrode of the second control transistor is electrically connected to the first clock signal terminal, provided that the rising edge of the first clock signal is not earlier than the input terminal Provides the falling edge of the input signal.
  • the first isolation subcircuit includes a first isolation transistor
  • the control electrode of the first isolation transistor is electrically connected to the second voltage terminal, the first electrode of the first isolation transistor is electrically connected to the first isolation node, and the second electrode of the first isolation transistor is electrically connected to the first isolation node.
  • the first input node is electrically connected.
  • the second voltage terminal when the first isolation transistor is a p-type transistor, the second voltage terminal may be a low voltage terminal; when the first isolation transistor is an n-type transistor, the second voltage terminal may is a high voltage terminal, so that the first isolation transistor is normally turned on.
  • a first isolation transistor may be added, so as to reduce the leakage of the first isolation node and improve the output response speed.
  • At least one embodiment of the gate driving unit described in the present disclosure further includes a first node control circuit 12 ; the first node control circuit 12 ;
  • the node control circuit 12 is electrically connected to the second input node P12, the third voltage terminal V3 and the first node P1, respectively, and is used for controlling the writing of the third voltage signal into the second input node P12 under the control of the potential of the second input node P12. Describe the first node P1;
  • the third voltage terminal V3 is used for providing the third voltage signal.
  • the third voltage terminal V3 may be a high voltage terminal, and the third voltage signal may be a high voltage signal, but not limited thereto.
  • the gate driving unit described in at least one embodiment of the present disclosure may further include a first node control circuit 12, and the first node control circuit 12 is connected to the second input Under the control of the potential of the node P12, the potential of the first node P1 is controlled.
  • the gate driving unit described in at least one embodiment of the present disclosure may further include a first tank circuit
  • the first energy storage circuit is electrically connected to the second node and the second clock signal terminal respectively, and is used for controlling the potential of the second node according to the second clock signal.
  • the gate driving unit may further include a first tank circuit, and in a preferred case, the first tank circuit may control the potential of the second node according to the second clock signal, so as to In the reset phase, the potential of the second node can be changed by the second clock signal, so that the gate output of the gate driving unit can be simultaneously controlled by the first output transistor controlled by the first node and the second output transistor controlled by the second node.
  • the drive signal is reset to achieve a complete and fast reset of the gate drive signal.
  • the gate driving unit described in at least one embodiment of the present disclosure may further include a gate driving signal output terminal and a first energy storage circuit;
  • the first energy storage circuit is electrically connected to the second node and the gate driving signal output terminal respectively, and is used for controlling the potential of the second node according to the gate driving signal output from the gate driving signal output terminal.
  • the gate driving unit may further include a first tank circuit, and in a preferred case, the first tank circuit is electrically connected to the gate driving signal output end of the gate driving unit, reducing the The capacitive load of the first energy storage circuit is reduced, which is beneficial to reduce power consumption.
  • the gate driving unit described in at least one embodiment of the present disclosure may further include a gate driving signal output terminal and an output circuit;
  • the output circuit is respectively electrically connected with the first node, the second node, the gate drive signal output terminal, the output voltage terminal and the second clock signal output terminal, and is used for controlling the output voltage under the control of the potential of the first node writing a signal into the gate driving signal output terminal, and under the control of the potential of the second node, writing a second clock signal into the gate driving signal output terminal;
  • the output voltage terminal is used for providing an output voltage signal.
  • the gate driving unit may include a gate driving signal output terminal and an output circuit, and the output circuit controls to output the gate driving signal under the control of the potential of the first node and the potential of the second node.
  • the output circuit includes a first output transistor and a second output transistor
  • the control electrode of the first output transistor is electrically connected to the first node, the first electrode of the first output transistor is electrically connected to the output voltage terminal, and the second electrode of the first output transistor is electrically connected to the output voltage terminal.
  • the gate drive signal output terminal is electrically connected;
  • the control electrode of the second output transistor is electrically connected to the second node, the first electrode of the second output transistor is electrically connected to the gate driving signal output terminal, and the second electrode of the second output transistor is electrically connected is electrically connected to the second clock signal terminal.
  • the gate driving unit described in at least one embodiment of the present disclosure may further include a second node control circuit
  • the second node control circuit includes a third input node control subcircuit, a second input node control subcircuit and a second node control subcircuit;
  • the third input node control sub-circuit is respectively electrically connected to the first clock signal terminal, the second voltage terminal, the first input node and the third input node, and is used for converting the second voltage signal under the control of the first clock signal writing to the third input node, and for writing the first clock signal into the third input node under the control of the potential of the first input node;
  • the second input node control sub-circuit is respectively electrically connected to the third input node, the second input node and the input clock signal terminal, and is used for writing the input clock signal under the control of the potential of the third input node the second input node for controlling the potential of the second input node according to the potential of the third input node;
  • the second node control sub-circuit is respectively electrically connected to the second input node, the first input node, the second node and the input clock signal terminal, and the second node control sub-circuit is further connected to the second clock signal terminal or the first clock signal terminal.
  • the three-voltage terminals are electrically connected for turning on or off the connection between the second input node and the second node under the control of an input clock signal, and for changing the potential of the first input node Under the control, the second clock signal or the third voltage signal is written into the second node.
  • the gate driving unit may further include a second node control circuit
  • the second node control circuit includes a third input node control subcircuit, a second input node control subcircuit and a second node control subcircuit, the first The three-input node control subcircuit controls the potential of the third input node, the second input node control subcircuit controls the potential of the second input node, and the second node control subcircuit controls the potential of the second node.
  • the third input node control sub-circuit includes a third control transistor and a fourth control transistor, wherein,
  • the control pole of the third control transistor is electrically connected to the first clock signal terminal, the first pole of the third control transistor is electrically connected to the second voltage terminal, and the second pole of the third control transistor is electrically connected to the third input Node electrical connection;
  • the control electrode of the fourth control transistor is electrically connected to the first input node, the first electrode of the fourth control transistor is electrically connected to the first clock signal terminal, and the second electrode of the fourth control transistor is electrically connected is electrically connected to the third input node.
  • the gate driving unit described in at least one embodiment of the present disclosure may further include a second node control circuit
  • the second node control circuit includes a third input node control subcircuit, a second input node control subcircuit and a second node control subcircuit;
  • the third input node control sub-circuit is respectively electrically connected to the first clock signal terminal, the second voltage terminal, the first isolation node and the third input node, and is used for converting the second voltage signal under the control of the first clock signal writing to the third input node, and for writing the first clock signal into the third input node under the control of the potential of the first isolation node;
  • the second input node control sub-circuit is respectively electrically connected to the third input node, the second input node and the input clock signal terminal, and is used for writing the input clock signal under the control of the potential of the third input node the second input node for controlling the potential of the second input node according to the potential of the third input node;
  • the second node control sub-circuit is respectively electrically connected to the second input node, the first input node, the second node and the input clock signal terminal, and the second node control sub-circuit is further connected to the second clock signal terminal or the first clock signal terminal.
  • the three-voltage terminals are electrically connected for turning on or off the connection between the second input node and the second node under the control of an input clock signal, and for changing the potential of the first input node Under the control, the second clock signal or the third voltage signal is written into the second node.
  • the third input node control sub-circuit includes a third control transistor and a fourth control transistor, wherein,
  • the control pole of the third control transistor is electrically connected to the first clock signal terminal, the first pole of the third control transistor is electrically connected to the second voltage terminal, and the second pole of the third control transistor is electrically connected to the third input Node electrical connection;
  • the control electrode of the fourth control transistor is electrically connected to the first isolation node, the first electrode of the fourth control transistor is electrically connected to the first clock signal terminal, and the second electrode of the fourth control transistor is electrically connected is electrically connected to the third input node.
  • the third input node control sub-circuit includes a third control transistor, a fourth control transistor and a second isolation transistor;
  • the control electrode of the third control transistor is electrically connected to the first clock signal terminal, the first electrode of the third control transistor is electrically connected to the second voltage terminal, and the second electrode of the third control transistor is isolated from the second voltage terminal Node electrical connection;
  • the control electrode of the fourth control transistor is electrically connected to the first isolation node, the first electrode of the fourth control transistor is electrically connected to the first clock signal terminal, and the second electrode of the fourth control transistor is electrically connected electrically connected to the second isolation node;
  • the control electrode of the second isolation transistor is electrically connected to the second voltage terminal, the first electrode of the second isolation transistor is electrically connected to the second isolation node, and the second electrode of the second isolation transistor is electrically connected to the third input node electrical connection.
  • the third input node control sub-circuit may use a second isolation transistor to prevent leakage to the third input node.
  • the second input node control sub-circuit includes a fifth control transistor and a first capacitor
  • the control electrode of the fifth control transistor is electrically connected to the third input node, the first electrode of the fifth control transistor is electrically connected to the second input node, and the second electrode of the fifth control transistor is electrically connected to the second input node.
  • the input clock signal terminal is electrically connected;
  • the first end of the first capacitor is electrically connected to the third input node, and the second end of the first capacitor is electrically connected to the second input node.
  • the second node control sub-circuit includes a sixth control transistor and a seventh control transistor;
  • the control electrode of the sixth control transistor is electrically connected to the input clock signal terminal, the first electrode of the sixth control transistor is electrically connected to the second input node, and the second electrode of the sixth control transistor is electrically connected to the second input node. the second node is electrically connected;
  • the control electrode of the seventh control transistor is electrically connected to the first isolation node, the first electrode of the seventh control transistor is electrically connected to the second clock signal terminal or the third voltage terminal, and the seventh control transistor is electrically connected to the second clock signal terminal or the third voltage terminal.
  • the second pole is electrically connected to the second node.
  • the gate driving unit may further include a first tank circuit 31 , a gate a drive signal output terminal O1, an output circuit 30 and a second node control circuit;
  • the first energy storage circuit 31 is electrically connected to the second node P2 and the second clock signal terminal K2 respectively, and is used for controlling the potential of the second node P2 according to the second clock signal; the second clock signal terminal K2 is used for for providing the second clock signal;
  • the output circuit 30 is respectively electrically connected to the first node P1, the second node P2, the gate driving signal output terminal O1, the output voltage terminal V0 and the second clock signal output terminal K2, and is used to adjust the potential of the first node P1. Under the control, the output voltage signal is controlled to be written into the gate drive signal output terminal O1, and under the control of the potential of the second node P2, the second clock signal is written into the gate drive signal output terminal O1; so The output voltage terminal V0 is used to provide the output voltage signal;
  • the second node control circuit includes a third input node control sub-circuit 32, a second input node control sub-circuit 33 and a second node control sub-circuit 34;
  • the third input node control sub-circuit 32 is electrically connected to the first clock signal terminal K1, the second voltage terminal V2, the first input node P11 and the third input node P13 respectively, and is used for, under the control of the first clock signal,
  • the second voltage signal is written into the third input node P13, and is used to write the first clock signal into the third input node P13 under the control of the potential of the first input node P11;
  • the first clock signal The terminal K1 is used to provide the first clock signal;
  • the second input node control sub-circuit 33 is respectively electrically connected to the third input node P13, the second input node P12 and the input clock signal terminal KI, and is used to control the potential of the third input node P13 to
  • the input clock signal is written into the second input node P12, and is used to control the potential of the second input node P12 according to the potential of the third input node P13; the input clock signal terminal KI is used to provide the input clock signal;
  • the second node control sub-circuit 34 is electrically connected to the input clock signal terminal KI, the second input node P12, the second node P2, the first input node P11 and the second clock signal terminal K2, respectively, and is used for the input clock signal. Under the control, the connection between the second input node P12 and the second node P2 is turned on or off, and is used to write the second clock signal under the control of the potential of the first input node P11 The second node P2.
  • the output voltage signal may be a low voltage signal, but is not limited thereto.
  • the gate driving unit may further include a first tank circuit 31 , a gate a drive signal output terminal O1, an output circuit 30 and a second node control circuit;
  • the first energy storage circuit 31 is electrically connected to the second node P2 and the gate driving signal output terminal O1 respectively, and is used for controlling the second node according to the gate driving signal output by the gate driving signal output terminal O1 The potential of P2;
  • the output circuit 30 is respectively electrically connected to the first node P1, the second node P2, the gate driving signal output terminal O1, the output voltage terminal V0 and the second clock signal output terminal K2, and is used to adjust the potential of the first node P1. Under the control, the output voltage signal is controlled to be written into the gate drive signal output terminal O1, and under the control of the potential of the second node P2, the second clock signal is written into the gate drive signal output terminal O1; so The output voltage terminal V0 is used to provide the output voltage signal;
  • the second node control circuit includes a third input node control sub-circuit 32, a second input node control sub-circuit 33 and a second node control sub-circuit 34;
  • the third input node control sub-circuit 32 is electrically connected to the first clock signal terminal K1, the second voltage terminal V2, the first input node P11 and the third input node P13 respectively, and is used for, under the control of the first clock signal,
  • the second voltage signal is written into the third input node P13, and is used to write the first clock signal into the third input node P13 under the control of the potential of the first input node P11;
  • the first clock signal The terminal K1 is used to provide the first clock signal;
  • the second input node control sub-circuit 33 is respectively electrically connected to the third input node P13, the second input node P12 and the input clock signal terminal KI, and is used to control the potential of the third input node P13 to
  • the input clock signal is written into the second input node P12, and is used to control the potential of the second input node P12 according to the potential of the third input node P13; the input clock signal terminal KI is used to provide the input clock signal;
  • the second node control subcircuit 34 is respectively electrically connected to the input clock signal terminal KI, the second input node P12, the second node P2, the first input node P11, the second clock signal terminal K2 and the second node P2, for Under the control of the input clock signal, the connection between the second input node P12 and the second node P2 is turned on or off, and is used to turn on or off the connection between the second input node P12 and the second node P2 under the control of the potential of the first input node P11 Two clock signals are written into the second node P2.
  • the difference between at least one embodiment of the gate driving unit shown in FIG. 7 and at least one embodiment of the gate driving unit shown in FIG. 6 is that the first tank circuit 31 and the gate driving signal output end O1 is electrically connected to control the potential of the second node P2 according to the gate driving signal output from the gate driving signal output terminal O1.
  • the gate driving unit described in at least one embodiment of the present disclosure may further include a first tank circuit 31 , a gate a drive signal output terminal O1, an output circuit 30 and a second node control circuit;
  • the first energy storage circuit 31 is electrically connected to the second node P2 and the second clock signal terminal K2 respectively, and is used for controlling the potential of the second node P2 according to the second clock signal; the second clock signal terminal K2 is used for for providing the second clock signal;
  • the output circuit 30 is respectively electrically connected to the first node P1, the second node P2, the gate driving signal output terminal O1, the output voltage terminal V0 and the second clock signal output terminal K2, and is used to adjust the potential of the first node P1. Under the control, the output voltage signal is controlled to be written into the gate drive signal output terminal O1, and under the control of the potential of the second node P2, the second clock signal is written into the gate drive signal output terminal O1; so The output voltage terminal V0 is used to provide the output voltage signal;
  • the second node control circuit includes a third input node control sub-circuit 32, a second input node control sub-circuit 33 and a second node control sub-circuit 34;
  • the third input node control sub-circuit 32 is electrically connected to the first clock signal terminal K1, the second voltage terminal V2, the first input node P11 and the third input node P13 respectively, and is used for, under the control of the first clock signal,
  • the second voltage signal is written into the third input node P13, and is used to write the first clock signal into the third input node P13 under the control of the potential of the first input node P11;
  • the first clock signal The terminal K1 is used to provide the first clock signal;
  • the second input node control sub-circuit 33 is respectively electrically connected to the third input node P13, the second input node P12 and the input clock signal terminal KI, and is used to control the potential of the third input node P13 to
  • the input clock signal is written into the second input node P12, and is used to control the potential of the second input node P12 according to the potential of the third input node P13; the input clock signal terminal KI is used to provide the input clock signal;
  • the second node control sub-circuit 34 is respectively electrically connected to the input clock signal terminal KI, the second input node P12, the second node P2, the first input node P11, the third voltage terminal V3 and the second node P2, and is used for Under the control of the input clock signal, the connection between the second input node P12 and the second node P2 is turned on or off, and is used to connect the third input node P11 under the control of the potential of the first input node P11.
  • the voltage signal is written into the second node P2; the third voltage terminal V3 is used to provide the third voltage signal.
  • the difference between at least one embodiment of the gate driving unit shown in FIG. 8 and at least one embodiment of the gate driving unit shown in FIG. 6 is that the second node control sub-circuit 34 is electrically connected to the third voltage terminal V3 , for writing the third voltage signal into the second node P2 under the control of the potential of the first input node P11 .
  • the gate driving unit may further include a first tank circuit 31 , a gate a drive signal output terminal O1, an output circuit 30 and a second node control circuit;
  • the first energy storage circuit 31 is electrically connected to the second node P2 and the gate driving signal output terminal O1 respectively, and is used for controlling the second node according to the gate driving signal output by the gate driving signal output terminal O1 The potential of P2;
  • the output circuit 30 is respectively electrically connected to the first node P1, the second node P2, the gate driving signal output terminal O1, the output voltage terminal V0 and the second clock signal output terminal K2, and is used to adjust the potential of the first node P1. Under the control, the output voltage signal is controlled to be written into the gate drive signal output terminal O1, and under the control of the potential of the second node P2, the second clock signal is written into the gate drive signal output terminal O1; so The output voltage terminal V0 is used to provide the output voltage signal;
  • the second node control circuit includes a third input node control sub-circuit 32, a second input node control sub-circuit 33 and a second node control sub-circuit 34;
  • the third input node control sub-circuit 32 is electrically connected to the first clock signal terminal K1, the second voltage terminal V2, the first input node P11 and the third input node P13 respectively, and is used for, under the control of the first clock signal,
  • the second voltage signal is written into the third input node P13, and is used to write the first clock signal into the third input node P13 under the control of the potential of the first input node P11;
  • the first clock signal The terminal K1 is used to provide the first clock signal;
  • the second input node control sub-circuit 33 is respectively electrically connected to the third input node P13, the second input node P12 and the input clock signal terminal KI, and is used to control the potential of the third input node P13 to
  • the input clock signal is written into the second input node P12, and is used to control the potential of the second input node P12 according to the potential of the third input node P13; the input clock signal terminal KI is used to provide the input clock signal;
  • the second node control sub-circuit 34 is respectively electrically connected to the input clock signal terminal KI, the second input node P12, the second node P2, the first input node P11, the third voltage terminal V3 and the second node P2, and is used for Under the control of the input clock signal, the connection between the second input node P12 and the second node P2 is turned on or off, and is used to connect the third input node P11 under the control of the potential of the first input node P11. The voltage signal is written into the second node P2.
  • the difference between at least one embodiment of the gate driving unit shown in FIG. 9 and at least one embodiment of the gate driving unit shown in FIG. 7 is that the second node control sub-circuit 34 is electrically connected to the third voltage terminal V3 , for writing the third voltage signal into the second node P2 under the control of the potential of the first input node P11 .
  • the gate driving unit described in at least one embodiment of the present disclosure may further include a first tank circuit 31 , a gate a drive signal output terminal O1, an output circuit 30 and a second node control circuit;
  • the first input node control circuit may include a first isolation node control sub-circuit 41 and a first isolation sub-circuit 42;
  • the first isolation node control sub-circuit 41 is electrically connected to the clock signal terminal K0, the input terminal I1 and the first isolation node P31 respectively, and is used to turn on or off under the control of the clock signal provided by the clock signal terminal K0. Open the connection between the input terminal I1 and the first isolation node P31;
  • the first isolation sub-circuit 42 is electrically connected to the second voltage terminal V2, the first isolation node P31 and the first input node P11, respectively, for controlling the second voltage signal provided at the second voltage terminal V2 Next, control the communication between the first isolation node P31 and the first input node P11;
  • the first energy storage circuit 31 is electrically connected to the second node P2 and the second clock signal terminal K2 respectively, and is used for controlling the potential of the second node P2 according to the second clock signal; the second clock signal terminal K2 is used for for providing the second clock signal;
  • the output circuit 30 is respectively electrically connected to the first node P1, the second node P2, the gate driving signal output terminal O1, the output voltage terminal V0 and the second clock signal output terminal K2, and is used to adjust the potential of the first node P1. Under the control, the output voltage signal is controlled to be written into the gate drive signal output terminal O1, and under the control of the potential of the second node P2, the second clock signal is written into the gate drive signal output terminal O1; so The output voltage terminal V0 is used to provide the output voltage signal;
  • the second node control circuit includes a third input node control sub-circuit 32, a second input node control sub-circuit 33 and a second node control sub-circuit 34;
  • the third input node control sub-circuit 32 is respectively electrically connected to the first clock signal terminal K1, the second voltage terminal V2, the first isolation node P31 and the third input node P13, and is used for, under the control of the first clock signal,
  • the second voltage signal is written into the third input node P13, and is used to write the first clock signal into the third input node P13 under the control of the potential of the first isolation node P31;
  • the first clock signal The terminal K1 is used to provide the first clock signal;
  • the second input node control sub-circuit 33 is respectively electrically connected to the third input node P13, the second input node P12 and the input clock signal terminal KI, and is used to control the potential of the third input node P13 to
  • the input clock signal is written into the second input node P12, and is used to control the potential of the second input node P12 according to the potential of the third input node P13; the input clock signal terminal KI is used to provide the input clock signal;
  • the second node control sub-circuit 34 is electrically connected to the input clock signal terminal KI, the second input node P12, the second node P2, the first input node P11 and the second clock signal terminal K2, respectively, and is used for the input clock signal. Under the control, the connection between the second input node P12 and the second node P2 is turned on or off, and is used to write the second clock signal under the control of the potential of the first input node P11 The second node P2.
  • the first input node control circuit includes a first The isolation node control sub-circuit 41 and the first isolation sub-circuit 42
  • the third input node control sub-circuit 32 is electrically connected to the first isolation node P31 instead of the first input node.
  • the gate driving unit may further include a first tank circuit 31 , a gate a drive signal output terminal O1, an output circuit 30 and a second node control circuit;
  • the first input node control circuit may include a first isolation node control sub-circuit 41 and a first isolation sub-circuit 42;
  • the first isolation node control sub-circuit 41 is electrically connected to the clock signal terminal K0, the input terminal I1 and the first isolation node P31 respectively, and is used to turn on or off under the control of the clock signal provided by the clock signal terminal K0. Open the connection between the input terminal I1 and the first isolation node P31;
  • the first isolation sub-circuit 42 is electrically connected to the second voltage terminal V2, the first isolation node P31 and the first input node P11 respectively, and is used for controlling the second voltage signal provided at the second voltage terminal V2 Next, control the communication between the first isolation node P31 and the first input node P11;
  • the first energy storage circuit 31 is electrically connected to the second node P2 and the gate driving signal output terminal O1 respectively, and is used for controlling the second node according to the gate driving signal output by the gate driving signal output terminal O1 The potential of P2;
  • the output circuit 30 is respectively electrically connected to the first node P1, the second node P2, the gate driving signal output terminal O1, the output voltage terminal V0 and the second clock signal output terminal K2, and is used to adjust the potential of the first node P1. Under the control, the output voltage signal is controlled to be written into the gate drive signal output terminal O1, and under the control of the potential of the second node P2, the second clock signal is written into the gate drive signal output terminal O1; so The output voltage terminal V0 is used to provide the output voltage signal;
  • the second node control circuit includes a third input node control sub-circuit 32, a second input node control sub-circuit 33 and a second node control sub-circuit 34;
  • the third input node control sub-circuit 32 is respectively electrically connected to the first clock signal terminal K1, the second voltage terminal V2, the first isolation node P31 and the third input node P13, and is used for, under the control of the first clock signal,
  • the second voltage signal is written into the third input node P13, and is used to write the first clock signal into the third input node P13 under the control of the potential of the first isolation node P31;
  • the first clock signal The terminal K1 is used to provide the first clock signal;
  • the second input node control sub-circuit 33 is respectively electrically connected to the third input node P13, the second input node P12 and the input clock signal terminal KI, and is used to control the potential of the third input node P13 to
  • the input clock signal is written into the second input node P12, and is used to control the potential of the second input node P12 according to the potential of the third input node P13; the input clock signal terminal KI is used to provide the input clock signal;
  • the second node control subcircuit 34 is respectively electrically connected to the input clock signal terminal KI, the second input node P12, the second node P2, the first input node P11, the second clock signal terminal K2 and the second node P2, for Under the control of the input clock signal, the connection between the second input node P12 and the second node P2 is turned on or off, and is used to turn on or off the connection between the second input node P12 and the second node P2 under the control of the potential of the first input node P11 Two clock signals are written into the second node P2.
  • the first input node control circuit includes a first The isolation node control sub-circuit 41 and the first isolation sub-circuit 42, the third input node control sub-circuit 32 is electrically connected to the first isolation node P31 instead of the first input node.
  • the gate driving unit may further include a first tank circuit 31 , a gate a drive signal output terminal O1, an output circuit 30 and a second node control circuit;
  • the first input node control circuit may include a first isolation node control sub-circuit 41 and a first isolation sub-circuit 42;
  • the first isolation node control sub-circuit 41 is electrically connected to the clock signal terminal K0, the input terminal I1 and the first isolation node P31 respectively, and is used to turn on or off under the control of the clock signal provided by the clock signal terminal K0. Open the connection between the input terminal I1 and the first isolation node P31;
  • the first isolation sub-circuit 42 is electrically connected to the second voltage terminal V2, the first isolation node P31 and the first input node P11 respectively, and is used for controlling the second voltage signal provided at the second voltage terminal V2 Next, control the communication between the first isolation node P31 and the first input node P11;
  • the first energy storage circuit 31 is electrically connected to the second node P2 and the second clock signal terminal K2 respectively, and is used for controlling the potential of the second node P2 according to the second clock signal; the second clock signal terminal K2 is used for for providing the second clock signal;
  • the output circuit 30 is respectively electrically connected to the first node P1, the second node P2, the gate driving signal output terminal O1, the output voltage terminal V0 and the second clock signal output terminal K2, and is used to adjust the potential of the first node P1. Under the control, the output voltage signal is controlled to be written into the gate drive signal output terminal O1, and under the control of the potential of the second node P2, the second clock signal is written into the gate drive signal output terminal O1; so The output voltage terminal V0 is used to provide the output voltage signal;
  • the second node control circuit includes a third input node control sub-circuit 32, a second input node control sub-circuit 33 and a second node control sub-circuit 34;
  • the third input node control sub-circuit 32 is respectively electrically connected to the first clock signal terminal K1, the second voltage terminal V2, the first isolation node P31 and the third input node P13, and is used for, under the control of the first clock signal,
  • the second voltage signal is written into the third input node P13, and is used to write the first clock signal into the third input node P13 under the control of the potential of the first isolation node P31;
  • the first clock signal The terminal K1 is used to provide the first clock signal;
  • the second input node control sub-circuit 33 is respectively electrically connected to the third input node P13, the second input node P12 and the input clock signal terminal KI, and is used to control the potential of the third input node P13 to
  • the input clock signal is written into the second input node P12, and is used to control the potential of the second input node P12 according to the potential of the third input node P13; the input clock signal terminal KI is used to provide the input clock signal;
  • the second node control sub-circuit 34 is respectively electrically connected to the input clock signal terminal KI, the second input node P12, the second node P2, the first input node P11, the third voltage terminal V3 and the second node P2, and is used for Under the control of the input clock signal, the connection between the second input node P12 and the second node P2 is turned on or off, and is used to connect the third input node P11 under the control of the potential of the first input node P11.
  • the voltage signal is written into the second node P2; the third voltage terminal V3 is used for providing the third voltage signal.
  • the first input node control circuit includes a first The isolation node control sub-circuit 41 and the first isolation sub-circuit 42
  • the third input node control sub-circuit 32 is electrically connected to the first isolation node P31 instead of the first input node.
  • the gate driving unit may further include a first tank circuit 31 , a gate a drive signal output terminal O1, an output circuit 30 and a second node control circuit;
  • the first input node control circuit may include a first isolation node control sub-circuit 41 and a first isolation sub-circuit 42;
  • the first isolation node control sub-circuit 41 is electrically connected to the clock signal terminal K0, the input terminal I1 and the first isolation node P31 respectively, and is used to turn on or off under the control of the clock signal provided by the clock signal terminal K0. Open the connection between the input terminal I1 and the first isolation node P31;
  • the first isolation sub-circuit 42 is electrically connected to the second voltage terminal V2, the first isolation node P31 and the first input node P11 respectively, and is used for controlling the second voltage signal provided at the second voltage terminal V2 Next, control the communication between the first isolation node P31 and the first input node P11;
  • the first energy storage circuit 31 is electrically connected to the second node P2 and the gate driving signal output terminal O1 respectively, and is used for controlling the second node according to the gate driving signal output by the gate driving signal output terminal O1 The potential of P2;
  • the output circuit 30 is respectively electrically connected to the first node P1, the second node P2, the gate driving signal output terminal O1, the output voltage terminal V0 and the second clock signal output terminal K2, and is used to adjust the potential of the first node P1. Under the control, the output voltage signal is controlled to be written into the gate drive signal output terminal O1, and under the control of the potential of the second node P2, the second clock signal is written into the gate drive signal output terminal O1; so The output voltage terminal V0 is used to provide the output voltage signal;
  • the second node control circuit includes a third input node control sub-circuit 32, a second input node control sub-circuit 33 and a second node control sub-circuit 34;
  • the third input node control sub-circuit 32 is electrically connected to the first clock signal terminal K1, the second voltage terminal V2, the first input node P11 and the third input node P13 respectively, and is used for, under the control of the first clock signal,
  • the second voltage signal is written into the third input node P13, and is used to write the first clock signal into the third input node P13 under the control of the potential of the first input node P11;
  • the first clock signal The terminal K1 is used to provide the first clock signal;
  • the second input node control sub-circuit 33 is respectively electrically connected to the third input node P13, the second input node P12 and the input clock signal terminal KI, and is used to control the potential of the third input node P13 to
  • the input clock signal is written into the second input node P12, and is used to control the potential of the second input node P12 according to the potential of the third input node P13; the input clock signal terminal KI is used to provide the input clock signal;
  • the second node control sub-circuit 34 is respectively electrically connected to the input clock signal terminal KI, the second input node P12, the second node P2, the first isolation node P31, the third voltage terminal V3 and the second node P2, and is used for Under the control of the input clock signal, the connection between the second input node P12 and the second node P2 is turned on or off, and is used to connect the third input node P31 under the control of the potential of the first isolation node P31.
  • the voltage signal is written into the second node P2.
  • the first input node control circuit includes a first The isolation node control sub-circuit 41 and the first isolation sub-circuit 42
  • the third input node control sub-circuit 32 is electrically connected to the first isolation node P31 instead of the first input node.
  • the first input node control circuit 10 includes a first control transistor T12 and a second control transistor T1, wherein,
  • the gate of the first control transistor T12 is electrically connected to the second clock signal terminal K2, and the source of the first control transistor T12 is electrically connected to the input terminal;
  • the gate of the second control transistor T1 is electrically connected to the first clock signal terminal K1, the source of the second control transistor T1 is electrically connected to the drain of the first control transistor T12, and the second control transistor T1 is electrically connected to the drain of the first control transistor T12. the drain of the control transistor T1 is electrically connected to the first input node P11;
  • the input energy storage sub-circuit 21 includes an input capacitor C4, the on-off control sub-circuit 22 includes an on-off control transistor T5, and the first energy storage sub-circuit 23 includes a first storage capacitor C3;
  • the input clock signal terminal KI is electrically connected, and the second terminal of C4 is electrically connected to the first input node P11;
  • the gate of T5 and the source of T5 are both electrically connected to the first input node P11, and the drain of T5 is electrically connected to the first node P1;
  • the first terminal of C3 is electrically connected to the first node P1, and the second terminal of C3 is electrically connected to the low voltage terminal; the low voltage terminal is used to provide the low voltage VSS;
  • the first node control circuit 12 includes a first node control transistor T11;
  • the gate of T11 is electrically connected to the second input node P12, the source of T11 is electrically connected to the high voltage terminal, and the drain of T11 is electrically connected to the first node P1; the high voltage terminal is used to provide a high voltage VDD;
  • the first energy storage circuit 31 includes a second storage capacitor C2;
  • the first end of C2 is electrically connected to the second node P2, and the second end of C2 is electrically connected to the second clock signal output end K2;
  • the output circuit 30 includes a first output transistor T10 and a second output transistor T9;
  • the gate of the first output transistor T10 is electrically connected to the first node P1, the source of the first output transistor T10 is electrically connected to the low voltage terminal, and the drain of the first output transistor T10 is electrically connected to the low voltage terminal.
  • the gate drive signal output terminal O1 is electrically connected;
  • the gate of the second output transistor T9 is electrically connected to the second node P2, the source of the second output transistor T9 is electrically connected to the gate driving signal output terminal O1, and the second output transistor T9
  • the second pole of is electrically connected to the second clock signal terminal K2;
  • the third input node control sub-circuit 32 includes a third control transistor T3 and a fourth control transistor T2, wherein,
  • the gate of T3 is electrically connected to the first clock signal terminal K1, the source of T3 is electrically connected to the low voltage terminal, and the drain of T3 is electrically connected to the third input node P13;
  • the gate of T2 is electrically connected to the first input node P11, the source of T2 is electrically connected to the first clock signal terminal K1, and the drain of T2 is electrically connected to the third input node P13;
  • the second input node control sub-circuit 33 includes a fifth control transistor T6 and a first capacitor C1;
  • the gate of T6 is electrically connected to the third input node P13, the source of the eighth control transistor T6 is electrically connected to the second input node P12, and the drain of the eighth control transistor T6 is connected to the input clock signal Terminal KI is electrically connected;
  • the first end of the first capacitor C1 is electrically connected to the third input node P13, and the second end of the first capacitor C1 is electrically connected to the second input node P12;
  • the second node control sub-circuit 34 includes a sixth control transistor T7 and a seventh control transistor T8;
  • the gate of T7 is electrically connected to the input clock signal terminal KI, the source of T7 is electrically connected to the second input node P12, and the drain of T7 is electrically connected to the second node P2;
  • the gate of T8 is electrically connected to the first input node P11, the source of T8 is electrically connected to the second clock signal terminal K2, and the drain of T8 is electrically connected to the second node P2.
  • all transistors are p-type thin film transistors
  • the first voltage signal is a negative voltage signal
  • the second voltage terminal is a low voltage terminal
  • the third voltage terminal is a high voltage terminal
  • the output The voltage terminal is a low voltage terminal, but not limited thereto.
  • the ratio of the capacitance value of C4 to the capacitance value of C1 may be greater than or equal to 1 and less than or equal to 10, but not limited thereto.
  • the potential of P1 is related to the capacitance value of C3, the capacitance value of C4, the parasitic capacitance of T13, the parasitic capacitance of T4, and the parasitic capacitance of T5, rather than the parasitic capacitance of T5. It is directly related to the ratio of the capacitance value of C4 to the capacitance value of C3.
  • K1 provides low voltage
  • KI provides high voltage
  • K2 provides low voltage
  • I1 provides high voltage
  • T12 and T1 are turned on
  • the potential of P11 is high voltage
  • T5 is turned off
  • T2 is turned off
  • T3 is turned on
  • P13 The potential is low voltage
  • T6 is open
  • the potential of P12 is high voltage
  • T7 is closed
  • T8 is closed
  • T11 is closed
  • the potential of P1 is maintained at a low voltage
  • the potential of P2 is maintained at a high voltage
  • T10 is open
  • T9 is closed
  • O1 outputs a low voltage
  • K1 provides a high voltage
  • KI provides a low voltage
  • K2 provides a high voltage
  • I1 provides a low voltage
  • both T12 and T1 are turned off
  • the potential of P11 is maintained at a high voltage
  • T5 is turned off
  • the potential of P13 is further pulled by C1 Low
  • T6 is open
  • the potential of P12 is low voltage
  • T7 is open
  • T8 is closed
  • T11 is open
  • the potential of P1 is high voltage
  • the potential of P2 is low voltage
  • T9 is open
  • T10 is closed
  • K1 provides a low voltage
  • KI provides a high voltage
  • K2 provides a low voltage
  • I1 provides a low voltage
  • both T12 and T1 are turned on, the potential of P11 is pulled low
  • T5 is turned on
  • the potential of P1 is pulled low
  • T10 is turned on
  • T8 is turned on, and the potential of P2 is pulled down by the second clock signal provided by K2, and T9 is also turned on.
  • K1 provides a high voltage
  • KI provides a low voltage
  • K2 provides a high voltage
  • I1 provides a low voltage
  • both T12 and T1 are turned off
  • KI pulls down the potential of P11 through C4
  • T5 is turned on
  • the potential of P1 is kept lower than VSS+Vth
  • Vth is the threshold voltage of T10, so that T10 is turned on, so that the potential of the gate drive signal output by O1 is maintained at VSS, which is not affected by noise interference
  • T3 is turned off
  • T2 On, the potential of P13 is high voltage
  • T6 is off
  • the potential of P12 is high voltage
  • T7 is on
  • the potential of P2 is high voltage
  • T9 is off
  • K1 supplies a low voltage
  • KI supplies a high voltage
  • K2 supplies a low voltage
  • I1 supplies a low voltage
  • both T12 and T1 are turned on, and the potential of the input clock signal supplied by KI rises, thereby Pull up the potential of P11 and turn off T5, which does not affect the potential of P1, so that the potential of P1 is kept lower than VSS+Vth
  • Vth is the threshold voltage of T10, so that T10 is turned on, and the potential of the gate drive signal output by O1 is maintained.
  • T3 is turned on, the potential of P13 is low voltage, T6 is turned on, the potential of P12 is high voltage, T7 is turned off, T8 is turned off, the potential of P2 is pulled down by the second clock signal, and T9 is turned on ;
  • K1 provides a high voltage
  • KI provides a low voltage
  • K2 provides a high voltage
  • I1 provides a low voltage
  • both T12 and T1 are turned off
  • KI pulls down the potential of P11 through C4
  • T5 is turned on
  • the potential of P1 is kept lower than VSS+Vth
  • Vth is the threshold voltage of T10, so that T10 is turned on, so that the potential of the gate drive signal output by O1 is maintained at VSS, which is not affected by noise interference
  • T3 is turned off
  • T2 On, the potential of P13 is high voltage
  • T6 is off
  • the potential of P12 is high voltage
  • T7 is on
  • T8 is on
  • the potential of P2 is high voltage
  • T9 is off
  • the potential of P1 can be maintained below VSS+Vth, Vth is the threshold voltage of T10, so that T10 is turned on, and the potential of the gate drive signal output by O1 is maintained at VSS, which is not affected by noise interference.
  • C4, T5 and C3 form a charge pump structure, and the charge pump is a structure similar to a water pump in the circuit, mainly through a capacitor, a clock signal and a diode rectification structure (
  • T5 adopts a diode connection mode) to realize the redistribution of electric charge and realize the purpose of boosting (or decreasing).
  • the potential of the input signal provided by I1 is a low voltage
  • T1 and T12 are used to initialize the potential of P11 so that the potential of P11 is VSS
  • C4 is used for
  • the potential of P11 is further pulled down, the low voltage is saved to P1 through T5, and the charge is stored through C3 to maintain the potential;
  • the fourth clock signal labeled as K4 is provided by the fourth clock signal terminal.
  • the charge pump circuit further includes a switch control sub-circuit 20;
  • the switch control sub-circuit 20 includes a switch control transistor T4;
  • the gate of T4 is electrically connected to the first input node P11, the source of T4 is electrically connected to the input clock signal terminal KI, and the drain of T4 is electrically connected to the first control node P21;
  • the first control node P21 is electrically connected to the first end of C4.
  • T4 is a p-type thin film transistor, but not limited thereto.
  • K1 provides a low voltage
  • KI provides a high voltage
  • K2 provides a low voltage
  • I1 provides a high voltage
  • T12 and T1 are turned on
  • the potential of P11 is a high voltage
  • both T5 and T4 are turned off
  • T2 is turned off
  • T3 is turned on.
  • the potential of P13 is low voltage
  • T6 is open
  • the potential of P12 is high voltage
  • T7 is closed
  • T8 is closed
  • T11 is closed
  • the potential of P1 is maintained at low voltage
  • the potential of P2 is maintained at high voltage
  • T10 is open
  • T9 is closed
  • K1 provides a high voltage
  • KI provides a low voltage
  • K2 provides a high voltage
  • I1 provides a low voltage
  • both T12 and T1 are turned off
  • the potential of P11 is maintained at a high voltage
  • T4 is turned off
  • T5 is turned off
  • the potential of P13 is turned off.
  • C1 is further pulled down, T6 is turned on, the potential of P12 is low voltage, T7 is turned on, T8 is turned off, T11 is turned on, the potential of P1 is high voltage, the potential of P2 is low voltage, T9 is turned on, T10 is turned off, and O1 outputs a high voltage;
  • K1 provides a low voltage
  • KI provides a high voltage
  • K2 provides a low voltage
  • I1 provides a low voltage
  • both T12 and T1 are turned on, the potential of P11 is pulled low
  • T5 is turned on
  • the potential of P1 is pulled low
  • T10 is turned on
  • T8 is turned on, and the potential of P2 is pulled down by the second clock signal provided by K2, and T9 is also turned on.
  • T9 and T10 the output terminal of the gate driving signal is discharged at the same time, which can improve the discharge speed of the output terminal of the gate driving signal. , so as to achieve a complete and fast reset of the gate drive signal;
  • K1 provides a high voltage
  • KI provides a low voltage
  • K2 provides a high voltage
  • I1 provides a low voltage
  • both T12 and T1 are turned off
  • T4 is turned on
  • KI pulls down the potential of P11 through C4
  • T5 is turned on, so that the potential of P1 is maintained below VSS+Vth
  • Vth is the threshold voltage of T10, so that T10 is turned on, so that the potential of the gate drive signal output by O1 is maintained at VSS, which is not affected by noise interference
  • T3 is off off
  • T2 is on
  • the potential of P13 is high voltage
  • T6 is off
  • the potential of P12 is high voltage
  • T7 is on
  • the potential of P2 is high voltage
  • T9 is off
  • K1 supplies a low voltage
  • KI supplies a high voltage
  • K2 supplies a low voltage
  • I1 supplies a low voltage
  • both T12 and T1 are turned on
  • T4 is turned on
  • the potential of the input clock signal provided by KI rises High, so that the potential of P11 is raised, T5 is turned off, and the potential of P1 is not affected, so that the potential of P1 is maintained below VSS+Vth
  • Vth is the threshold voltage of T10, so that T10 is turned on, and then the gate drive signal output by O1
  • the potential of P12 is maintained at VSS, which is not affected by noise interference
  • T3 is turned on, the potential of P13 is low voltage
  • T6 is turned on, the potential of P12 is high voltage
  • T7 is turned off
  • T8 is turned off
  • the potential of P2 is pulled down by the second clock signal
  • T9 opens;
  • K1 provides a high voltage
  • KI provides a low voltage
  • K2 provides a high voltage
  • I1 provides a low voltage
  • both T12 and T1 are turned off
  • T4 is turned on
  • KI pulls down the potential of P11 through C4
  • T5 is turned on, so that the potential of P1 is maintained below VSS+Vth
  • Vth is the threshold voltage of T10, so that T10 is turned on, so that the potential of the gate drive signal output by O1 is maintained at VSS, which is not affected by noise interference
  • T3 is off off
  • T2 is on
  • the potential of P13 is high voltage
  • T6 is off
  • the potential of P12 is high voltage
  • T7 is on
  • T8 is on
  • the potential of P2 is high voltage
  • T9 is off
  • the potential of P1 can be maintained below VSS+Vth, Vth is the threshold voltage of T10, so that T10 is turned on, and the potential of the gate drive signal output by O1 is maintained at VSS, which is not affected by noise interference.
  • T4, C4, T5 and C3 form a charge pump structure
  • the charge pump is a structure similar to a water pump in the circuit, which is mainly rectified by capacitors, clock signals and diodes
  • the structure in Fig. 12, T5 adopts the diode connection mode), realizes the redistribution of the electric charge, and realizes the purpose of boosting (or stepping down).
  • the potential of the input signal provided by I1 is a low voltage
  • T1 and T12 are used to initialize the potential of P11 so that the potential of P11 is VSS
  • C4 is used for
  • the potential of P11 is further pulled down, the low voltage is saved to P1 through T5, and the charge is stored through C3 to maintain the potential;
  • the charge pump circuit further includes a switch control sub-circuit 20; the switch control sub-circuit 20 includes a switch control transistor T4;
  • the first isolated node control sub-circuit 41 includes a first control transistor T12 and a second control transistor T1, wherein,
  • the gate of the first control transistor T12 is electrically connected to the second clock signal terminal K2, and the source of the first control transistor T12 is electrically connected to the input terminal;
  • the gate of the second control transistor T1 is electrically connected to the first clock signal terminal K1, the source of the second control transistor T1 is electrically connected to the drain of the first control transistor T12, and the second control transistor T1 is electrically connected to the drain of the first control transistor T12. the drain of the control transistor T1 is electrically connected to the first isolation node P31;
  • the first isolation sub-circuit 42 includes a first isolation transistor T13;
  • the gate of T13 is electrically connected to the low voltage terminal, the source of T13 is electrically connected to the first isolation node P31, and the drain of T13 is electrically connected to the first input node P11; the low voltage terminal is used to provide the low voltage VSS ;
  • the input energy storage sub-circuit 21 includes an input capacitor C4, the on-off control sub-circuit 22 includes an on-off control transistor T5, and the first energy storage sub-circuit 23 includes a first storage capacitor C3;
  • the gate of T4 is electrically connected to the first input node P11, the source of T4 is electrically connected to the input clock signal terminal KI, and the drain of T4 is electrically connected to the first control node P21;
  • the first control node P21 is electrically connected to the first end of C4, the second end of C4 is electrically connected to the first input node P11; the gate of T5 and the source of T5 are both connected to the first input node P11 Electrically connected, the drain of T5 is electrically connected to the first node P1;
  • the first terminal of C3 is electrically connected to the first node P1, and the second terminal of C3 is electrically connected to the low voltage terminal; the low voltage terminal is used to provide the low voltage VSS;
  • the first node control circuit 12 includes a first node control transistor T11;
  • the gate of T11 is electrically connected to the second input node P12, the source of T11 is electrically connected to the high voltage terminal, and the drain of T11 is electrically connected to the first node P1; the high voltage terminal is used to provide a high voltage VDD;
  • the first energy storage circuit 31 includes a second storage capacitor C2;
  • the first end of C2 is electrically connected to the second node P2, and the second end of C2 is electrically connected to the second clock signal output end K2;
  • the output circuit 30 includes a first output transistor T10 and a second output transistor T9;
  • the gate of the first output transistor T10 is electrically connected to the first node P1, the source of the first output transistor T10 is electrically connected to the low voltage terminal, and the drain of the first output transistor T10 is electrically connected to the low voltage terminal.
  • the gate drive signal output terminal O1 is electrically connected;
  • the gate of the second output transistor T9 is electrically connected to the second node P2, the source of the second output transistor T9 is electrically connected to the gate driving signal output terminal O1, and the second output transistor T9
  • the second pole of is electrically connected to the second clock signal terminal K2;
  • the third input node control subcircuit includes a third isolation node control subcircuit 321 and a second isolation subcircuit 40; the third isolation node control subcircuit 321 includes a third control transistor T3 and a fourth control transistor T2;
  • the second isolation sub-circuit 40 includes a second isolation transistor T14, wherein,
  • the gate of T3 is electrically connected to the first clock signal terminal K1, the source of T3 is electrically connected to the low voltage terminal, and the drain of T3 is electrically connected to the second isolation node P32;
  • the gate of T2 is electrically connected to the first isolation node P31, the source of T2 is electrically connected to the first clock signal terminal K1, and the drain of T2 is electrically connected to the second isolation node P32;
  • the gate of T14 is electrically connected to the low voltage terminal, the source of T14 is electrically connected to the second isolation node P32, and the drain of T14 is electrically connected to the third input node P13;
  • the second input node control sub-circuit 33 includes a fifth control transistor T6 and a first capacitor C1;
  • the gate of T6 is electrically connected to the third input node P13, the source of the eighth control transistor T6 is electrically connected to the second input node P12, and the drain of the eighth control transistor T6 is connected to the input clock signal Terminal KI is electrically connected;
  • the first end of the first capacitor C1 is electrically connected to the third input node P13, and the second end of the first capacitor C1 is electrically connected to the second input node P12;
  • the second node control sub-circuit 34 includes a sixth control transistor T7 and a seventh control transistor T8;
  • the gate of T7 is electrically connected to the input clock signal terminal KI, the source of T7 is electrically connected to the second input node P12, and the drain of T7 is electrically connected to the second node P2;
  • the gate of T8 is electrically connected to the first isolation node P31, the source of T8 is electrically connected to the second clock signal terminal K2, and the drain of T8 is electrically connected to the second node P2.
  • the ratio of the capacitance value of C4 to the capacitance value of C1 may be greater than or equal to 1 and less than or equal to 10, but not limited thereto.
  • all transistors are p-type thin film transistors
  • the first voltage signal is a negative voltage signal
  • the second voltage terminal is a low voltage terminal
  • the third voltage terminal is a high voltage terminal
  • the output The voltage terminal is a low voltage terminal, but not limited thereto.
  • T7 can prevent the leakage of electricity to the third input node P13, and isolate the influence of C1 on the second node P2, and enhance the second clock signal provided by the second clock signal terminal K2.
  • the coupling effect of the two nodes P2 makes the potential of the second node P2 lower when the potential of the second clock signal decreases, thereby accelerating the discharge speed of the second output transistor T9 to the gate driving signal output terminal O1.
  • the difference between at least one embodiment of the gate driving unit shown in FIG. 17 and at least one embodiment of the gate driving unit shown in FIG. 14 is that a first isolation transistor T13 and a second isolation transistor T14 are added;
  • T13 can reduce the leakage of P11, and T14 can reduce the leakage of P13, so that the response speed of the gate drive signal output is faster.
  • K1 provides low voltage
  • KI provides high voltage
  • K2 provides low voltage
  • I1 provides high voltage
  • T12 and T1 are turned on
  • T13 is turned on
  • P11 is at high voltage
  • P31 is at high voltage
  • T5 and T4 All are turned off
  • T2 is turned off
  • T3 is turned on
  • T14 is turned on
  • the potential of P32 is low voltage
  • the potential of P13 is low voltage
  • T6 is on
  • the potential of P12 is high voltage
  • T7 is off
  • T8 is off
  • T11 is off
  • the potential of P1 Maintain a low voltage
  • the potential of P2 is maintained at a high voltage
  • T10 is turned on
  • T9 is turned off
  • O1 outputs a low voltage
  • K1 provides high voltage
  • KI provides low voltage
  • K2 provides high voltage
  • I1 provides low voltage
  • both T12 and T1 are turned off
  • the potential of P11 is maintained at high voltage
  • T13 is turned on
  • the potential of P31 is high voltage
  • T4 is turned off
  • T5 is turned off
  • the potential of P32 is maintained at a low voltage
  • T14 is turned from on to off
  • the potential of P13 is further pulled down by C1
  • T6 is turned on
  • the potential of P12 is low voltage
  • T7 is turned on
  • T8 is turned off
  • T11 is turned on
  • P1 The potential of P2 is a high voltage
  • the potential of P2 is a low voltage
  • T9 is turned on
  • T10 is turned off
  • O1 outputs a high voltage
  • K1 provides a low voltage
  • KI provides a high voltage
  • K2 provides a low voltage
  • I1 provides a low voltage
  • both T12 and T1 are turned on, the potential of P11 is pulled low
  • T13 is turned on
  • the potential of P31 is pulled low
  • T5 is turned on
  • the potential of P1 is pulled down
  • T10 is turned on
  • T3 is turned on
  • the potential of P32 is low voltage
  • T14 is turned on, the potential of P13 and P12 are pulled up
  • T7 is turned off
  • T8 is turned on, and the potential of P2 is turned off.
  • the second clock signal provided by K2 is pulled low
  • T9 is also turned on.
  • K1 provides a high voltage
  • KI provides a low voltage
  • K2 provides a high voltage
  • I1 provides a low voltage
  • both T12 and T1 are closed
  • the potential of P11 is maintained at a low voltage
  • T13 changes from open to
  • T4 is turned on
  • KI pulls down the potential of P31 through C4
  • T5 is turned on, so that the potential of P1 is maintained below VSS+Vth
  • Vth is the threshold voltage of T10, so that T10 is turned on, which in turn makes the gate drive of O1 output.
  • T3 is turned off, T2 is turned on, P32 is at high voltage, T14 is turned on, P13 is at high voltage, P12 is at high voltage, T7 is turned on, T8 is turned on, The potential of P2 is a high voltage, and T9 is turned off;
  • K1 provides a low voltage
  • KI provides a high voltage
  • K2 provides a low voltage
  • I1 provides a low voltage
  • both T12 and T1 are turned on
  • the potential of P11 is a low voltage
  • T13 is turned on
  • T4 is turned on by Turns on and turns off
  • the potential of the input clock signal provided by KI increases, thereby pulling up the potential of P31
  • T5 is turned off, which does not affect the potential of P1, so that the potential of P1 remains lower than VSS+Vth
  • Vth is the threshold voltage of T10 , so that T10 is turned on, and the potential of the gate drive signal output by O1 is maintained at VSS, which is not affected by noise interference
  • T3 is turned on, the potential of P32 is low voltage
  • T2 is turned off
  • T14 is turned on
  • the potential of P13 low voltage
  • T6 is turned on
  • the potential of P12 is a high voltage
  • T7 is turned off
  • T8 is turned off
  • K1 provides a high voltage
  • KI provides a low voltage
  • K2 provides a high voltage
  • I1 provides a low voltage
  • both T12 and T1 are turned off
  • the potential of P11 is maintained at a low voltage
  • T4 is turned on
  • KI The potential of P31 is pulled down by C4, and T5 is turned on, so that the potential of P1 is kept lower than VSS+Vth
  • Vth is the threshold voltage of T10, so that T10 is turned on, so that the potential of the gate drive signal output by O1 is maintained at VSS, Not affected by noise interference
  • T3 is turned off
  • T2 is turned on
  • the potential of P32 is high voltage
  • T14 is turned on
  • the potential of P13 is high voltage
  • T6 is turned off
  • the potential of P12 is high voltage
  • T7 is turned on
  • T8 is turned on
  • the potential of P2 is High voltage
  • T9 is turned off
  • T13 changes from on to off
  • the potential of P1 can be maintained below VSS+Vth, Vth is the threshold voltage of T10, so that T10 is turned on, and the potential of the gate drive signal output by O1 is maintained at VSS, which is not affected by noise interference.
  • T4, C4, T5 and C3 form a charge pump structure
  • the charge pump is a structure similar to a water pump in the circuit, mainly rectified by capacitors, clock signals and diodes
  • the structure in Fig. 17, T5 adopts the diode connection mode), realizes the redistribution of electric charge, and realizes the purpose of boosting (or stepping down).
  • the difference between the at least one embodiment of the gate driving unit described in the present disclosure and the at least one embodiment of the gate driving unit shown in FIG. 17 of the present disclosure is:
  • the first terminal of C2 is electrically connected to the second node P2, and the second terminal of C2 is electrically connected to the gate driving signal output terminal O1.
  • the first voltage signal is a negative voltage signal
  • the second voltage terminal is a low voltage terminal
  • the third voltage terminal is a high voltage terminal
  • the output voltage terminal is a low voltage terminal. This is limited.
  • the difference between the fourth specific embodiment of the gate driving unit shown in FIG. 19 and the third specific embodiment of the gate driving unit shown in FIG. 17 of the present disclosure is that the second terminal of C2 and the gate driving signal output terminal
  • the electrical connection of O1 reduces the capacitive load on the second clock signal terminal, which is beneficial to reduce power consumption.
  • FIG. 18 A working timing diagram of at least one embodiment of the gate driving unit shown in FIG. 19 is shown in FIG. 18 .
  • the charge pump circuit further includes a switch a control sub-circuit 20; the switch control sub-circuit 20 includes a switch control transistor T4;
  • the first isolated node control sub-circuit 41 includes a first control transistor T12 and a second control transistor T1, wherein,
  • the gate of the first control transistor T12 is electrically connected to the second clock signal terminal K2, and the source of the first control transistor T12 is electrically connected to the input terminal;
  • the gate of the second control transistor T1 is electrically connected to the first clock signal terminal K1, the source of the second control transistor T1 is electrically connected to the drain of the first control transistor T12, and the second control transistor T1 is electrically connected to the drain of the first control transistor T12. the drain of the control transistor T1 is electrically connected to the first isolation node P31;
  • the first isolation sub-circuit 42 includes a first isolation transistor T13;
  • the electrode of the first isolation transistor T13 is electrically connected to the low voltage terminal, the source of the first isolation transistor T13 is electrically connected to the first isolation node P31, and the drain of the first isolation transistor T13 is electrically connected to the first isolation node P31.
  • the first input node P11 is electrically connected; the low voltage terminal is used to provide the low voltage VSS;
  • the input energy storage sub-circuit 21 includes an input capacitor C4, the on-off control sub-circuit 22 includes an on-off control transistor T5, and the first energy storage sub-circuit 23 includes a first storage capacitor C3;
  • the gate of T4 is electrically connected to the first input node P11, the source of T4 is electrically connected to the input clock signal terminal KI, the drain of T4 is electrically connected to the first terminal of C4; the second terminal of C4 is electrically connected to the first input
  • the node P11 is electrically connected; the first end of C4 is electrically connected to the first control node P21;
  • the gate of T5 and the source of T5 are both electrically connected to the first input node P11, and the drain of T5 is electrically connected to the first node P1;
  • the first terminal of C3 is electrically connected to the first node P1, and the second terminal of C3 is electrically connected to the low voltage terminal; the low voltage terminal is used to provide the low voltage VSS;
  • the first node control circuit 12 includes a first node control transistor T11;
  • the gate of T11 is electrically connected to the second input node P12, the source of T11 is electrically connected to the high voltage terminal, and the drain of T11 is electrically connected to the first node P1; the high voltage terminal is used to provide a high voltage VDD;
  • the first energy storage circuit 31 includes a second storage capacitor C2;
  • the first end of C2 is electrically connected to the second node P2, and the second end of C2 is electrically connected to the second clock signal output end K2;
  • the output circuit 30 includes a first output transistor T10 and a second output transistor T9;
  • the gate of the first output transistor T10 is electrically connected to the first node P1, the source of the first output transistor T10 is electrically connected to the low voltage terminal, and the drain of the first output transistor T10 is electrically connected to the low voltage terminal.
  • the gate drive signal output terminal O1 is electrically connected;
  • the gate of the second output transistor T9 is electrically connected to the second node P2, the source of the second output transistor T9 is electrically connected to the gate driving signal output terminal O1, and the second output transistor T9
  • the second pole of is electrically connected to the second clock signal terminal K2;
  • the third input node control subcircuit includes a third isolation node control subcircuit 321 and a second isolation subcircuit 40; the third isolation node control subcircuit 321 includes a third control transistor T3 and a fourth control transistor T2;
  • the second isolation sub-circuit 40 includes a second isolation transistor T14, wherein,
  • the gate of T3 is electrically connected to the first clock signal terminal K1, the source of T3 is electrically connected to the low voltage terminal, and the drain of T3 is electrically connected to the second isolation node P32;
  • the gate of T2 is electrically connected to the first isolation node P31, the source of T2 is electrically connected to the first clock signal terminal K1, and the drain of T2 is electrically connected to the second isolation node P32;
  • the gate of T14 is electrically connected to the low voltage terminal, the source of T14 is electrically connected to the second isolation node P32, and the drain of T14 is electrically connected to the third input node P13; the low voltage terminal is used to provide low voltage voltage VSS;
  • the second input node control sub-circuit 33 includes a fifth control transistor T6 and a first capacitor C1;
  • the gate of T6 is electrically connected to the third input node P13, the source of the eighth control transistor T6 is electrically connected to the second input node P12, and the drain of the eighth control transistor T6 is connected to the input clock signal Terminal KI is electrically connected;
  • the first end of the first capacitor C1 is electrically connected to the third input node P13, and the second end of the first capacitor C1 is electrically connected to the second input node P12;
  • the second node control sub-circuit 34 includes a sixth control transistor T7 and a seventh control transistor T8;
  • the gate of T7 is electrically connected to the input clock signal terminal KI, the source of T7 is electrically connected to the second input node P12, and the drain of T7 is electrically connected to the second node P2;
  • the gate of T8 is electrically connected to the first isolation node P31, the source of T8 is electrically connected to the high voltage terminal, and the drain of T8 is electrically connected to the second node P2; the high voltage terminal is used to provide a high voltage VDD.
  • the ratio of the capacitance value of C4 to the capacitance value of C1 may be greater than or equal to 1 and less than or equal to 10, but not limited thereto.
  • all transistors are p-type thin film transistors
  • the first voltage signal is a negative voltage signal
  • the second voltage terminal is a low voltage terminal
  • the third voltage terminal is a high voltage terminal
  • the output The voltage terminal is a low voltage terminal, but not limited thereto.
  • the difference between at least one embodiment of the gate driving unit shown in FIG. 20 and at least one embodiment of the gate driving unit shown in FIG. 17 is that the source of T8 and the high voltage terminal (the high voltage terminal is used to provide The high voltage VDD) is electrically connected, which reduces the load on the second clock signal terminal, and does not need to repeatedly charge and discharge P2, which is beneficial to further reduce the load.
  • K1 provides low voltage
  • KI provides high voltage
  • K2 provides low voltage
  • I1 provides high voltage
  • T12 and T1 are turned on
  • T13 is turned on
  • P11 is at high voltage
  • P31 is at high voltage
  • T5 and T4 All are turned off
  • T2 is turned off
  • T3 is turned on
  • T14 is turned on
  • the potential of P32 is low voltage
  • the potential of P13 is low voltage
  • T6 is on
  • the potential of P12 is high voltage
  • T7 is off
  • T8 is off
  • T11 is off
  • the potential of P1 Maintain a low voltage
  • the potential of P2 is maintained at a high voltage
  • T10 is turned on
  • T9 is turned off
  • O1 outputs a low voltage
  • K1 provides high voltage
  • KI provides low voltage
  • K2 provides high voltage
  • I1 provides low voltage
  • both T12 and T1 are turned off
  • the potential of P11 is maintained at high voltage
  • T13 is turned on
  • the potential of P31 is high voltage
  • T4 is turned off
  • T5 is turned off
  • the potential of P32 is maintained at a low voltage
  • T14 is turned on
  • the potential of P13 is further pulled down by C1
  • T6 is turned on
  • the potential of P12 is low voltage
  • T7 is turned on
  • T8 is turned off
  • T11 is turned on
  • the potential of P1 is high voltage
  • the potential of P2 is a low voltage
  • T9 is turned on
  • T10 is turned off
  • O1 outputs a high voltage
  • K1 provides a low voltage
  • KI provides a high voltage
  • K2 provides a low voltage
  • I1 provides a low voltage
  • both T12 and T1 are turned on, the potential of P11 is pulled low
  • T13 is turned on
  • the potential of P31 is pulled low
  • T5 is turned on
  • the potential of P1 is pulled down
  • T10 is turned on
  • T3 is turned on
  • the potential of P32 is low voltage
  • T14 is turned on, the potential of P13 and P12 are pulled up
  • T7 is turned off
  • T8 is turned on
  • the potential of P2 is
  • T9 is also turned on.
  • K1 provides a high voltage
  • KI provides a low voltage
  • K2 provides a high voltage
  • I1 provides a low voltage
  • both T12 and T1 are turned off
  • the potential of P11 is maintained at a low voltage
  • T13 is turned on
  • T4 Turn on, KI pulls down the potential of P31 through C4, and T5 is turned on, so that the potential of P1 is maintained below VSS+Vth
  • Vth is the threshold voltage of T10, so that T10 is turned on, and the potential of the gate drive signal output by O1 is maintained.
  • T3 is turned off, T2 is turned on, the potential of P32 is high voltage, T14 is turned on, the potential of P13 is high voltage, the potential of P12 is high voltage, T7 is turned on, T8 is turned on, and the potential of P2 is High voltage, T9 is turned off;
  • K1 provides a low voltage
  • KI provides a high voltage
  • K2 provides a low voltage
  • I1 provides a low voltage
  • both T12 and T1 are turned on
  • the potential of P11 is a low voltage
  • T13 is turned on
  • T4 is turned on
  • the potential of the input clock signal provided by KI increases, thereby pulling up the potential of P31
  • T5 is turned off, and does not affect the potential of P1, so that the potential of P1 is maintained below VSS+Vth
  • Vth is the threshold voltage of T10, so that T10 is turned on , so that the potential of the gate drive signal output by O1 is maintained at VSS, which is not affected by noise interference
  • T3 is turned on, the potential of P32 is low voltage
  • T2 is turned off
  • T14 is turned on
  • the potential of P13 low voltage
  • T6 is turned on
  • P12 The potential of P2 is high voltage
  • T7 is turned off
  • T8 is turned on
  • the potential of P2 is
  • K1 provides a high voltage
  • KI provides a low voltage
  • K2 provides a high voltage
  • I1 provides a low voltage
  • both T12 and T1 are turned off
  • the potential of P11 is maintained at a low voltage
  • T4 is turned on
  • KI The potential of P31 is pulled down by C4, and T5 is turned on, so that the potential of P1 is kept lower than VSS+Vth
  • Vth is the threshold voltage of T10, so that T10 is turned on, so that the potential of the gate drive signal output by O1 is maintained at VSS, Not affected by noise interference
  • T3 is turned off
  • T2 is turned on
  • the potential of P32 is high voltage
  • T14 is turned on
  • the potential of P13 is high voltage
  • T6 is turned off
  • the potential of P12 is high voltage
  • T7 is turned on
  • T8 is turned on
  • the potential of P2 is High voltage
  • T9 is turned off
  • the potential of P1 can be maintained below VSS+Vth, Vth is the threshold voltage of T10, so that T10 is turned on, and the potential of the gate drive signal output by O1 is maintained at VSS, which is not affected by noise interference.
  • the first isolated node control sub-circuit 41 includes a first control transistor T12 and a second control transistor T1, wherein,
  • the gate of the first control transistor T12 is electrically connected to the second clock signal terminal K2, and the source of the first control transistor T12 is electrically connected to the input terminal;
  • the gate of the second control transistor T1 is electrically connected to the first clock signal terminal K1, the source of the second control transistor T1 is electrically connected to the drain of the first control transistor T12, and the second control transistor T1 is electrically connected to the drain of the first control transistor T12. the drain of the control transistor T1 is electrically connected to the first isolation node P31;
  • the first isolation sub-circuit 42 includes a first isolation transistor T13;
  • the electrode of the first isolation transistor T13 is electrically connected to the low voltage terminal, the source of the first isolation transistor T13 is electrically connected to the first isolation node P31, and the drain of the first isolation transistor T13 is electrically connected to the first isolation node P31.
  • the first input node P11 is electrically connected; the low voltage terminal is used to provide the low voltage VSS;
  • the input energy storage sub-circuit 21 includes an input capacitor C4, the on-off control sub-circuit 22 includes an on-off control transistor T5, and the first energy storage sub-circuit 23 includes a first storage capacitor C3;
  • the first end of C4 is electrically connected to the input clock signal KI, and the second end of C4 is electrically connected to the first input node P11;
  • the gate of T5 and the source of T5 are both electrically connected to the first input node P11, and the drain of T5 is electrically connected to the first node P1;
  • the first terminal of C3 is electrically connected to the first node P1, and the second terminal of C3 is electrically connected to the low voltage terminal; the low voltage terminal is used to provide the low voltage VSS;
  • the first node control circuit 12 includes a first node control transistor T11;
  • the gate of T11 is electrically connected to the second input node P12, the source of T11 is electrically connected to the high voltage terminal, and the drain of T11 is electrically connected to the first node P1; the high voltage terminal is used to provide a high voltage VDD;
  • the first energy storage circuit 31 includes a second storage capacitor C2;
  • the first end of C2 is electrically connected to the second node P2, and the second end of C2 is electrically connected to the second clock signal output end K2;
  • the output circuit 30 includes a first output transistor T10 and a second output transistor T9;
  • the gate of the first output transistor T10 is electrically connected to the first node P1, the source of the first output transistor T10 is electrically connected to the low voltage terminal, and the drain of the first output transistor T10 is electrically connected to the low voltage terminal.
  • the gate drive signal output terminal O1 is electrically connected;
  • the gate of the second output transistor T9 is electrically connected to the second node P2, the source of the second output transistor T9 is electrically connected to the gate driving signal output terminal O1, and the second output transistor T9
  • the second pole of is electrically connected to the second clock signal terminal K2;
  • the third input node control subcircuit includes a third isolation node control subcircuit 321 and a second isolation subcircuit 40; the third isolation node control subcircuit 321 includes a third control transistor T3 and a fourth control transistor T2;
  • the second isolation sub-circuit 40 includes a second isolation transistor T14, wherein,
  • the gate of T3 is electrically connected to the first clock signal terminal K1, the source of T3 is electrically connected to the low voltage terminal, and the drain of T3 is electrically connected to the second isolation node P32;
  • the gate of T2 is electrically connected to the first isolation node P31, the source of T2 is electrically connected to the first clock signal terminal K1, and the drain of T2 is electrically connected to the second isolation node P32;
  • the gate of T14 is electrically connected to the low voltage terminal, the source of T14 is electrically connected to the second isolation node P32, and the drain of T14 is electrically connected to the third input node P13;
  • the second input node control sub-circuit 33 includes a fifth control transistor T6 and a first capacitor C1;
  • the gate of T6 is electrically connected to the third input node P13, the source of the eighth control transistor T6 is electrically connected to the second input node P12, and the drain of the eighth control transistor T6 is connected to the input clock signal Terminal KI is electrically connected;
  • the first end of the first capacitor C1 is electrically connected to the third input node P13, and the second end of the first capacitor C1 is electrically connected to the second input node P12;
  • the second node control sub-circuit 34 includes a sixth control transistor T7 and a seventh control transistor T8;
  • the gate of T7 is electrically connected to the input clock signal terminal KI, the source of T7 is electrically connected to the second input node P12, and the drain of T7 is electrically connected to the second node P2;
  • the gate of T8 is electrically connected to the first isolation node P31, the source of T8 is electrically connected to the high voltage terminal, and the drain of T8 is electrically connected to the second node P2; the high voltage terminal is used to provide a high voltage VDD.
  • the ratio of the capacitance value of C4 to the capacitance value of C1 may be greater than or equal to 1 and less than or equal to 10, but not limited thereto.
  • all transistors are p-type thin film transistors
  • the first voltage signal is a negative voltage signal
  • the second voltage terminal is a low voltage terminal
  • the third voltage terminal is a high voltage terminal
  • the output The voltage terminal is a low voltage terminal, but not limited thereto.
  • the charge pump circuit does not include a switch control sub-circuit .
  • the charge pump circuit further includes a switch The control subcircuit 20; the switch control subcircuit 20 includes a switch control transistor T4; the first input node control circuit 10 includes a first control transistor T12 and a second control transistor T1, wherein,
  • the gate of the first control transistor T12 is electrically connected to the second clock signal terminal K2, and the source of the first control transistor T12 is electrically connected to the input terminal;
  • the gate of the second control transistor T1 is electrically connected to the first clock signal terminal K1, the source of the second control transistor T1 is electrically connected to the drain of the first control transistor T12, and the second control transistor T1 is electrically connected to the drain of the first control transistor T12.
  • the drain of the control transistor T1 is electrically connected to the first input node P11;
  • the input energy storage sub-circuit 21 includes an input capacitor C4,
  • the on-off control sub-circuit 22 includes an on-off control transistor T5, and the first energy storage sub-circuit 21 includes an on-off control transistor T5.
  • the energy sub-circuit 23 includes a first storage capacitor C3;
  • the gate of T4 is electrically connected to the first input node P11, the source of T4 is electrically connected to the input clock signal terminal KI, the drain of T4 is electrically connected to the first terminal of C4; the second terminal of C4 is electrically connected to the first input
  • the node P11 is electrically connected; the first end of C4 is electrically connected to the first control node P21;
  • the gate of T5 and the source of T5 are both electrically connected to the first input node P11, and the drain of T5 is electrically connected to the first node P1;
  • the first terminal of C3 is electrically connected to the first node P1, and the second terminal of C3 is electrically connected to the low voltage terminal; the low voltage terminal is used to provide the low voltage VSS;
  • the first node control circuit 12 includes a first node control transistor T11;
  • the gate of T11 is electrically connected to the second input node P12, the source of T11 is electrically connected to the high voltage terminal, and the drain of T11 is electrically connected to the first node P1; the high voltage terminal is used to provide a high voltage VDD;
  • the first energy storage circuit 31 includes a second storage capacitor C2;
  • the first end of C2 is electrically connected to the second node P2, and the second end of C2 is electrically connected to the second clock signal output end K2;
  • the output circuit 30 includes a first output transistor T10 and a second output transistor T9;
  • the gate of the first output transistor T10 is electrically connected to the first node P1, the source of the first output transistor T10 is electrically connected to the low voltage terminal, and the drain of the first output transistor T10 is electrically connected to the low voltage terminal.
  • the gate drive signal output terminal O1 is electrically connected;
  • the gate of the second output transistor T9 is electrically connected to the second node P2, the source of the second output transistor T9 is electrically connected to the gate driving signal output terminal O1, and the second output transistor T9
  • the second pole of is electrically connected to the second clock signal terminal K2;
  • the third input node control sub-circuit 32 includes a third control transistor T3 and a fourth control transistor T2, wherein,
  • the gate of T3 is electrically connected to the first clock signal terminal K1, the source of T3 is electrically connected to the low voltage terminal, and the drain of T3 is electrically connected to the third input node P13;
  • the gate of T2 is electrically connected to the first input node P11, the source of T2 is electrically connected to the first clock signal terminal K1, the drain of T2 is electrically connected to the third input node P13;
  • the second The input node control sub-circuit 33 includes a fifth control transistor T6 and a first capacitor C1;
  • the gate of T6 is electrically connected to the third input node P13, the source of the eighth control transistor T6 is electrically connected to the second input node P12, and the drain of the eighth control transistor T6 is connected to the input clock signal Terminal KI is electrically connected;
  • the first end of the first capacitor C1 is electrically connected to the third input node P13, and the second end of the first capacitor C1 is electrically connected to the second input node P12;
  • the second node control sub-circuit 34 includes a sixth control transistor T7 and a seventh control transistor T8;
  • the gate of T7 is electrically connected to the input clock signal terminal KI, the source of T7 is electrically connected to the second input node P12, and the drain of T7 is electrically connected to the second node P2;
  • the gate of T8 is electrically connected to the first isolation node P31, the source of T8 is electrically connected to the high voltage terminal, and the drain of T8 is electrically connected to the second node P2; the high voltage terminal is used to provide a high voltage VDD.
  • the ratio of the capacitance value of C4 to the capacitance value of C1 may be greater than or equal to 1 and less than or equal to 10, but not limited thereto.
  • all transistors are p-type thin film transistors
  • the first voltage signal is a negative voltage signal
  • the second voltage terminal is a low voltage terminal
  • the third voltage terminal is a high voltage terminal
  • the output The voltage terminal is a low voltage terminal, but not limited thereto.
  • the gate driving unit does not include the first isolation transistor and a second isolation transistor.
  • the charge pump circuit further includes a switch a control sub-circuit 20; the switch control sub-circuit 20 includes a switch control transistor T4;
  • the first isolated node control sub-circuit 41 includes a first control transistor T12, wherein,
  • the gate of the first control transistor T12 is electrically connected to the second clock signal terminal K2, and the source of the first control transistor T12 is electrically connected to the input terminal;
  • the first isolation sub-circuit 42 includes a first isolation transistor T13;
  • the electrode of the first isolation transistor T13 is electrically connected to the low voltage terminal, the source of the first isolation transistor T13 is electrically connected to the first isolation node P31, and the drain of the first isolation transistor T13 is electrically connected to the first isolation node P31.
  • the first input node P11 is electrically connected; the low voltage terminal is used to provide the low voltage VSS;
  • the input energy storage sub-circuit 21 includes an input capacitor C4, the on-off control sub-circuit 22 includes an on-off control transistor T5, and the first energy storage sub-circuit 23 includes a first storage capacitor C3;
  • the gate of T4 is electrically connected to the first input node P11, the source of T4 is electrically connected to the input clock signal terminal KI, the drain of T4 is electrically connected to the first terminal of C4; the second terminal of C4 is electrically connected to the first input
  • the node P11 is electrically connected; the first end of C4 is electrically connected to the first control node P21;
  • the gate of T5 and the source of T5 are both electrically connected to the first input node P11, and the drain of T5 is electrically connected to the first node P1;
  • the first terminal of C3 is electrically connected to the first node P1, and the second terminal of C3 is electrically connected to the low voltage terminal; the low voltage terminal is used to provide the low voltage VSS;
  • the first node control circuit 12 includes a first node control transistor T11;
  • the gate of T11 is electrically connected to the second input node P12, the source of T11 is electrically connected to the high voltage terminal, and the drain of T11 is electrically connected to the first node P1; the high voltage terminal is used to provide a high voltage VDD;
  • the first energy storage circuit 31 includes a second storage capacitor C2;
  • the first end of C2 is electrically connected to the second node P2, and the second end of C2 is electrically connected to the second clock signal output end K2;
  • the output circuit 30 includes a first output transistor T10 and a second output transistor T9;
  • the gate of the first output transistor T10 is electrically connected to the first node P1, the source of the first output transistor T10 is electrically connected to the low voltage terminal, and the drain of the first output transistor T10 is electrically connected to the low voltage terminal.
  • the gate drive signal output terminal O1 is electrically connected;
  • the gate of the second output transistor T9 is electrically connected to the second node P2, the source of the second output transistor T9 is electrically connected to the gate driving signal output terminal O1, and the second output transistor T9
  • the second pole of is electrically connected to the second clock signal terminal K2;
  • the third input node control subcircuit includes a third isolation node control subcircuit 321 and a second isolation subcircuit 40; the third isolation node control subcircuit 321 includes a third control transistor T3 and a fourth control transistor T2;
  • the second isolation sub-circuit 40 includes a second isolation transistor T14, wherein,
  • the gate of T3 is electrically connected to the first clock signal terminal K1, the source of T3 is electrically connected to the low voltage terminal, and the drain of T3 is electrically connected to the second isolation node P32;
  • the gate of T2 is electrically connected to the first isolation node P31, the source of T2 is electrically connected to the first clock signal terminal K1, and the drain of T2 is electrically connected to the second isolation node P32;
  • the gate of T14 is electrically connected to the low voltage terminal, the source of T14 is electrically connected to the second isolation node P32, and the drain of T14 is electrically connected to the third input node P13; the low voltage terminal is used to provide low voltage voltage VSS;
  • the second input node control sub-circuit 33 includes a fifth control transistor T6 and a first capacitor C1;
  • the gate of T6 is electrically connected to the third input node P13, the source of the eighth control transistor T6 is electrically connected to the second input node P12, and the drain of the eighth control transistor T6 is connected to the input clock signal Terminal KI is electrically connected;
  • the first end of the first capacitor C1 is electrically connected to the third input node P13, and the second end of the first capacitor C1 is electrically connected to the second input node P12;
  • the second node control sub-circuit 34 includes a sixth control transistor T7 and a seventh control transistor T8;
  • the gate of T7 is electrically connected to the input clock signal terminal KI, the source of T7 is electrically connected to the second input node P12, and the drain of T7 is electrically connected to the second node P2;
  • the gate of T8 is electrically connected to the first isolation node P31, the source of T8 is electrically connected to the high voltage terminal, and the drain of T8 is electrically connected to the second node P2; the high voltage terminal is used to provide a high voltage VDD.
  • the ratio of the capacitance value of C4 to the capacitance value of C1 may be greater than or equal to 1 and less than or equal to 10, but not limited thereto.
  • all transistors are p-type thin film transistors
  • the first voltage signal is a negative voltage signal
  • the second voltage terminal is a low voltage terminal
  • the third voltage terminal is a high voltage terminal
  • the output The voltage terminal is a low voltage terminal, but not limited thereto.
  • the difference between at least one embodiment of the gate driving unit shown in FIG. 24 of the present disclosure and at least one embodiment of the gate driving unit shown in FIG. 20 of the present disclosure is as follows: the first isolation node control sub-circuit 41 only Including the first control transistor T12, the first isolation node control sub-circuit 41 does not include the second control transistor T1, provided that the rising edge of the second clock signal is not earlier than the falling edge of the input signal provided by I1.
  • the charge pump circuit further includes a switch a control sub-circuit 20; the switch control sub-circuit 20 includes a switch control transistor T4;
  • the first isolated node control sub-circuit 41 includes a second control transistor T1, wherein,
  • the gate of the second control transistor T1 is electrically connected to the first clock signal terminal K1, the source of the second control transistor T1 is electrically connected to the drain of the first control transistor T12, and the second control transistor T1 is electrically connected to the drain of the first control transistor T12. the drain of the control transistor T1 is electrically connected to the first input node P11;
  • the first isolation sub-circuit 42 includes a first isolation transistor T13;
  • the electrode of the first isolation transistor T13 is electrically connected to the low voltage terminal, the source of the first isolation transistor T13 is electrically connected to the first isolation node P31, and the drain of the first isolation transistor T13 is electrically connected to the first isolation node P31.
  • the first input node P11 is electrically connected; the low voltage terminal is used to provide the low voltage VSS;
  • the input energy storage sub-circuit 21 includes an input capacitor C4, the on-off control sub-circuit 22 includes an on-off control transistor T5, and the first energy storage sub-circuit 23 includes a first storage capacitor C3;
  • the gate of T4 is electrically connected to the first input node P11, the source of T4 is electrically connected to the input clock signal terminal KI, the drain of T4 is electrically connected to the first terminal of C4; the second terminal of C4 is electrically connected to the first input
  • the node P11 is electrically connected; the first end of C4 is electrically connected to the first control node P21;
  • the gate of T5 and the source of T5 are both electrically connected to the first input node P11, and the drain of T5 is electrically connected to the first node P1;
  • the first terminal of C3 is electrically connected to the first node P1, and the second terminal of C3 is electrically connected to the low voltage terminal; the low voltage terminal is used to provide the low voltage VSS;
  • the first node control circuit 12 includes a first node control transistor T11;
  • the gate of T11 is electrically connected to the second input node P12, the source of T11 is electrically connected to the high voltage terminal, and the drain of T11 is electrically connected to the first node P1; the high voltage terminal is used to provide a high voltage VDD;
  • the first energy storage circuit 31 includes a second storage capacitor C2;
  • the first end of C2 is electrically connected to the second node P2, and the second end of C2 is electrically connected to the second clock signal output end K2;
  • the output circuit 30 includes a first output transistor T10 and a second output transistor T9;
  • the gate of the first output transistor T10 is electrically connected to the first node P1, the source of the first output transistor T10 is electrically connected to the low voltage terminal, and the drain of the first output transistor T10 is electrically connected to the low voltage terminal.
  • the gate drive signal output terminal O1 is electrically connected;
  • the gate of the second output transistor T9 is electrically connected to the second node P2, the source of the second output transistor T9 is electrically connected to the gate driving signal output terminal O1, and the second output transistor T9
  • the second pole of is electrically connected to the second clock signal terminal K2;
  • the third input node control subcircuit includes a third isolation node control subcircuit 321 and a second isolation subcircuit 40; the third isolation node control subcircuit 321 includes a third control transistor T3 and a fourth control transistor T2;
  • the second isolation sub-circuit 40 includes a second isolation transistor T14, wherein,
  • the gate of T3 is electrically connected to the first clock signal terminal K1, the source of T3 is electrically connected to the low voltage terminal, and the drain of T3 is electrically connected to the second isolation node P32;
  • the gate of T2 is electrically connected to the first isolation node P31, the source of T2 is electrically connected to the first clock signal terminal K1, and the drain of T2 is electrically connected to the second isolation node P32;
  • the gate of T14 is electrically connected to the low voltage terminal, the source of T14 is electrically connected to the second isolation node P32, and the drain of T14 is electrically connected to the third input node P13; the low voltage terminal is used to provide low voltage voltage VSS;
  • the second input node control sub-circuit 33 includes a fifth control transistor T6 and a first capacitor C1;
  • the gate of T6 is electrically connected to the third input node P13, the source of the eighth control transistor T6 is electrically connected to the second input node P12, and the drain of the eighth control transistor T6 is connected to the input clock signal Terminal KI is electrically connected;
  • the first end of the first capacitor C1 is electrically connected to the third input node P13, and the second end of the first capacitor C1 is electrically connected to the second input node P12;
  • the second node control sub-circuit 34 includes a sixth control transistor T7 and a seventh control transistor T8;
  • the gate of T7 is electrically connected to the input clock signal terminal KI, the source of T7 is electrically connected to the second input node P12, and the drain of T7 is electrically connected to the second node P2;
  • the gate of T8 is electrically connected to the first isolation node P31, the source of T8 is electrically connected to the high voltage terminal, and the drain of T8 is electrically connected to the second node P2; the high voltage terminal is used to provide a high voltage VDD.
  • the ratio of the capacitance value of C4 to the capacitance value of C1 may be greater than or equal to 1 and less than or equal to 10, but not limited thereto.
  • all transistors are p-type thin film transistors
  • the first voltage signal is a negative voltage signal
  • the second voltage terminal is a low voltage terminal
  • the third voltage terminal is a high voltage terminal
  • the output The voltage terminal is a low voltage terminal, but not limited thereto.
  • the difference between at least one embodiment of the gate driving unit shown in FIG. 25 of the present disclosure and at least one embodiment of the gate driving unit shown in FIG. 20 of the present disclosure is as follows: the first isolation node control sub-circuit 41 only Including the second control transistor T1, the first isolated node control sub-circuit 41 does not include the first control transistor T12, provided that the rising edge of the first clock signal is not earlier than the falling edge of the input signal provided by I1.
  • the charge pump circuit further includes a switch control sub-circuit 20; the switch control sub-circuit 20 includes a switch control transistor T4;
  • the first isolated node control sub-circuit 41 includes a first control transistor T12 and a second control transistor T1, wherein,
  • the gate of the first control transistor T12 is electrically connected to the second clock signal terminal K2, and the source of the first control transistor T12 is electrically connected to the input terminal;
  • the gate of the second control transistor T1 is electrically connected to the first clock signal terminal K1, the source of the second control transistor T1 is electrically connected to the drain of the first control transistor T12, and the second control transistor T1 is electrically connected to the drain of the first control transistor T12. the drain of the control transistor T1 is electrically connected to the first isolation node P31;
  • the first isolation sub-circuit 42 includes a first isolation transistor T13;
  • the electrode of the first isolation transistor T13 is electrically connected to the low voltage terminal, the source of the first isolation transistor T13 is electrically connected to the first isolation node P31, and the drain of the first isolation transistor T13 is electrically connected to the first isolation node P31.
  • the first input node P11 is electrically connected; the low voltage terminal is used to provide the low voltage VSS;
  • the input energy storage sub-circuit 21 includes an input capacitor C4, the on-off control sub-circuit 22 includes an on-off control transistor T5, and the first energy storage sub-circuit 23 includes a first storage capacitor C3;
  • the gate of T4 is electrically connected to the first input node P11, the source of T4 is electrically connected to the input clock signal terminal KI, the drain of T4 is electrically connected to the first terminal of C4; the second terminal of C4 is electrically connected to the first input
  • the node P11 is electrically connected; the first end of C4 is electrically connected to the first control node P21;
  • the gate of T5 and the source of T5 are both electrically connected to the first input node P11, and the drain of T5 is electrically connected to the first node P1;
  • the first terminal of C3 is electrically connected to the first node P1, and the second terminal of C3 is electrically connected to the low voltage terminal; the low voltage terminal is used to provide the low voltage VSS;
  • the first node control circuit 12 includes a first node control transistor T11;
  • the gate of T11 is electrically connected to the second input node P12, the source of T11 is electrically connected to the high voltage terminal, and the drain of T11 is electrically connected to the first node P1; the high voltage terminal is used to provide a high voltage VDD;
  • the first energy storage circuit 31 includes a second storage capacitor C2;
  • the first end of C2 is electrically connected to the second node P2, and the second end of C2 is electrically connected to the gate driving signal output end O1;
  • the output circuit 30 includes a first output transistor T10 and a second output transistor T9;
  • the gate of the first output transistor T10 is electrically connected to the first node P1, the source of the first output transistor T10 is electrically connected to the low voltage terminal, and the drain of the first output transistor T10 is electrically connected to the low voltage terminal.
  • the gate drive signal output terminal O1 is electrically connected;
  • the gate of the second output transistor T9 is electrically connected to the second node P2, the source of the second output transistor T9 is electrically connected to the gate driving signal output terminal O1, and the second output transistor T9
  • the second pole of is electrically connected to the second clock signal terminal K2;
  • the third input node control subcircuit includes a third isolation node control subcircuit 321 and a second isolation subcircuit 40; the third isolation node control subcircuit 321 includes a third control transistor T3 and a fourth control transistor T2;
  • the second isolation sub-circuit 40 includes a second isolation transistor T14, wherein,
  • the gate of T3 is electrically connected to the first clock signal terminal K1, the source of T3 is electrically connected to the low voltage terminal, and the drain of T3 is electrically connected to the second isolation node P32;
  • the gate of T2 is electrically connected to the first isolation node P31, the source of T2 is electrically connected to the first clock signal terminal K1, and the drain of T2 is electrically connected to the second isolation node P32;
  • the gate of T14 is electrically connected to the low voltage terminal, the source of T14 is electrically connected to the second isolation node P32, and the drain of T14 is electrically connected to the third input node P13; the low voltage terminal is used to provide low voltage voltage VSS;
  • the second input node control sub-circuit 33 includes a fifth control transistor T6 and a first capacitor C1;
  • the gate of T6 is electrically connected to the third input node P13, the source of the eighth control transistor T6 is electrically connected to the second input node P12, and the drain of the eighth control transistor T6 is connected to the input clock signal Terminal KI is electrically connected;
  • the first end of the first capacitor C1 is electrically connected to the third input node P13, and the second end of the first capacitor C1 is electrically connected to the second input node P12;
  • the second node control sub-circuit 34 includes a sixth control transistor T7 and a seventh control transistor T8;
  • the gate of T7 is electrically connected to the input clock signal terminal KI, the source of T7 is electrically connected to the second input node P12, and the drain of T7 is electrically connected to the second node P2;
  • the gate of T8 is electrically connected to the first isolation node P31, the source of T8 is electrically connected to the high voltage terminal, and the drain of T8 is electrically connected to the second node P2; the high voltage terminal is used to provide a high voltage VDD.
  • the ratio of the capacitance value of C4 to the capacitance value of C1 may be greater than or equal to 1 and less than or equal to 10, but not limited thereto.
  • all transistors are p-type thin film transistors
  • the first voltage signal is a negative voltage signal
  • the second voltage terminal is a low voltage terminal
  • the third voltage terminal is a high voltage terminal
  • the output The voltage terminal is a low voltage terminal, but not limited thereto.
  • the difference between at least one embodiment of the gate driving unit shown in FIG. 26 and at least one embodiment of the gate driving unit shown in FIG. 20 is that the second terminal of C2 is electrically connected to the gate driving signal output terminal, which reduces the The capacitive load at the second clock signal terminal is beneficial to reduce power consumption.
  • the operation timing diagram of at least one embodiment of the gate driving unit shown in FIG. 26 may be as shown in FIG. 21 .
  • the driving method described in the embodiment of the present disclosure is applied to the above-mentioned gate driving unit, and the driving method includes:
  • the first input node control circuit turns on or off the connection between the input terminal and the first input node under the control of the clock signal provided by the clock signal terminal;
  • the charge pump circuit controls to convert the voltage signal of the first input node into the first voltage signal under the control of the input clock signal provided by the input clock signal terminal.
  • a voltage signal of a node, and the polarity of the voltage signal of the first node is the same as the polarity of the voltage signal of the first input node, and the absolute value of the voltage value of the voltage signal of the first node is greater than all The absolute value of the voltage value of the voltage signal of the first input node.
  • the gate driving unit can sufficiently pull down or raise the potential of the first node in the hold phase, so that in the hold phase, the first output transistor controlled by the first node is held It is turned on, so that in the hold phase, the potential of the output gate driving signal is not affected by noise interference.
  • the gate driving circuit according to the embodiment of the present disclosure includes the above-mentioned gate driving unit.
  • the display device includes the above-mentioned gate driving circuit.
  • the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.

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Abstract

一种栅极驱动单元、驱动方法、栅极驱动电路和显示装置。栅极驱动单元包括第一输入节点控制电路（10）和电荷泵电路（11）；第一输入节点控制电路（10）在时钟信号（K0）的控制下，导通或断开输入端(I1)与第一输入节点（P11）之间的连接；电荷泵电路（11）当第一输入节点（P11）的电压信号为第一电压信号时，在输入时钟信号（KI）的控制下，控制将第一输入节点（P11）的电压信号转换为第一节点（P1）的电压信号，且使得第一节点（P1）的电压信号的极性与第一输入节点（P11）的电压信号的极性相同，第一节点（P1）的电压信号的电压值的绝对值大于第一输入节点（P11）的电压信号的电压值的绝对值。由此能够在保持阶段充分拉低或升高第一节点的电位，使得输出的栅极驱动信号的电位不受噪声干扰的影响。

Description

栅极驱动单元、驱动方法、栅极驱动电路和显示装置
相关申请的交叉引用
本申请主张在2020年9月2日在中国提交的中国专利申请号No.202010908595.6的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种栅极驱动单元、驱动方法、栅极驱动电路和显示装置。
背景技术
为了使保持像素亮度波动在合理的范围内，静态画面时仍然需要刷新数据，因为控制亮度的电压会由于漏电而随时间变化。为了降低功耗，降低刷新频率是比较有效的方法，同时还需要保持显示质量，就需要减少像素漏电速度，而氧化物半导体具有超低漏电的特性，满足这种需求。为了保证像素充电速度和较小的寄生电容，比较好的办法是结合采用LTPO(Low Temperature Polycrystalline Oxide，低温多晶氧化物)工艺。现有的栅极驱动单元在工作时，不能在保持阶段使得输出的栅极驱动信号的电位不受噪声干扰的影响。
发明内容
在一个方面中，本公开实施例提供了一种栅极驱动单元，包括第一输入节点控制电路和电荷泵电路；
所述第一输入节点控制电路分别与时钟信号端、输入端和第一输入节点电连接，用于在所述时钟信号端提供的时钟信号的控制下，导通或断开所述输入端与所述第一输入节点之间的连接；
所述电荷泵电路分别与所述第一输入节点、输入时钟信号端和第一节点电连接，用于当所述第一输入节点的电压信号为第一电压信号时，在所述输 入时钟信号端提供的输入时钟信号的控制下，控制将所述第一输入节点的电压信号转换为所述第一节点的电压信号，且使得所述第一节点的电压信号的极性与所述第一输入节点的电压信号的极性相同，所述第一节点的电压信号的电压值的绝对值大于所述第一输入节点的电压信号的电压值的绝对值。
可选的，所述栅极驱动单元包括输出电路，所述输出电路包括第一输出晶体管，所述第一输出晶体管的控制极与所述第一节点电连接，所述第一输出晶体管的第一极与输出电压端电连接，所述第一输出晶体管的第二极与栅极驱动信号输出端电连接。
可选的，所述电荷泵电路包括输入储能子电路、通断控制子电路和第一储能子电路；
所述输入储能子电路的第一端与所述输入时钟信号端电连接，所述输入储能子电路的第二端与所述第一输入节点电连接，用于储存电能且根据所述输入时钟信号的电位控制所述第一输入节点的电位；
所述通断控制子电路分别与所述第一输入节点和所述第一节点电连接，用于在所述第一输入节点的电位的控制下，导通或断开所述第一输入节点与所述第一节点之间的连接；
所述第一储能子电路与所述第一节点电连接，用于储存电能且维持所述第一节点的电位。
可选的，所述电荷泵电路包括输入储能子电路、通断控制子电路、开关控制子电路和第一储能子电路；
所述输入储能子电路的第一端与第一控制节点电连接，所述输入储能子电路的第二端与所述第一输入节点电连接，用于储存电能且根据第一控制节点的电位控制所述第一输入节点的电位；
所述通断控制子电路分别与所述第一输入节点和所述第一节点电连接，用于在所述第一输入节点的电位的控制下，导通或断开所述第一输入节点与所述第一节点之间的连接；
所述第一储能子电路与所述第一节点电连接，用于储存电能且维持所述第一节点的电位；
所述开关控制子电路分别与所述第一输入节点、输入时钟信号端和所述 第一控制节点电连接，用于在所述第一输入节点的电位的控制下，导通或断开所述输入时钟信号端与所述第一控制节点之间的连接。
可选的，所述输入储能子电路包括输入电容，所述第一储能子电路包括第一存储电容，所述通断控制子电路包括通断控制晶体管；
所述输入电容的第一端与所述输入时钟信号端电连接，所述输入电容的第二端与所述第一输入节点电连接；
所述第一存储电容的第一端与所述第一节点电连接，所述第一存储电容的第二端与第二电压端电连接；
所述通断控制晶体管的控制极和所述通断控制晶体管的第一极与所述第一输入节点电连接，所述通断控制晶体管的第二极与所述第一节点电连接。
可选的，所述输入储能子电路包括输入电容，所述第一储能子电路包括第一存储电容，所述通断控制子电路包括通断控制晶体管；
所述输入电容的第一端与所述第一控制节点电连接，所述输入电容的第二端与所述第一输入节点电连接；
所述第一存储电容的第一端与所述第一节点电连接，所述第一存储电容的第二端与第二电压端电连接；
所述通断控制晶体管的控制极和所述通断控制晶体管的第一极与所述第一输入节点电连接，所述通断控制晶体管的第二极与所述第一节点电连接。
可选的，所述输入电容的电容值与所述第一存储电容的电容值之间的比值大于或等于1而小于或等于10。
可选的，所述开关控制子电路包括开关控制晶体管；
所述开关控制晶体管的控制极与所述第一输入节点电连接，所述开关控制晶体管的第一极与所述输入时钟信号端电连接，所述开关控制晶体管的第二极与所述第一控制节点电连接。
可选的，所述第一输入节点控制电路包括第一隔离节点控制子电路和第一隔离子电路；
所述第一隔离节点控制子电路分别与时钟信号端、输入端和第一隔离节点电连接，用于在所述时钟信号端提供的时钟信号的控制下，导通或断开所述输入端与所述第一隔离节点之间的连接；
所述第一隔离子电路分别与第二电压端、所述第一隔离节点和所述第一输入节点电连接，用于在第二电压端提供的第二电压信号的控制下，控制所述第一隔离节点与所述第一输入节点之间连通。
可选的，所述时钟信号端包括第一时钟信号端和第二时钟信号端；第一隔离节点控制子电路包括第一控制晶体管和第二控制晶体管；所述第一控制晶体管的控制极与所述第二时钟信号端电连接，所述第一控制晶体管的第一极与所述输入端电连接；所述第二控制晶体管的控制极与所述第一时钟信号端电连接，所述第二控制晶体管的第一极与所述第一控制晶体管的第二极电连接，所述第二控制晶体管的第二极与所述第一隔离节点电连接；或者，
所述时钟信号端包括第二时钟信号端，所述第一隔离节点控制子电路包括第一控制晶体管；所述第一控制晶体管的控制极与所述第二时钟信号端电连接，所述第一控制晶体管的第一极与所述输入端电连接，所述第一控制晶体管的第二极与所述第一隔离节点电连接；或者，
所述时钟信号端包括第一时钟信号端，所述第一隔离节点控制子电路包括第二控制晶体管；所述第二控制晶体管的控制极与所述第一时钟信号端电连接，所述第一控制晶体管的第一极与所述输入端电连接，所述第二控制晶体管的第二极与所述第一隔离节点电连接。
可选的，所述第一隔离子电路包括第一隔离晶体管；
所述第一隔离晶体管的控制极与所述第二电压端电连接，所述第一隔离晶体管的第一极与所述第一隔离节点电连接，所述第一隔离晶体管的第二极与所述第一输入节点电连接。
可选的，本公开至少一实施例所述的栅极驱动单元还包括第一节点控制电路；
所述第一节点控制电路分别与第二输入节点、第三电压端和第一节点电连接，用于在所述第二输入节点的电位的控制下，控制将第三电压端输入的第三电压信号写入所述第一节点。
可选的，所述第一节点控制电路包括第一节点控制晶体管；
所述第一节点控制晶体管的控制极与所述第二输入节点电连接，所述第一节点控制晶体管的第一极与第三电压端电连接，所述第一节点控制晶体管 的第二极与所述第一节点电连接。
可选的，本公开至少一实施例所述的栅极驱动单元还包括第一储能电路；
所述第一储能电路分别与第二节点和第二时钟信号端电连接，用于根据第二时钟信号控制所述第二节点的电位。
可选的，本公开至少一实施例所述的栅极驱动单元还包括栅极驱动信号输出端和第一储能电路；
所述第一储能电路分别与第二节点和所述栅极驱动信号输出端电连接，用于根据所述栅极驱动信号输出端输出的栅极驱动信号，控制第二节点的电位。
可选的，本公开至少一实施例所述的栅极驱动单元还包括输出电路；
所述输出电路分别与第一节点、第二节点、栅极驱动信号输出端、输出电压端和第二时钟信号输出端电连接，用于在第一节点的电位的控制下，控制将输出电压信号写入所述栅极驱动信号输出端，并在第二节点的电位的控制下，将第二时钟信号写入所述栅极驱动信号输出端；
所述输出电压端用于提供输出电压信号。
可选的，所述输出电路包括第一输出晶体管和第二输出晶体管；
所述第一输出晶体管的控制极与所述第一节点电连接，所述第一输出晶体管的第一极与所述输出电压端电连接，所述第一输出晶体管的第二极与所述栅极驱动信号输出端电连接；
所述第二输出晶体管的控制极与所述第二节点电连接，所述第二输出晶体管的第一极与所述栅极驱动信号输出端电连接，所述第二输出晶体管的第二极与所述第二时钟信号端电连接。
可选的，本公开至少一实施例所述的栅极驱动单元还包括第二节点控制电路；
所述第二节点控制电路包括第三输入节点控制子电路、第二输入节点控制子电路和第二节点控制子电路；
所述第三输入节点控制子电路分别与第一时钟信号端、第二电压端、第一输入节点和第三输入节点电连接，用于在第一时钟信号的控制下，将第二电压信号写入所述第三输入节点，并用于在第一输入节点的电位的控制下， 将第一时钟信号写入所述第三输入节点；
所述第二输入节点控制子电路分别与所述第三输入节点、第二输入节点和输入时钟信号端电连接，用于在所述第三输入节点的电位的控制下将输入时钟信号写入所述第二输入节点，并用于根据所述第三输入节点的电位控制第二输入节点的电位；
所述第二节点控制子电路分别与所述第二输入节点、第一输入节点、第二节点和输入时钟信号端电连接，所述第二节点控制子电路还与第二时钟信号端或第三电压端电连接，用于在输入时钟信号的控制下，导通或断开所述第二输入节点与所述第二节点之间的连接，并用于在所述第一输入节点的电位的控制下，将第二时钟信号或第三电压信号写入第二节点。
可选的，所述第三输入节点控制子电路包括第三控制晶体管和第四控制晶体管，其中，
所述第三控制晶体管的控制极与第一时钟信号端电连接，所述第三控制晶体管的第一极与第二电压端电连接，所述第三控制晶体管的第二极与第三输入节点电连接；
所述第四控制晶体管的控制极与所述第一输入节点电连接，所述第四控制晶体管的第一极与所述第一时钟信号端电连接，所述第四控制晶体管的第二极与所述第三输入节点电连接。
可选的，本公开至少一实施例所述的栅极驱动单元还包括第二节点控制电路；
所述第二节点控制电路包括第三输入节点控制子电路、第二输入节点控制子电路和第二节点控制子电路；
所述第三输入节点控制子电路分别与第一时钟信号端、第二电压端、第一隔离节点和第三输入节点电连接，用于在第一时钟信号的控制下，将第二电压信号写入所述第三输入节点，并用于在第一隔离节点的电位的控制下，将第一时钟信号写入所述第三输入节点；
所述第二输入节点控制子电路分别与所述第三输入节点、第二输入节点和输入时钟信号端电连接，用于在所述第三输入节点的电位的控制下将输入时钟信号写入所述第二输入节点，并用于根据所述第三输入节点的电位控制 第二输入节点的电位；
所述第二节点控制子电路分别与所述第二输入节点、第一隔离节点、第二节点和输入时钟信号端电连接，所述第二节点控制子电路还与第二时钟信号端或第三电压端电连接，用于在输入时钟信号的控制下，导通或断开所述第二输入节点与所述第二节点之间的连接，并用于在所述第一输入节点的电位的控制下，将第二时钟信号或第三电压信号写入第二节点。
可选的，所述第三输入节点控制子电路包括第三控制晶体管和第四控制晶体管，其中，
所述第三控制晶体管的控制极与第一时钟信号端电连接，所述第三控制晶体管的第一极与第二电压端电连接，所述第三控制晶体管的第二极与第三输入节点电连接；
所述第四控制晶体管的控制极与所述第一隔离节点电连接，所述第四控制晶体管的第一极与所述第一时钟信号端电连接，所述第四控制晶体管的第二极与所述第三输入节点电连接。
可选的，所述第三输入节点控制子电路包括第三控制晶体管、第四控制晶体管和第二隔离晶体管；
所述第三控制晶体管的控制极与第一时钟信号端电连接，所述第三控制晶体管的第一极与第二电压端电连接，所述第三控制晶体管的第二极与第二隔离节点电连接；
所述第四控制晶体管的控制极与所述第一隔离节点电连接，所述第四控制晶体管的第一极与所述第一时钟信号端电连接，所述第四控制晶体管的第二极与所述第二隔离节点电连接；
所述第二隔离晶体管的控制极与第二电压端电连接，所述第二隔离晶体管的第一极与第二隔离节点电连接，所述第二隔离晶体管的第二极与第三输入节点电连接。
可选的，所述第二输入节点控制子电路包括第五控制晶体管和第一电容；
所述第五控制晶体管的控制极与所述第三输入节点电连接，所述第五控制晶体管的第一极与所述第二输入节点电连接，所述第五控制晶体管的第二极与输入时钟信号端电连接；
所述第一电容的第一端与所述第三输入节点电连接，所述第一电容的第二端与所述第二输入节点电连接。
可选的，所述第二节点控制子电路包括第六控制晶体管和第七控制晶体管；
所述第六控制晶体管的控制极与输入时钟信号端电连接，所述第六控制晶体管的第一极与所述第二输入节点电连接，所述第六控制晶体管的第二极与所述第二节点电连接；
所述第七控制晶体管的控制极与所述第一隔离节点电连接，所述第七控制晶体管的第一极与第二时钟信号端或第三电压端电连接，所述第七控制晶体管的第二极与所述第二节点电连接。
在第二个方面中，本公开实施例还提供了一种驱动方法，应用于上述的栅极驱动单元，所述驱动方法包括：
第一输入节点控制电路在时钟信号端提供的时钟信号的控制下，导通或断开输入端与第一输入节点之间的连接；
当所述第一输入节点的电压信号为第一电压信号时，电荷泵电路在输入时钟信号端提供的输入时钟信号的控制下，控制将所述第一输入节点的电压信号转换为所述第一节点的电压信号，且使得所述第一节点的电压信号的极性与所述第一输入节点的电压信号的极性相同，所述第一节点的电压信号的电压值的绝对值大于所述第一输入节点的电压信号的电压值的绝对值。
在第三个方面中，本公开实施例还提供了一种栅极驱动电路，包括上述的栅极驱动单元。
在第四个方面中，本公开实施例还提供了一种显示装置，包括上述的栅极驱动电路。
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图1是本公开实施例所述的栅极驱动单元的结构图；
图2是本公开至少一实施例所述的栅极驱动单元的结构图；
图3是本公开至少一实施例所述的栅极驱动单元的结构图；
图4是本公开至少一实施例所述的栅极驱动单元的结构图；
图5是本公开至少一实施例所述的栅极驱动单元的结构图；
图6是本公开至少一实施例所述的栅极驱动单元的结构图；
图7是本公开至少一实施例所述的栅极驱动单元的结构图；
图8是本公开至少一实施例所述的栅极驱动单元的结构图；
图9是本公开至少一实施例所述的栅极驱动单元的结构图；
图10是本公开至少一实施例所述的栅极驱动单元的结构图；
图11是本公开至少一实施例所述的栅极驱动单元的结构图；
图12是本公开至少一实施例所述的栅极驱动单元的结构图；
图13是本公开至少一实施例所述的栅极驱动单元的结构图；
图14是本发明所述的栅极驱动单元的至少一实施例的电路图；
图15是本发明所述的栅极驱动单元如图14所示的至少一实施例的工作时序图；
图16是本发明所述的栅极驱动单元的至少一实施例的电路图；
图17是本发明所述的栅极驱动单元的至少一实施例的电路图；
图18是本发明所述的栅极驱动单元如图17所示的至少一实施例的工作时序图；
图19是本发明所述的栅极驱动单元的至少一具体实施例的电路图；
图20是本发明所述的栅极驱动单元的至少一具体实施例的电路图；
图21是本发明所述的栅极驱动单元如图20所示的至少一具体实施例的工作时序图；
图22是本发明所述的栅极驱动单元的至少一实施例的电路图；
图23是本发明所述的栅极驱动单元的至少一实施例的电路图；
图24是本发明所述的栅极驱动单元的至少一实施例的电路图；
图25是本发明所述的栅极驱动单元的至少一实施例的电路图；
图26是本发明所述的栅极驱动单元的至少一实施例的电路图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而 不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为三极管、薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除控制极之外的两极，将其中一极称为第一极，另一极称为第二极。
在实际操作时，当所述晶体管为三极管时，所述控制极可以为基极，所述第一极可以为集电极，所述第二极可以发射极；或者，所述控制极可以为基极，所述第一极可以为发射极，所述第二极可以集电极。
在实际操作时，当所述晶体管为薄膜晶体管或场效应管时，所述控制极可以为栅极，所述第一极可以为漏极，所述第二极可以为源极；或者，所述控制极可以为栅极，所述第一极可以为源极，所述第二极可以为漏极。
如图1所示，本公开实施例所述的栅极驱动单元包括第一输入节点控制电路10和电荷泵电路11；
所述第一输入节点控制电路10分别与时钟信号端K0、输入端I1和第一输入节点P11电连接，用于在所述时钟信号端K0提供的时钟信号的控制下，导通或断开所述输入端I1与所述第一输入节点P11之间的连接；
所述电荷泵电路11分别与所述第一输入节点P11、输入时钟信号端KI和第一节点P1电连接，用于当所述第一输入节点P11的电压信号为第一电压信号时，在所述输入时钟信号端KI提供的输入时钟信号的控制下，控制将所述第一输入节点P11的电压信号转换为所述第一节点P1的电压信号，且使得所述第一节点P1的电压信号的极性与所述第一输入节点P11的电压信号的极性相同，所述第一节点P1的电压信号的电压值的绝对值大于所述第一输入节点P11的电压信号的电压值的绝对值。
本公开实施例所述的栅极驱动单元能够通过电荷泵电路11在保持阶段充分拉低或升高第一节点P1的电位，使得在保持阶段，由P1控制的第一输出晶体管保持开启，进而使得在保持阶段，能够使得输出的栅极驱动信号的电位不受噪声干扰的影响。
所述第一节点P1的电压信号的极性与所述第一输入节点P11的电压信号的极性相同指的是：当P1的电压信号为正电压信号时，P11的电压信号为正 电压信号；当P1的电压信号为负电压信号时，P11的电压信号为负电压信号。
所述第一节点P1的电压信号的电压值的绝对值大于所述第一输入节点P11的电压信号的电压值的绝对值指的是：
当P11的电压信号为正电压信号时，P1的电压信号的电压值大于P11的电压信号的电压值；
当P11的电压信号为负电压信号时，P1的电压信号的电压值小于P11的电压信号的电压值。
本公开至少一实施例所述的栅极驱动单元在工作时，电荷泵结构能够在保持阶段进一步拉低或升高第一节点的电位。
本公开至少一实施例所述的栅极驱动单元在工作时，当P11的电位为-5V，P1的电位大于或等于-15V而小于或等于-10V，也即所述电荷泵电路可以将P11的电位泵低2-3倍，但不以此为限。
在具体实施时，所述栅极驱动单元可以包括输出电路，所述输出电路包括第一输出晶体管，所述第一输出晶体管的控制极与所述第一节点电连接，所述第一输出晶体管的第一极与输出电压端电连接，所述第一输出晶体管的第二极与栅极驱动信号输出端电连接。
可选的，所述第一输出晶体管为p型晶体管，第一电压信号为负电压信号；或者，
所述第一输出晶体管的n型晶体管，第一电压信号为正电压信号。
在具体实施时，当所述第一输出晶体管为p型晶体管时，第一电压信号可以为负电压信号，所述电荷泵结构需要进一步拉低第一节点的电位；当所述第一输出晶体管为n型晶体管时，第一电压信号可以为正电压信号，所述电荷泵结构需要进一步升高第一节点的电位；但不以此为限。在本公开至少一实施例中，栅极驱动单元的一工作周期可以包括依次设置的输入阶段、输出阶段、复位阶段和保持阶段，在输入阶段，输入端提供输入信号；在输出阶段，栅极驱动单元输出有效的栅极驱动信号；在复位阶段，对所述栅极驱动信号进行复位，使得栅极驱动单元输出无效的栅极驱动信号；在保持阶段，栅极驱动单元需要保持输出无效的栅极驱动信号。
在具体实施时，当像素电路包括的栅极接入所述栅极驱动信号的晶体管 为n型晶体管时，有效的栅极驱动信号的电位为高电压，无效的栅极驱动信号的电位为低电压；
当像素电路包括的栅极接入所述栅极驱动信号的晶体管为p型晶体管时，有效的栅极驱动信号的电位为低电压，无效的栅极驱动信号的电位为高电压。
根据一种具体实施方式，如图2所示，在图1所示的栅极驱动单元的实施例的基础上，所述电荷泵电路包括输入储能子电路21、通断控制子电路22和第一储能子电路23；
所述输入储能子电路21的第一端与所述输入时钟信号端KI电连接，所述输入储能子电路21的第二端与所述第一输入节点P11电连接，用于储存电能且根据所述输入时钟信号的电位控制所述第一输入节点P11的电位；
所述通断控制子电路22分别与所述第一输入节点P11和所述第一节点P1电连接，用于在所述第一输入节点P11的电位的控制下，导通或断开所述第一输入节点P11与所述第一节点P1之间的连接；
所述第一储能子电路23与所述第一节点P1电连接，用于储存电能且维持所述第一节点P1的电位。
在图2所示的栅极驱动单元的至少一实施例中，所述输入储能子电路21、所述通断控制子电路22和所述第一储能子电路23组成电荷泵电路。
在本公开至少一实施例中，所述输入储能子电路21包括的输入电容的电容值与所述第一储能子电路包括的第一存储电容的电容值之间的比值可以大于或等于1:1而小于或等于10:1，但不以此为限。
可选的，所述输入储能子电路包括输入电容，所述第一储能子电路包括第一存储电容，所述通断控制子电路包括通断控制晶体管；
所述输入电容的第一端与所述输入时钟信号端电连接，所述输入电容的第二端与所述第一输入节点电连接；
所述第一存储电容的第一端与所述第一节点电连接，所述第一存储电容的第二端与第二电压端电连接；
所述通断控制晶体管的控制极和所述通断控制晶体管的第一极与所述第一输入节点电连接，所述通断控制晶体管的第二极与所述第一节点电连接。
在具体实施时，所述输入储能子电路21和所述第一储能子电路23可以 包括电容，所述通断控制子电路22可以包括二极管连接的晶体管，但不以此为限。
根据另一种具体实施方式，如图3所示，在图1所示的栅极驱动单元的实施例的基础上，所述电荷泵电路包括输入储能子电路21、通断控制子电路22、开关控制子电路20和第一储能子电路23；
所述输入储能子电路21的第一端与第一控制节点P21电连接，所述输入储能子电路21的第二端与所述第一输入节点P11电连接，用于储存电能且根据第一控制节点P21的电位控制所述第一输入节点P11的电位；
所述通断控制子电路22分别与所述第一输入节点P11和所述第一节点P1电连接，用于在所述第一输入节点P11的电位的控制下，导通或断开所述第一输入节点P11与所述第一节点P1之间的连接；
所述第一储能子电路23与所述第一节点P1电连接，用于储存电能且维持所述第一节点P1的电位；
所述开关控制子电路20分别与所述第一输入节点P11、输入时钟信号端KI和所述第一控制节点P21电连接，用于在所述第一输入节点P11的电位的控制下，导通或断开所述输入时钟信号端KI与所述第一控制节点P21之间的连接。
在图3所示的栅极驱动单元的至少一实施例中，所述输入储能子电路21、所述通断控制子电路22、所述开关控制子电路20和所述第一储能子电路23组成电荷泵电路。
与图2所示的栅极驱动单元的至少一实施例相比，在图3所示的栅极驱动电路的至少一实施例中，所述电荷泵电路增设了开关控制子电路20，所述开关控制子电路20在所述第一输入节点P11的电位的控制下，导通或断开所述输入时钟信号端KI与所述第一控制节点P21之间的连接；所述开关控制子电路20能够控制输入时钟信号端KI是否与输入储能子电路21连通，控制是否通过输入时钟信号控制P11的电位。
可选的，所述输入储能子电路包括输入电容，所述第一储能子电路包括第一存储电容，所述通断控制子电路包括通断控制晶体管；
所述输入电容的第一端与所述第一控制节点电连接，所述输入电容的第 二端与所述第一输入节点电连接；
所述第一存储电容的第一端与所述第一节点电连接，所述第一存储电容的第二端与第二电压端电连接；
所述通断控制晶体管的控制极和所述通断控制晶体管的第一极与所述第一输入节点电连接，所述通断控制晶体管的第二极与所述第一节点电连接。
可选的，所述开关控制子电路包括开关控制晶体管；
所述开关控制晶体管的控制极与所述第一输入节点电连接，所述开关控制晶体管的第一极与所述输入时钟信号端电连接，所述开关控制晶体管的第二极与所述第一控制节点电连接。
在本公开至少一实施例中，所述输入电容的电容值与所述第一存储电容的电容值之间的比值大于或等于1而小于或等于10，但不以此为限。
在具体实施时，如图4所示，在图1所示的栅极驱动单元的实施例的基础上，所述第一输入节点控制电路可以包括第一隔离节点控制子电路41和第一隔离子电路42；
所述第一隔离节点控制子电路41分别与时钟信号端K0、输入端I1和第一隔离节点P31电连接，用于在所述时钟信号端K0提供的时钟信号的控制下，导通或断开所述输入端I1与所述第一隔离节点P31之间的连接；
所述第一隔离子电路42分别与第二电压端V2、所述第一隔离节点P31和所述第一输入节点P11电连接，用于在第二电压端V2提供的第二电压信号的控制下，控制所述第一隔离节点P31与所述第一输入节点P11之间连通。
在图4所示的栅极驱动单元的至少一实施例工作时，所述第一隔离子电路42控制所述第一隔离节点P31与所述第一输入节点P11之间连通，第一隔离节点控制子电路41在K0提供的时钟信号的控制下，控制是否将输入信号写入第一隔离节点P31。
根据一种具体实施方式，所述时钟信号端可以包括第一时钟信号端和第二时钟信号端；第一隔离节点控制子电路包括第一控制晶体管和第二控制晶体管；所述第一控制晶体管的控制极与所述第二时钟信号端电连接，所述第一控制晶体管的第一极与所述输入端电连接；所述第二控制晶体管的控制极与所述第一时钟信号端电连接，所述第二控制晶体管的第一极与所述第一控 制晶体管的第二极电连接，所述第二控制晶体管的第二极与所述第一隔离节点电连接。
根据另一种具体实施方式，所述时钟信号端可以包括第二时钟信号端，所述第一隔离节点控制子电路可以包括第一控制晶体管；所述第一控制晶体管的控制极与所述第二时钟信号端电连接，所述第一控制晶体管的第一极与所述输入端电连接，所述第一控制晶体管的第二极与所述第一隔离节点电连接。
根据再一种具体实施方式，所述时钟信号端可以包括第一时钟信号端，所述第一隔离节点控制子电路可以包括第二控制晶体管；所述第二控制晶体管的控制极与所述第一时钟信号端电连接，所述第一控制晶体管的第一极与所述输入端电连接，所述第二控制晶体管的第二极与所述第一隔离节点电连接。
在实际操作时，所述第一隔离节点控制子电路可以仅包括第一控制晶体管，该第一控制晶体管的控制极与所述第二时钟信号端电连接，前提是第二时钟信号的上升沿不早于输入端提供的输入信号的下降沿；或者，
所述第一隔离节点控制子电路可以仅包括第二控制晶体管，该第二控制晶体管的控制极与所述第一时钟信号端电连接，前提是第一时钟信号的上升沿不早于输入端提供的输入信号的下降沿。
可选的，所述第一隔离子电路包括第一隔离晶体管；
所述第一隔离晶体管的控制极与所述第二电压端电连接，所述第一隔离晶体管的第一极与所述第一隔离节点电连接，所述第一隔离晶体管的第二极与所述第一输入节点电连接。
在具体实施时，当所述第一隔离晶体管为p型晶体管时，所述第二电压端可以为低电压端；当所述第一隔离晶体管为n型晶体管时，所述第二电压端可以为高电压端，以使得所述第一隔离晶体管常开。
在优选情况下，在所述第一输入节点控制电路中，可以增加第一隔离晶体管，以能够减小降低第一隔离节点的漏电，提升输出响应速度。
如图5所示，在图1所示的栅极驱动单元的实施例的基础上，本公开所述的栅极驱动单元的至少一实施例还包括第一节点控制电路12；所述第一节 点控制电路12分别与第二输入节点P12、第三电压端V3和第一节点P1电连接，用于在所述第二输入节点P12的电位的控制下，控制将第三电压信号写入所述第一节点P1；
所述第三电压端V3用于提供所述第三电压信号。
在本公开至少一实施例中，所述第三电压端V3可以为高电压端，所述第三电压信号可以为高电压信号，但不以此为限。
在图5所示的栅极驱动单元的至少一实施例中，本公开至少一实施例所述的栅极驱动单元还可以包括第一节点控制电路12，第一节点控制电路12在第二输入节点P12的电位的控制下，控制第一节点P1的电位。
根据一种具体实施方式，本公开至少一实施例所述的栅极驱动单元还可以包括第一储能电路；
所述第一储能电路分别与第二节点和第二时钟信号端电连接，用于根据第二时钟信号控制所述第二节点的电位。
在本公开至少一实施例中，所述栅极驱动单元还可以包括第一储能电路，在优选情况下，所述第一储能电路可以根据第二时钟信号控制第二节点的电位，以使得在复位阶段，可以通过第二时钟信号改变第二节点的电位，以能够通过第一节点控制的第一输出晶体管和第二节点控制的第二输出晶体管同时对栅极驱动单元输出的栅极驱动信号进行复位，实现对栅极驱动信号的完全、快速的复位。
根据另一种具体实施方式，本公开至少一实施例所述的栅极驱动单元还可以包括栅极驱动信号输出端和第一储能电路；
所述第一储能电路分别与第二节点和栅极驱动信号输出端电连接，用于根据所述栅极驱动信号输出端输出的栅极驱动信号，控制第二节点的电位。
在本公开至少一实施例中，所述栅极驱动单元还可以包括第一储能电路，在优选情况下，第一储能电路与栅极驱动单元的栅极驱动信号输出端电连接，减少了第一储能电路的电容负载，有利于降低功耗。
具体的，本公开至少一实施例所述的栅极驱动单元还可以包括栅极驱动信号输出端和输出电路；
所述输出电路分别与第一节点、第二节点、栅极驱动信号输出端、输出 电压端和第二时钟信号输出端电连接，用于在第一节点的电位的控制下，控制将输出电压信号写入所述栅极驱动信号输出端，并在第二节点的电位的控制下，将第二时钟信号写入所述栅极驱动信号输出端；
所述输出电压端用于提供输出电压信号。
在具体实施时，所述栅极驱动单元可以包括栅极驱动信号输出端和输出电路，输出电路在第一节点的电位和第二节点的电位的控制下，控制输出栅极驱动信号。
可选的，所述输出电路包括第一输出晶体管和第二输出晶体管；
所述第一输出晶体管的控制极与所述第一节点电连接，所述第一输出晶体管的第一极与所述输出电压端电连接，所述第一输出晶体管的第二极与所述栅极驱动信号输出端电连接；
所述第二输出晶体管的控制极与所述第二节点电连接，所述第二输出晶体管的第一极与所述栅极驱动信号输出端电连接，所述第二输出晶体管的第二极与所述第二时钟信号端电连接。
具体的，本公开至少一实施例所述的栅极驱动单元还可以包括第二节点控制电路；
所述第二节点控制电路包括第三输入节点控制子电路、第二输入节点控制子电路和第二节点控制子电路；
所述第三输入节点控制子电路分别与第一时钟信号端、第二电压端、第一输入节点和第三输入节点电连接，用于在第一时钟信号的控制下，将第二电压信号写入所述第三输入节点，并用于在第一输入节点的电位的控制下，将第一时钟信号写入所述第三输入节点；
所述第二输入节点控制子电路分别与所述第三输入节点、第二输入节点和输入时钟信号端电连接，用于在所述第三输入节点的电位的控制下将输入时钟信号写入所述第二输入节点，并用于根据所述第三输入节点的电位控制第二输入节点的电位；
所述第二节点控制子电路分别与所述第二输入节点、第一输入节点、第二节点和输入时钟信号端电连接，所述第二节点控制子电路还与第二时钟信号端或第三电压端电连接，用于在输入时钟信号的控制下，导通或断开所述 第二输入节点与所述第二节点之间的连接，并用于在所述第一输入节点的电位的控制下，将第二时钟信号或第三电压信号写入第二节点。
在具体实施时，所述栅极驱动单元还可以包括第二节点控制电路，第二节点控制电路包括第三输入节点控制子电路、第二输入节点控制子电路和第二节点控制子电路，第三输入节点控制子电路控制第三输入节点的电位，第二输入节点控制子电路控制第二输入节点的电位，第二节点控制子电路控制第二节点的电位。
可选的，所述第三输入节点控制子电路包括第三控制晶体管和第四控制晶体管，其中，
所述第三控制晶体管的控制极与第一时钟信号端电连接，所述第三控制晶体管的第一极与第二电压端电连接，所述第三控制晶体管的第二极与第三输入节点电连接；
所述第四控制晶体管的控制极与所述第一输入节点电连接，所述第四控制晶体管的第一极与所述第一时钟信号端电连接，所述第四控制晶体管的第二极与所述第三输入节点电连接。
在具体实施时，本公开至少一实施例所述的栅极驱动单元还可以包括第二节点控制电路；
所述第二节点控制电路包括第三输入节点控制子电路、第二输入节点控制子电路和第二节点控制子电路；
所述第三输入节点控制子电路分别与第一时钟信号端、第二电压端、第一隔离节点和第三输入节点电连接，用于在第一时钟信号的控制下，将第二电压信号写入所述第三输入节点，并用于在第一隔离节点的电位的控制下，将第一时钟信号写入所述第三输入节点；
所述第二输入节点控制子电路分别与所述第三输入节点、第二输入节点和输入时钟信号端电连接，用于在所述第三输入节点的电位的控制下将输入时钟信号写入所述第二输入节点，并用于根据所述第三输入节点的电位控制第二输入节点的电位；
所述第二节点控制子电路分别与所述第二输入节点、第一输入节点、第二节点和输入时钟信号端电连接，所述第二节点控制子电路还与第二时钟信 号端或第三电压端电连接，用于在输入时钟信号的控制下，导通或断开所述第二输入节点与所述第二节点之间的连接，并用于在所述第一输入节点的电位的控制下，将第二时钟信号或第三电压信号写入第二节点。
可选的，所述第三输入节点控制子电路包括第三控制晶体管和第四控制晶体管，其中，
所述第三控制晶体管的控制极与第一时钟信号端电连接，所述第三控制晶体管的第一极与第二电压端电连接，所述第三控制晶体管的第二极与第三输入节点电连接；
所述第四控制晶体管的控制极与所述第一隔离节点电连接，所述第四控制晶体管的第一极与所述第一时钟信号端电连接，所述第四控制晶体管的第二极与所述第三输入节点电连接。
可选的，所述第三输入节点控制子电路包括第三控制晶体管、第四控制晶体管和第二隔离晶体管；
所述第三控制晶体管的控制极与第一时钟信号端电连接，所述第三控制晶体管的第一极与第二电压端电连接，所述第三控制晶体管的第二极与第二隔离节点电连接；
所述第四控制晶体管的控制极与所述第一隔离节点电连接，所述第四控制晶体管的第一极与所述第一时钟信号端电连接，所述第四控制晶体管的第二极与所述第二隔离节点电连接；
所述第二隔离晶体管的控制极与第二电压端电连接，所述第二隔离晶体管的第一极与第二隔离节点电连接，所述第二隔离晶体管的第二极与第三输入节点电连接。
在优选情况下，所述第三输入节点控制子电路可以采用第二隔离晶体管，以防止对第三输入节点的漏电。
可选的，所述第二输入节点控制子电路包括第五控制晶体管和第一电容；
所述第五控制晶体管的控制极与所述第三输入节点电连接，所述第五控制晶体管的第一极与所述第二输入节点电连接，所述第五控制晶体管的第二极与输入时钟信号端电连接；
所述第一电容的第一端与所述第三输入节点电连接，所述第一电容的第 二端与所述第二输入节点电连接。
可选的，所述第二节点控制子电路包括第六控制晶体管和第七控制晶体管；
所述第六控制晶体管的控制极与输入时钟信号端电连接，所述第六控制晶体管的第一极与所述第二输入节点电连接，所述第六控制晶体管的第二极与所述第二节点电连接；
所述第七控制晶体管的控制极与所述第一隔离节点电连接，所述第七控制晶体管的第一极与第二时钟信号端或第三电压端电连接，所述第七控制晶体管的第二极与所述第二节点电连接。
如图6所示，在图5所示的栅极驱动单元的至少一实施例的基础上，本公开至少一实施例所述的栅极驱动单元还可以包括第一储能电路31、栅极驱动信号输出端O1、输出电路30和第二节点控制电路；
所述第一储能电路31分别与第二节点P2和第二时钟信号端K2电连接，用于根据第二时钟信号控制所述第二节点P2的电位；所述第二时钟信号端K2用于提供所述第二时钟信号；
所述输出电路30分别与第一节点P1、第二节点P2、栅极驱动信号输出端O1、输出电压端V0和第二时钟信号输出端K2电连接，用于在第一节点P1的电位的控制下，控制将输出电压信号写入所述栅极驱动信号输出端O1，并在第二节点P2的电位的控制下，将第二时钟信号写入所述栅极驱动信号输出端O1；所述输出电压端V0用于提供输出电压信号；
所述第二节点控制电路包括第三输入节点控制子电路32、第二输入节点控制子电路33和第二节点控制子电路34；
所述第三输入节点控制子电路32分别与第一时钟信号端K1、第二电压端V2、第一输入节点P11和第三输入节点P13电连接，用于在第一时钟信号的控制下，将第二电压信号写入所述第三输入节点P13，并用于在第一输入节点P11的电位的控制下，将第一时钟信号写入所述第三输入节点P13；所述第一时钟信号端K1用于提供所述第一时钟信号；
所述第二输入节点控制子电路33分别与所述第三输入节点P13、第二输入节点P12和输入时钟信号端KI电连接，用于在所述第三输入节点P13的电 位的控制下将输入时钟信号写入所述第二输入节点P12，并用于根据所述第三输入节点P13的电位控制第二输入节点P12的电位；所述输入时钟信号端KI用于提供所述输入时钟信号；
所述第二节点控制子电路34分别与输入时钟信号端KI、第二输入节点P12、第二节点P2、第一输入节点P11和第二时钟信号端K2电连接，用于在输入时钟信号的控制下，导通或断开所述第二输入节点P12与所述第二节点P2之间的连接，并用于在所述第一输入节点P11的电位的控制下，将第二时钟信号写入第二节点P2。
在本公开至少一实施例中，所述输出电压信号可以为低电压信号，但不以此为限。
如图7所示，在图5所示的栅极驱动单元的至少一实施例的基础上，本公开至少一实施例所述的栅极驱动单元还可以包括第一储能电路31、栅极驱动信号输出端O1、输出电路30和第二节点控制电路；
所述第一储能电路31分别与第二节点P2和所述栅极驱动信号输出端O1电连接，用于根据所述栅极驱动信号输出端O1输出的栅极驱动信号，控制第二节点P2的电位；
所述输出电路30分别与第一节点P1、第二节点P2、栅极驱动信号输出端O1、输出电压端V0和第二时钟信号输出端K2电连接，用于在第一节点P1的电位的控制下，控制将输出电压信号写入所述栅极驱动信号输出端O1，并在第二节点P2的电位的控制下，将第二时钟信号写入所述栅极驱动信号输出端O1；所述输出电压端V0用于提供输出电压信号；
所述第二节点控制电路包括第三输入节点控制子电路32、第二输入节点控制子电路33和第二节点控制子电路34；
所述第三输入节点控制子电路32分别与第一时钟信号端K1、第二电压端V2、第一输入节点P11和第三输入节点P13电连接，用于在第一时钟信号的控制下，将第二电压信号写入所述第三输入节点P13，并用于在第一输入节点P11的电位的控制下，将第一时钟信号写入所述第三输入节点P13；所述第一时钟信号端K1用于提供所述第一时钟信号；
所述第二输入节点控制子电路33分别与所述第三输入节点P13、第二输 入节点P12和输入时钟信号端KI电连接，用于在所述第三输入节点P13的电位的控制下将输入时钟信号写入所述第二输入节点P12，并用于根据所述第三输入节点P13的电位控制第二输入节点P12的电位；所述输入时钟信号端KI用于提供所述输入时钟信号；
所述第二节点控制子电路34分别与输入时钟信号端KI、第二输入节点P12、第二节点P2、第一输入节点P11、第二时钟信号端K2和第二节点P2电连接，用于在输入时钟信号的控制下，导通或断开所述第二输入节点P12与所述第二节点P2之间的连接，并用于在所述第一输入节点P11的电位的控制下，将第二时钟信号写入第二节点P2。
图7所示的栅极驱动单元的至少一实施例与图6所示的栅极驱动单元的至少一实施例的区别在于：所述第一储能电路31与所述栅极驱动信号输出端O1电连接，用于根据所述栅极驱动信号输出端O1输出的栅极驱动信号，控制第二节点P2的电位。
如图8所示，在图5所示的栅极驱动单元的至少一实施例的基础上，本公开至少一实施例所述的栅极驱动单元还可以包括第一储能电路31、栅极驱动信号输出端O1、输出电路30和第二节点控制电路；
所述第一储能电路31分别与第二节点P2和第二时钟信号端K2电连接，用于根据第二时钟信号控制所述第二节点P2的电位；所述第二时钟信号端K2用于提供所述第二时钟信号；
所述输出电路30分别与第一节点P1、第二节点P2、栅极驱动信号输出端O1、输出电压端V0和第二时钟信号输出端K2电连接，用于在第一节点P1的电位的控制下，控制将输出电压信号写入所述栅极驱动信号输出端O1，并在第二节点P2的电位的控制下，将第二时钟信号写入所述栅极驱动信号输出端O1；所述输出电压端V0用于提供输出电压信号；
所述第二节点控制电路包括第三输入节点控制子电路32、第二输入节点控制子电路33和第二节点控制子电路34；
所述第三输入节点控制子电路32分别与第一时钟信号端K1、第二电压端V2、第一输入节点P11和第三输入节点P13电连接，用于在第一时钟信号的控制下，将第二电压信号写入所述第三输入节点P13，并用于在第一输入 节点P11的电位的控制下，将第一时钟信号写入所述第三输入节点P13；所述第一时钟信号端K1用于提供所述第一时钟信号；
所述第二输入节点控制子电路33分别与所述第三输入节点P13、第二输入节点P12和输入时钟信号端KI电连接，用于在所述第三输入节点P13的电位的控制下将输入时钟信号写入所述第二输入节点P12，并用于根据所述第三输入节点P13的电位控制第二输入节点P12的电位；所述输入时钟信号端KI用于提供所述输入时钟信号；
所述第二节点控制子电路34分别与输入时钟信号端KI、第二输入节点P12、第二节点P2、第一输入节点P11、第三电压端V3和第二节点P2电连接，用于在输入时钟信号的控制下，导通或断开所述第二输入节点P12与所述第二节点P2之间的连接，并用于在所述第一输入节点P11的电位的控制下，将第三电压信号写入第二节点P2；所述第三电压端V3用于提供所述第三电压信号。
图8所示的栅极驱动单元的至少一实施例与图6所示的栅极驱动单元的至少一实施例的区别在于：所述第二节点控制子电路34与第三电压端V3电连接，用于在所述第一输入节点P11的电位的控制下，将第三电压信号写入第二节点P2。
如图9所示，在图5所示的栅极驱动单元的至少一实施例的基础上，本公开至少一实施例所述的栅极驱动单元还可以包括第一储能电路31、栅极驱动信号输出端O1、输出电路30和第二节点控制电路；
所述第一储能电路31分别与第二节点P2和所述栅极驱动信号输出端O1电连接，用于根据所述栅极驱动信号输出端O1输出的栅极驱动信号，控制第二节点P2的电位；
所述输出电路30分别与第一节点P1、第二节点P2、栅极驱动信号输出端O1、输出电压端V0和第二时钟信号输出端K2电连接，用于在第一节点P1的电位的控制下，控制将输出电压信号写入所述栅极驱动信号输出端O1，并在第二节点P2的电位的控制下，将第二时钟信号写入所述栅极驱动信号输出端O1；所述输出电压端V0用于提供输出电压信号；
所述第二节点控制电路包括第三输入节点控制子电路32、第二输入节点 控制子电路33和第二节点控制子电路34；
所述第三输入节点控制子电路32分别与第一时钟信号端K1、第二电压端V2、第一输入节点P11和第三输入节点P13电连接，用于在第一时钟信号的控制下，将第二电压信号写入所述第三输入节点P13，并用于在第一输入节点P11的电位的控制下，将第一时钟信号写入所述第三输入节点P13；所述第一时钟信号端K1用于提供所述第一时钟信号；
所述第二输入节点控制子电路33分别与所述第三输入节点P13、第二输入节点P12和输入时钟信号端KI电连接，用于在所述第三输入节点P13的电位的控制下将输入时钟信号写入所述第二输入节点P12，并用于根据所述第三输入节点P13的电位控制第二输入节点P12的电位；所述输入时钟信号端KI用于提供所述输入时钟信号；
所述第二节点控制子电路34分别与输入时钟信号端KI、第二输入节点P12、第二节点P2、第一输入节点P11、第三电压端V3和第二节点P2电连接，用于在输入时钟信号的控制下，导通或断开所述第二输入节点P12与所述第二节点P2之间的连接，并用于在所述第一输入节点P11的电位的控制下，将第三电压信号写入第二节点P2。
图9所示的栅极驱动单元的至少一实施例与图7所示的栅极驱动单元的至少一实施例的区别在于：所述第二节点控制子电路34与第三电压端V3电连接，用于在所述第一输入节点P11的电位的控制下，将第三电压信号写入第二节点P2。
如图10所示，在图5所示的栅极驱动单元的至少一实施例的基础上，本公开至少一实施例所述的栅极驱动单元还可以包括第一储能电路31、栅极驱动信号输出端O1、输出电路30和第二节点控制电路；
所述第一输入节点控制电路可以包括第一隔离节点控制子电路41和第一隔离子电路42；
所述第一隔离节点控制子电路41分别与时钟信号端K0、输入端I1和第一隔离节点P31电连接，用于在所述时钟信号端K0提供的时钟信号的控制下，导通或断开所述输入端I1与所述第一隔离节点P31之间的连接；
所述第一隔离子电路42分别与第二电压端V2、所述第一隔离节点P31 和所述第一输入节点P11电连接，用于在第二电压端V2提供的第二电压信号的控制下，控制所述第一隔离节点P31与所述第一输入节点P11之间连通；
所述第一储能电路31分别与第二节点P2和第二时钟信号端K2电连接，用于根据第二时钟信号控制所述第二节点P2的电位；所述第二时钟信号端K2用于提供所述第二时钟信号；
所述输出电路30分别与第一节点P1、第二节点P2、栅极驱动信号输出端O1、输出电压端V0和第二时钟信号输出端K2电连接，用于在第一节点P1的电位的控制下，控制将输出电压信号写入所述栅极驱动信号输出端O1，并在第二节点P2的电位的控制下，将第二时钟信号写入所述栅极驱动信号输出端O1；所述输出电压端V0用于提供输出电压信号；
所述第二节点控制电路包括第三输入节点控制子电路32、第二输入节点控制子电路33和第二节点控制子电路34；
所述第三输入节点控制子电路32分别与第一时钟信号端K1、第二电压端V2、第一隔离节点P31和第三输入节点P13电连接，用于在第一时钟信号的控制下，将第二电压信号写入所述第三输入节点P13，并用于在第一隔离节点P31的电位的控制下，将第一时钟信号写入所述第三输入节点P13；所述第一时钟信号端K1用于提供所述第一时钟信号；
所述第二输入节点控制子电路33分别与所述第三输入节点P13、第二输入节点P12和输入时钟信号端KI电连接，用于在所述第三输入节点P13的电位的控制下将输入时钟信号写入所述第二输入节点P12，并用于根据所述第三输入节点P13的电位控制第二输入节点P12的电位；所述输入时钟信号端KI用于提供所述输入时钟信号；
所述第二节点控制子电路34分别与输入时钟信号端KI、第二输入节点P12、第二节点P2、第一输入节点P11和第二时钟信号端K2电连接，用于在输入时钟信号的控制下，导通或断开所述第二输入节点P12与所述第二节点P2之间的连接，并用于在所述第一输入节点P11的电位的控制下，将第二时钟信号写入第二节点P2。
本公开如图10所示的栅极驱动单元的至少一实施例与本公开如图6所示的栅极驱动单元的至少一实施例的区别如下：所述第一输入节点控制电路包 括第一隔离节点控制子电路41和第一隔离子电路42，所述第三输入节点控制子电路32与第一隔离节点P31电连接，而非与第一输入节点电连接。
如图11所示，在图5所示的栅极驱动单元的至少一实施例的基础上，本公开至少一实施例所述的栅极驱动单元还可以包括第一储能电路31、栅极驱动信号输出端O1、输出电路30和第二节点控制电路；
所述第一输入节点控制电路可以包括第一隔离节点控制子电路41和第一隔离子电路42；
所述第一隔离节点控制子电路41分别与时钟信号端K0、输入端I1和第一隔离节点P31电连接，用于在所述时钟信号端K0提供的时钟信号的控制下，导通或断开所述输入端I1与所述第一隔离节点P31之间的连接；
所述第一隔离子电路42分别与第二电压端V2、所述第一隔离节点P31和所述第一输入节点P11电连接，用于在第二电压端V2提供的第二电压信号的控制下，控制所述第一隔离节点P31与所述第一输入节点P11之间连通；
所述第一储能电路31分别与第二节点P2和所述栅极驱动信号输出端O1电连接，用于根据所述栅极驱动信号输出端O1输出的栅极驱动信号，控制第二节点P2的电位；
所述输出电路30分别与第一节点P1、第二节点P2、栅极驱动信号输出端O1、输出电压端V0和第二时钟信号输出端K2电连接，用于在第一节点P1的电位的控制下，控制将输出电压信号写入所述栅极驱动信号输出端O1，并在第二节点P2的电位的控制下，将第二时钟信号写入所述栅极驱动信号输出端O1；所述输出电压端V0用于提供输出电压信号；
所述第二节点控制电路包括第三输入节点控制子电路32、第二输入节点控制子电路33和第二节点控制子电路34；
所述第三输入节点控制子电路32分别与第一时钟信号端K1、第二电压端V2、第一隔离节点P31和第三输入节点P13电连接，用于在第一时钟信号的控制下，将第二电压信号写入所述第三输入节点P13，并用于在第一隔离节点P31的电位的控制下，将第一时钟信号写入所述第三输入节点P13；所述第一时钟信号端K1用于提供所述第一时钟信号；
所述第二输入节点控制子电路33分别与所述第三输入节点P13、第二输 入节点P12和输入时钟信号端KI电连接，用于在所述第三输入节点P13的电位的控制下将输入时钟信号写入所述第二输入节点P12，并用于根据所述第三输入节点P13的电位控制第二输入节点P12的电位；所述输入时钟信号端KI用于提供所述输入时钟信号；
所述第二节点控制子电路34分别与输入时钟信号端KI、第二输入节点P12、第二节点P2、第一输入节点P11、第二时钟信号端K2和第二节点P2电连接，用于在输入时钟信号的控制下，导通或断开所述第二输入节点P12与所述第二节点P2之间的连接，并用于在所述第一输入节点P11的电位的控制下，将第二时钟信号写入第二节点P2。
本公开如图11所示的栅极驱动单元的至少一实施例与本公开如图7所示的栅极驱动单元的至少一实施例的区别如下：所述第一输入节点控制电路包括第一隔离节点控制子电路41和第一隔离子电路42，所述第三输入节点控制子电路32与第一隔离节点P31电连接，而非与第一输入节点电连接。
如图12所示，在图5所示的栅极驱动单元的至少一实施例的基础上，本公开至少一实施例所述的栅极驱动单元还可以包括第一储能电路31、栅极驱动信号输出端O1、输出电路30和第二节点控制电路；
所述第一输入节点控制电路可以包括第一隔离节点控制子电路41和第一隔离子电路42；
所述第一隔离节点控制子电路41分别与时钟信号端K0、输入端I1和第一隔离节点P31电连接，用于在所述时钟信号端K0提供的时钟信号的控制下，导通或断开所述输入端I1与所述第一隔离节点P31之间的连接；
所述第一隔离子电路42分别与第二电压端V2、所述第一隔离节点P31和所述第一输入节点P11电连接，用于在第二电压端V2提供的第二电压信号的控制下，控制所述第一隔离节点P31与所述第一输入节点P11之间连通；
所述第一储能电路31分别与第二节点P2和第二时钟信号端K2电连接，用于根据第二时钟信号控制所述第二节点P2的电位；所述第二时钟信号端K2用于提供所述第二时钟信号；
所述输出电路30分别与第一节点P1、第二节点P2、栅极驱动信号输出端O1、输出电压端V0和第二时钟信号输出端K2电连接，用于在第一节点 P1的电位的控制下，控制将输出电压信号写入所述栅极驱动信号输出端O1，并在第二节点P2的电位的控制下，将第二时钟信号写入所述栅极驱动信号输出端O1；所述输出电压端V0用于提供输出电压信号；
所述第二节点控制电路包括第三输入节点控制子电路32、第二输入节点控制子电路33和第二节点控制子电路34；
所述第三输入节点控制子电路32分别与第一时钟信号端K1、第二电压端V2、第一隔离节点P31和第三输入节点P13电连接，用于在第一时钟信号的控制下，将第二电压信号写入所述第三输入节点P13，并用于在第一隔离节点P31的电位的控制下，将第一时钟信号写入所述第三输入节点P13；所述第一时钟信号端K1用于提供所述第一时钟信号；
所述第二输入节点控制子电路33分别与所述第三输入节点P13、第二输入节点P12和输入时钟信号端KI电连接，用于在所述第三输入节点P13的电位的控制下将输入时钟信号写入所述第二输入节点P12，并用于根据所述第三输入节点P13的电位控制第二输入节点P12的电位；所述输入时钟信号端KI用于提供所述输入时钟信号；
所述第二节点控制子电路34分别与输入时钟信号端KI、第二输入节点P12、第二节点P2、第一输入节点P11、第三电压端V3和第二节点P2电连接，用于在输入时钟信号的控制下，导通或断开所述第二输入节点P12与所述第二节点P2之间的连接，并用于在所述第一输入节点P11的电位的控制下，将第三电压信号写入第二节点P2；所述第三电压端V3用于提供所述第三电压信号。
本公开如图12所示的栅极驱动单元的至少一实施例与本公开如图8所示的栅极驱动单元的至少一实施例的区别如下：所述第一输入节点控制电路包括第一隔离节点控制子电路41和第一隔离子电路42，所述第三输入节点控制子电路32与第一隔离节点P31电连接，而非与第一输入节点电连接。
如图13所示，在图5所示的栅极驱动单元的至少一实施例的基础上，本公开至少一实施例所述的栅极驱动单元还可以包括第一储能电路31、栅极驱动信号输出端O1、输出电路30和第二节点控制电路；
所述第一输入节点控制电路可以包括第一隔离节点控制子电路41和第 一隔离子电路42；
所述第一隔离节点控制子电路41分别与时钟信号端K0、输入端I1和第一隔离节点P31电连接，用于在所述时钟信号端K0提供的时钟信号的控制下，导通或断开所述输入端I1与所述第一隔离节点P31之间的连接；
所述第一隔离子电路42分别与第二电压端V2、所述第一隔离节点P31和所述第一输入节点P11电连接，用于在第二电压端V2提供的第二电压信号的控制下，控制所述第一隔离节点P31与所述第一输入节点P11之间连通；
所述第一储能电路31分别与第二节点P2和所述栅极驱动信号输出端O1电连接，用于根据所述栅极驱动信号输出端O1输出的栅极驱动信号，控制第二节点P2的电位；
所述输出电路30分别与第一节点P1、第二节点P2、栅极驱动信号输出端O1、输出电压端V0和第二时钟信号输出端K2电连接，用于在第一节点P1的电位的控制下，控制将输出电压信号写入所述栅极驱动信号输出端O1，并在第二节点P2的电位的控制下，将第二时钟信号写入所述栅极驱动信号输出端O1；所述输出电压端V0用于提供输出电压信号；
所述第二节点控制电路包括第三输入节点控制子电路32、第二输入节点控制子电路33和第二节点控制子电路34；
所述第三输入节点控制子电路32分别与第一时钟信号端K1、第二电压端V2、第一输入节点P11和第三输入节点P13电连接，用于在第一时钟信号的控制下，将第二电压信号写入所述第三输入节点P13，并用于在第一输入节点P11的电位的控制下，将第一时钟信号写入所述第三输入节点P13；所述第一时钟信号端K1用于提供所述第一时钟信号；
所述第二输入节点控制子电路33分别与所述第三输入节点P13、第二输入节点P12和输入时钟信号端KI电连接，用于在所述第三输入节点P13的电位的控制下将输入时钟信号写入所述第二输入节点P12，并用于根据所述第三输入节点P13的电位控制第二输入节点P12的电位；所述输入时钟信号端KI用于提供所述输入时钟信号；
所述第二节点控制子电路34分别与输入时钟信号端KI、第二输入节点P12、第二节点P2、第一隔离节点P31、第三电压端V3和第二节点P2电连 接，用于在输入时钟信号的控制下，导通或断开所述第二输入节点P12与所述第二节点P2之间的连接，并用于在所述第一隔离节点P31的电位的控制下，将第三电压信号写入第二节点P2。
本公开如图13所示的栅极驱动单元的至少一实施例与本公开如图9所示的栅极驱动单元的至少一实施例的区别如下：所述第一输入节点控制电路包括第一隔离节点控制子电路41和第一隔离子电路42，所述第三输入节点控制子电路32与第一隔离节点P31电连接，而非与第一输入节点电连接。
如图14所示，在图6所示的栅极驱动单元的至少一实施例的基础上，在本公开所述的栅极驱动单元的至少一实施例中，
所述第一输入节点控制电路10包括第一控制晶体管T12和第二控制晶体管T1，其中，
所述第一控制晶体管T12的栅极与所述第二时钟信号端K2电连接，所述第一控制晶体管T12的源极与所述输入端电连接；
所述第二控制晶体管T1的栅极与所述第一时钟信号端K1电连接，所述第二控制晶体管T1的源极与所述第一控制晶体管T12的漏极电连接，所述第二控制晶体管T1的漏极与所述第一输入节点P11电连接；
所述输入储能子电路21包括输入电容C4，所述通断控制子电路22包括通断控制晶体管T5，所述第一储能子电路23包括第一存储电容C3；C4的第一端与输入时钟信号端KI电连接，C4的第二端与所述第一输入节点P11电连接；
T5的栅极与T5的源极都与所述第一输入节点P11电连接，T5的漏极与所述第一节点P1电连接；
C3的第一端与所述第一节点P1电连接，C3的第二端与低电压端电连接；所述低电压端用于提供低电压VSS；
所述第一节点控制电路12包括第一节点控制晶体管T11；
T11的栅极与所述第二输入节点P12电连接，T11的源极与高电压端电连接，T11的漏极与所述第一节点P1电连接；所述高电压端用于提供高电压VDD；
所述第一储能电路31包括第二存储电容C2；
C2的第一端与第二节点P2电连接，C2的第二端与第二时钟信号输出端K2电连接；
所述输出电路30包括第一输出晶体管T10和第二输出晶体管T9；
所述第一输出晶体管T10的栅极与所述第一节点P1电连接，所述第一输出晶体管T10的源极与所述低电压端电连接，所述第一输出晶体管T10的漏极与所述栅极驱动信号输出端O1电连接；
所述第二输出晶体管T9的栅极与所述第二节点P2电连接，所述第二输出晶体管T9的源极与所述栅极驱动信号输出端O1电连接，所述第二输出晶体管T9的第二极与所述第二时钟信号端K2电连接；
所述第三输入节点控制子电路32包括第三控制晶体管T3和第四控制晶体管T2，其中，
T3的栅极与第一时钟信号端K1电连接，T3的源极与所述低电压端电连接，T3的漏极与第三输入节点P13电连接；
T2的栅极与所述第一输入节点P11电连接，T2的源极与所述第一时钟信号端K1电连接，T2的漏极与所述第三输入节点P13电连接；
所述第二输入节点控制子电路33包括第五控制晶体管T6和第一电容C1；
T6的栅极与所述第三输入节点P13电连接，所述第八控制晶体管T6的源极与所述第二输入节点P12电连接，所述第八控制晶体管T6的漏极与输入时钟信号端KI电连接；
所述第一电容C1的第一端与所述第三输入节点P13电连接，所述第一电容C1的第二端与所述第二输入节点P12电连接；
所述第二节点控制子电路34包括第六控制晶体管T7和第七控制晶体管T8；
T7的栅极与输入时钟信号端KI电连接，T7的源极与所述第二输入节点P12电连接，T7的漏极与所述第二节点P2电连接；
T8的栅极与所述第一输入节点P11电连接，T8的源极与第二时钟信号端K2电连接，T8的漏极与所述第二节点P2电连接。
在图14所示的至少一实施例中，所有的晶体管都为p型薄膜晶体管，第一电压信号为负电压信号，第二电压端为低电压端，第三电压端为高电压端， 输出电压端为低电压端，但不以此为限。
在图14所示的至少一实施例中，C4的电容值与C1的电容值的比值可以大于或等于1而小于或等于10，但不以此为限。
本公开至少一实施例所述的栅极驱动单元在工作时，P1的电位与C3的电容值、C4的电容值、T13的寄生电容、T4的寄生电容，以及T5的寄生电容有关，而不是直接与C4的电容值与C3的电容值的比值相关，通过增大C4的电容值，会降低P1的电位，但是P1的电位不会无限制的降低。
如图15所示，如图14所示的栅极驱动单元的至少一实施例在工作时，
在输入阶段t1，K1提供低电压，KI提供高电压，K2提供低电压，I1提供高电压，T12和T1打开，P11的电位为高电压，T5关断；T2关断，T3打开，P13的电位为低电压，T6打开，P12的电位为高电压，T7关闭，T8关闭，T11关闭，P1的电位维持为低电压，P2的电位维持为高电压，T10打开，T9关闭，O1输出低电压；
在输出阶段t2，K1提供高电压，KI提供低电压，K2提供高电压，I1提供低电压，T12和T1都关断，P11的电位维持为高电压，T5关闭，P13的电位被C1进一步拉低，T6打开，P12的电位为低电压，T7打开，T8关闭，T11打开，P1的电位为高电压，P2的电位为低电压，T9打开，T10关闭，O1输出高电压；
在复位阶段t3，K1提供低电压，KI提供高电压，K2提供低电压，I1提供低电压，T12和T1都打开，P11的电位被拉低，T5打开，P1的电位被拉低；T10打开；并此时T8打开，并P2的电位被K2提供的第二时钟信号拉低，T9也打开，通过T9和T10同时为栅极驱动信号输出端放电，可以提升栅极驱动信号输出端的放电速度，从而实现对栅极驱动信号的完全、快速的复位；
在保持阶段包括的第一保持时间段t4，K1提供高电压，KI提供低电压，K2提供高电压，I1提供低电压，T12和T1都关闭，KI通过C4拉低P11的电位，T5打开，进而使得P1的电位维持为低于VSS+Vth，Vth为T10的阈值电压，使得T10开启，进而使得O1输出的栅极驱动信号的电位维持为VSS，不受噪声干扰影响；T3关断，T2打开，P13的电位为高电压，T6关断，P12 的电位为高电压，T7打开，P2的电位为高电压，T9关断；
在保持阶段包括的第二保持时间段t5，K1提供低电压，KI提供高电压，K2提供低电压，I1提供低电压，T12和T1都打开，KI提供的输入时钟信号的电位升高，从而拉升P11的电位，T5关闭，不影响P1的电位，使得P1的电位维持为低于VSS+Vth，Vth为T10的阈值电压，使得T10开启，进而使得O1输出的栅极驱动信号的电位维持为VSS，不受噪声干扰影响；T3打开，P13的电位为低电压，T6打开，P12的电位为高电压，T7关断，T8关断，P2的电位被第二时钟信号拉低，T9打开；
在保持阶段包括的第三保持时间段t6，K1提供高电压，KI提供低电压，K2提供高电压，I1提供低电压，T12和T1都关闭，KI通过C4拉低P11的电位，T5打开，进而使得P1的电位维持为低于VSS+Vth，Vth为T10的阈值电压，使得T10开启，进而使得O1输出的栅极驱动信号的电位维持为VSS，不受噪声干扰影响；T3关断，T2打开，P13的电位为高电压，T6关断，P12的电位为高电压，T7打开，T8打开，P2的电位为高电压，T9关断；
在保持阶段，P1的电位可以维持为低于VSS+Vth，Vth为T10的阈值电压，使得T10开启，进而使得O1输出的栅极驱动信号的电位维持为VSS，不受噪声干扰影响。
在图14所示的栅极驱动单元的至少一实施例中，C4、T5和C3组成电荷泵结构，电荷泵是电路中一种类似水泵的结构，主要通过电容、时钟信号和二极管整流结构(在图7中，T5采用二极管连接方式)，实现对电荷的再分配，实现升压(或降压)的目的。
图14所示的栅极驱动单元的至少一实施例在工作时，在I1提供的输入信号的电位为低电压，T1和T12用来初始化P11的电位，使P11的电位为VSS，C4用于在输入时钟信号的下降沿进一步拉低P11电位，通过T5将低电压保存到P1，同时通过C3存储电荷，保持电位；
在保持阶段，当输入时钟信号的电位升高时，P11的电位被推高，T5截止，不影响P1的电位；当第一时钟信号的电位和第二时钟信号的电位为低电压时，多余的电荷通过T1和T12放到输入端I1，后续循环以上过程。
在本公开至少一实施例中，标号为K4的为第四时钟信号端提供的第四 时钟信号。
如图16所示，在图14所示的栅极驱动电路的至少一实施例的基础上，在本公开所述的栅极驱动电路的至少一实施例中，所述电荷泵电路还包括开关控制子电路20；
所述开关控制子电路20包括开关控制晶体管T4；
T4的栅极与所述第一输入节点P11电连接，T4的源极与所述输入时钟信号端KI电连接，T4的漏极与第一控制节点P21电连接；
所述第一控制节点P21与C4的第一端电连接。
在图16所示的栅极驱动电路的至少一实施例中，T4为p型薄膜晶体管，但不以此为限。
如图15所示，如图16所示的栅极驱动单元的至少一实施例在工作时，
在输入阶段t1，K1提供低电压，KI提供高电压，K2提供低电压，I1提供高电压，T12和T1打开，P11的电位为高电压，T5和T4都关断；T2关断，T3打开，P13的电位为低电压，T6打开，P12的电位为高电压，T7关闭，T8关闭，T11关闭，P1的电位维持为低电压，P2的电位维持为高电压，T10打开，T9关闭，O1输出低电压；
在输出阶段t2，K1提供高电压，KI提供低电压，K2提供高电压，I1提供低电压，T12和T1都关断，P11的电位维持为高电压，T4关闭，T5关闭，P13的电位被C1进一步拉低，T6打开，P12的电位为低电压，T7打开，T8关闭，T11打开，P1的电位为高电压，P2的电位为低电压，T9打开，T10关闭，O1输出高电压；
在复位阶段t3，K1提供低电压，KI提供高电压，K2提供低电压，I1提供低电压，T12和T1都打开，P11的电位被拉低，T5打开，P1的电位被拉低；T10打开；并此时T8打开，并P2的电位被K2提供的第二时钟信号拉低，T9也打开，通过T9和T10同时为栅极驱动信号输出端放电，可以提升栅极驱动信号输出端的放电速度，从而实现对栅极驱动信号的完全、快速的复位；
在保持阶段包括的第一保持时间段t4，K1提供高电压，KI提供低电压，K2提供高电压，I1提供低电压，T12和T1都关闭，T4打开，KI通过C4拉 低P11的电位，T5打开，进而使得P1的电位维持为低于VSS+Vth，Vth为T10的阈值电压，使得T10开启，进而使得O1输出的栅极驱动信号的电位维持为VSS，不受噪声干扰影响；T3关断，T2打开，P13的电位为高电压，T6关断，P12的电位为高电压，T7打开，P2的电位为高电压，T9关断；
在保持阶段包括的第二保持时间段t5，K1提供低电压，KI提供高电压，K2提供低电压，I1提供低电压，T12和T1都打开，T4打开，KI提供的输入时钟信号的电位升高，从而拉升P11的电位，T5关闭，不影响P1的电位，使得P1的电位维持为低于VSS+Vth，Vth为T10的阈值电压，使得T10开启，进而使得O1输出的栅极驱动信号的电位维持为VSS，不受噪声干扰影响；T3打开，P13的电位为低电压，T6打开，P12的电位为高电压，T7关断，T8关断，P2的电位被第二时钟信号拉低，T9打开；
在保持阶段包括的第三保持时间段t6，K1提供高电压，KI提供低电压，K2提供高电压，I1提供低电压，T12和T1都关闭，T4打开，KI通过C4拉低P11的电位，T5打开，进而使得P1的电位维持为低于VSS+Vth，Vth为T10的阈值电压，使得T10开启，进而使得O1输出的栅极驱动信号的电位维持为VSS，不受噪声干扰影响；T3关断，T2打开，P13的电位为高电压，T6关断，P12的电位为高电压，T7打开，T8打开，P2的电位为高电压，T9关断；
在保持阶段，P1的电位可以维持为低于VSS+Vth，Vth为T10的阈值电压，使得T10开启，进而使得O1输出的栅极驱动信号的电位维持为VSS，不受噪声干扰影响。
在图16所示的栅极驱动单元的至少一实施例中，T4、C4、T5和C3组成电荷泵结构，电荷泵是电路中一种类似水泵的结构，主要通过电容、时钟信号和二极管整流结构(在图12中，T5采用二极管连接方式)，实现对电荷的再分配，实现升压(或降压)的目的。
图16所示的栅极驱动单元的至少一实施例在工作时，在I1提供的输入信号的电位为低电压，T1和T12用来初始化P11的电位，使P11的电位为VSS，C4用于在输入时钟信号的下降沿进一步拉低P11电位，通过T5将低电压保存到P1，同时通过C3存储电荷，保持电位；
在保持阶段，当输入时钟信号的电位升高时，P11的电位被推高，T5截止，不影响P1的电位；当第一时钟信号的电位和第二时钟信号的电位为低电压时，多余的电荷通过T1和T12放到输入端I1，后续循环以上过程。
如图17所示，在图10所示的栅极驱动单元的至少一实施例的基础上，在本公开所述的栅极驱动单元的至少一实施例中，
所述电荷泵电路还包括开关控制子电路20；所述开关控制子电路20包括开关控制晶体管T4；
所述第一隔离节点控制子电路41包括第一控制晶体管T12和第二控制晶体管T1，其中，
所述第一控制晶体管T12的栅极与所述第二时钟信号端K2电连接，所述第一控制晶体管T12的源极与所述输入端电连接；
所述第二控制晶体管T1的栅极与所述第一时钟信号端K1电连接，所述第二控制晶体管T1的源极与所述第一控制晶体管T12的漏极电连接，所述第二控制晶体管T1的漏极与所述第一隔离节点P31电连接；
所述第一隔离子电路42包括第一隔离晶体管T13；
T13的栅极与低电压端电连接，T13的源极与第一隔离节点P31电连接，T13的漏极与所述第一输入节点P11电连接；所述低电压端用于提供低电压VSS；
所述输入储能子电路21包括输入电容C4，所述通断控制子电路22包括通断控制晶体管T5，所述第一储能子电路23包括第一存储电容C3；
T4的栅极与所述第一输入节点P11电连接，T4的源极与所述输入时钟信号端KI电连接，T4的漏极与第一控制节点P21电连接；
所述第一控制节点P21与C4的第一端电连接，C4的第二端与所述第一输入节点P11电连接；T5的栅极与T5的源极都与所述第一输入节点P11电连接，T5的漏极与所述第一节点P1电连接；
C3的第一端与所述第一节点P1电连接，C3的第二端与低电压端电连接；所述低电压端用于提供低电压VSS；
所述第一节点控制电路12包括第一节点控制晶体管T11；
T11的栅极与所述第二输入节点P12电连接，T11的源极与高电压端电连 接，T11的漏极与所述第一节点P1电连接；所述高电压端用于提供高电压VDD；
所述第一储能电路31包括第二存储电容C2；
C2的第一端与第二节点P2电连接，C2的第二端与第二时钟信号输出端K2电连接；
所述输出电路30包括第一输出晶体管T10和第二输出晶体管T9；
所述第一输出晶体管T10的栅极与所述第一节点P1电连接，所述第一输出晶体管T10的源极与所述低电压端电连接，所述第一输出晶体管T10的漏极与所述栅极驱动信号输出端O1电连接；
所述第二输出晶体管T9的栅极与所述第二节点P2电连接，所述第二输出晶体管T9的源极与所述栅极驱动信号输出端O1电连接，所述第二输出晶体管T9的第二极与所述第二时钟信号端K2电连接；
所述第三输入节点控制子电路包括第三隔离节点控制子电路321和第二隔离子电路40；所述第三隔离节点控制子电路321包括第三控制晶体管T3和第四控制晶体管T2；所述第二隔离子电路40包括第二隔离晶体管T14，其中，
T3的栅极与第一时钟信号端K1电连接，T3的源极与所述低电压端电连接，T3的漏极与第二隔离节点P32电连接；
T2的栅极与所述第一隔离节点P31电连接，T2的源极与所述第一时钟信号端K1电连接，T2的漏极与所述第二隔离节点P32电连接；
T14的栅极与低电压端电连接，T14的源极与所述第二隔离节点P32电连接，T14的漏极与所述第三输入节点P13电连接；
所述第二输入节点控制子电路33包括第五控制晶体管T6和第一电容C1；
T6的栅极与所述第三输入节点P13电连接，所述第八控制晶体管T6的源极与所述第二输入节点P12电连接，所述第八控制晶体管T6的漏极与输入时钟信号端KI电连接；
所述第一电容C1的第一端与所述第三输入节点P13电连接，所述第一电容C1的第二端与所述第二输入节点P12电连接；
所述第二节点控制子电路34包括第六控制晶体管T7和第七控制晶体管 T8；
T7的栅极与输入时钟信号端KI电连接，T7的源极与所述第二输入节点P12电连接，T7的漏极与所述第二节点P2电连接；
T8的栅极与所述第一隔离节点P31电连接，T8的源极与第二时钟信号端K2电连接，T8的漏极与所述第二节点P2电连接。
在图17所示的至少一实施例中，C4的电容值与C1的电容值的比值可以大于或等于1而小于或等于10，但不以此为限。
在图17所示的至少一实施例中，所有的晶体管都为p型薄膜晶体管，第一电压信号为负电压信号，第二电压端为低电压端，第三电压端为高电压端，输出电压端为低电压端，但不以此为限。
在图17所示的至少一实施例中，T7可以防止对第三输入节点P13的漏电，并隔离C1对第二节点P2的影响，增强第二时钟信号端K2提供的第二时钟信号对第二节点P2的耦合作用，使得当第二时钟信号的电位降低时，第二节点P2的电位可以更低，从而加快第二输出晶体管T9对栅极驱动信号输出端O1的放电速度。
图17所示的栅极驱动单元的至少一实施例与图14所示的栅极驱动单元的至少一实施例的区别在于：增加了第一隔离晶体管T13和第二隔离晶体管T14；
T13以降低P11漏电，T14可以降低P13漏电，使得栅极驱动信号输出的响应速度更快。
如图18所示，本公开图17所示的栅极驱动单元的至少一实施例在工作时，
在输入阶段t1，K1提供低电压，KI提供高电压，K2提供低电压，I1提供高电压，T12和T1打开，T13打开，P11的电位为高电压，P31的电位为高电压，T5和T4都关断；T2关断，T3打开，T14打开，P32的电位为低电压，P13的电位为低电压，T6打开，P12的电位为高电压，T7关闭，T8关闭，T11关闭，P1的电位维持为低电压，P2的电位维持为高电压，T10打开，T9关闭，O1输出低电压；
在输出阶段t2，K1提供高电压，KI提供低电压，K2提供高电压，I1提 供低电压，T12和T1都关断，P11的电位维持为高电压，T13打开，P31的电位为高电压；T4关闭，T5关闭，P32的电位维持为低电压，T14由打开变为关闭，P13的电位被C1进一步拉低，T6打开，P12的电位为低电压，T7打开，T8关闭，T11打开，P1的电位为高电压，P2的电位为低电压，T9打开，T10关闭，O1输出高电压；
在复位阶段t3，K1提供低电压，KI提供高电压，K2提供低电压，I1提供低电压，T12和T1都打开，P11的电位被拉低，T13打开，P31的电位被拉低，T5打开，P1的电位被拉低；T10打开；T3打开，P32的电位为低电压，T14打开，P13的电位和P12的电位被拉高，T7关断；并此时T8打开，并P2的电位被K2提供的第二时钟信号拉低，T9也打开，通过T9和T10同时为栅极驱动信号输出端放电，可以提升栅极驱动信号输出端的放电速度，从而实现对栅极驱动信号的完全、快速的复位；
在保持阶段包括的第一保持时间段t4，K1提供高电压，KI提供低电压，K2提供高电压，I1提供低电压，T12和T1都关闭，P11的电位维持为低电压，T13由打开变为关闭，T4打开，KI通过C4拉低P31的电位，T5打开，进而使得P1的电位维持为低于VSS+Vth，Vth为T10的阈值电压，使得T10开启，进而使得O1输出的栅极驱动信号的电位维持为VSS，不受噪声干扰影响；T3关断，T2打开，P32的电位为高电压，T14打开，P13的电位为高电压，P12的电位为高电压，T7打开，T8打开，P2的电位为高电压，T9关断；
在保持阶段包括的第二保持时间段t5，K1提供低电压，KI提供高电压，K2提供低电压，I1提供低电压，T12和T1都打开，P11的电位为低电压，T13打开，T4由打开变为关闭，KI提供的输入时钟信号的电位升高，从而拉升P31的电位，T5关闭，不影响P1的电位，使得P1的电位维持为低于VSS+Vth，Vth为T10的阈值电压，使得T10开启，进而使得O1输出的栅极驱动信号的电位维持为VSS，不受噪声干扰影响；T3打开，P32的电位为低电压，T2关断，T14打开，P13的电位为低电压，T6打开，P12的电位为高电压，T7关断，T8关断，P2的电位被第二时钟信号拉低，T9打开；
在保持阶段包括的第三保持时间段t6，K1提供高电压，KI提供低电压， K2提供高电压，I1提供低电压，T12和T1都关闭，P11的电位维持为低电压，T4打开，KI通过C4拉低P31的电位，T5打开，进而使得P1的电位维持为低于VSS+Vth，Vth为T10的阈值电压，使得T10开启，进而使得O1输出的栅极驱动信号的电位维持为VSS，不受噪声干扰影响；T3关断，T2打开，P32的电位为高电压，T14打开，P13的电位为高电压，T6关闭，P12的电位为高电压，T7打开，T8打开，P2的电位为高电压，T9关断；
在所述第三保持时间段t6，T13由打开变为关闭；
在保持阶段，P1的电位可以维持为低于VSS+Vth，Vth为T10的阈值电压，使得T10开启，进而使得O1输出的栅极驱动信号的电位维持为VSS，不受噪声干扰影响。
在图17所示的栅极驱动单元的至少一实施例中，T4、C4、T5和C3组成电荷泵结构，电荷泵是电路中一种类似水泵的结构，主要通过电容、时钟信号和二极管整流结构(在图17中，T5采用二极管连接方式)，实现对电荷的再分配，实现升压(或降压)的目的。
如图19所示，本公开所述的栅极驱动单元的第至少一实施例，与本公开如图17所示的栅极驱动单元的至少一实施例的区别在于：
C2的第一端与第二节点P2电连接，C2的第二端与所述栅极驱动信号输出端O1电连接。
在图19所示的至少一实施例中，第一电压信号为负电压信号，第二电压端为低电压端，第三电压端为高电压端，输出电压端为低电压端，但不以此为限。
图19所示的栅极驱动单元的第四具体实施例与本公开如图17所示的栅极驱动单元的第三具体实施例的区别在于：C2的第二端与栅极驱动信号输出端O1电连接，减少了第二时钟信号端的电容负载，有利于降低功耗。
图19所示的栅极驱动单元的至少一实施例的工作时序图如图18所示。
如图20所示，在图12所示的栅极驱动单元的至少一实施例的基础上，在本公开所述的栅极驱动单元的至少一实施例中，所述电荷泵电路还包括开关控制子电路20；所述开关控制子电路20包括开关控制晶体管T4；
所述第一隔离节点控制子电路41包括第一控制晶体管T12和第二控制晶 体管T1，其中，
所述第一控制晶体管T12的栅极与所述第二时钟信号端K2电连接，所述第一控制晶体管T12的源极与所述输入端电连接；
所述第二控制晶体管T1的栅极与所述第一时钟信号端K1电连接，所述第二控制晶体管T1的源极与所述第一控制晶体管T12的漏极电连接，所述第二控制晶体管T1的漏极与所述第一隔离节点P31电连接；
所述第一隔离子电路42包括第一隔离晶体管T13；
所述第一隔离晶体管T13的电极与低电压端电连接，所述第一隔离晶体管T13的源极与所述第一隔离节点P31电连接，所述第一隔离晶体管T13的漏极与所述第一输入节点P11电连接；所述低电压端用于提供低电压VSS；
所述输入储能子电路21包括输入电容C4，所述通断控制子电路22包括通断控制晶体管T5，所述第一储能子电路23包括第一存储电容C3；
T4的栅极与第一输入节点P11电连接，T4的源极与输入时钟信号端KI电连接，T4的漏极与C4的第一端电连接；C4的第二端与所述第一输入节点P11电连接；C4的第一端与第一控制节点P21电连接；
T5的栅极与T5的源极都与所述第一输入节点P11电连接，T5的漏极与所述第一节点P1电连接；
C3的第一端与所述第一节点P1电连接，C3的第二端与低电压端电连接；所述低电压端用于提供低电压VSS；
所述第一节点控制电路12包括第一节点控制晶体管T11；
T11的栅极与所述第二输入节点P12电连接，T11的源极与高电压端电连接，T11的漏极与所述第一节点P1电连接；所述高电压端用于提供高电压VDD；
所述第一储能电路31包括第二存储电容C2；
C2的第一端与第二节点P2电连接，C2的第二端与第二时钟信号输出端K2电连接；
所述输出电路30包括第一输出晶体管T10和第二输出晶体管T9；
所述第一输出晶体管T10的栅极与所述第一节点P1电连接，所述第一输出晶体管T10的源极与所述低电压端电连接，所述第一输出晶体管T10的漏 极与所述栅极驱动信号输出端O1电连接；
所述第二输出晶体管T9的栅极与所述第二节点P2电连接，所述第二输出晶体管T9的源极与所述栅极驱动信号输出端O1电连接，所述第二输出晶体管T9的第二极与所述第二时钟信号端K2电连接；
所述第三输入节点控制子电路包括第三隔离节点控制子电路321和第二隔离子电路40；所述第三隔离节点控制子电路321包括第三控制晶体管T3和第四控制晶体管T2；所述第二隔离子电路40包括第二隔离晶体管T14，其中，
T3的栅极与第一时钟信号端K1电连接，T3的源极与所述低电压端电连接，T3的漏极与第二隔离节点P32电连接；
T2的栅极与所述第一隔离节点P31电连接，T2的源极与所述第一时钟信号端K1电连接，T2的漏极与所述第二隔离节点P32电连接；
T14的栅极与低电压端电连接，T14的源极与所述第二隔离节点P32电连接，T14的漏极与所述第三输入节点P13电连接；所述低电压端用于提供低电压VSS；
所述第二输入节点控制子电路33包括第五控制晶体管T6和第一电容C1；
T6的栅极与所述第三输入节点P13电连接，所述第八控制晶体管T6的源极与所述第二输入节点P12电连接，所述第八控制晶体管T6的漏极与输入时钟信号端KI电连接；
所述第一电容C1的第一端与所述第三输入节点P13电连接，所述第一电容C1的第二端与所述第二输入节点P12电连接；
所述第二节点控制子电路34包括第六控制晶体管T7和第七控制晶体管T8；
T7的栅极与输入时钟信号端KI电连接，T7的源极与所述第二输入节点P12电连接，T7的漏极与所述第二节点P2电连接；
T8的栅极与所述第一隔离节点P31电连接，T8的源极与高电压端电连接，T8的漏极与所述第二节点P2电连接；所述高电压端用于提供高电压VDD。
在图20所示的至少一实施例中，C4的电容值与C1的电容值的比值可以大于或等于1而小于或等于10，但不以此为限。
在图20所示的至少一实施例中，所有的晶体管都为p型薄膜晶体管，第一电压信号为负电压信号，第二电压端为低电压端，第三电压端为高电压端，输出电压端为低电压端，但不以此为限。
图20所示的栅极驱动单元的至少一实施例与图17所示的栅极驱动单元的至少一实施例的区别在于：T8的源极与高电压端(所述高电压端用于提供高电压VDD)电连接，减少了第二时钟信号端的负载，不用反复的对P2充放电，有利于进一步降低负载。
如图21所示，图20所示的栅极驱动单元的至少一实施例在工作时，
在输入阶段t1，K1提供低电压，KI提供高电压，K2提供低电压，I1提供高电压，T12和T1打开，T13打开，P11的电位为高电压，P31的电位为高电压，T5和T4都关断；T2关断，T3打开，T14打开，P32的电位为低电压，P13的电位为低电压，T6打开，P12的电位为高电压，T7关闭，T8关闭，T11关闭，P1的电位维持为低电压，P2的电位维持为高电压，T10打开，T9关闭，O1输出低电压；
在输出阶段t2，K1提供高电压，KI提供低电压，K2提供高电压，I1提供低电压，T12和T1都关断，P11的电位维持为高电压，T13打开，P31的电位为高电压；T4关闭，T5关闭，P32的电位维持为低电压，T14打开，P13的电位被C1进一步拉低，T6打开，P12的电位为低电压，T7打开，T8关闭，T11打开，P1的电位为高电压，P2的电位为低电压，T9打开，T10关闭，O1输出高电压；
在复位阶段t3，K1提供低电压，KI提供高电压，K2提供低电压，I1提供低电压，T12和T1都打开，P11的电位被拉低，T13打开，P31的电位被拉低，T5打开，P1的电位被拉低；T10打开；T3打开，P32的电位为低电压，T14打开，P13的电位和P12的电位被拉高，T7关断；并此时T8打开，并P2的电位为高电压，T9也打开，通过T9和T10同时为栅极驱动信号输出端放电，可以提升栅极驱动信号输出端的放电速度，从而实现对栅极驱动信号的完全、快速的复位；
在保持阶段包括的第一保持时间段t4，K1提供高电压，KI提供低电压，K2提供高电压，I1提供低电压，T12和T1都关闭，P11的电位维持为低电 压，T13打开，T4打开，KI通过C4拉低P31的电位，T5打开，进而使得P1的电位维持为低于VSS+Vth，Vth为T10的阈值电压，使得T10开启，进而使得O1输出的栅极驱动信号的电位维持为VSS，不受噪声干扰影响；T3关断，T2打开，P32的电位为高电压，T14打开，P13的电位为高电压，P12的电位为高电压，T7打开，T8打开，P2的电位为高电压，T9关断；
在保持阶段包括的第二保持时间段t5，K1提供低电压，KI提供高电压，K2提供低电压，I1提供低电压，T12和T1都打开，P11的电位为低电压，T13打开，T4打开，KI提供的输入时钟信号的电位升高，从而拉升P31的电位，T5关闭，不影响P1的电位，使得P1的电位维持为低于VSS+Vth，Vth为T10的阈值电压，使得T10开启，进而使得O1输出的栅极驱动信号的电位维持为VSS，不受噪声干扰影响；T3打开，P32的电位为低电压，T2关断，T14打开，P13的电位为低电压，T6打开，P12的电位为高电压，T7关断，T8打开，P2的电位为高电压，T9关断；
在保持阶段包括的第三保持时间段t6，K1提供高电压，KI提供低电压，K2提供高电压，I1提供低电压，T12和T1都关闭，P11的电位维持为低电压，T4打开，KI通过C4拉低P31的电位，T5打开，进而使得P1的电位维持为低于VSS+Vth，Vth为T10的阈值电压，使得T10开启，进而使得O1输出的栅极驱动信号的电位维持为VSS，不受噪声干扰影响；T3关断，T2打开，P32的电位为高电压，T14打开，P13的电位为高电压，T6关闭，P12的电位为高电压，T7打开，T8打开，P2的电位为高电压，T9关断；
在保持阶段，P1的电位可以维持为低于VSS+Vth，Vth为T10的阈值电压，使得T10开启，进而使得O1输出的栅极驱动信号的电位维持为VSS，不受噪声干扰影响。
如图22所示，在图12所示的栅极驱动单元的至少一实施例的基础上，在本公开所述的栅极驱动单元的至少一实施例中，
所述第一隔离节点控制子电路41包括第一控制晶体管T12和第二控制晶体管T1，其中，
所述第一控制晶体管T12的栅极与所述第二时钟信号端K2电连接，所述第一控制晶体管T12的源极与所述输入端电连接；
所述第二控制晶体管T1的栅极与所述第一时钟信号端K1电连接，所述第二控制晶体管T1的源极与所述第一控制晶体管T12的漏极电连接，所述第二控制晶体管T1的漏极与所述第一隔离节点P31电连接；
所述第一隔离子电路42包括第一隔离晶体管T13；
所述第一隔离晶体管T13的电极与低电压端电连接，所述第一隔离晶体管T13的源极与所述第一隔离节点P31电连接，所述第一隔离晶体管T13的漏极与所述第一输入节点P11电连接；所述低电压端用于提供低电压VSS；
所述输入储能子电路21包括输入电容C4，所述通断控制子电路22包括通断控制晶体管T5，所述第一储能子电路23包括第一存储电容C3；
C4的第一端与输入时钟信号KI电连接，C4的第二端与所述第一输入节点P11电连接；
T5的栅极与T5的源极都与所述第一输入节点P11电连接，T5的漏极与所述第一节点P1电连接；
C3的第一端与所述第一节点P1电连接，C3的第二端与低电压端电连接；所述低电压端用于提供低电压VSS；
所述第一节点控制电路12包括第一节点控制晶体管T11；
T11的栅极与所述第二输入节点P12电连接，T11的源极与高电压端电连接，T11的漏极与所述第一节点P1电连接；所述高电压端用于提供高电压VDD；
所述第一储能电路31包括第二存储电容C2；
C2的第一端与第二节点P2电连接，C2的第二端与第二时钟信号输出端K2电连接；
所述输出电路30包括第一输出晶体管T10和第二输出晶体管T9；
所述第一输出晶体管T10的栅极与所述第一节点P1电连接，所述第一输出晶体管T10的源极与所述低电压端电连接，所述第一输出晶体管T10的漏极与所述栅极驱动信号输出端O1电连接；
所述第二输出晶体管T9的栅极与所述第二节点P2电连接，所述第二输出晶体管T9的源极与所述栅极驱动信号输出端O1电连接，所述第二输出晶体管T9的第二极与所述第二时钟信号端K2电连接；
所述第三输入节点控制子电路包括第三隔离节点控制子电路321和第二隔离子电路40；所述第三隔离节点控制子电路321包括第三控制晶体管T3和第四控制晶体管T2；所述第二隔离子电路40包括第二隔离晶体管T14，其中，
T3的栅极与第一时钟信号端K1电连接，T3的源极与所述低电压端电连接，T3的漏极与第二隔离节点P32电连接；
T2的栅极与所述第一隔离节点P31电连接，T2的源极与所述第一时钟信号端K1电连接，T2的漏极与所述第二隔离节点P32电连接；
T14的栅极与低电压端电连接，T14的源极与所述第二隔离节点P32电连接，T14的漏极与所述第三输入节点P13电连接；
所述第二输入节点控制子电路33包括第五控制晶体管T6和第一电容C1；
T6的栅极与所述第三输入节点P13电连接，所述第八控制晶体管T6的源极与所述第二输入节点P12电连接，所述第八控制晶体管T6的漏极与输入时钟信号端KI电连接；
所述第一电容C1的第一端与所述第三输入节点P13电连接，所述第一电容C1的第二端与所述第二输入节点P12电连接；
所述第二节点控制子电路34包括第六控制晶体管T7和第七控制晶体管T8；
T7的栅极与输入时钟信号端KI电连接，T7的源极与所述第二输入节点P12电连接，T7的漏极与所述第二节点P2电连接；
T8的栅极与所述第一隔离节点P31电连接，T8的源极与高电压端电连接，T8的漏极与所述第二节点P2电连接；所述高电压端用于提供高电压VDD。
在图22所示的至少一实施例中，C4的电容值与C1的电容值的比值可以大于或等于1而小于或等于10，但不以此为限。
在图22所示的至少一实施例中，所有的晶体管都为p型薄膜晶体管，第一电压信号为负电压信号，第二电压端为低电压端，第三电压端为高电压端，输出电压端为低电压端，但不以此为限。
本公开如图22所示的栅极驱动单元的至少一实施例与本公开如图20所示的栅极驱动单元的至少一实施例的区别如下：所述电荷泵电路不包含开关 控制子电路。
如图23所示，在图8所示的栅极驱动单元的至少一实施例的基础上，在本公开所述的栅极驱动单元的至少一实施例中，所述电荷泵电路还包括开关控制子电路20；所述开关控制子电路20包括开关控制晶体管T4；所述第一输入节点控制电路10包括第一控制晶体管T12和第二控制晶体管T1，其中，
所述第一控制晶体管T12的栅极与所述第二时钟信号端K2电连接，所述第一控制晶体管T12的源极与所述输入端电连接；
所述第二控制晶体管T1的栅极与所述第一时钟信号端K1电连接，所述第二控制晶体管T1的源极与所述第一控制晶体管T12的漏极电连接，所述第二控制晶体管T1的漏极与所述第一输入节点P11电连接；所述输入储能子电路21包括输入电容C4，所述通断控制子电路22包括通断控制晶体管T5，所述第一储能子电路23包括第一存储电容C3；
T4的栅极与第一输入节点P11电连接，T4的源极与输入时钟信号端KI电连接，T4的漏极与C4的第一端电连接；C4的第二端与所述第一输入节点P11电连接；C4的第一端与第一控制节点P21电连接；
T5的栅极与T5的源极都与所述第一输入节点P11电连接，T5的漏极与所述第一节点P1电连接；
C3的第一端与所述第一节点P1电连接，C3的第二端与低电压端电连接；所述低电压端用于提供低电压VSS；
所述第一节点控制电路12包括第一节点控制晶体管T11；
T11的栅极与所述第二输入节点P12电连接，T11的源极与高电压端电连接，T11的漏极与所述第一节点P1电连接；所述高电压端用于提供高电压VDD；
所述第一储能电路31包括第二存储电容C2；
C2的第一端与第二节点P2电连接，C2的第二端与第二时钟信号输出端K2电连接；
所述输出电路30包括第一输出晶体管T10和第二输出晶体管T9；
所述第一输出晶体管T10的栅极与所述第一节点P1电连接，所述第一输出晶体管T10的源极与所述低电压端电连接，所述第一输出晶体管T10的漏 极与所述栅极驱动信号输出端O1电连接；
所述第二输出晶体管T9的栅极与所述第二节点P2电连接，所述第二输出晶体管T9的源极与所述栅极驱动信号输出端O1电连接，所述第二输出晶体管T9的第二极与所述第二时钟信号端K2电连接；
所述第三输入节点控制子电路32包括第三控制晶体管T3和第四控制晶体管T2，其中，
T3的栅极与第一时钟信号端K1电连接，T3的源极与所述低电压端电连接，T3的漏极与第三输入节点P13电连接；
T2的栅极与所述第一输入节点P11电连接，T2的源极与所述第一时钟信号端K1电连接，T2的漏极与所述第三输入节点P13电连接；所述第二输入节点控制子电路33包括第五控制晶体管T6和第一电容C1；
T6的栅极与所述第三输入节点P13电连接，所述第八控制晶体管T6的源极与所述第二输入节点P12电连接，所述第八控制晶体管T6的漏极与输入时钟信号端KI电连接；
所述第一电容C1的第一端与所述第三输入节点P13电连接，所述第一电容C1的第二端与所述第二输入节点P12电连接；
所述第二节点控制子电路34包括第六控制晶体管T7和第七控制晶体管T8；
T7的栅极与输入时钟信号端KI电连接，T7的源极与所述第二输入节点P12电连接，T7的漏极与所述第二节点P2电连接；
T8的栅极与所述第一隔离节点P31电连接，T8的源极与高电压端电连接，T8的漏极与所述第二节点P2电连接；所述高电压端用于提供高电压VDD。
在图23所示的第至少一实施例中，C4的电容值与C1的电容值的比值可以大于或等于1而小于或等于10，但不以此为限。
在图23所示的至少一实施例中，所有的晶体管都为p型薄膜晶体管，第一电压信号为负电压信号，第二电压端为低电压端，第三电压端为高电压端，输出电压端为低电压端，但不以此为限。
本公开如图23所示的栅极驱动单元的至少一实施例与本公开如图20所示的栅极驱动单元的至少一实施例的区别如下：所述栅极驱动单元不包含第 一隔离晶体管和第二隔离晶体管。
如图24所示，在图12所示的栅极驱动单元的至少一实施例的基础上，在本公开所述的栅极驱动单元的至少一实施例中，所述电荷泵电路还包括开关控制子电路20；所述开关控制子电路20包括开关控制晶体管T4；
所述第一隔离节点控制子电路41包括第一控制晶体管T12，其中，
所述第一控制晶体管T12的栅极与所述第二时钟信号端K2电连接，所述第一控制晶体管T12的源极与所述输入端电连接；
所述第一隔离子电路42包括第一隔离晶体管T13；
所述第一隔离晶体管T13的电极与低电压端电连接，所述第一隔离晶体管T13的源极与所述第一隔离节点P31电连接，所述第一隔离晶体管T13的漏极与所述第一输入节点P11电连接；所述低电压端用于提供低电压VSS；
所述输入储能子电路21包括输入电容C4，所述通断控制子电路22包括通断控制晶体管T5，所述第一储能子电路23包括第一存储电容C3；
T4的栅极与第一输入节点P11电连接，T4的源极与输入时钟信号端KI电连接，T4的漏极与C4的第一端电连接；C4的第二端与所述第一输入节点P11电连接；C4的第一端与第一控制节点P21电连接；
T5的栅极与T5的源极都与所述第一输入节点P11电连接，T5的漏极与所述第一节点P1电连接；
C3的第一端与所述第一节点P1电连接，C3的第二端与低电压端电连接；所述低电压端用于提供低电压VSS；
所述第一节点控制电路12包括第一节点控制晶体管T11；
T11的栅极与所述第二输入节点P12电连接，T11的源极与高电压端电连接，T11的漏极与所述第一节点P1电连接；所述高电压端用于提供高电压VDD；
所述第一储能电路31包括第二存储电容C2；
C2的第一端与第二节点P2电连接，C2的第二端与第二时钟信号输出端K2电连接；
所述输出电路30包括第一输出晶体管T10和第二输出晶体管T9；
所述第一输出晶体管T10的栅极与所述第一节点P1电连接，所述第一输 出晶体管T10的源极与所述低电压端电连接，所述第一输出晶体管T10的漏极与所述栅极驱动信号输出端O1电连接；
所述第二输出晶体管T9的栅极与所述第二节点P2电连接，所述第二输出晶体管T9的源极与所述栅极驱动信号输出端O1电连接，所述第二输出晶体管T9的第二极与所述第二时钟信号端K2电连接；
所述第三输入节点控制子电路包括第三隔离节点控制子电路321和第二隔离子电路40；所述第三隔离节点控制子电路321包括第三控制晶体管T3和第四控制晶体管T2；所述第二隔离子电路40包括第二隔离晶体管T14，其中，
T3的栅极与第一时钟信号端K1电连接，T3的源极与所述低电压端电连接，T3的漏极与第二隔离节点P32电连接；
T2的栅极与所述第一隔离节点P31电连接，T2的源极与所述第一时钟信号端K1电连接，T2的漏极与所述第二隔离节点P32电连接；
T14的栅极与低电压端电连接，T14的源极与所述第二隔离节点P32电连接，T14的漏极与所述第三输入节点P13电连接；所述低电压端用于提供低电压VSS；
所述第二输入节点控制子电路33包括第五控制晶体管T6和第一电容C1；
T6的栅极与所述第三输入节点P13电连接，所述第八控制晶体管T6的源极与所述第二输入节点P12电连接，所述第八控制晶体管T6的漏极与输入时钟信号端KI电连接；
所述第一电容C1的第一端与所述第三输入节点P13电连接，所述第一电容C1的第二端与所述第二输入节点P12电连接；
所述第二节点控制子电路34包括第六控制晶体管T7和第七控制晶体管T8；
T7的栅极与输入时钟信号端KI电连接，T7的源极与所述第二输入节点P12电连接，T7的漏极与所述第二节点P2电连接；
T8的栅极与所述第一隔离节点P31电连接，T8的源极与高电压端电连接，T8的漏极与所述第二节点P2电连接；所述高电压端用于提供高电压VDD。
在图24所示的至少一实施例中，C4的电容值与C1的电容值的比值可以 大于或等于1而小于或等于10，但不以此为限。
在图24所示的至少一实施例中，所有的晶体管都为p型薄膜晶体管，第一电压信号为负电压信号，第二电压端为低电压端，第三电压端为高电压端，输出电压端为低电压端，但不以此为限。
本公开如图24所示的栅极驱动单元的至少一实施例与本公开如图20所示的栅极驱动单元的至少一实施例的区别如下：所述第一隔离节点控制子电路41仅包括第一控制晶体管T12，所述第一隔离节点控制子电路41不包括第二控制晶体管T1，前提是第二时钟信号的上升沿不早于I1提供的输入信号的下降沿。
如图25所示，在图12所示的栅极驱动单元的至少一实施例的基础上，在本公开所述的栅极驱动单元的至少一实施例中，所述电荷泵电路还包括开关控制子电路20；所述开关控制子电路20包括开关控制晶体管T4；
所述第一隔离节点控制子电路41包括第二控制晶体管T1，其中，
所述第二控制晶体管T1的栅极与所述第一时钟信号端K1电连接，所述第二控制晶体管T1的源极与所述第一控制晶体管T12的漏极电连接，所述第二控制晶体管T1的漏极与所述第一输入节点P11电连接；
所述第一隔离子电路42包括第一隔离晶体管T13；
所述第一隔离晶体管T13的电极与低电压端电连接，所述第一隔离晶体管T13的源极与所述第一隔离节点P31电连接，所述第一隔离晶体管T13的漏极与所述第一输入节点P11电连接；所述低电压端用于提供低电压VSS；
所述输入储能子电路21包括输入电容C4，所述通断控制子电路22包括通断控制晶体管T5，所述第一储能子电路23包括第一存储电容C3；
T4的栅极与第一输入节点P11电连接，T4的源极与输入时钟信号端KI电连接，T4的漏极与C4的第一端电连接；C4的第二端与所述第一输入节点P11电连接；C4的第一端与第一控制节点P21电连接；
T5的栅极与T5的源极都与所述第一输入节点P11电连接，T5的漏极与所述第一节点P1电连接；
C3的第一端与所述第一节点P1电连接，C3的第二端与低电压端电连接；所述低电压端用于提供低电压VSS；
所述第一节点控制电路12包括第一节点控制晶体管T11；
T11的栅极与所述第二输入节点P12电连接，T11的源极与高电压端电连接，T11的漏极与所述第一节点P1电连接；所述高电压端用于提供高电压VDD；
所述第一储能电路31包括第二存储电容C2；
C2的第一端与第二节点P2电连接，C2的第二端与第二时钟信号输出端K2电连接；
所述输出电路30包括第一输出晶体管T10和第二输出晶体管T9；
所述第一输出晶体管T10的栅极与所述第一节点P1电连接，所述第一输出晶体管T10的源极与所述低电压端电连接，所述第一输出晶体管T10的漏极与所述栅极驱动信号输出端O1电连接；
所述第二输出晶体管T9的栅极与所述第二节点P2电连接，所述第二输出晶体管T9的源极与所述栅极驱动信号输出端O1电连接，所述第二输出晶体管T9的第二极与所述第二时钟信号端K2电连接；
所述第三输入节点控制子电路包括第三隔离节点控制子电路321和第二隔离子电路40；所述第三隔离节点控制子电路321包括第三控制晶体管T3和第四控制晶体管T2；所述第二隔离子电路40包括第二隔离晶体管T14，其中，
T3的栅极与第一时钟信号端K1电连接，T3的源极与所述低电压端电连接，T3的漏极与第二隔离节点P32电连接；
T2的栅极与所述第一隔离节点P31电连接，T2的源极与所述第一时钟信号端K1电连接，T2的漏极与所述第二隔离节点P32电连接；
T14的栅极与低电压端电连接，T14的源极与所述第二隔离节点P32电连接，T14的漏极与所述第三输入节点P13电连接；所述低电压端用于提供低电压VSS；
所述第二输入节点控制子电路33包括第五控制晶体管T6和第一电容C1；
T6的栅极与所述第三输入节点P13电连接，所述第八控制晶体管T6的源极与所述第二输入节点P12电连接，所述第八控制晶体管T6的漏极与输入时钟信号端KI电连接；
所述第一电容C1的第一端与所述第三输入节点P13电连接，所述第一电容C1的第二端与所述第二输入节点P12电连接；
所述第二节点控制子电路34包括第六控制晶体管T7和第七控制晶体管T8；
T7的栅极与输入时钟信号端KI电连接，T7的源极与所述第二输入节点P12电连接，T7的漏极与所述第二节点P2电连接；
T8的栅极与所述第一隔离节点P31电连接，T8的源极与高电压端电连接，T8的漏极与所述第二节点P2电连接；所述高电压端用于提供高电压VDD。
在图25所示的至少一实施例中，C4的电容值与C1的电容值的比值可以大于或等于1而小于或等于10，但不以此为限。
在图25所示的至少一实施例中，所有的晶体管都为p型薄膜晶体管，第一电压信号为负电压信号，第二电压端为低电压端，第三电压端为高电压端，输出电压端为低电压端，但不以此为限。
本公开如图25所示的栅极驱动单元的至少一实施例与本公开如图20所示的栅极驱动单元的至少一实施例的区别如下：所述第一隔离节点控制子电路41仅包括第二控制晶体管T1，所述第一隔离节点控制子电路41不包括第一控制晶体管T12，前提是第一时钟信号的上升沿不早于I1提供的输入信号的下降沿。
如图26所示，在图13所示的栅极驱动单元的至少一实施例的基础上，在本公开所述的栅极驱动单元的至少一实施例中，
所述电荷泵电路还包括开关控制子电路20；所述开关控制子电路20包括开关控制晶体管T4；
所述第一隔离节点控制子电路41包括第一控制晶体管T12和第二控制晶体管T1，其中，
所述第一控制晶体管T12的栅极与所述第二时钟信号端K2电连接，所述第一控制晶体管T12的源极与所述输入端电连接；
所述第二控制晶体管T1的栅极与所述第一时钟信号端K1电连接，所述第二控制晶体管T1的源极与所述第一控制晶体管T12的漏极电连接，所述第二控制晶体管T1的漏极与所述第一隔离节点P31电连接；
所述第一隔离子电路42包括第一隔离晶体管T13；
所述第一隔离晶体管T13的电极与低电压端电连接，所述第一隔离晶体管T13的源极与所述第一隔离节点P31电连接，所述第一隔离晶体管T13的漏极与所述第一输入节点P11电连接；所述低电压端用于提供低电压VSS；
所述输入储能子电路21包括输入电容C4，所述通断控制子电路22包括通断控制晶体管T5，所述第一储能子电路23包括第一存储电容C3；
T4的栅极与第一输入节点P11电连接，T4的源极与输入时钟信号端KI电连接，T4的漏极与C4的第一端电连接；C4的第二端与所述第一输入节点P11电连接；C4的第一端与第一控制节点P21电连接；
T5的栅极与T5的源极都与所述第一输入节点P11电连接，T5的漏极与所述第一节点P1电连接；
C3的第一端与所述第一节点P1电连接，C3的第二端与低电压端电连接；所述低电压端用于提供低电压VSS；
所述第一节点控制电路12包括第一节点控制晶体管T11；
T11的栅极与所述第二输入节点P12电连接，T11的源极与高电压端电连接，T11的漏极与所述第一节点P1电连接；所述高电压端用于提供高电压VDD；
所述第一储能电路31包括第二存储电容C2；
C2的第一端与第二节点P2电连接，C2的第二端与栅极驱动信号输出端O1电连接；
所述输出电路30包括第一输出晶体管T10和第二输出晶体管T9；
所述第一输出晶体管T10的栅极与所述第一节点P1电连接，所述第一输出晶体管T10的源极与所述低电压端电连接，所述第一输出晶体管T10的漏极与所述栅极驱动信号输出端O1电连接；
所述第二输出晶体管T9的栅极与所述第二节点P2电连接，所述第二输出晶体管T9的源极与所述栅极驱动信号输出端O1电连接，所述第二输出晶体管T9的第二极与所述第二时钟信号端K2电连接；
所述第三输入节点控制子电路包括第三隔离节点控制子电路321和第二隔离子电路40；所述第三隔离节点控制子电路321包括第三控制晶体管T3 和第四控制晶体管T2；所述第二隔离子电路40包括第二隔离晶体管T14，其中，
T3的栅极与第一时钟信号端K1电连接，T3的源极与所述低电压端电连接，T3的漏极与第二隔离节点P32电连接；
T2的栅极与所述第一隔离节点P31电连接，T2的源极与所述第一时钟信号端K1电连接，T2的漏极与所述第二隔离节点P32电连接；
T14的栅极与低电压端电连接，T14的源极与所述第二隔离节点P32电连接，T14的漏极与所述第三输入节点P13电连接；所述低电压端用于提供低电压VSS；
所述第二输入节点控制子电路33包括第五控制晶体管T6和第一电容C1；
T6的栅极与所述第三输入节点P13电连接，所述第八控制晶体管T6的源极与所述第二输入节点P12电连接，所述第八控制晶体管T6的漏极与输入时钟信号端KI电连接；
所述第一电容C1的第一端与所述第三输入节点P13电连接，所述第一电容C1的第二端与所述第二输入节点P12电连接；
所述第二节点控制子电路34包括第六控制晶体管T7和第七控制晶体管T8；
T7的栅极与输入时钟信号端KI电连接，T7的源极与所述第二输入节点P12电连接，T7的漏极与所述第二节点P2电连接；
T8的栅极与所述第一隔离节点P31电连接，T8的源极与高电压端电连接，T8的漏极与所述第二节点P2电连接；所述高电压端用于提供高电压VDD。
在图26所示的至少一实施例中，C4的电容值与C1的电容值的比值可以大于或等于1而小于或等于10，但不以此为限。
在图26所示的至少一实施例中，所有的晶体管都为p型薄膜晶体管，第一电压信号为负电压信号，第二电压端为低电压端，第三电压端为高电压端，输出电压端为低电压端，但不以此为限。
图26所示的栅极驱动单元的至少一实施例与图20所示的栅极驱动单元的至少一实施例的区别在于：C2的第二端与栅极驱动信号输出端电连接，减少了第二时钟信号端的电容负载，有利于降低功耗。
图26所示的栅极驱动单元的至少一实施例的工作时序图可以如图21所示。
本公开实施例所述的驱动方法，应用于上述的栅极驱动单元，所述驱动方法包括：
第一输入节点控制电路在时钟信号端提供的时钟信号的控制下，导通或断开输入端与第一输入节点之间的连接；
当所述第一输入节点的电压信号为第一电压信号时，电荷泵电路在输入时钟信号端提供的输入时钟信号的控制下，控制将所述第一输入节点的电压信号转换为所述第一节点的电压信号，且使得所述第一节点的电压信号的极性与所述第一输入节点的电压信号的极性相同，所述第一节点的电压信号的电压值的绝对值大于所述第一输入节点的电压信号的电压值的绝对值。
在本公开实施例所述的驱动方法中，所述栅极驱动单元能够在保持阶段充分拉低或升高第一节点的电位，使得在保持阶段，由第一节点控制的第一输出晶体管保持开启，进而使得在保持阶段，能够使得输出的栅极驱动信号的电位不受噪声干扰的影响。
本公开实施例所述的栅极驱动电路包括上述的栅极驱动单元。
本公开实施例所述的显示装置包括上述的栅极驱动电路。
本公开实施例所提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (27)

  1. 一种栅极驱动单元，包括第一输入节点控制电路和电荷泵电路；
    所述第一输入节点控制电路分别与时钟信号端、输入端和第一输入节点电连接，用于在所述时钟信号端提供的时钟信号的控制下，导通或断开所述输入端与所述第一输入节点之间的连接；
    所述电荷泵电路分别与所述第一输入节点、输入时钟信号端和第一节点电连接，用于当所述第一输入节点的电压信号为第一电压信号时，在所述输入时钟信号端提供的输入时钟信号的控制下，控制将所述第一输入节点的电压信号转换为所述第一节点的电压信号，且使得所述第一节点的电压信号的极性与所述第一输入节点的电压信号的极性相同，所述第一节点的电压信号的电压值的绝对值大于所述第一输入节点的电压信号的电压值的绝对值。
  2. 如权利要求1所述的栅极驱动单元，其中，所述栅极驱动单元包括输出电路，所述输出电路包括第一输出晶体管，所述第一输出晶体管的控制极与所述第一节点电连接，所述第一输出晶体管的第一极与输出电压端电连接，所述第一输出晶体管的第二极与栅极驱动信号输出端电连接。
  3. 如权利要求1所述的栅极驱动单元，其中，所述电荷泵电路包括输入储能子电路、通断控制子电路和第一储能子电路；
    所述输入储能子电路的第一端与所述输入时钟信号端电连接，所述输入储能子电路的第二端与所述第一输入节点电连接，用于储存电能且根据所述输入时钟信号的电位控制所述第一输入节点的电位；
    所述通断控制子电路分别与所述第一输入节点和所述第一节点电连接，用于在所述第一输入节点的电位的控制下，导通或断开所述第一输入节点与所述第一节点之间的连接；
    所述第一储能子电路与所述第一节点电连接，用于储存电能且维持所述第一节点的电位。
  4. 如权利要求1所述的栅极驱动单元，其中，所述电荷泵电路包括输入储能子电路、通断控制子电路、开关控制子电路和第一储能子电路；
    所述输入储能子电路的第一端与第一控制节点电连接，所述输入储能子 电路的第二端与所述第一输入节点电连接，用于储存电能且根据第一控制节点的电位控制所述第一输入节点的电位；
    所述通断控制子电路分别与所述第一输入节点和所述第一节点电连接，用于在所述第一输入节点的电位的控制下，导通或断开所述第一输入节点与所述第一节点之间的连接；
    所述第一储能子电路与所述第一节点电连接，用于储存电能且维持所述第一节点的电位；
    所述开关控制子电路分别与所述第一输入节点、输入时钟信号端和所述第一控制节点电连接，用于在所述第一输入节点的电位的控制下，导通或断开所述输入时钟信号端与所述第一控制节点之间的连接。
  5. 如权利要求3所述的栅极驱动单元，其中，所述输入储能子电路包括输入电容，所述第一储能子电路包括第一存储电容，所述通断控制子电路包括通断控制晶体管；
    所述输入电容的第一端与所述输入时钟信号端电连接，所述输入电容的第二端与所述第一输入节点电连接；
    所述第一存储电容的第一端与所述第一节点电连接，所述第一存储电容的第二端与第二电压端电连接；
    所述通断控制晶体管的控制极和所述通断控制晶体管的第一极与所述第一输入节点电连接，所述通断控制晶体管的第二极与所述第一节点电连接。
  6. 如权利要求4所述的栅极驱动单元，其中，所述输入储能子电路包括输入电容，所述第一储能子电路包括第一存储电容，所述通断控制子电路包括通断控制晶体管；
    所述输入电容的第一端与所述第一控制节点电连接，所述输入电容的第二端与所述第一输入节点电连接；
    所述第一存储电容的第一端与所述第一节点电连接，所述第一存储电容的第二端与第二电压端电连接；
    所述通断控制晶体管的控制极和所述通断控制晶体管的第一极与所述第一输入节点电连接，所述通断控制晶体管的第二极与所述第一节点电连接。
  7. 如权利要求5或6所述的栅极驱动单元，其中，所述输入电容的电容 值与所述第一存储电容的电容值之间的比值大于或等于1而小于或等于10。
  8. 如权利要求4所述的栅极驱动单元，其中，所述开关控制子电路包括开关控制晶体管；
    所述开关控制晶体管的控制极与所述第一输入节点电连接，所述开关控制晶体管的第一极与所述输入时钟信号端电连接，所述开关控制晶体管的第二极与所述第一控制节点电连接。
  9. 如权利要求1所述的栅极驱动单元，其中，所述第一输入节点控制电路包括第一隔离节点控制子电路和第一隔离子电路；
    所述第一隔离节点控制子电路分别与时钟信号端、输入端和第一隔离节点电连接，用于在所述时钟信号端提供的时钟信号的控制下，导通或断开所述输入端与所述第一隔离节点之间的连接；
    所述第一隔离子电路分别与第二电压端、所述第一隔离节点和所述第一输入节点电连接，用于在第二电压端提供的第二电压信号的控制下，控制所述第一隔离节点与所述第一输入节点之间连通。
  10. 如权利要求9所述的栅极驱动单元，其中，所述时钟信号端包括第一时钟信号端和第二时钟信号端；第一隔离节点控制子电路包括第一控制晶体管和第二控制晶体管；所述第一控制晶体管的控制极与所述第二时钟信号端电连接，所述第一控制晶体管的第一极与所述输入端电连接；所述第二控制晶体管的控制极与所述第一时钟信号端电连接，所述第二控制晶体管的第一极与所述第一控制晶体管的第二极电连接，所述第二控制晶体管的第二极与所述第一隔离节点电连接；或者，
    所述时钟信号端包括第二时钟信号端，所述第一隔离节点控制子电路包括第一控制晶体管；所述第一控制晶体管的控制极与所述第二时钟信号端电连接，所述第一控制晶体管的第一极与所述输入端电连接，所述第一控制晶体管的第二极与所述第一隔离节点电连接；或者，
    所述时钟信号端包括第一时钟信号端，所述第一隔离节点控制子电路包括第二控制晶体管；所述第二控制晶体管的控制极与所述第一时钟信号端电连接，所述第一控制晶体管的第一极与所述输入端电连接，所述第二控制晶体管的第二极与所述第一隔离节点电连接。
  11. 如权利要求9所述的栅极驱动单元，其中，所述第一隔离子电路包括第一隔离晶体管；
    所述第一隔离晶体管的控制极与所述第二电压端电连接，所述第一隔离晶体管的第一极与所述第一隔离节点电连接，所述第一隔离晶体管的第二极与所述第一输入节点电连接。
  12. 如权利要求1或2所述的栅极驱动单元，其中，还包括第一节点控制电路；
    所述第一节点控制电路分别与第二输入节点、第三电压端和第一节点电连接，用于在所述第二输入节点的电位的控制下，控制将第三电压端输入的第三电压信号写入所述第一节点。
  13. 如权利要求12所述的栅极驱动单元，其中，所述第一节点控制电路包括第一节点控制晶体管；
    所述第一节点控制晶体管的控制极与所述第二输入节点电连接，所述第一节点控制晶体管的第一极与第三电压端电连接，所述第一节点控制晶体管的第二极与所述第一节点电连接。
  14. 如权利要求1或2所述的栅极驱动单元，其中，还包括第一储能电路；
    所述第一储能电路分别与第二节点和第二时钟信号端电连接，用于根据第二时钟信号控制所述第二节点的电位。
  15. 如权利要求1或2所述的栅极驱动单元，其中，还包括栅极驱动信号输出端和第一储能电路；
    所述第一储能电路分别与第二节点和所述栅极驱动信号输出端电连接，用于根据所述栅极驱动信号输出端输出的栅极驱动信号，控制第二节点的电位。
  16. 如权利要求1所述的栅极驱动单元，其中，还包括输出电路；
    所述输出电路分别与第一节点、第二节点、栅极驱动信号输出端、输出电压端和第二时钟信号输出端电连接，用于在第一节点的电位的控制下，控制将输出电压信号写入所述栅极驱动信号输出端，并在第二节点的电位的控制下，将第二时钟信号写入所述栅极驱动信号输出端；
    所述输出电压端用于提供输出电压信号。
  17. 如权利要求16所述的栅极驱动单元，其中，所述输出电路包括第一输出晶体管和第二输出晶体管；
    所述第一输出晶体管的控制极与所述第一节点电连接，所述第一输出晶体管的第一极与所述输出电压端电连接，所述第一输出晶体管的第二极与所述栅极驱动信号输出端电连接；
    所述第二输出晶体管的控制极与所述第二节点电连接，所述第二输出晶体管的第一极与所述栅极驱动信号输出端电连接，所述第二输出晶体管的第二极与所述第二时钟信号端电连接。
  18. 如权利要求1所述的栅极驱动单元，其中，还包括第二节点控制电路；
    所述第二节点控制电路包括第三输入节点控制子电路、第二输入节点控制子电路和第二节点控制子电路；
    所述第三输入节点控制子电路分别与第一时钟信号端、第二电压端、第一输入节点和第三输入节点电连接，用于在第一时钟信号的控制下，将第二电压信号写入所述第三输入节点，并用于在第一输入节点的电位的控制下，将第一时钟信号写入所述第三输入节点；
    所述第二输入节点控制子电路分别与所述第三输入节点、第二输入节点和输入时钟信号端电连接，用于在所述第三输入节点的电位的控制下将输入时钟信号写入所述第二输入节点，并用于根据所述第三输入节点的电位控制第二输入节点的电位；
    所述第二节点控制子电路分别与所述第二输入节点、第一输入节点、第二节点和输入时钟信号端电连接，所述第二节点控制子电路还与第二时钟信号端或第三电压端电连接，用于在输入时钟信号的控制下，导通或断开所述第二输入节点与所述第二节点之间的连接，并用于在所述第一输入节点的电位的控制下，将第二时钟信号或第三电压信号写入第二节点。
  19. 如权利要求18所述的栅极驱动单元，其中，所述第三输入节点控制子电路包括第三控制晶体管和第四控制晶体管，其中，
    所述第三控制晶体管的控制极与第一时钟信号端电连接，所述第三控制 晶体管的第一极与第二电压端电连接，所述第三控制晶体管的第二极与第三输入节点电连接；
    所述第四控制晶体管的控制极与所述第一输入节点电连接，所述第四控制晶体管的第一极与所述第一时钟信号端电连接，所述第四控制晶体管的第二极与所述第三输入节点电连接。
  20. 如权利要求9所述的栅极驱动单元，其中，还包括第二节点控制电路；
    所述第二节点控制电路包括第三输入节点控制子电路、第二输入节点控制子电路和第二节点控制子电路；
    所述第三输入节点控制子电路分别与第一时钟信号端、第二电压端、第一隔离节点和第三输入节点电连接，用于在第一时钟信号的控制下，将第二电压信号写入所述第三输入节点，并用于在第一隔离节点的电位的控制下，将第一时钟信号写入所述第三输入节点；
    所述第二输入节点控制子电路分别与所述第三输入节点、第二输入节点和输入时钟信号端电连接，用于在所述第三输入节点的电位的控制下将输入时钟信号写入所述第二输入节点，并用于根据所述第三输入节点的电位控制第二输入节点的电位；
    所述第二节点控制子电路分别与所述第二输入节点、第一隔离节点、第二节点和输入时钟信号端电连接，所述第二节点控制子电路还与第二时钟信号端或第三电压端电连接，用于在输入时钟信号的控制下，导通或断开所述第二输入节点与所述第二节点之间的连接，并用于在所述第一输入节点的电位的控制下，将第二时钟信号或第三电压信号写入第二节点。
  21. 如权利要求20所述的栅极驱动单元，其中，所述第三输入节点控制子电路包括第三控制晶体管和第四控制晶体管，其中，
    所述第三控制晶体管的控制极与第一时钟信号端电连接，所述第三控制晶体管的第一极与第二电压端电连接，所述第三控制晶体管的第二极与第三输入节点电连接；
    所述第四控制晶体管的控制极与所述第一隔离节点电连接，所述第四控制晶体管的第一极与所述第一时钟信号端电连接，所述第四控制晶体管的第 二极与所述第三输入节点电连接。
  22. 如权利要求20所述的栅极驱动单元，其中，所述第三输入节点控制子电路包括第三控制晶体管、第四控制晶体管和第二隔离晶体管；
    所述第三控制晶体管的控制极与第一时钟信号端电连接，所述第三控制晶体管的第一极与第二电压端电连接，所述第三控制晶体管的第二极与第二隔离节点电连接；
    所述第四控制晶体管的控制极与所述第一隔离节点电连接，所述第四控制晶体管的第一极与所述第一时钟信号端电连接，所述第四控制晶体管的第二极与所述第二隔离节点电连接；
    所述第二隔离晶体管的控制极与第二电压端电连接，所述第二隔离晶体管的第一极与第二隔离节点电连接，所述第二隔离晶体管的第二极与第三输入节点电连接。
  23. 如权利要求18至22中任一权利要求所述的栅极驱动单元，其中，所述第二输入节点控制子电路包括第五控制晶体管和第一电容；
    所述第五控制晶体管的控制极与所述第三输入节点电连接，所述第五控制晶体管的第一极与所述第二输入节点电连接，所述第五控制晶体管的第二极与输入时钟信号端电连接；
    所述第一电容的第一端与所述第三输入节点电连接，所述第一电容的第二端与所述第二输入节点电连接。
  24. 如权利要求20至22中任一权利要求所述的栅极驱动单元，其中，所述第二节点控制子电路包括第六控制晶体管和第七控制晶体管；
    所述第六控制晶体管的控制极与输入时钟信号端电连接，所述第六控制晶体管的第一极与所述第二输入节点电连接，所述第六控制晶体管的第二极与所述第二节点电连接；
    所述第七控制晶体管的控制极与所述第一隔离节点电连接，所述第七控制晶体管的第一极与第二时钟信号端或第三电压端电连接，所述第七控制晶体管的第二极与所述第二节点电连接。
  25. 一种驱动方法，应用于如权利要求1至24中任一权利要求所述的栅极驱动单元所述驱动方法包括：
    第一输入节点控制电路在时钟信号端提供的时钟信号的控制下，导通或断开输入端与第一输入节点之间的连接；
    当所述第一输入节点的电压信号为第一电压信号时，电荷泵电路在输入时钟信号端提供的输入时钟信号的控制下，控制将所述第一输入节点的电压信号转换为所述第一节点的电压信号，且使得所述第一节点的电压信号的极性与所述第一输入节点的电压信号的极性相同，所述第一节点的电压信号的电压值的绝对值大于所述第一输入节点的电压信号的电压值的绝对值。
  26. 一种栅极驱动电路，包括如权利要求1至24中任一权利要求所述的栅极驱动单元。
  27. 一种显示装置，包括如权利要求26所述的栅极驱动电路。
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1755757A (zh) * 2004-10-01 2006-04-05 三星电子株式会社 驱动电压产生电路及包括该驱动电压产生电路的显示装置
US20100033415A1 (en) * 2008-08-06 2010-02-11 Samsung Electronics Co., Ltd. Liquid crystal display and method of operating the same
US20110273416A1 (en) * 2010-05-06 2011-11-10 Samsung Electronics Co., Ltd. Voltage generating circuit and display apparatus having the same
CN106057138A (zh) * 2015-04-01 2016-10-26 矽创电子股份有限公司 电源电路、栅极驱动电路及显示模块
CN111415624A (zh) * 2020-04-29 2020-07-14 京东方科技集团股份有限公司 移位寄存器电路及其驱动方法、栅极驱动电路、显示装置
CN111445832A (zh) * 2020-05-07 2020-07-24 合肥京东方卓印科技有限公司 移位寄存单元、信号生成单元电路、驱动方法和显示装置

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101490476B1 (ko) * 2007-11-19 2015-02-05 삼성디스플레이 주식회사 게이트 구동회로 및 이를 포함하는 디스플레이장치
CN103996369B (zh) * 2014-05-14 2016-10-05 京东方科技集团股份有限公司 电荷泵电路的控制系统、方法、装置及显示装置
CN104505013B (zh) * 2014-12-24 2017-06-27 深圳市华星光电技术有限公司 驱动电路
CN105185294B (zh) * 2015-10-23 2017-11-14 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、移位寄存器和显示装置
KR102519822B1 (ko) * 2015-12-31 2023-04-12 엘지디스플레이 주식회사 유기발광다이오드 표시장치
CN106652918A (zh) * 2017-03-20 2017-05-10 京东方科技集团股份有限公司 一种goa单元及其驱动方法、goa电路、显示装置
KR102404766B1 (ko) * 2017-06-13 2022-06-03 삼성디스플레이 주식회사 스캔 구동부 및 이를 포함하는 표시 장치
US10339887B1 (en) * 2017-12-08 2019-07-02 Wuhan China Star Optoelectronics Technology Co., Ltd. Gate driver on array circuit
KR20200013923A (ko) * 2018-07-31 2020-02-10 엘지디스플레이 주식회사 게이트 구동부 및 이를 이용한 전계발광 표시장치
KR102047973B1 (ko) * 2018-12-03 2019-12-02 성균관대학교산학협력단 게이트 구동 회로 및 이를 포함하는 디스플레이 장치
CN109935187B (zh) * 2019-01-18 2020-08-18 合肥京东方卓印科技有限公司 移位寄存器单元、栅极驱动电路、显示装置及驱动方法
CN109686292B (zh) * 2019-01-25 2022-05-27 鄂尔多斯市源盛光电有限责任公司 栅极驱动单元、栅极驱动方法、栅极驱动电路和显示装置
CN109802561B (zh) * 2019-02-14 2020-07-07 京东方科技集团股份有限公司 一种电荷泵及其电压控制方法和显示面板
CN109903715B (zh) * 2019-04-09 2021-01-22 京东方科技集团股份有限公司 栅极驱动单元、栅极驱动方法、栅极驱动电路和显示装置
WO2021056239A1 (zh) * 2019-09-25 2021-04-01 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路和显示装置
CN111445833B (zh) * 2020-05-09 2022-09-13 合肥京东方卓印科技有限公司 移位寄存器单元及其控制方法、和栅极驱动电路

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1755757A (zh) * 2004-10-01 2006-04-05 三星电子株式会社 驱动电压产生电路及包括该驱动电压产生电路的显示装置
US20100033415A1 (en) * 2008-08-06 2010-02-11 Samsung Electronics Co., Ltd. Liquid crystal display and method of operating the same
US20110273416A1 (en) * 2010-05-06 2011-11-10 Samsung Electronics Co., Ltd. Voltage generating circuit and display apparatus having the same
CN106057138A (zh) * 2015-04-01 2016-10-26 矽创电子股份有限公司 电源电路、栅极驱动电路及显示模块
CN111415624A (zh) * 2020-04-29 2020-07-14 京东方科技集团股份有限公司 移位寄存器电路及其驱动方法、栅极驱动电路、显示装置
CN111445832A (zh) * 2020-05-07 2020-07-24 合肥京东方卓印科技有限公司 移位寄存单元、信号生成单元电路、驱动方法和显示装置

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