WO2022089067A1 - 栅极驱动单元、栅极驱动方法，栅极驱动电路和显示装置 - Google Patents

栅极驱动单元、栅极驱动方法，栅极驱动电路和显示装置 Download PDF

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Publication number
WO2022089067A1
WO2022089067A1 PCT/CN2021/118263 CN2021118263W WO2022089067A1 WO 2022089067 A1 WO2022089067 A1 WO 2022089067A1 CN 2021118263 W CN2021118263 W CN 2021118263W WO 2022089067 A1 WO2022089067 A1 WO 2022089067A1
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Prior art keywords
control
node
terminal
electrically connected
clock signal
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PCT/CN2021/118263
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English (en)
French (fr)
Inventor
李文强
姜春桐
石领
陈义鹏
谢帅
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to US17/785,742 priority Critical patent/US11830410B2/en
Publication of WO2022089067A1 publication Critical patent/WO2022089067A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a gate driving unit, a gate driving method, a gate driving circuit and a display device.
  • the gate drive signal required by the P-type transistor is generally output by the P-type transistor, and then the N-type transistor is obtained through the inverter.
  • the related gate driving unit applied to the LTPO pixel circuit needs to adopt a large number of transistors.
  • an embodiment of the present disclosure provides a gate driving unit, comprising a first clock signal terminal, a second clock signal terminal, a third clock signal terminal, a fourth clock signal terminal, a first output node control circuit, The second output node control circuit, the first control node control circuit and the output circuit, wherein,
  • the first output node control circuit is respectively connected with the first output node, the input end, the first clock signal end, the fourth clock signal end, the first control node, the third clock signal end, the first voltage end and the second voltage end an electrical connection for, under the control of an input signal provided by the input terminal, a first clock signal provided by the first clock signal terminal, and a fourth clock signal provided by the fourth clock signal terminal, according to the input signal and the first voltage signal provided by the first voltage terminal to control the potential of the first output node, and the control of the potential of the first control node and the third clock signal provided by the third clock signal terminal
  • the first control node control circuit is respectively electrically connected with the first clock signal terminal, the first voltage terminal, the first control node and the first control terminal, and is used for converting the first voltage under the control of the first clock signal writing the signal into the first control node, and under the control of the potential of the first control terminal, writing the first clock signal into the first control node;
  • the second output node control circuit is electrically connected to the second control terminal, the second clock signal terminal, the second output node, the first output node and the fourth clock signal terminal, respectively, and is used for under the potential of the second control terminal , write the second clock signal provided by the second clock signal terminal into the second control node, and control the communication between the second control node and the second output node under the control of the second clock signal , and under the control of the potential of the first output node, write a fourth clock signal into the second output node, and control and adjust the potential of the second output node according to the fourth clock signal;
  • the output circuit is respectively electrically connected with the first output node, the second output node, the fourth clock signal terminal, the first voltage terminal and the gate driving signal output terminal, and is used under the control of the potential of the first output node , controlling the writing of the first voltage signal into the gate driving signal output terminal, and controlling the writing of the fourth clock signal into the gate driving signal output terminal under the control of the potential of the second output node.
  • the first control terminal is the first output node; or,
  • the first control terminal is a first isolation node
  • the gate driving unit further includes a first isolation circuit; the first isolation node is electrically connected to the first output node through the first isolation circuit;
  • the control terminal of the first isolation circuit is electrically connected to the first control voltage terminal, and the first isolation circuit is used for controlling the first control voltage under the control of the first control voltage provided by the first control voltage terminal
  • the terminal communicates with the first output node.
  • the second control terminal is the first control node; or,
  • the second control terminal is a second isolation node, and the gate driving unit further includes a second isolation circuit
  • the control terminal of the second isolation circuit is electrically connected to the second control voltage terminal, and the second isolation circuit is used for controlling the second control voltage under the control of the second control voltage provided by the second control voltage terminal
  • the terminal communicates with the first control node.
  • the first output node control circuit includes a first control terminal control sub-circuit and a first output node control sub-circuit;
  • the first control terminal control sub-circuit is respectively electrically connected with the first node, the second node, the input terminal, the first clock signal terminal, the fourth clock signal terminal, the first voltage terminal and the first control terminal, and is used for Under the control of the input signal, the connection between the first voltage terminal and the first node is controlled, and is used to control the potential of the first node according to the input signal, and under the control of the fourth clock signal, control communication between the first node and the second node, and for controlling the communication between the second node and the first control terminal under the control of the first clock signal;
  • the first output node control sub-circuit is electrically connected to the second voltage terminal, the first control node, the third clock signal terminal and the first output node, respectively, and is used for the first control node at the Under the control of the potential and the third clock signal, the second voltage signal provided by the second voltage terminal is written into the first output node, and the potential of the first output node is controlled and adjusted according to the third clock signal.
  • the first control terminal control sub-circuit includes a first node control transistor, a second node control transistor, a third node control transistor and a first capacitor, wherein,
  • a control electrode of the first node control transistor is electrically connected to the input terminal, a first electrode of the first node control transistor is electrically connected to the first voltage terminal, and a second electrode of the first node control transistor is electrically connected electrically connected to the first node;
  • the control electrode of the second node control transistor is electrically connected to the fourth clock signal terminal, the first electrode of the second node control transistor is electrically connected to the first node, and the second node control transistor is electrically connected to the first node.
  • a diode is electrically connected to the second node;
  • the first end of the first capacitor is electrically connected to the input end, and the second end of the first capacitor is electrically connected to the first node;
  • the control electrode of the third node control transistor is electrically connected to the first clock signal terminal, the first electrode of the third node control transistor is electrically connected to the second node, and the third node control transistor is electrically connected to the second node.
  • the diode is electrically connected to the first control terminal.
  • the first output node control sub-circuit includes a fourth node control transistor, a fifth node control transistor and a second capacitor, wherein,
  • the control electrode of the fourth node control transistor is electrically connected to the first control node, and the first electrode of the fourth node control transistor is electrically connected to the second voltage terminal;
  • the control electrode of the fifth node control transistor is electrically connected to the third clock signal terminal, the first electrode of the fifth node control transistor is electrically connected to the second electrode of the fourth node control transistor, and the The second pole of the five-node control transistor is electrically connected to the first output node;
  • the first terminal of the second capacitor is electrically connected to the first output node, and the second terminal of the second capacitor is electrically connected to the third clock signal terminal.
  • the gate driving unit further includes a first isolation circuit
  • the first isolation circuit includes a first isolation transistor
  • the control electrode of the first isolation transistor is electrically connected to the first control voltage terminal, the first electrode of the first isolation transistor is electrically connected to the first control terminal, and the second electrode of the first isolation transistor is electrically connected is electrically connected to the first output node.
  • the first control node control circuit includes a sixth node control transistor and a seventh node control transistor, wherein,
  • the control electrode of the sixth node control transistor is electrically connected to the first clock signal terminal, the first electrode of the sixth node control transistor is electrically connected to the first voltage terminal, and the sixth node control transistor is electrically connected to the first voltage terminal.
  • the second pole is electrically connected to the first control node;
  • the control electrode of the seventh node control transistor is electrically connected to the first control terminal
  • the first electrode of the seventh node control transistor is electrically connected to the first control node
  • the third node of the seventh node control transistor is electrically connected to the first control node.
  • the diode is electrically connected to the first clock signal terminal.
  • the second output node control circuit includes an eighth node control transistor, a ninth node control transistor, a tenth node control transistor, a third capacitor and a fourth capacitor, wherein,
  • the control electrode of the eighth node control transistor is electrically connected to the second control terminal, and the first electrode of the eighth node control transistor is electrically connected to the second clock signal terminal;
  • the first end of the fourth capacitor is electrically connected to the second control end, and the second end of the fourth capacitor is electrically connected to the second pole of the eighth node control transistor;
  • the control pole of the ninth node control transistor is electrically connected to the second clock signal terminal, the first pole of the ninth node control transistor is electrically connected to the second pole of the eighth node control transistor, and the first pole of the ninth node control transistor is electrically connected to the second pole of the eighth node control transistor.
  • the second pole of the nine-node control transistor is electrically connected to the second output node;
  • a control electrode of the tenth node control transistor is electrically connected to the first output node, a first electrode of the tenth node control transistor is electrically connected to the second output node, and a first electrode of the tenth node control transistor is electrically connected to the second output node.
  • the diode is electrically connected to the fourth clock signal terminal;
  • the first terminal of the third capacitor is electrically connected to the second output node, and the second terminal of the third capacitor is electrically connected to the fourth clock signal terminal.
  • the second isolation circuit includes a second isolation transistor
  • the control electrode of the second isolation transistor is electrically connected to the second control voltage terminal, the first electrode of the second isolation transistor is electrically connected to the first control node, and the second electrode of the second isolation transistor is electrically connected is electrically connected to the second control terminal.
  • the output circuit includes a first output transistor and a second output transistor
  • the control electrode of the first output transistor is electrically connected to the first output node, the first electrode of the first output transistor is electrically connected to the gate drive signal output terminal, and the second electrode of the first output transistor is electrically connected to the gate drive signal output terminal.
  • the first voltage terminal is electrically connected;
  • the control electrode of the second output transistor is electrically connected to the second output node, the first electrode of the second output transistor is electrically connected to the fourth clock signal terminal, and the second electrode of the second output transistor is electrically connected is electrically connected to the gate driving signal output terminal.
  • an embodiment of the present disclosure further provides a gate driving method, which is applied to the above gate driving unit, and the gate driving method includes:
  • the first output node control circuit controls the potential of the first output node according to the input signal and the first voltage signal under the control of the input signal, the first clock signal and the fourth clock signal. Under the control of the potential of the control node and the third clock signal, the second voltage signal is written into the first output node, and the potential of the first output node is controlled and adjusted according to the third clock signal;
  • the first control node control circuit writes the first voltage signal into the first control node under the control of the first clock signal, and writes the first clock signal into the first control node under the control of the potential of the first control terminal;
  • the second output node control circuit writes the second clock signal into the second control node under the potential of the second control terminal, and controls the communication between the second control node and the second output node under the control of the second clock signal, and the first Under the control of the potential of the first output node, the two-output node control circuit writes the fourth clock signal into the second output node, and controls and adjusts the potential of the second output node according to the fourth clock signal;
  • the output circuit controls to write the first voltage signal into the gate drive signal output terminal, and the output circuit controls the fourth clock to be written under the control of the potential of the second output node. A signal is written to the gate drive signal output terminal.
  • an embodiment of the present disclosure further provides a gate driving circuit, which includes the above-mentioned gate driving unit in multiple stages.
  • an embodiment of the present disclosure further provides a display device including the above gate driving circuit.
  • FIG. 1 is a structural diagram of a gate driving unit according to at least one embodiment of the present disclosure
  • FIG. 2 is a structural diagram of a gate driving unit according to at least one embodiment of the present disclosure
  • FIG. 3 is a structural diagram of a gate driving unit according to at least one embodiment of the present disclosure.
  • FIG. 4 is a structural diagram of a gate driving unit according to at least one embodiment of the present disclosure.
  • FIG. 5 is a structural diagram of a gate driving unit according to at least one embodiment of the present disclosure.
  • 6A and 6B are circuit diagrams of a gate driving unit according to at least one embodiment of the present disclosure.
  • FIG. 7 is an operation timing diagram of at least one embodiment of the gate driving unit shown in FIG. 6A of the present disclosure.
  • FIG. 8 is a simulation operation timing diagram corresponding to FIG. 7 of at least one embodiment of the gate driving unit shown in FIG. 6A of the present disclosure
  • FIG. 9 is a waveform diagram of each node during operation of at least one embodiment of the gate driving unit shown in FIG. 6A of the present disclosure.
  • the gate driving unit includes a first clock signal terminal, a second clock signal terminal, a third clock signal terminal, a fourth clock signal terminal, and a first output node control circuit 11.
  • the first output node control circuit 11 is respectively connected with the first output node N9, the input terminal I1, the first clock signal terminal, the fourth clock signal terminal, the first control node N4, the third clock signal terminal, and the first voltage terminal V1.
  • the potential of the first output node N9 is controlled according to the input signal and the first voltage signal provided by the first voltage terminal V1
  • the potential of the first control node N4 and the first voltage Under the control of the third clock signal CK3 provided by the three clock signal terminals, the second voltage signal provided by the second voltage terminal V2 is written into the first output node N9, and the first output node is controlled and adjusted according to the third clock signal CK3
  • the first control node control circuit 13 is respectively electrically connected to the first clock signal terminal, the first voltage terminal V1, the first control node N4 and the first control terminal N3, and is used for under the control of the first clock signal CK1 , write the first voltage signal into the first control node N4, and under the control of the potential of the first control terminal N3, write the first clock signal CK1 into the first control node N4;
  • the second output node control circuit 12 is respectively electrically connected with the second control terminal N6, the second clock signal terminal, the second output node N8, the first output node N9 and the fourth clock signal terminal, and is used for the second output node Under the potential of the control terminal N6, the second clock signal CK2 provided by the second clock signal terminal is written into the second control node N7, and under the control of the second clock signal CK2, the second control node N7 is controlled communicated with the second output node N8, and under the control of the potential of the first output node N9, the fourth clock signal CK4 is written into the second output node N8, and according to the fourth clock signal CK4 controlling and adjusting the potential of the second output node N8;
  • the output circuit 14 is respectively electrically connected with the first output node N9, the second output node N8, the fourth clock signal terminal, the first voltage terminal V1 and the gate driving signal output terminal O1, and is used for connecting the first output node at the first output node.
  • the first voltage signal is controlled to be written into the gate driving signal output terminal O1
  • the fourth clock signal CK4 is controlled to be written into the gate drive signal output terminal O1.
  • the gate driving unit described in at least one embodiment of the present disclosure can provide a gate driving signal required by an N-type transistor for an LTPO (low temperature polycrystalline oxide) pixel circuit, and can reduce the number of transistors used, which is conducive to realizing a narrow frame.
  • LTPO low temperature polycrystalline oxide
  • the first voltage terminal may be a low voltage terminal
  • the second voltage terminal may be a high voltage terminal, but not limited thereto.
  • the first output node control circuit 11 is controlled by the input signal, the first clock signal CK1 and the fourth clock signal CK4 according to the input signal. and the first voltage signal to control the potential of the first output node N9, and under the control of the potential of the first control node N4 and the third clock signal CK3, write a second voltage signal into the first output node N9, and control and adjust the potential of the first output node N9 according to the third clock signal CK3;
  • the first control node control circuit 13 Under the control of the first clock signal CK1, the first control node control circuit 13 writes a first voltage signal into the first control node N4, and under the control of the potential of the first control terminal N3, writes the first voltage signal to the first control node N4.
  • the first clock signal CK1 is written into the first control node N4;
  • the second output node control circuit 12 writes the second clock signal CK2 into the second control node N7 under the potential of the second control terminal N6, and controls the second clock signal CK2 under the control of the second clock signal CK2.
  • the second control node N7 is communicated with the second output node N8, and under the control of the potential of the first output node N9, the fourth clock signal CK4 is written into the second output node N8, and according to the The fourth clock signal CK4 controls and adjusts the potential of the second output node N8;
  • the output circuit 14 controls the writing of the first voltage signal into the gate driving signal output terminal O1, and the control of the potential of the second output node N8 Next, the fourth clock signal CK4 is controlled to be written into the gate driving signal output terminal O1.
  • the first control terminal is the first output node; or,
  • the first control terminal is a first isolation node
  • the gate driving unit further includes a first isolation circuit; the first isolation node is electrically connected to the first output node through the first isolation circuit;
  • the control terminal of the first isolation circuit is electrically connected to the first control voltage terminal, and the first isolation circuit is used for controlling the first control voltage under the control of the first control voltage provided by the first control voltage terminal
  • the terminal communicates with the first output node.
  • the second control terminal is the first control node; or,
  • the second control terminal is a second isolation node, and the gate driving unit further includes a second isolation circuit
  • the control terminal of the second isolation circuit is electrically connected to the second control voltage terminal, and the second isolation circuit is used for controlling the second control voltage under the control of the second control voltage provided by the second control voltage terminal
  • the terminal communicates with the first control node.
  • the first control terminal and is the first output node N9
  • the second control terminal is the The first control node N4.
  • the gate driving unit according to at least one embodiment of the present disclosure further includes a first isolation circuit 31 and a second isolation circuit 32;
  • the control terminal of the first isolation circuit 31 is electrically connected to the first control voltage terminal Vc1, the first terminal of the first isolation circuit 31 is electrically connected to the first control terminal N3, and the first isolation circuit 31 is electrically connected to the first control terminal N3.
  • the second terminal is electrically connected to the first output node N9, and the first isolation circuit 31 is configured to control the first control terminal N3 under the control of the first control voltage provided by the first control voltage terminal Vc1 communicated with the first output node N9;
  • the control terminal of the second isolation circuit 32 is electrically connected to the second control voltage terminal Vc2, the first terminal of the second isolation circuit 32 is electrically connected to the second control terminal N6, and the second isolation circuit 32 is electrically connected to the second control terminal N6.
  • the second terminal is electrically connected to the first control node N4, and the second isolation circuit 32 is configured to control the second control terminal N6 under the control of the second control voltage provided by the second control voltage terminal Vc2 It communicates with the first control node N4.
  • the gate driving unit when the gate driving unit according to at least one embodiment of the present disclosure further includes a first isolation circuit 31 and a second isolation circuit 32 , the first control terminal N3 is also connected to the first isolation circuit 31 and the first isolation circuit 32 .
  • the output node control circuit 11 is electrically connected.
  • the first isolation circuit 31 may include a first isolation transistor
  • the second isolation circuit 32 may include a second isolation transistor.
  • the first isolation transistor and the second isolation transistor are P-type In the case of transistors
  • the first control voltage terminal and the second control voltage terminal may be low voltages
  • the first isolation transistor and the second isolation transistor may be normally-on transistors
  • the first isolation transistor is used for To stabilize the potential of the first output node
  • the second isolation transistor is used to stabilize the potential of the second control terminal N6.
  • the first output node control circuit may include a first control terminal controller circuit 111 and the first output node control sub-circuit 112;
  • the first control terminal control sub-circuit 111 is electrically connected to the first node N1, the second node N2, the input terminal I1, the first clock signal terminal, the fourth clock signal terminal, the first voltage terminal V1 and the first control terminal N3 respectively. connection, for controlling the connection between the first voltage terminal V1 and the first node N1 under the control of the input signal, and for controlling the potential of the first node N1 according to the input signal, in the Under the control of the fourth clock signal CK4, the communication between the first node N1 and the second node N2 is controlled, and is used to control the second node N2 and the second node N2 under the control of the first clock signal CK1. communication between the first control terminals N3;
  • the first output node control sub-circuit 112 is electrically connected to the second voltage terminal V2, the first control node N4, the third clock signal terminal and the first output node N9, respectively, and is used for the first output node N9. Under the control of the potential of a control node N4 and the third clock signal CK3, the second voltage signal provided by the second voltage terminal V2 is written into the first output node N9, and the first output is controlled and adjusted according to the third clock signal CK3 The potential of node N9;
  • the first output node control circuit 11 includes a first control terminal control sub-circuit 111 and a first output node control sub-circuit 112, the first control terminal control sub-circuit 111 controls the potential of the first control terminal N3, The first output node control sub-circuit 112 controls the potential of the first output node N9.
  • the first control terminal control sub-circuit includes a first node control transistor, a second node control transistor, a third node control transistor and a first capacitor, wherein,
  • a control electrode of the first node control transistor is electrically connected to the input terminal, a first electrode of the first node control transistor is electrically connected to the first voltage terminal, and a second electrode of the first node control transistor is electrically connected electrically connected to the first node;
  • the control electrode of the second node control transistor is electrically connected to the fourth clock signal terminal, the first electrode of the second node control transistor is electrically connected to the first node, and the second node control transistor is electrically connected to the first node.
  • a diode is electrically connected to the second node;
  • the first end of the first capacitor is electrically connected to the input end, and the second end of the first capacitor is electrically connected to the first node;
  • the control electrode of the third node control transistor is electrically connected to the first clock signal terminal, the first electrode of the third node control transistor is electrically connected to the second node, and the third node control transistor is electrically connected to the second node.
  • the diode is electrically connected to the first control terminal.
  • the first output node control sub-circuit includes a fourth node control transistor, a fifth node control transistor and a second capacitor, wherein,
  • the control electrode of the fourth node control transistor is electrically connected to the first control node, and the first electrode of the fourth node control transistor is electrically connected to the second voltage terminal;
  • the control electrode of the fifth node control transistor is electrically connected to the third clock signal terminal, the first electrode of the fifth node control transistor is electrically connected to the second electrode of the fourth node control transistor, and the first electrode of the fifth node control transistor is electrically connected to the second electrode of the fourth node control transistor.
  • the second pole of the five-node control transistor is electrically connected to the first output node;
  • the first terminal of the second capacitor is electrically connected to the first output node, and the second terminal of the second capacitor is electrically connected to the third clock signal terminal.
  • the gate driving unit when the gate driving unit further includes a first isolation circuit, the first isolation circuit includes a first isolation transistor;
  • the control electrode of the first isolation transistor is electrically connected to the first control voltage terminal, the first electrode of the first isolation transistor is electrically connected to the first control terminal, and the second electrode of the first isolation transistor is electrically connected is electrically connected to the first output node.
  • the first control node control circuit includes a sixth node control transistor and a seventh node control transistor, wherein,
  • the control electrode of the sixth node control transistor is electrically connected to the first clock signal terminal, the first electrode of the sixth node control transistor is electrically connected to the first voltage terminal, and the sixth node control transistor is electrically connected to the first voltage terminal.
  • the second pole is electrically connected to the first control node;
  • the control electrode of the seventh node control transistor is electrically connected to the first control terminal
  • the first electrode of the seventh node control transistor is electrically connected to the first control node
  • the third node of the seventh node control transistor is electrically connected to the first control node.
  • the diode is electrically connected to the first clock signal terminal.
  • the second output node control circuit includes an eighth node control transistor, a ninth node control transistor, a tenth node control transistor, a third capacitor and a fourth capacitor, wherein,
  • the control electrode of the eighth node control transistor is electrically connected to the second control terminal, and the first electrode of the eighth node control transistor is electrically connected to the second clock signal terminal;
  • the first end of the fourth capacitor is electrically connected to the second control end, and the second end of the fourth capacitor is electrically connected to the second pole of the eighth node control transistor;
  • the control pole of the ninth node control transistor is electrically connected to the second clock signal terminal, the first pole of the ninth node control transistor is electrically connected to the second pole of the eighth node control transistor, and the first pole of the ninth node control transistor is electrically connected to the second pole of the eighth node control transistor.
  • the second pole of the nine-node control transistor is electrically connected to the second output node;
  • a control electrode of the tenth node control transistor is electrically connected to the first output node, a first electrode of the tenth node control transistor is electrically connected to the second output node, and a first electrode of the tenth node control transistor is electrically connected to the second output node.
  • the diode is electrically connected to the fourth clock signal terminal;
  • the first terminal of the third capacitor is electrically connected to the second output node, and the second terminal of the third capacitor is electrically connected to the fourth clock signal terminal.
  • the second isolation circuit includes a second isolation transistor
  • the control electrode of the second isolation transistor is electrically connected to the second control voltage terminal, the first electrode of the second isolation transistor is electrically connected to the first control node, and the second electrode of the second isolation transistor is electrically connected is electrically connected to the second control terminal.
  • the first isolation circuit 31 includes a first isolation transistor T13
  • the second isolation circuit 32 includes a second isolation circuit transistor T14;
  • the gate of the first isolation transistor T13 is electrically connected to the first control voltage terminal Vc1, the drain of the first isolation transistor T13 is electrically connected to the first control terminal N3, and the first isolation transistor T13 The source of is electrically connected to the first output node N9;
  • the gate of the second isolation transistor T14 is electrically connected to the second control voltage terminal Vc2
  • the drain of the second isolation transistor T14 is electrically connected to the first control node N4
  • the second isolation transistor T14 is electrically connected to the first control node N4.
  • the source electrode of is electrically connected to the second control terminal N6.
  • T13 and T14 may be P-type thin film transistors, Vc1 and Vc2 may be low voltage terminals, and T13 and T14 may be normally-on transistors, but not limited thereto.
  • the output circuit includes a first output transistor and a second output transistor
  • the control electrode of the first output transistor is electrically connected to the first output node, the first electrode of the first output transistor is electrically connected to the gate drive signal output terminal, and the second electrode of the first output transistor is electrically connected to the gate drive signal output terminal.
  • the first voltage terminal is electrically connected;
  • the control electrode of the second output transistor is electrically connected to the second output node, the first electrode of the second output transistor is electrically connected to the fourth clock signal terminal, and the second electrode of the second output transistor is electrically connected is electrically connected to the gate driving signal output terminal.
  • the first output node control circuit includes a first control terminal control sub-circuit and a first output node control sub-circuit;
  • the first control terminal control sub-circuit includes a first node control transistor T1, a second node control transistor T2, a third node control transistor T3 and a first capacitor C1, wherein,
  • the gate of the first node control transistor T1 is electrically connected to the input terminal I1, the drain of the first node control transistor T1 is electrically connected to the low voltage terminal, and the source of the first node control transistor T1 is electrically connected to the low voltage terminal.
  • the first node N1 is electrically connected; the low voltage terminal is used for providing the low voltage VGL;
  • the gate of the second node control transistor T3 is electrically connected to the fourth clock signal terminal, the drain of the second node control transistor T3 is electrically connected to the first node N1, and the second node control transistor T3 is electrically connected to the first node N1.
  • the source of T3 is electrically connected to the second node N2; the fourth clock signal terminal is used to provide a fourth clock signal CK4;
  • the first end of the first capacitor C1 is electrically connected to the input end I1, and the second end of the first capacitor C1 is electrically connected to the first node N1;
  • the gate of the third node control transistor T3 is electrically connected to the first clock signal terminal, the drain of the third node control transistor T3 is electrically connected to the second node N2, and the third node control transistor T3 is electrically connected to the second node N2.
  • the source of T3 is electrically connected to the first control terminal N3;
  • the first output node control sub-circuit includes a fourth node control transistor T7, a fifth node control transistor T6 and a second capacitor C4, wherein,
  • the gate of the fourth node control transistor T7 is electrically connected to the first control node N4, and the drain of the fourth node control transistor T7 is electrically connected to a high voltage terminal; the high voltage terminal is used to provide a high voltage VGH;
  • the gate of the fifth node control transistor T6 is electrically connected to the third clock signal terminal, the drain of the fifth node control transistor T6 is electrically connected to the source of the fourth node control transistor T7, and the source of the fifth node control transistor T6 is electrically connected to the first output node N9;
  • the third clock signal terminal is used for providing the third clock signal CK3;
  • the first end of the second capacitor C4 is electrically connected to the first output node N9, and the second end of the second capacitor C4 is electrically connected to the third clock signal terminal;
  • the first control node control circuit includes a sixth node control transistor T5 and a seventh node control transistor T4, wherein,
  • the gate of the sixth node control transistor T5 is electrically connected to the first clock signal terminal, the drain of the sixth node control transistor T5 is electrically connected to the low voltage terminal, and the sixth node control transistor T5
  • the source is electrically connected to the first control node N4; the first clock signal terminal is used to provide the first clock signal CK1;
  • the gate of the seventh node control transistor T4 is electrically connected to the first control terminal N3, the drain of the seventh node control transistor T4 is electrically connected to the first control node N4, and the seventh node controls the source of the transistor T4 is electrically connected to the first clock signal terminal;
  • the second output node control circuit includes an eighth node control transistor T8, a ninth node control transistor T9, a tenth node control transistor T10, a third capacitor C3 and a fourth capacitor C2, wherein,
  • the gate of the eighth node control transistor T8 is electrically connected to the second control terminal N6, and the drain of the eighth node control transistor T8 is electrically connected to the second clock signal terminal; the second clock signal The terminal is used to provide the second clock signal CK2;
  • the first terminal of the fourth capacitor C2 is electrically connected to the second control terminal N6, and the second terminal of the fourth capacitor C2 is electrically connected to the source of the eighth node control transistor T8;
  • the gate of the ninth node control transistor T9 is electrically connected to the second clock signal terminal, the drain of the ninth node control transistor T9 is electrically connected to the source of the eighth node control transistor T8, and the source of the ninth node control transistor T9 is electrically connected to the second output node N8;
  • the gate of the tenth node control transistor T10 is electrically connected to the first output node N9, the drain of the tenth node control transistor T10 is electrically connected to the second output node N8, and the tenth node controls
  • the source of the transistor T10 is electrically connected to the fourth clock signal terminal; the fourth clock signal terminal is used to provide the fourth clock signal CK4;
  • the first terminal of the third capacitor C3 is electrically connected to the second output node N8, and the second terminal of the third capacitor C3 is electrically connected to the fourth clock signal terminal;
  • the output circuit includes a first output transistor T12 and a second output transistor T11;
  • the gate of the first output transistor T12 is electrically connected to the first output node N9, the drain of the first output transistor T12 is electrically connected to the gate driving signal output terminal O1, and the first output transistor T12 has an electrical connection.
  • the source electrode is electrically connected to the low voltage terminal;
  • the gate of the second output transistor T11 is electrically connected to the second output node N8, the drain of the second output transistor T11 is electrically connected to the fourth clock signal terminal, and the drain of the second output transistor T11 is electrically connected to the fourth clock signal terminal.
  • the source electrode is electrically connected to the gate driving signal output terminal O1.
  • all transistors are P-type thin film transistors, but not limited thereto.
  • FIG. 6B is a drawing in which reference numerals 31 , 32 , 111 , 112 , 12 , 13 and 14 are added on the basis of FIG. 6A .
  • N7 is a node electrically connected to the source of T8
  • N5 is a node electrically connected to the drain of T6 .
  • I1 provides a low voltage
  • CK2 is a high voltage
  • CK4 is a low voltage
  • T1 and T2 are continuously turned on, and T5 is turned on when CK1 is low, so that N4
  • the potential is VGL-Vth(5), where Vth(5) is the threshold voltage of T5; when CK3 becomes high voltage, T6 is turned off, CK1 is low voltage at this time, and the potential of N3 drops to turn on T4, N4
  • the potential is low voltage, T14 is turned on, the potential of N6 is low voltage, until CK1 becomes high voltage, the potential of N4 and the potential of N6 are pulled high; when CK1 is low voltage, CK3 is high voltage, the potential of N3 and N9
  • the potential can be written to a low potential to turn on T4; T9 continues to be off, the falling edge of CK3 will pull down the potential of N9 due to the capacitor bootstrap, T10 is
  • I1 provides low voltage
  • CK1 is high voltage
  • CK3 is low voltage
  • the potential of N1, N2 and N3 are kept as low voltage
  • CK1 is high voltage
  • the potential of N4 and the potential of N6 are
  • the voltage is high
  • the potential of N9 is kept at a low voltage
  • T12 is turned on
  • the potential of CK4 is raised from a low voltage to a high voltage, due to the bootstrapping effect of C3
  • the potential of N8 is pulled high
  • T11 is turned off, and O1 outputs a low voltage
  • I1 provides a high voltage
  • CK2 is a high voltage
  • CK4 is a low voltage
  • the potential of N1 is pulled high due to the bootstrap effect of C1
  • T1 is turned off
  • T2 is turned on
  • T3 is turned on when CK1 is low voltage
  • T13 is turned on
  • the potential of N1, N2, N3 and N9 will be pulled up to varying degrees when the potential of CK1 is set low
  • T10 and T12 are turned off, T9 is continuously turned off, and the potential of N8 remains at Low voltage
  • T11 is turned on, O1 outputs low voltage
  • I1 provides a low voltage
  • CK1 is a high voltage
  • CK3 is a low voltage
  • T6 is turned off
  • the potential of N9 is maintained at a high voltage
  • T10 and T12 are turned off
  • T5 is turned off
  • T4 is turned off
  • T1 is turned off
  • the potential of N4 is maintained at low voltage
  • the potential of N6 is low voltage
  • the potential of CK2 becomes low voltage
  • T8 and T8 are turned on
  • the potential of N7 and N8 are low voltage
  • T11 is turned on
  • O1 Output CK4 when the potential of CK2 jumps from high voltage to low voltage, due to the bootstrapping effect of C2, the potential of N6 will be pulled lower, making T8 open more thoroughly;
  • I1 provides a low voltage
  • CK2 is a high voltage
  • CK4 is a low voltage
  • T1 and T2 are turned on
  • the potential of N1 and N2 is a low voltage
  • T3 is turned on
  • the potential of N1 is turned on.
  • N2 and N3 are pulled down, T4 is turned on, when CK1 is low voltage, T5 is turned on, N4 is low voltage, T14 is turned on (T14 is always open), N6 is low voltage, T8 is turned on,
  • the potential of N7 is a high voltage (the high potential of CK2 writes the potential of N7 as a high voltage); when the potential of CK1 changes from a low voltage to a high voltage, T5 is turned off, and the potential of N4 becomes a high voltage (at this time, the potential of T4 Turn on, the high potential of CK1 writes the potential of N4 as a high voltage), T14 is turned on (T14 is always open), the potential of N6 is high voltage, T8 is turned off, and the potential of N7 is maintained as a high voltage; T9 is turned off, the potential of N8 In the fourth stage S4 is low, and the potential of N8 is pulled to a lower voltage by C3 in the fifth stage S5, T11 is completely turned on, the potential of
  • the potential of N9 can be periodically lowered under the control of the third clock signal CK3, so that T12 can be turned on completely, reducing the The output waveform suffers from the loss of the threshold voltage of T12.
  • the first isolation transistor T13 is used to stabilize the potential of the first output node N9
  • the second isolation transistor T14 is used to stabilize the second Control the potential of the terminal N6; since both N9 and N6 are electrically connected to the capacitor, the stability of the potential of N9 and the potential of N6 are very beneficial to the stable operation of the circuit.
  • the falling edge of CK1 precedes the rising edge of CK3
  • the rising edge of CK1 precedes the falling edge of CK3
  • the falling edge of CK2 precedes the rising edge of CK4
  • the rising edge of CK2 precedes the falling edge of CK4. But not limited to this.
  • At least one embodiment of the gate driving unit shown in FIG. 6A of the present disclosure can provide the gate driving signal required for the operation of the N-type transistor through O1, and uses a small number of transistors, which is beneficial to realize a narrow frame.
  • FIG. 8 is a simulation operation timing diagram corresponding to FIG. 7 of at least one embodiment of the gate driving unit shown in FIG. 6A of the present disclosure
  • FIG. 9 is a waveform diagram of each node during operation of at least one embodiment of the gate driving unit shown in FIG. 6A of the present disclosure.
  • the gate driving method described in at least one embodiment of the present disclosure is applied to the above-mentioned gate driving unit, and the gate driving method includes:
  • the first output node control circuit controls the potential of the first output node according to the input signal and the first voltage signal under the control of the input signal, the first clock signal and the fourth clock signal. Under the control of the potential of the control node and the third clock signal, the second voltage signal is written into the first output node, and the potential of the first output node is controlled and adjusted according to the third clock signal;
  • the first control node control circuit writes the first voltage signal into the first control node under the control of the first clock signal, and writes the first clock signal into the first control node under the control of the potential of the first control terminal;
  • the second output node control circuit writes the second clock signal into the second control node under the potential of the second control terminal, and controls the communication between the second control node and the second output node under the control of the second clock signal, and the first Under the control of the potential of the first output node, the two-output node control circuit writes the fourth clock signal into the second output node, and controls and adjusts the potential of the second output node according to the fourth clock signal;
  • the output circuit controls to write the first voltage signal into the gate drive signal output terminal, and the output circuit controls the fourth clock to be written under the control of the potential of the second output node. A signal is written to the gate drive signal output terminal.
  • the gate driving circuit according to the embodiment of the present disclosure includes multiple stages of the above-mentioned gate driving units.
  • the input terminal of the gate driving unit in the gate driving circuit is electrically connected to the gate driving signal output terminal of the adjacent upper-stage gate driving unit.
  • a display device includes the above-mentioned gate driving circuit.
  • the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.

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Abstract

一种栅极驱动单元、栅极驱动方法，栅极驱动电路和显示装置。栅极驱动单元包括第一时钟信号端、第二时钟信号端、第三时钟信号端、第四时钟信号端、第一输出节点控制电路（11）、第二输出节点控制电路（12）、第一控制节点控制电路（13）和输出电路（14）。栅极驱动单元能够为LTPO(低温多晶氧化物)像素电路提供N型晶体管需要的栅极驱动信号，并能够减少采用的晶体管的数目，利于实现窄边框。

Description

栅极驱动单元、栅极驱动方法，栅极驱动电路和显示装置
相关申请的交叉引用
本申请主张在2020年10月26日在中国提交的中国专利申请号No.202011155389.9的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种栅极驱动单元、栅极驱动方法，栅极驱动电路和显示装置。
背景技术
在相关的应用于LTPO(低温多晶氧化物)像素电路的栅极驱动单元中，一般是由P型晶体管管输出P型晶体管所需的栅极驱动信号，再通过反相器得到N型晶体管所需的栅极驱动信号，相关的应用于LTPO像素电路的栅极驱动单元需要采用的晶体管的数目多。
发明内容
在一个方面中，本公开实施例提供了一种栅极驱动单元，包括第一时钟信号端、第二时钟信号端、第三时钟信号端、第四时钟信号端、第一输出节点控制电路、第二输出节点控制电路、第一控制节点控制电路和输出电路，其中，
所述第一输出节点控制电路分别与第一输出节点、输入端、第一时钟信号端、第四时钟信号端、第一控制节点、第三时钟信号端、第一电压端和第二电压端电连接，用于在所述输入端提供的输入信号、所述第一时钟信号端提供的第一时钟信号和所述第四时钟信号端提供的第四时钟信号的控制下，根据所述输入信号和所述第一电压端提供的第一电压信号控制所述第一输出节点的电位，并在所述第一控制节点的电位和所述第三时钟信号端提供的第三时钟信号的控制下，将第二电压端提供的第二电压信号写入所述第一输出节点，并根据第三时钟信号控制调节第一输出节点的电位；
所述第一控制节点控制电路分别与第一时钟信号端、第一电压端、第一控制节点和第一控制端电连接，用于在所述第一时钟信号的控制下，将第一电压信号写入第一控制节点，并在所述第一控制端的电位的控制下，将第一时钟信号写入第一控制节点；
所述第二输出节点控制电路分别与第二控制端、第二时钟信号端、第二输出节点、第一输出节点和第四时钟信号端电连接，用于在所述第二控制端的电位下，将所述第二时钟信号端提供的第二时钟信号写入第二控制节点，在所述第二时钟信号的控制下，控制所述第二控制节点与所述第二输出节点之间连通，并在第一输出节点的电位的控制下，将第四时钟信号写入所述第二输出节点，并根据所述第四时钟信号控制调节第二输出节点的电位；
所述输出电路分别与第一输出节点、第二输出节点、第四时钟信号端、第一电压端和栅极驱动信号输出端电连接，用于在所述第一输出节点的电位的控制下，控制将第一电压信号写入所述栅极驱动信号输出端，在所述第二输出节点的电位的控制下，控制将第四时钟信号写入所述栅极驱动信号输出端。
可选的，第一控制端为所述第一输出节点；或者，
所述第一控制端为第一隔离节点，所述栅极驱动单元还包括第一隔离电路；所述第一隔离节点通过所述第一隔离电路与所述第一输出节点电连接；
所述第一隔离电路的控制端与第一控制电压端电连接，所述第一隔离电路用于在所述第一控制电压端提供的第一控制电压的控制下，控制所述第一控制端与所述第一输出节点之间连通。
可选的，所述第二控制端为所述第一控制节点；或者，
所述第二控制端为第二隔离节点，所述栅极驱动单元还包括第二隔离电路；
所述第二隔离电路的控制端与第二控制电压端电连接，所述第二隔离电路用于在所述第二控制电压端提供的第二控制电压的控制下，控制所述第二控制端与所述第一控制节点之间连通。
可选的，所述第一输出节点控制电路包括第一控制端控制子电路和第一输出节点控制子电路；
所述第一控制端控制子电路分别与第一节点、第二节点、输入端、第一时钟信号端、第四时钟信号端、第一电压端和第一控制端电连接，用于在所述输入信号的控制下，控制所述第一电压端与第一节点之间连通，并用于根据所述输入信号控制所述第一节点的电位，在所述第四时钟信号的控制下，控制所述第一节点与所述第二节点之间连通，并用于在所述第一时钟信号的控制下，控制所述第二节点与所述第一控制端之间连通；
所述第一输出节点控制子电路分别与第二电压端、所述第一控制节点、所述第三时钟信号端和所述第一输出节点电连接，用于在所述第一控制节点的电位和第三时钟信号的控制下，将第二电压端提供的第二电压信号写入所述第一输出节点，并根据第三时钟信号控制调节第一输出节点的电位。
可选的，所述第一控制端控制子电路包括第一节点控制晶体管、第二节点控制晶体管、第三节点控制晶体管和第一电容，其中，
所述第一节点控制晶体管的控制极与所述输入端电连接，所述第一节点控制晶体管的第一极与所述第一电压端电连接，所述第一节点控制晶体管的第二极与所述第一节点电连接；
所述第二节点控制晶体管的控制极与所述第四时钟信号端电连接，所述第二节点控制晶体管的第一极与所述第一节点电连接，所述第二节点控制晶体管的第二极与所述第二节点电连接；
所述第一电容的第一端与所述输入端电连接，所述第一电容的第二端与所述第一节点电连接；
所述第三节点控制晶体管的控制极与所述第一时钟信号端电连接，所述第三节点控制晶体管的第一极与所述第二节点电连接，所述第三节点控制晶体管的第二极与所述第一控制端电连接。
可选的，所述第一输出节点控制子电路包括第四节点控制晶体管、第五节点控制晶体管和第二电容，其中，
所述第四节点控制晶体管的控制极与所述第一控制节点电连接，所述第四节点控制晶体管的第一极与所述第二电压端电连接；
所述第五节点控制晶体管的控制极与所述第三时钟信号端电连接，所述第五节点控制晶体管的第一极与所述第四节点控制晶体管的第二极电连接， 所述第五节点控制晶体管的第二极与所述第一输出节点电连接；
所述第二电容的第一端与所述第一输出节点电连接，所述第二电容的第二端与所述第三时钟信号端电连接。
可选的，当所述栅极驱动单元还包括第一隔离电路时，所述第一隔离电路包括第一隔离晶体管；
所述第一隔离晶体管的控制极与所述第一控制电压端电连接，所述第一隔离晶体管的第一极与所述第一控制端电连接，所述第一隔离晶体管的第二极与所述第一输出节点电连接。
可选的，所述第一控制节点控制电路包括第六节点控制晶体管和第七节点控制晶体管，其中，
所述第六节点控制晶体管的控制极与所述第一时钟信号端电连接，所述第六节点控制晶体管的第一极与所述第一电压端电连接，所述第六节点控制晶体管的第二极与所述第一控制节点电连接；
所述第七节点控制晶体管的控制极与所述第一控制端电连接，所述第七节点控制晶体管的第一极与所述第一控制节点电连接，所述第七节点控制晶体管的第二极与所述第一时钟信号端电连接。
可选的，所述第二输出节点控制电路包括第八节点控制晶体管、第九节点控制晶体管、第十节点控制晶体管、第三电容和第四电容，其中，
所述第八节点控制晶体管的控制极与所述第二控制端电连接，所述第八节点控制晶体管的第一极与所述第二时钟信号端电连接；
所述第四电容的第一端与所述第二控制端电连接，所述第四电容的第二端与所述第八节点控制晶体管的第二极电连接；
所述第九节点控制晶体管的控制极与所述第二时钟信号端电连接，所述第九节点控制晶体管的第一极与所述第八节点控制晶体管的第二极电连接，所述第九节点控制晶体管的第二极与所述第二输出节点电连接；
所述第十节点控制晶体管的控制极与所述第一输出节点电连接，所述第十节点控制晶体管的第一极与所述第二输出节点电连接，所述第十节点控制晶体管的第二极与所述第四时钟信号端电连接；
所述第三电容的第一端与所述第二输出节点电连接，所述第三电容的第 二端与所述第四时钟信号端电连接。
可选的，当所述栅极驱动单元还包括第二隔离电路时，所述第二隔离电路包括第二隔离晶体管；
所述第二隔离晶体管的控制极与所述第二控制电压端电连接，所述第二隔离晶体管的第一极与所述第一控制节点电连接，所述第二隔离晶体管的第二极与所述第二控制端电连接。
可选的，所述输出电路包括第一输出晶体管和第二输出晶体管；
所述第一输出晶体管的控制极与所述第一输出节点电连接，所述第一输出晶体管的第一极与栅极驱动信号输出端电连接，所述第一输出晶体管的第二极与所述第一电压端电连接；
所述第二输出晶体管的控制极与所述第二输出节点电连接，所述第二输出晶体管的第一极与所述第四时钟信号端电连接，所述第二输出晶体管的第二极与所述栅极驱动信号输出端电连接。
在第二个方面中，本公开实施例还提供了一种栅极驱动方法，应用于上述的栅极驱动单元，所述栅极驱动方法包括：
第一输出节点控制电路在输入信号、第一时钟信号和第四时钟信号的控制下，根据所述输入信号和第一电压信号控制第一输出节点的电位，第一输出节点控制电路在第一控制节点的电位和第三时钟信号的控制下，将第二电压信号写入第一输出节点，并根据第三时钟信号控制调节第一输出节点的电位；
第一控制节点控制电路在第一时钟信号的控制下，将第一电压信号写入第一控制节点，并在第一控制端的电位的控制下，将第一时钟信号写入第一控制节点；
第二输出节点控制电路在第二控制端的电位下，将第二时钟信号写入第二控制节点，在第二时钟信号的控制下，控制第二控制节点与第二输出节点之间连通，第二输出节点控制电路在第一输出节点的电位的控制下，将第四时钟信号写入第二输出节点，并根据第四时钟信号控制调节第二输出节点的电位；
输出电路在所述第一输出节点的电位的控制下，控制将第一电压信号写 入栅极驱动信号输出端，输出电路在所述第二输出节点的电位的控制下，控制将第四时钟信号写入所述栅极驱动信号输出端。
在第三个方面中，本公开实施例还提供了一种栅极驱动电路，包括多级上述的栅极驱动单元。
在第四个方面中，本公开实施例还提供了一种显示装置，包括上述的栅极驱动电路。
附图说明
图1是本公开至少一实施例所述的栅极驱动单元的结构图；
图2是本公开至少一实施例所述的栅极驱动单元的结构图；
图3是本公开至少一实施例所述的栅极驱动单元的结构图；
图4是本公开至少一实施例所述的栅极驱动单元的结构图；
图5是本公开至少一实施例所述的栅极驱动单元的结构图；
图6A和图6B为本公开至少一实施例所述的栅极驱动单元的电路图；
图7是本公开如图6A所示的栅极驱动单元的至少一实施例的工作时序图
图8是本公开如图6A所示的栅极驱动单元的至少一实施例的与图7对应的仿真工作时序图；
图9是本公开如图6A所示的栅极驱动单元的至少一实施例在工作时，各节点的波形图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
如图1所示，本公开至少一实施例所述的栅极驱动单元包括第一时钟信号端、第二时钟信号端、第三时钟信号端、第四时钟信号端、第一输出节点控制电路11、第二输出节点控制电路12、第一控制节点控制电路13和输出 电路14，其中，
所述第一输出节点控制电路11分别与第一输出节点N9、输入端I1、第一时钟信号端、第四时钟信号端、第一控制节点N4、第三时钟信号端、第一电压端V1和第二电压端V2电连接，用于在所述输入端I1提供的输入信号、所述第一时钟信号端提供的第一时钟信号CK1和所述第四时钟信号端提供的第四时钟信号CK4的控制下，根据所述输入信号和所述第一电压端V1提供的第一电压信号控制所述第一输出节点N9的电位，并在所述第一控制节点N4的电位和所述第三时钟信号端提供的第三时钟信号CK3的控制下，将第二电压端V2提供的第二电压信号写入所述第一输出节点N9，并根据第三时钟信号CK3控制调节第一输出节点N9的电位；
所述第一控制节点控制电路13分别与第一时钟信号端、第一电压端V1、第一控制节点N4和第一控制端N3电连接，用于在所述第一时钟信号CK1的控制下，将第一电压信号写入第一控制节点N4，并在所述第一控制端N3的电位的控制下，将第一时钟信号CK1写入第一控制节点N4；
所述第二输出节点控制电路12分别与第二控制端N6、第二时钟信号端、第二输出节点N8、第一输出节点N9和第四时钟信号端电连接，用于在所述第二控制端N6的电位下，将所述第二时钟信号端提供的第二时钟信号CK2写入第二控制节点N7，在所述第二时钟信号CK2的控制下，控制所述第二控制节点N7与所述第二输出节点N8之间连通，并在第一输出节点N9的电位的控制下，将第四时钟信号CK4写入所述第二输出节点N8，并根据所述第四时钟信号CK4控制调节第二输出节点N8的电位；
所述输出电路14分别与第一输出节点N9、第二输出节点N8、第四时钟信号端、第一电压端V1和栅极驱动信号输出端O1电连接，用于在所述第一输出节点N9的电位的控制下，控制将第一电压信号写入所述栅极驱动信号输出端O1，在所述第二输出节点N8的电位的控制下，控制将第四时钟信号CK4写入所述栅极驱动信号输出端O1。
本公开至少一实施例所述的栅极驱动单元能够为LTPO(低温多晶氧化物)像素电路提供N型晶体管需要的栅极驱动信号，并能够减少采用的晶体管的数目，利于实现窄边框。
在本公开至少一实施例中，所述第一电压端可以为低电压端，所述第二电压端可以为高电压端，但不以此为限。
本公开至少一实施例所述的栅极驱动单元在工作时，所述第一输出节点控制电路11在输入信号、第一时钟信号CK1和第四时钟信号CK4的控制下，根据所述输入信号和第一电压信号控制所述第一输出节点N9的电位，并在所述第一控制节点N4的电位和第三时钟信号CK3的控制下，将第二电压信号写入所述第一输出节点N9，并根据第三时钟信号CK3控制调节第一输出节点N9的电位；
所述第一控制节点控制电路13在所述第一时钟信号CK1的控制下，将第一电压信号写入第一控制节点N4，并在所述第一控制端N3的电位的控制下，将第一时钟信号CK1写入第一控制节点N4；
所述第二输出节点控制电路12在所述第二控制端N6的电位下，将第二时钟信号CK2写入第二控制节点N7，在所述第二时钟信号CK2的控制下，控制所述第二控制节点N7与所述第二输出节点N8之间连通，并在第一输出节点N9的电位的控制下，将第四时钟信号CK4写入所述第二输出节点N8，并根据所述第四时钟信号CK4控制调节第二输出节点N8的电位；
所述输出电路14分在所述第一输出节点N9的电位的控制下，控制将第一电压信号写入所述栅极驱动信号输出端O1，在所述第二输出节点N8的电位的控制下，控制将第四时钟信号CK4写入所述栅极驱动信号输出端O1。
可选的，第一控制端为所述第一输出节点；或者，
所述第一控制端为第一隔离节点，所述栅极驱动单元还包括第一隔离电路；所述第一隔离节点通过所述第一隔离电路与所述第一输出节点电连接；
所述第一隔离电路的控制端与第一控制电压端电连接，所述第一隔离电路用于在所述第一控制电压端提供的第一控制电压的控制下，控制所述第一控制端与所述第一输出节点之间连通。
可选的，所述第二控制端为所述第一控制节点；或者，
所述第二控制端为第二隔离节点，所述栅极驱动单元还包括第二隔离电路；
所述第二隔离电路的控制端与第二控制电压端电连接，所述第二隔离电 路用于在所述第二控制电压端提供的第二控制电压的控制下，控制所述第二控制端与所述第一控制节点之间连通。
如图2所示，在图1所示的栅极驱动单元的至少一实施例的基础上，所述第一控制端与为所述第一输出节点N9，所述第二控制端为所述第一控制节点N4。
如图3所示，在图1所示的栅极驱动单元的至少一实施例的基础上，本公开至少一实施例所述的栅极驱动单元还包括第一隔离电路31和第二隔离电路32；
所述第一隔离电路31的控制端与第一控制电压端Vc1电连接，所述第一隔离电路31的第一端与所述第一控制端N3电连接，所述第一隔离电路31的第二端与所述第一输出节点N9电连接，所述第一隔离电路31用于在所述第一控制电压端Vc1提供的第一控制电压的控制下，控制所述第一控制端N3与所述第一输出节点N9之间连通；
所述第二隔离电路32的控制端与第二控制电压端Vc2电连接，所述第二隔离电路32的第一端与所述第二控制端N6电连接，所述第二隔离电路32的第二端与所述第一控制节点N4电连接，所述第二隔离电路32用于在所述第二控制电压端Vc2提供的第二控制电压的控制下，控制所述第二控制端N6与所述第一控制节点N4之间连通。
并且，如图3所示，当本公开至少一实施例所述的栅极驱动单元还包括第一隔离电路31和第二隔离电路32时，所述第一控制端N3还与所述第一输出节点控制电路11电连接。
在具体实施时，所述第一隔离电路31可以包括第一隔离晶体管，所述第二隔离电路32可以包括第二隔离晶体管，当所述第一隔离晶体管和所述第二隔离晶体管为P型晶体管时，所述第一控制电压端和所述第二控制电压端可以为低电压，所述第一隔离晶体管和所述第二隔离晶体管可以为常开晶体管，所述第一隔离晶体管用于稳定第一输出节点的电位，所述第二隔离晶体管用于稳定第二控制端N6的电位。
在本公开至少一实施例中，如图4所示，在图1所示的栅极驱动单元的至少一实施例的基础上，所述第一输出节点控制电路可以包括第一控制端控 制子电路111和第一输出节点控制子电路112；
所述第一控制端控制子电路111分别与第一节点N1、第二节点N2、输入端I1、第一时钟信号端、第四时钟信号端、第一电压端V1和第一控制端N3电连接，用于在所述输入信号的控制下，控制所述第一电压端V1与第一节点N1之间连通，并用于根据所述输入信号控制所述第一节点N1的电位，在所述第四时钟信号CK4的控制下，控制所述第一节点N1与所述第二节点N2之间连通，并用于在所述第一时钟信号CK1的控制下，控制所述第二节点N2与所述第一控制端N3之间连通；
所述第一输出节点控制子电路112分别与第二电压端V2、所述第一控制节点N4、所述第三时钟信号端和所述第一输出节点N9电连接，用于在所述第一控制节点N4的电位和第三时钟信号CK3的控制下，将第二电压端V2提供的第二电压信号写入所述第一输出节点N9，并根据第三时钟信号CK3控制调节第一输出节点N9的电位；
在具体实施时，所述第一输出节点控制电路11包括第一控制端控制子电路111和第一输出节点控制子电路112，第一控制端控制子电路111控制第一控制端N3的电位，所述第一输出节点控制子电路112控制第一输出节点N9的电位。
可选的，所述第一控制端控制子电路包括第一节点控制晶体管、第二节点控制晶体管、第三节点控制晶体管和第一电容，其中，
所述第一节点控制晶体管的控制极与所述输入端电连接，所述第一节点控制晶体管的第一极与所述第一电压端电连接，所述第一节点控制晶体管的第二极与所述第一节点电连接；
所述第二节点控制晶体管的控制极与所述第四时钟信号端电连接，所述第二节点控制晶体管的第一极与所述第一节点电连接，所述第二节点控制晶体管的第二极与所述第二节点电连接；
所述第一电容的第一端与所述输入端电连接，所述第一电容的第二端与所述第一节点电连接；
所述第三节点控制晶体管的控制极与所述第一时钟信号端电连接，所述第三节点控制晶体管的第一极与所述第二节点电连接，所述第三节点控制晶 体管的第二极与所述第一控制端电连接。
可选的，所述第一输出节点控制子电路包括第四节点控制晶体管、第五节点控制晶体管和第二电容，其中，
所述第四节点控制晶体管的控制极与所述第一控制节点电连接，所述第四节点控制晶体管的第一极与所述第二电压端电连接；
所述第五节点控制晶体管的控制极与所述第三时钟信号端电连接，所述第五节点控制晶体管的第一极与所述第四节点控制晶体管的第二极电连接，所述第五节点控制晶体管的第二极与所述第一输出节点电连接；
所述第二电容的第一端与所述第一输出节点电连接，所述第二电容的第二端与所述第三时钟信号端电连接。
在本公开至少一实施例中，当所述栅极驱动单元还包括第一隔离电路时，所述第一隔离电路包括第一隔离晶体管；
所述第一隔离晶体管的控制极与所述第一控制电压端电连接，所述第一隔离晶体管的第一极与所述第一控制端电连接，所述第一隔离晶体管的第二极与所述第一输出节点电连接。
可选的，所述第一控制节点控制电路包括第六节点控制晶体管和第七节点控制晶体管，其中，
所述第六节点控制晶体管的控制极与所述第一时钟信号端电连接，所述第六节点控制晶体管的第一极与所述第一电压端电连接，所述第六节点控制晶体管的第二极与所述第一控制节点电连接；
所述第七节点控制晶体管的控制极与所述第一控制端电连接，所述第七节点控制晶体管的第一极与所述第一控制节点电连接，所述第七节点控制晶体管的第二极与所述第一时钟信号端电连接。
可选的，所述第二输出节点控制电路包括第八节点控制晶体管、第九节点控制晶体管、第十节点控制晶体管、第三电容和第四电容，其中，
所述第八节点控制晶体管的控制极与所述第二控制端电连接，所述第八节点控制晶体管的第一极与所述第二时钟信号端电连接；
所述第四电容的第一端与所述第二控制端电连接，所述第四电容的第二端与所述第八节点控制晶体管的第二极电连接；
所述第九节点控制晶体管的控制极与所述第二时钟信号端电连接，所述第九节点控制晶体管的第一极与所述第八节点控制晶体管的第二极电连接，所述第九节点控制晶体管的第二极与所述第二输出节点电连接；
所述第十节点控制晶体管的控制极与所述第一输出节点电连接，所述第十节点控制晶体管的第一极与所述第二输出节点电连接，所述第十节点控制晶体管的第二极与所述第四时钟信号端电连接；
所述第三电容的第一端与所述第二输出节点电连接，所述第三电容的第二端与所述第四时钟信号端电连接。
在具体实施时，当所述栅极驱动单元还包括第二隔离电路时，所述第二隔离电路包括第二隔离晶体管；
所述第二隔离晶体管的控制极与所述第二控制电压端电连接，所述第二隔离晶体管的第一极与所述第一控制节点电连接，所述第二隔离晶体管的第二极与所述第二控制端电连接。
如图5所示，在图3所示的栅极驱动单元的至少一实施例的基础上，所述第一隔离电路31包括第一隔离晶体管T13，所述第二隔离电路32包括第二隔离晶体管T14；
所述第一隔离晶体管T13的栅极与所述第一控制电压端Vc1电连接，所述第一隔离晶体管T13的漏极与所述第一控制端N3电连接，所述第一隔离晶体管T13的源极与所述第一输出节点N9电连接；
所述第二隔离晶体管T14的栅极与所述第二控制电压端Vc2电连接，所述第二隔离晶体管T14的漏极与所述第一控制节点N4电连接，所述第二隔离晶体管T14的源极与所述第二控制端N6电连接。
在图5所示的至少一实施例中，T13和T14可以为P型薄膜晶体管，Vc1和Vc2可以为低电压端，T13和T14可以为常开晶体管，但不以此为限。
可选的，所述输出电路包括第一输出晶体管和第二输出晶体管；
所述第一输出晶体管的控制极与所述第一输出节点电连接，所述第一输出晶体管的第一极与栅极驱动信号输出端电连接，所述第一输出晶体管的第二极与所述第一电压端电连接；
所述第二输出晶体管的控制极与所述第二输出节点电连接，所述第二输 出晶体管的第一极与所述第四时钟信号端电连接，所述第二输出晶体管的第二极与所述栅极驱动信号输出端电连接。
如图6A所示，在图5所示的栅极驱动单元的至少一实施例的基础上，所述第一输出节点控制电路包括第一控制端控制子电路和第一输出节点控制子电路；
所述第一控制端控制子电路包括第一节点控制晶体管T1、第二节点控制晶体管T2、第三节点控制晶体管T3和第一电容C1，其中，
所述第一节点控制晶体管T1的栅极与所述输入端I1电连接，所述第一节点控制晶体管T1的漏极与低电压端电连接，所述第一节点控制晶体管T1的源极与第一节点N1电连接；所述低电压端用于提供低电压VGL；
所述第二节点控制晶体管T3的栅极与所述第四时钟信号端电连接，所述第二节点控制晶体管T3的漏极与所述第一节点N1电连接，所述第二节点控制晶体管T3的源极与所述第二节点N2电连接；所述第四时钟信号端用于提供第四时钟信号CK4；
所述第一电容C1的第一端与所述输入端I1电连接，所述第一电容C1的第二端与所述第一节点N1电连接；
所述第三节点控制晶体管T3的栅极与所述第一时钟信号端电连接，所述第三节点控制晶体管T3的漏极与所述第二节点N2电连接，所述第三节点控制晶体管T3的源极与所述第一控制端N3电连接；
所述第一输出节点控制子电路包括第四节点控制晶体管T7、第五节点控制晶体管T6和第二电容C4，其中，
所述第四节点控制晶体管T7的栅极与所述第一控制节点N4电连接，所述第四节点控制晶体管T7的漏极与高电压端电连接；所述高电压端用于提供高电压VGH；
所述第五节点控制晶体管T6的栅极与所述第三时钟信号端电连接，所述第五节点控制晶体管T6的漏极与所述第四节点控制晶体管T7的源极电连接，所述第五节点控制晶体管T6的源极与所述第一输出节点N9电连接；所述第三时钟信号端用于提供第三时钟信号CK3；
所述第二电容C4的第一端与所述第一输出节点N9电连接，所述第二电 容C4的第二端与所述第三时钟信号端电连接；
所述第一控制节点控制电路包括第六节点控制晶体管T5和第七节点控制晶体管T4，其中，
所述第六节点控制晶体管T5的栅极与所述第一时钟信号端电连接，所述第六节点控制晶体管T5的漏极与所述低电压端电连接，所述第六节点控制晶体管T5的源极与所述第一控制节点N4电连接；所述第一时钟信号端用于提供第一时钟信号CK1；
所述第七节点控制晶体管T4的栅极与所述第一控制端N3电连接，所述第七节点控制晶体管T4的漏极与所述第一控制节点N4电连接，所述第七节点控制晶体管T4的源极与所述第一时钟信号端电连接；
所述第二输出节点控制电路包括第八节点控制晶体管T8、第九节点控制晶体管T9、第十节点控制晶体管T10、第三电容C3和第四电容C2，其中，
所述第八节点控制晶体管T8的栅极与所述第二控制端N6电连接，所述第八节点控制晶体管T8的漏极与所述第二时钟信号端电连接；所述第二时钟信号端用于提供第二时钟信号CK2；
所述第四电容C2的第一端与所述第二控制端N6电连接，所述第四电容C2的第二端与所述第八节点控制晶体管T8的源极电连接；
所述第九节点控制晶体管T9的栅极与所述第二时钟信号端电连接，所述第九节点控制晶体管T9的漏极与所述第八节点控制晶体管T8的源极电连接，所述第九节点控制晶体管T9的源极与所述第二输出节点N8电连接；
所述第十节点控制晶体管T10的栅极与所述第一输出节点N9电连接，所述第十节点控制晶体管T10的漏极与所述第二输出节点N8电连接，所述第十节点控制晶体管T10的源极与所述第四时钟信号端电连接；所述第四时钟信号端用于提供第四时钟信号CK4；
所述第三电容C3的第一端与所述第二输出节点N8电连接，所述第三电容C3的第二端与所述第四时钟信号端电连接；
所述输出电路包括第一输出晶体管T12和第二输出晶体管T11；
所述第一输出晶体管T12的栅极与所述第一输出节点N9电连接，所述第一输出晶体管T12的漏极与栅极驱动信号输出端O1电连接，所述第一输 出晶体管T12的源极与所述低电压端电连接；
所述第二输出晶体管T11的栅极与所述第二输出节点N8电连接，所述第二输出晶体管T11的漏极与所述第四时钟信号端电连接，所述第二输出晶体管T11的源极与所述栅极驱动信号输出端O1电连接。
在图6A所示的栅极驱动单元的至少一实施例中，所有的晶体管都为P型薄膜晶体管，但不以此为限。
图6B是在图6A的基础上，添加标号31、32、111、112、12、13和14的附图。
在图6A所示的栅极驱动单元的至少一实施例中，N7为与T8的源极电连接的节点，N5为与T6的漏极电连接的节点。
如图7所示，本公开图6A所示的栅极驱动单元的至少一实施例在工作时，
在第一阶段S1，I1提供低电压，CK2为高电压，CK4为低电压，CK1的下降沿先于CK3的上升沿；T1和T2持续打开，T5在CK1为低电压时打开，以使得N4的电位为VGL-Vth(5)，其中，Vth(5)为T5的阈值电压；当CK3变为高电压，T6关闭，此时CK1为低电压，N3的电位下降，以打开T4，N4的电位为低电压，T14打开，N6的电位为低电压，直到CK1变为高电压，N4的电位和N6的电位被拉高；当CK1为低电压，CK3为高电压时，N3的电位和N9的电位才能被写至低电位，以打开T4；T9持续关闭，CK3的下降沿会由于电容自举将N9的电位拉低，T10打开，N8的电位为低电压，T11和T12打开，O1输出低电压；
在第二阶段S2，I1提供低电压，CK1为高电压，CK3为低电压，N1的电位、N2的电位和N3的电位保持为低电压，CK1为高电压，N4的电位和N6的电位为高电压，N9的电位保持为低电压，T12打开，CK4的电位由低电压提升为高电压时，由于C3的自举作用，N8的电位被拉高，T11关闭，O1输出低电压；
在第三阶段S3，I1提供高电压，CK2为高电压，CK4为低电压，N1的电位由于C1的自举作用被拉高，T1关断，T2打开，在CK1为低电压时T3打开，T13打开，N1的电位、N2的电位、N3的电位和N9的电位在CK1的 电位被置低时会被不同程度的拉高；T10和T12关断，T9持续关断，N8的电位保持为低电压，T11打开，O1输出低电压；
在第三阶段S3，当CK1为低电压时，T5打开，N4的电位为低电压；
在第四阶段S4，I1提供低电压，CK1为高电压，CK3为低电压，T3关断，T6关断，N9的电位维持为高电压，T10和T12关断，T5关断，T4关断，T1关断，N4的电位维持为低电压，N6的电位为低电压，在CK2的电位变为低电压时，T8和T8打开，N7的电位和N8的电位为低电压，T11打开，O1输出CK4；在CK2的电位由高电压跳变为低电压时，由于C2的自举作用会将N6的电位拉至更低，使得T8打开更彻底；
在第五阶段S5，I1提供低电压，CK2为高电压，CK4为低电压，T1和T2打开，N1和N2的电位为低电压，当CK1的电位为低电压时，T3打开，N1的电位、N2的电位和N3的电位被拉低，T4打开，当CK1为低电压时，T5打开，N4的电位为低电压，T14打开(T14常开)，N6的电位为低电压，T8打开，N7的电位为高电压(CK2的高电位将N7的电位写为高电压)；当CK1的电位由低电压变为高电压时，T5关断，N4的电位变为高电压(此时，T4打开，CK1的高电位将N4的电位写为高电压)，T14打开(T14常开)，N6的电位为高电压，T8关断，N7的电位维持为高电压；T9关断，N8的电位在第四阶段S4为低，并N8的电位在第五阶段S5被C3自举拉至更低电压，T11彻底打开，N9的电位在T7关断后持续下降，N9的电位在CK3的电位跳变为低电压时被C4进一步拉低，T12彻底打开，O1输出低电压。
在图6A、图6B所示的栅极驱动单元的至少一实施例中，利用C3，可以周期性的在第三时钟信号CK3的控制下，降低N9的电位，以使得T12能够彻底打开，降低输出波形受到T12的阈值电压的损耗的问题。
在图6A、图6B所示的栅极驱动单元的至少一实施例中，所述第一隔离晶体管T13用于稳定第一输出节点N9的电位，所述第二隔离晶体管T14用于稳定第二控制端N6的电位；由于N9和N6都与电容电连接，因此N9的电位的稳定性和N6的电位的稳定性对电路稳定工作非常有益。
如图7所示，CK1的下降沿先于CK3的上升沿，CK1的上升沿先于CK3的下降沿，CK2的下降沿先于CK4的上升沿，CK2的上升沿先于CK4的下 降沿，但不以此为限。
本公开图6A所示的栅极驱动单元的至少一实施例能够通过O1提供N型晶体管工作所需的栅极驱动信号，并采用的晶体管的数目少，利于实现窄边框。
图8是本公开如图6A所示的栅极驱动单元的至少一实施例的与图7对应的仿真工作时序图；
图9是本公开如图6A所示的栅极驱动单元的至少一实施例在工作时，各节点的波形图。
本公开至少一实施例所述的栅极驱动方法，应用于上述的栅极驱动单元，所述栅极驱动方法包括：
第一输出节点控制电路在输入信号、第一时钟信号和第四时钟信号的控制下，根据所述输入信号和第一电压信号控制第一输出节点的电位，第一输出节点控制电路在第一控制节点的电位和第三时钟信号的控制下，将第二电压信号写入第一输出节点，并根据第三时钟信号控制调节第一输出节点的电位；
第一控制节点控制电路在第一时钟信号的控制下，将第一电压信号写入第一控制节点，并在第一控制端的电位的控制下，将第一时钟信号写入第一控制节点；
第二输出节点控制电路在第二控制端的电位下，将第二时钟信号写入第二控制节点，在第二时钟信号的控制下，控制第二控制节点与第二输出节点之间连通，第二输出节点控制电路在第一输出节点的电位的控制下，将第四时钟信号写入第二输出节点，并根据第四时钟信号控制调节第二输出节点的电位；
输出电路在所述第一输出节点的电位的控制下，控制将第一电压信号写入栅极驱动信号输出端，输出电路在所述第二输出节点的电位的控制下，控制将第四时钟信号写入所述栅极驱动信号输出端。
本公开实施例所述的栅极驱动电路包括多级上述的栅极驱动单元。
在具体实施时，所述栅极驱动电路中的栅极驱动单元的输入端与相邻上一级栅极驱动单元的栅极驱动信号输出端电连接。
本公开实施例所述的一种显示装置包括上述的栅极驱动电路。
本公开实施例所提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (14)

  1. 一种栅极驱动单元，包括第一时钟信号端、第二时钟信号端、第三时钟信号端、第四时钟信号端、第一输出节点控制电路、第二输出节点控制电路、第一控制节点控制电路和输出电路，其中，
    所述第一输出节点控制电路分别与第一输出节点、输入端、第一时钟信号端、第四时钟信号端、第一控制节点、第三时钟信号端、第一电压端和第二电压端电连接，用于在所述输入端提供的输入信号、所述第一时钟信号端提供的第一时钟信号和所述第四时钟信号端提供的第四时钟信号的控制下，根据所述输入信号和所述第一电压端提供的第一电压信号控制所述第一输出节点的电位，并在所述第一控制节点的电位和所述第三时钟信号端提供的第三时钟信号的控制下，将第二电压端提供的第二电压信号写入所述第一输出节点，并根据第三时钟信号控制调节第一输出节点的电位；
    所述第一控制节点控制电路分别与第一时钟信号端、第一电压端、第一控制节点和第一控制端电连接，用于在所述第一时钟信号的控制下，将第一电压信号写入第一控制节点，并在所述第一控制端的电位的控制下，将第一时钟信号写入第一控制节点；
    所述第二输出节点控制电路分别与第二控制端、第二时钟信号端、第二输出节点、第一输出节点和第四时钟信号端电连接，用于在所述第二控制端的电位下，将所述第二时钟信号端提供的第二时钟信号写入第二控制节点，在所述第二时钟信号的控制下，控制所述第二控制节点与所述第二输出节点之间连通，并在第一输出节点的电位的控制下，将第四时钟信号写入所述第二输出节点，并根据所述第四时钟信号控制调节第二输出节点的电位；
    所述输出电路分别与第一输出节点、第二输出节点、第四时钟信号端、第一电压端和栅极驱动信号输出端电连接，用于在所述第一输出节点的电位的控制下，控制将第一电压信号写入所述栅极驱动信号输出端，在所述第二输出节点的电位的控制下，控制将第四时钟信号写入所述栅极驱动信号输出端。
  2. 如权利要求1所述的栅极驱动单元，其中，第一控制端为所述第一输 出节点；或者，
    所述第一控制端为第一隔离节点，所述栅极驱动单元还包括第一隔离电路；所述第一隔离节点通过所述第一隔离电路与所述第一输出节点电连接；
    所述第一隔离电路的控制端与第一控制电压端电连接，所述第一隔离电路用于在所述第一控制电压端提供的第一控制电压的控制下，控制所述第一控制端与所述第一输出节点之间连通。
  3. 如权利要求1所述的栅极驱动单元，其中，所述第二控制端为所述第一控制节点；或者，
    所述第二控制端为第二隔离节点，所述栅极驱动单元还包括第二隔离电路；
    所述第二隔离电路的控制端与第二控制电压端电连接，所述第二隔离电路用于在所述第二控制电压端提供的第二控制电压的控制下，控制所述第二控制端与所述第一控制节点之间连通。
  4. 如权利要求2所述的栅极驱动单元，其中，所述第一输出节点控制电路包括第一控制端控制子电路和第一输出节点控制子电路；
    所述第一控制端控制子电路分别与第一节点、第二节点、输入端、第一时钟信号端、第四时钟信号端、第一电压端和第一控制端电连接，用于在所述输入信号的控制下，控制所述第一电压端与第一节点之间连通，并用于根据所述输入信号控制所述第一节点的电位，在所述第四时钟信号的控制下，控制所述第一节点与所述第二节点之间连通，并用于在所述第一时钟信号的控制下，控制所述第二节点与所述第一控制端之间连通；
    所述第一输出节点控制子电路分别与第二电压端、所述第一控制节点、所述第三时钟信号端和所述第一输出节点电连接，用于在所述第一控制节点的电位和第三时钟信号的控制下，将第二电压端提供的第二电压信号写入所述第一输出节点，并根据第三时钟信号控制调节第一输出节点的电位。
  5. 如权利要求4所述的栅极驱动单元，其中，所述第一控制端控制子电路包括第一节点控制晶体管、第二节点控制晶体管、第三节点控制晶体管和第一电容，其中，
    所述第一节点控制晶体管的控制极与所述输入端电连接，所述第一节点 控制晶体管的第一极与所述第一电压端电连接，所述第一节点控制晶体管的第二极与所述第一节点电连接；
    所述第二节点控制晶体管的控制极与所述第四时钟信号端电连接，所述第二节点控制晶体管的第一极与所述第一节点电连接，所述第二节点控制晶体管的第二极与所述第二节点电连接；
    所述第一电容的第一端与所述输入端电连接，所述第一电容的第二端与所述第一节点电连接；
    所述第三节点控制晶体管的控制极与所述第一时钟信号端电连接，所述第三节点控制晶体管的第一极与所述第二节点电连接，所述第三节点控制晶体管的第二极与所述第一控制端电连接。
  6. 如权利要求4所述的栅极驱动单元，其中，所述第一输出节点控制子电路包括第四节点控制晶体管、第五节点控制晶体管和第二电容，其中，
    所述第四节点控制晶体管的控制极与所述第一控制节点电连接，所述第四节点控制晶体管的第一极与所述第二电压端电连接；
    所述第五节点控制晶体管的控制极与所述第三时钟信号端电连接，所述第五节点控制晶体管的第一极与所述第四节点控制晶体管的第二极电连接，所述第五节点控制晶体管的第二极与所述第一输出节点电连接；
    所述第二电容的第一端与所述第一输出节点电连接，所述第二电容的第二端与所述第三时钟信号端电连接。
  7. 如权利要求2所述的栅极驱动单元，其中，当所述栅极驱动单元还包括第一隔离电路时，所述第一隔离电路包括第一隔离晶体管；
    所述第一隔离晶体管的控制极与所述第一控制电压端电连接，所述第一隔离晶体管的第一极与所述第一控制端电连接，所述第一隔离晶体管的第二极与所述第一输出节点电连接。
  8. 如权利要求1至7中任一权利要求所述的栅极驱动单元，其中，所述第一控制节点控制电路包括第六节点控制晶体管和第七节点控制晶体管，其中，
    所述第六节点控制晶体管的控制极与所述第一时钟信号端电连接，所述第六节点控制晶体管的第一极与所述第一电压端电连接，所述第六节点控制 晶体管的第二极与所述第一控制节点电连接；
    所述第七节点控制晶体管的控制极与所述第一控制端电连接，所述第七节点控制晶体管的第一极与所述第一控制节点电连接，所述第七节点控制晶体管的第二极与所述第一时钟信号端电连接。
  9. 如权利要求3所述的栅极驱动单元，其中，所述第二输出节点控制电路包括第八节点控制晶体管、第九节点控制晶体管、第十节点控制晶体管、第三电容和第四电容，其中，
    所述第八节点控制晶体管的控制极与所述第二控制端电连接，所述第八节点控制晶体管的第一极与所述第二时钟信号端电连接；
    所述第四电容的第一端与所述第二控制端电连接，所述第四电容的第二端与所述第八节点控制晶体管的第二极电连接；
    所述第九节点控制晶体管的控制极与所述第二时钟信号端电连接，所述第九节点控制晶体管的第一极与所述第八节点控制晶体管的第二极电连接，所述第九节点控制晶体管的第二极与所述第二输出节点电连接；
    所述第十节点控制晶体管的控制极与所述第一输出节点电连接，所述第十节点控制晶体管的第一极与所述第二输出节点电连接，所述第十节点控制晶体管的第二极与所述第四时钟信号端电连接；
    所述第三电容的第一端与所述第二输出节点电连接，所述第三电容的第二端与所述第四时钟信号端电连接。
  10. 如权利要求3所述的栅极驱动单元，其中，当所述栅极驱动单元还包括第二隔离电路时，所述第二隔离电路包括第二隔离晶体管；
    所述第二隔离晶体管的控制极与所述第二控制电压端电连接，所述第二隔离晶体管的第一极与所述第一控制节点电连接，所述第二隔离晶体管的第二极与所述第二控制端电连接。
  11. 如权利要求1、2、3、4、5、6、7、9或10所述的栅极驱动单元，其中，所述输出电路包括第一输出晶体管和第二输出晶体管；
    所述第一输出晶体管的控制极与所述第一输出节点电连接，所述第一输出晶体管的第一极与栅极驱动信号输出端电连接，所述第一输出晶体管的第二极与所述第一电压端电连接；
    所述第二输出晶体管的控制极与所述第二输出节点电连接，所述第二输出晶体管的第一极与所述第四时钟信号端电连接，所述第二输出晶体管的第二极与所述栅极驱动信号输出端电连接。
  12. 一种栅极驱动方法，应用于如权利要求1至11中任一权利要求所述的栅极驱动单元，所述栅极驱动方法包括：
    第一输出节点控制电路在输入信号、第一时钟信号和第四时钟信号的控制下，根据所述输入信号和第一电压信号控制第一输出节点的电位，第一输出节点控制电路在第一控制节点的电位和第三时钟信号的控制下，将第二电压信号写入第一输出节点，并根据第三时钟信号控制调节第一输出节点的电位；
    第一控制节点控制电路在第一时钟信号的控制下，将第一电压信号写入第一控制节点，并在第一控制端的电位的控制下，将第一时钟信号写入第一控制节点；
    第二输出节点控制电路在第二控制端的电位下，将第二时钟信号写入第二控制节点，在第二时钟信号的控制下，控制第二控制节点与第二输出节点之间连通，第二输出节点控制电路在第一输出节点的电位的控制下，将第四时钟信号写入第二输出节点，并根据第四时钟信号控制调节第二输出节点的电位；
    输出电路在所述第一输出节点的电位的控制下，控制将第一电压信号写入栅极驱动信号输出端，输出电路在所述第二输出节点的电位的控制下，控制将第四时钟信号写入所述栅极驱动信号输出端。
  13. 一种栅极驱动电路，包括多级如权利要求1至11中任一权利要求所述的栅极驱动单元。
  14. 一种显示装置，包括如权利要求13所述的栅极驱动电路。
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WO2019218625A1 (zh) * 2018-05-16 2019-11-21 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
CN108877682A (zh) * 2018-07-18 2018-11-23 京东方科技集团股份有限公司 一种移位寄存器及其驱动方法、栅极驱动电路
CN109872673A (zh) * 2019-04-09 2019-06-11 京东方科技集团股份有限公司 栅极驱动单元、栅极驱动方法、栅极驱动电路和显示装置
CN111508433A (zh) * 2020-05-28 2020-08-07 京东方科技集团股份有限公司 信号生成电路、信号生成方法、信号生成模组和显示装置
CN111768733A (zh) * 2020-06-10 2020-10-13 京东方科技集团股份有限公司 发光控制信号生成电路、方法和显示装置
CN112185297A (zh) * 2020-10-26 2021-01-05 京东方科技集团股份有限公司 栅极驱动单元、栅极驱动方法，栅极驱动电路和显示装置

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