WO2021227766A1 - 移位寄存器单元及其控制方法、栅极驱动电路和显示装置 - Google Patents

移位寄存器单元及其控制方法、栅极驱动电路和显示装置 Download PDF

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Publication number
WO2021227766A1
WO2021227766A1 PCT/CN2021/087472 CN2021087472W WO2021227766A1 WO 2021227766 A1 WO2021227766 A1 WO 2021227766A1 CN 2021087472 W CN2021087472 W CN 2021087472W WO 2021227766 A1 WO2021227766 A1 WO 2021227766A1
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Prior art keywords
transistor
electrically connected
control
electrode
circuit
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PCT/CN2021/087472
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English (en)
French (fr)
Inventor
袁志东
李永谦
袁粲
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京东方科技集团股份有限公司
合肥京东方卓印科技有限公司
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Priority to US17/766,828 priority Critical patent/US11972821B2/en
Publication of WO2021227766A1 publication Critical patent/WO2021227766A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a shift register unit and a control method thereof, a gate driving circuit and a display device.
  • GOA Gate Driver on Array
  • the display device adopting the GOA technology has the problem that it is difficult to adjust the pulse width of the gate scan signal.
  • the embodiments of the present disclosure provide a shift register unit and a control method thereof, a gate drive circuit, and a display device, so as to solve the problem of difficulty in adjusting the pulse width of the gate scan signal in the display device adopting the GOA technology in the related art.
  • embodiments of the present disclosure provide a shift register unit, including a first control circuit, a pull-down control circuit, a second control circuit, a first pull-down circuit, a tank circuit, and an output circuit;
  • the first control circuit is configured to write the first clock signal provided by the first clock signal terminal into the first node under the control of the potential of the cascade output terminal;
  • the pull-down control circuit is configured to write the electrical signal of the second node into the control terminal of the first pull-down circuit under the control of the second clock signal provided by the second clock signal terminal;
  • the second control circuit is configured to write the third clock signal provided by the third clock signal terminal into the control terminal of the first pull-down circuit under the control of the input signal provided by the input signal terminal;
  • the first pull-down circuit is configured to pull down the potential of the first node under the control of the potential of the control terminal of the first pull-down circuit
  • the tank circuit is used to control the potential of the first node
  • the output circuit is used for outputting the first voltage signal provided by the first voltage terminal to the signal output terminal under the control of the potential of the first node.
  • the first control circuit includes a first transistor and a second transistor, the control electrode of the first transistor is electrically connected to the cascade output terminal, and the first electrode of the first transistor is electrically connected to the first transistor.
  • the clock signal terminal is electrically connected
  • the second electrode of the first transistor is electrically connected to the first electrode of the second transistor
  • the second electrode of the second transistor is electrically connected to the first node
  • the second electrode is electrically connected to the first node.
  • the control electrode of the transistor is electrically connected to the first clock signal terminal.
  • the first pull-down circuit includes a third transistor, the control electrode of the third transistor is electrically connected to the output terminal of the pull-down control circuit, and the first electrode of the third transistor is connected to the first node.
  • the second electrode of the third transistor is electrically connected to the second voltage terminal.
  • the pull-down control circuit includes a fourth transistor, a control electrode of the fourth transistor is electrically connected to the second clock signal terminal, and a first electrode of the fourth transistor is electrically connected to the second node, The second pole of the fourth transistor is electrically connected to the control terminal of the first pull-down circuit.
  • the output circuit includes a fifth transistor and a sixth transistor
  • the first electrode of the fifth transistor is electrically connected to the first voltage terminal
  • the second electrode of the fifth transistor is electrically connected to the first electrode of the sixth transistor
  • the control electrode of the fifth transistor is electrically connected to The first node is electrically connected
  • the control electrode of the sixth transistor is electrically connected to the output terminal of the pull-down control circuit, and the second electrode of the sixth transistor is electrically connected to the second voltage terminal.
  • the second control circuit includes a seventh transistor, a control electrode of the seventh transistor is electrically connected to the input signal terminal, and a first electrode of the seventh transistor is electrically connected to the third clock signal terminal , The second pole of the seventh transistor is electrically connected to the control terminal of the first pull-down circuit.
  • the energy storage circuit includes a capacitor, one end of the capacitor is electrically connected to the first voltage terminal, and the other end of the capacitor is electrically connected to the first node.
  • the shift register further includes an input circuit, a third control circuit, an inverter circuit and a cascade circuit;
  • the input circuit is used to write the input signal provided by the input signal terminal into the control terminal of the third control circuit under the control of the third clock signal;
  • the third control circuit is configured to write the second clock signal provided by the second clock signal terminal to the third node under the control of the input signal;
  • the inverter circuit is used to write an electrical signal with the opposite potential of the third node to the second node;
  • the cascade circuit is used to write the first voltage signal provided by the first voltage terminal into the cascade output terminal under the control of the potential of the third node.
  • the input circuit includes an eighth transistor, a control electrode of the eighth transistor is electrically connected to the third clock signal terminal, a first electrode of the eighth transistor is electrically connected to the input signal terminal, and The second electrode of the eighth transistor is electrically connected to the control electrode of the third control circuit.
  • the third control circuit includes a ninth transistor and a tenth transistor
  • the control electrode of the ninth transistor is electrically connected to the output terminal of the input circuit, the first electrode of the ninth transistor is electrically connected to the second timing signal terminal, and the second electrode of the ninth transistor is electrically connected to the output terminal of the input circuit.
  • the first electrode of the tenth transistor is electrically connected;
  • the control electrode of the tenth transistor is electrically connected to the second timing signal terminal, and the second electrode of the tenth transistor is electrically connected to the third node.
  • the inverter circuit includes an eleventh transistor, a twelfth transistor, a thirteenth transistor, and a fourteenth transistor;
  • the control electrode of the eleventh transistor is electrically connected to the first voltage terminal, the first electrode of the eleventh transistor is electrically connected to the third timing signal terminal, and the second electrode of the eleventh transistor is electrically connected to the The control electrode of the twelfth transistor is electrically connected;
  • the first electrode of the twelfth transistor is electrically connected to the first voltage terminal, and the second electrode of the twelfth transistor is electrically connected to the second node;
  • the control electrode of the thirteenth transistor is electrically connected to the input signal terminal, the first electrode of the thirteenth transistor is electrically connected to the second electrode of the eleventh transistor, and the second electrode of the thirteenth transistor is electrically connected. Electrically connected to the second voltage terminal;
  • the control electrode of the fourteenth transistor is electrically connected to the input signal terminal, the first electrode of the fourteenth transistor is electrically connected to the second node, and the second electrode of the fourteenth transistor is electrically connected to the The second voltage terminal is electrically connected.
  • the cascade circuit includes a fifteenth transistor and a sixteenth transistor
  • the control electrode of the fifteenth transistor is electrically connected to the third node, the first electrode of the fifteenth transistor is electrically connected to the first voltage terminal, and the second electrode of the fifteenth transistor is electrically connected to the cascade output Terminal electrical connection;
  • the control electrode of the sixteenth transistor is electrically connected to the second node, the first electrode of the sixteenth transistor is electrically connected to the second electrode of the fifteenth transistor, and the second electrode of the sixteenth transistor is electrically connected. It is electrically connected to the second voltage terminal.
  • the shift register further includes a reset circuit
  • the reset circuit is used to pull up the potential of the second node under the control of a reset signal provided by a reset signal line.
  • the reset circuit includes a seventeenth transistor, a control electrode of the seventeenth transistor is electrically connected to the reset signal line, and a first electrode of the seventeenth transistor is electrically connected to the first voltage terminal , The second electrode of the seventeenth transistor is electrically connected to the second node.
  • embodiments of the present disclosure also provide a driving method of a shift register unit, which is applied to the above-mentioned shift register unit, and the method includes:
  • the first stage includes alternate first and second sub-stages; in the first sub-stage, the first clock signal is written into the first node, so that the output circuit outputs a high-potential signal; in the second sub-stage, In the stage, the input signal controls the first pull-down circuit to pull down the potential of the first node, so that the output circuit outputs a low-level signal;
  • the second stage it includes a third sub-stage and a fourth sub-stage; in the third sub-stage, the first clock signal is written into the first node, so that the output circuit outputs a high-potential signal; in the fourth sub-stage Wherein the capacitor bootstrap maintains the potential of the first node, and the output circuit continuously outputs a high potential signal;
  • the second clock signal controls the pull-down circuit to pull down the potential of the first node, so that the output circuit outputs a low-level signal.
  • embodiments of the present disclosure also provide a gate driving circuit, including the shift register unit described above.
  • FIG. 1 is a schematic diagram of a part of the structure of a shift register unit provided by an embodiment of the present disclosure
  • Figure 2 is a circuit diagram corresponding to Figure 1;
  • FIG. 3 is a circuit diagram of a shift register unit provided by another embodiment of the present disclosure.
  • FIG. 4 is a timing diagram of each signal in FIG. 3;
  • FIG. 5 is a schematic diagram of the connection of the gate driving circuit provided by an embodiment of the present disclosure.
  • the transistor mentioned in the embodiment of this application can be a P-type transistor, in which case the first electrode has a drain electrode and the second electrode has a source electrode; it can also be an N-type transistor, in which case the first electrode has a source electrode.
  • the second pole is the drain.
  • the above-mentioned transistors may all be transistors of the same type, or may be different transistors respectively, which is not limited here.
  • the effective potential mentioned in the embodiments of the present application is a potential that enables the first pole and the second pole of the connected transistor to be turned on. For example, if the transistor is an N-type transistor, the effective potential is a high potential, and the ineffective potential is Low potential.
  • the embodiment of the present disclosure provides a shift register unit, as shown in FIG. 1, including a first control circuit 110, a pull-down control circuit 120, a second control circuit 130, a first pull-down circuit 140, a tank circuit 150, and an output circuit 160;
  • the first control circuit 110 is configured to write the first clock signal provided by the first clock signal terminal CLK1 to the first node Q1 under the control of the potential of the cascade output terminal CR;
  • the pull-down control circuit 120 is configured to write the electrical signal of the second node Q2 into the control terminal of the first pull-down circuit 140 under the control of the second clock signal provided by the second clock signal terminal CLK2;
  • the second control circuit 130 is configured to write the third clock signal provided by the third clock signal terminal CLK3 into the control terminal of the first pull-down circuit 140 under the control of the input signal provided by the input signal terminal STU;
  • the first pull-down circuit 140 is configured to pull down the potential of the first node Q1 under the control of the potential of the control terminal of the first pull-down circuit 140;
  • the tank circuit 150 is used to control the potential of the first node Q1;
  • the output circuit 160 is configured to output the first voltage signal provided by the first voltage terminal VDD to the signal output terminal under the control of the potential of the first node Q1.
  • the potential of the first node is directly controlled by the first control circuit and the tank circuit, and the potential of the first node is indirectly controlled by the pull-down control circuit and the second control circuit using the first pull-down circuit to control the potential of the first node.
  • the control terminal of the first control circuit 110 is electrically connected to the cascade output terminal CR, the input terminal of the first control circuit 110 is electrically connected to the first clock signal terminal CLK1, and the output terminal of the first control circuit 110 is electrically connected to the first clock signal terminal CLK1.
  • a node Q1 is electrically connected. Under the control of the cascade signal output by the cascade output terminal CR, the conduction between the first clock signal terminal CLK1 and the first node Q1 is controlled, so that the first clock signal provided by the first clock signal terminal CLK1 is written into the first Node Q1.
  • the control terminal of the pull-down control circuit 120 is electrically connected to the second clock signal terminal CLK2, the input terminal of the pull-down control circuit 120 is electrically connected to the second node Q2, and the output terminal of the pull-down control circuit 120 is electrically connected to the first pull-down control circuit 120.
  • the control terminal of the pull circuit 140 is electrically connected. Under the control of the second clock signal provided by the second clock signal terminal CLK2, the conduction between the second node Q2 and the control terminal of the first pull-down circuit 140 is controlled, so that the electrical signal of the second node Q2 is written into the first downstream Pull the control terminal of the circuit 140.
  • the control terminal of the second control circuit 130 is electrically connected to the input signal terminal STU, the input terminal of the second control circuit 130 is electrically connected to the third clock signal terminal, and the output terminal of the second control circuit 130 is respectively connected to the The control terminal of the first pull-down circuit 140 is electrically connected to the output circuit 160.
  • the conduction between the third clock signal terminal and the control terminal of the first pull-down circuit 140 is controlled, so that the third clock signal provided by the third clock signal terminal is written into the first The control terminal of the pull-down circuit 140.
  • the input terminal of the first pull-down circuit 140 is electrically connected to the first node Q1, and the output terminal of the first pull-down circuit 140 is electrically connected to the second voltage terminal VGL. Under the control of the potential of the control terminal of the first pull-down circuit 140, the first node Q1 and the second voltage terminal VGL are controlled to conduct, so as to pull down the potential of the first node Q1.
  • One end of the above-mentioned tank circuit 150 is electrically connected to the first voltage terminal VDD, and the other end of the tank circuit 150 is electrically connected to the first node Q1, so as to prevent a sudden change in the potential of the first node Q1.
  • the first control terminal of the output circuit 160 is electrically connected to the first node Q1
  • the second control terminal of the output circuit 160 is electrically connected to the output terminal of the second control circuit 130
  • the input terminal of the output circuit 160 is electrically connected to
  • the first voltage terminal VDD is electrically connected
  • the signal output terminal of the output circuit 160 may be electrically connected to the gate line in the pixel driving circuit.
  • the conduction between the first voltage terminal VDD and the signal output terminal of the output circuit 160 is controlled, so that the signal output terminal of the output circuit 160 outputs the first voltage signal provided by the first voltage terminal VDD
  • the conduction between the second voltage terminal VGL and the signal output terminal of the output circuit 160 is controlled, so that the signal output terminal of the output circuit 160 outputs the voltage provided by the second voltage terminal VGL The second voltage signal.
  • the first voltage terminal VDD continuously provides the first voltage signal whose potential is the effective potential.
  • the first control circuit 110 includes a first transistor T1 and a second transistor T2.
  • the control electrode of the first transistor T1 is electrically connected to the cascade output terminal CR.
  • the first electrode of a transistor T1 is electrically connected to the first clock signal terminal CLK1
  • the second electrode of the first transistor T1 is electrically connected to the first electrode of the second transistor T2
  • the second electrode of the second transistor T2 is electrically connected.
  • the second electrode is electrically connected to the first node Q1
  • the control electrode of the second transistor T2 is electrically connected to the first clock signal terminal CLK1.
  • the potential of the cascade signal provided by the cascade output terminal CR is an effective potential and the potential of the first clock signal is also an effective potential
  • the first pole of the first transistor T1 and the second pole of the second transistor T2 are turned on
  • the first pole of the second transistor T2 and the second pole of the second transistor T2 are turned on, and the first clock signal is directly written into the first node Q1.
  • the potential of the first node Q1 is the effective potential, so that the output circuit 160 outputs The first voltage signal provided by the first voltage terminal VDD.
  • the first pull-down circuit 140 includes a third transistor T3, the control electrode of the third transistor T3 is electrically connected to the output terminal of the pull-down control circuit 120, and the third transistor The first electrode of T3 is electrically connected to the first node Q1, and the second electrode of the third transistor T3 is electrically connected to the second voltage terminal VGL.
  • the second voltage terminal VGL continuously provides a second voltage signal with an invalid potential.
  • the first electrode of the third transistor T3 and the second electrode of the third transistor T3 are turned on, and the first node Q1 is connected to the second voltage terminal VGL at this time, thereby The potential of the first node Q1 is pulled down, so that the output circuit 160 can stop outputting the first voltage signal.
  • the pull-down control circuit 120 includes a fourth transistor T4.
  • the control electrode of the fourth transistor T4 is electrically connected to the second clock signal terminal CLK2.
  • One pole is electrically connected to the second node Q2, and the second pole of the fourth transistor T4 is electrically connected to the control terminal of the first pull-down circuit 140.
  • the potential of the second clock signal is the effective potential and the potential of the second node Q2 is also the effective potential
  • the first pole of the fourth transistor T4 and the second pole of the fourth transistor T4 are turned on, and the second node Q2 is turned on.
  • the effective potential is directly written into the control electrode of the first pull-down circuit 140140, so that the first node Q1 and the second voltage terminal VGL are turned on, thereby pulling down the potential of the first node Q1, so that the output circuit 160 can stop outputting the first voltage signal .
  • the output circuit 160 includes a fifth transistor T5 and a sixth transistor T6;
  • the first electrode of the fifth transistor T5 is electrically connected to the first voltage terminal VDD, the second electrode of the fifth transistor T5 is electrically connected to the first electrode of the sixth transistor T6, and the fifth transistor
  • the control electrode of T5 is electrically connected to the first node Q1;
  • the control electrode of the sixth transistor T6 is electrically connected to the control end of the pull-down control circuit 120, and the second electrode of the sixth transistor T6 is electrically connected to the second voltage terminal VGL.
  • the first pole of the pull-down control circuit 120 and the second pole of the pull-down control circuit 120 must be disconnected, that is, the potential of the control terminal of the pull-down control circuit 120 is an invalid potential.
  • the control electrode of the sixth transistor T6 is electrically connected to the control terminal of the pull-down control circuit 120. Therefore, the potential of the control electrode of the sixth transistor T6 is an invalid potential.
  • the first electrode of the sixth transistor T6 is different from the second electrode of the sixth transistor T6. Disconnected from time to time. At this time, the fifth transistor T5 outputs the first voltage signal of the first voltage terminal VDD under the control of the effective potential of the first node Q1.
  • the potential of the control electrode of the sixth transistor T6 is an effective potential
  • the control electrode of the sixth transistor T6 is electrically connected to the control terminal of the pull-down control circuit 120
  • the first electrode of the pull-down control circuit 120 is connected to the pull-down control circuit 120.
  • the second pole of the sixth transistor T6 is turned on, and the pull-down control circuit 120 pulls down the potential of the first node Q1, so that the first pole of the fifth transistor T5 and the second pole of the fifth transistor T5 are disconnected, and the first pole of the sixth transistor T6 and the second pole of the sixth transistor T6 are turned off.
  • the second pole of the six transistor T6 is turned on, so that the signal output terminal of the output circuit 160 outputs the second voltage signal.
  • the second control circuit 130 includes a seventh transistor T7, the control electrode of the seventh transistor T7 is electrically connected to the input signal terminal STU, and the first transistor T7 of the seventh transistor T7 The electrode is electrically connected to the third clock signal terminal, and the second electrode of the seventh transistor T7 is electrically connected to the control terminal of the first pull-down circuit 140.
  • the first pole of the seventh transistor T7 and the second pole of the seventh transistor T7 are turned on, and the effective potential of the third clock signal is turned on.
  • Writing directly to the control electrode of the first pull-down circuit 140140 makes the first node Q1 and the second voltage terminal VGL conduct, thereby pulling down the potential of the first node Q1, so that the output circuit 160 can stop outputting the first voltage signal.
  • the tank circuit 150 includes a first capacitor C1, one end of the first capacitor C1 is electrically connected to the first voltage terminal VDD, and the other end of the first capacitor C1 is electrically connected to the first voltage terminal VDD.
  • the first node Q1 is electrically connected.
  • the first capacitor C1 prevents the first node Q1 A sudden change in the current of, and a bootstrap occurs, so that the first node Q1 maintains an effective potential, and the output circuit 160 continues to output the first voltage signal.
  • the shift register further includes an input circuit 310, a third control circuit 320, an inverter circuit 330, and a cascade circuit 340;
  • the input circuit 310 is configured to write the input signal provided by the input signal terminal STU into the control terminal of the third control circuit 320 under the control of the third clock signal;
  • the third control circuit 320 is configured to write the second clock signal provided by the second clock signal terminal CLK2 to the third node Q3 under the control of the input signal;
  • the inverter circuit 330 is used to write an electrical signal with the opposite potential of the third node Q3 to the second node Q2;
  • the cascade circuit 340 is configured to write the first voltage signal provided by the first voltage terminal VDD into the cascade output terminal CR under the control of the potential of the third node Q3.
  • control terminal of the input circuit 310 is electrically connected to the third clock signal terminal
  • first terminal of the input circuit 310 is electrically connected to the input signal terminal STU
  • second terminal of the input circuit 310 is electrically connected to the third control circuit 320.
  • the control terminal is electrically connected. Under the control that the potential of the third clock signal is the effective potential, the input signal is written into the first end of the input circuit 310.
  • the control terminal of the third control circuit 320 is electrically connected to the output terminal of the input circuit 310, the input terminal of the third control circuit 320 is electrically connected to the second clock signal terminal CLK2, and the output terminal of the third control circuit 320 is electrically connected to the third node Q3. Electric connection. Under the control that the potential of the input signal is the effective potential, the second clock signal is written into the third node Q3.
  • the first control terminal of the inverter circuit 330 is electrically connected to the first voltage terminal VDD
  • the second control terminal of the inverter circuit 330 is electrically connected to the input signal terminal STU
  • the first input terminal of the inverter circuit 330 is electrically connected to the third clock signal.
  • the second input terminal of the inverter circuit 330 is electrically connected to the first voltage terminal VDD
  • the output terminal of the inverter circuit 330 is electrically connected to the second node Q2.
  • the inverter circuit 330 is used to always control the potential of the second node Q2 to be opposite to the potential of the third node Q3.
  • the first control terminal of the cascade circuit 340 is electrically connected to the third node Q3, the second control terminal of the cascade circuit 340 is electrically connected to the second node Q2, and the input terminal of the cascade circuit 340 is electrically connected to the first voltage terminal VDD.
  • the cascade output terminal CR of the cascade circuit 340 is electrically connected to the control terminal of the first control circuit 110.
  • the cascade output terminal CR of the cascade circuit 340 When the potential of the third node Q3 is an effective potential and the potential of the second node Q2 is an ineffective potential, the cascade output terminal CR of the cascade circuit 340 is controlled to conduct with the first voltage terminal VDD, and the cascade output of the cascade circuit 340 The terminal CR outputs the first voltage signal; when the potential of the third node Q3 is an invalid potential and the potential of the second node Q2 is an effective potential, the cascade output terminal CR of the cascade circuit 340 is controlled to conduct with the second voltage terminal VGL, The cascade output terminal CR of the cascade circuit 340 outputs the second voltage signal.
  • the input circuit 310 includes an eighth transistor T8, the control electrode of the eighth transistor T8 is electrically connected to the third clock signal terminal, and the first electrode of the eighth transistor T8 It is electrically connected to the input signal terminal STU, and the second electrode of the eighth transistor T8 is electrically connected to the control electrode of the third control circuit 320.
  • the first pole of the eighth transistor T8 and the second pole of the eighth transistor T8 are turned on, so that the input signal is written into the control terminal of the third control circuit 320.
  • the third control circuit 320 includes a ninth transistor T9 and a tenth transistor T10;
  • the control electrode of the ninth transistor T9 is electrically connected to the output terminal of the input circuit 310, the first electrode of the ninth transistor T9 is electrically connected to the second timing signal terminal, and the first electrode of the ninth transistor T9 is electrically connected to the second timing signal terminal.
  • the two poles are electrically connected to the first pole of the tenth transistor T10;
  • the control electrode of the tenth transistor T10 is electrically connected to the second timing signal terminal, and the second electrode of the tenth transistor T10 is electrically connected to the third node Q3.
  • the first pole of the ninth transistor T9 and the second pole of the ninth transistor T9 are turned on, and the first pole of the tenth transistor T10 is connected to each other.
  • the second pole of the tenth transistor T10 is turned on, and the effective potential of the second clock signal is written into the third node Q3.
  • the inverter circuit 330 includes an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, and a fourteenth transistor T14;
  • the control electrode of the eleventh transistor T11 is electrically connected to the first voltage terminal VDD, the first electrode of the eleventh transistor T11 is electrically connected to the third timing signal terminal, and the first electrode of the eleventh transistor T11 is electrically connected to the third timing signal terminal.
  • the two poles are electrically connected to the control pole of the twelfth transistor T12;
  • the first electrode of the twelfth transistor T12 is electrically connected to the first voltage terminal VDD, and the second electrode of the twelfth transistor T12 is electrically connected to the second node Q2;
  • the control electrode of the thirteenth transistor T13 is electrically connected to the input signal terminal STU, the first electrode of the thirteenth transistor T13 is electrically connected to the second electrode of the eleventh transistor T11, and the thirteenth transistor The second pole of T13 is electrically connected to the second voltage terminal VGL;
  • the control electrode of the fourteenth transistor T14 is electrically connected to the input signal terminal STU, the first electrode of the fourteenth transistor T14 is electrically connected to the second node Q2, and the first electrode of the fourteenth transistor T14 is electrically connected to the second node Q2.
  • the two poles are electrically connected to the second voltage terminal VGL.
  • the potential of the control electrode of the eleventh transistor T11 is always at the effective potential, so the first electrode of the eleventh transistor T11 is electrically connected to the second electrode of the eleventh transistor T11, and the third timing signal is always written into the twelfth transistor T12 The control pole.
  • the potential of the third timing signal is the effective potential
  • the first pole of the twelfth transistor T12 and the second pole of the twelfth transistor T12 are turned on, so that the second pole of the twelfth transistor T12 outputs to the second node Q2 The first voltage signal.
  • the first pole of the thirteenth transistor T13 and the second pole of the thirteenth transistor T13 are turned on, and the first pole of the fourteenth transistor T14 is connected to the second pole of the fourteenth transistor T14.
  • the electrode is turned on, thereby pulling down the potential of the control electrode of the twelfth transistor T12 and the potential of the second electrode of the twelfth transistor T12.
  • the potential of the second node Q2 is the same as the potential of the second voltage signal.
  • it may also include a second capacitor C2, one end of the second capacitor is electrically connected to the first voltage terminal VDD, and the other end of the second capacitor is electrically connected to the third node Q3.
  • the control terminal of the third control circuit 320 obtains the effective potential.
  • the second clock signal is written into the third node Q3.
  • the node Q3 is an effective potential; when the potential of the second clock signal is an ineffective potential, the second capacitor C2 prevents a sudden change in the potential of the third node Q3 and provides an effective potential for the third node Q3, and the third node Q3 is still an effective potential.
  • the thirteenth transistor T13 will pull down the potential of the control terminal of the twelfth transistor T12, and the fourteenth transistor T14 will pull down the potential of the second node Q2, and at this time the potential of the second node Q2 It is an invalid potential, which is opposite to the potential of the third node Q3.
  • the potential of the input signal is an invalid potential
  • the first pole of the twelfth transistor T12 and the second pole of the twelfth transistor T12 are turned on, the first voltage signal is written into the second node Q2, and the potential of the second node Q2 is Effective potential.
  • the potential of the control terminal of the third control circuit 320 is an ineffective potential
  • the third node Q3 is an ineffective potential.
  • the potential of the second node Q2 is an ineffective potential, which is opposite to the potential of the third node Q3.
  • the cascade circuit 340 includes a fifteenth transistor T15 and a sixteenth transistor T16;
  • the control electrode of the fifteenth transistor T15 is electrically connected to the third node Q3, the first electrode of the fifteenth transistor T15 is electrically connected to the first voltage terminal VDD, and the second electrode of the fifteenth transistor T15 is electrically connected to The cascade output terminal CR is electrically connected;
  • the control electrode of the sixteenth transistor T16 is electrically connected to the second node Q2
  • the first electrode of the sixteenth transistor T16 is electrically connected to the second electrode of the fifteenth transistor T15
  • the sixteenth transistor The second pole of T16 is electrically connected to the second voltage terminal VGL.
  • the first pole of the fifteenth transistor T15 and the second pole of the fifteenth transistor T15 are turned on, so that the first voltage signal is written into the cascade output terminal CR, and the cascade output The terminal CR is at an effective potential, so that the control terminal of the first control circuit 110 obtains an effective potential.
  • the potential of the second node Q2 is an invalid potential
  • the first pole of the sixteenth transistor T16 and the second pole of the sixteenth transistor T16 are disconnected, and the control terminal of the first pull-down circuit 140 is provided with an invalid potential.
  • the potential of the second node Q2 is the effective potential
  • the first pole of the sixteenth transistor T16 and the second pole of the sixteenth transistor T16 are turned on, so that the second voltage signal is written into the cascade output terminal CR, and the cascade output The terminal CR is at an invalid potential, so that the control terminal of the first control circuit 110 obtains an invalid potential.
  • the potential of the third node Q3 is an invalid potential, and the first pole of the fifteenth transistor T15 and the second pole of the fifteenth transistor T15 are disconnected.
  • the shift register further includes a reset circuit 350;
  • the reset circuit 350 is configured to pull up the potential of the second node Q2 under the control of the reset signal provided by the reset signal line TST.
  • the reset signal line TST provides a reset signal whose potential is an effective potential after the end of each frame, so that the second node Q2 is electrically connected to the first voltage signal, so that the potential of the second node Q2 is the effective potential, thereby realizing the pull-down cascade The potential of the output terminal CR and the potential of the pull-down first node Q1.
  • the reset circuit 350 includes a seventeenth transistor T17.
  • the control electrode of the seventeenth transistor T17 is electrically connected to the reset signal line TST.
  • One pole is electrically connected to the first voltage terminal VDD, and the second pole of the seventeenth transistor T17 is electrically connected to the second node Q2.
  • the potential of the reset signal provided by the reset signal line TST is an effective potential
  • the first pole of the seventeenth transistor T17 and the second pole of the seventeenth transistor T17 are turned on, so that the first voltage signal is written into the second node Q2, Therefore, the effective potential of the second node Q2 can pull down the potential of the cascade output terminal CR and the potential of the first node Q1.
  • the shift register unit may further include a second pull-down circuit 360 for pulling down the potential of the third node Q3 under the control of the potential of the second node Q2.
  • the control terminal of the second pull-down circuit 360 is electrically connected to the second node Q2, the input terminal of the second pull-down circuit 360 is electrically connected to the third node Q3, and the output terminal of the second pull-down circuit 360 is electrically connected to the second voltage terminal VGL .
  • the potential of the second node Q2 is an effective potential
  • the third node Q3 and the second voltage terminal VGL are turned on, thereby pulling down the potential of the third node Q3.
  • the second pull-down circuit 360 includes an eighteenth transistor T18, the control electrode of the eighteenth transistor T18 is electrically connected to the second node Q2, and the first electrode of the eighteenth transistor T18 is electrically connected to the third node Q2. Q3 is electrically connected, and the second electrode of the eighteenth transistor T18 is electrically connected to the second voltage terminal VGL.
  • the first pole of the eighteenth transistor T18 and the second pole of the eighteenth transistor T18 are turned on, so that the second voltage signal is written into the third node Q3, so that the third node The potential of Q3 is an invalid potential.
  • the embodiment of the present disclosure also provides a driving method of the shift register unit, which is applied to the above-mentioned shift register unit, and the method includes:
  • the first stage includes alternate first and second sub-stages; in the first sub-stage, the first clock signal is written into the first node, so that the output circuit outputs a high-potential signal; in the second sub-stage, In the stage, the input signal controls the first pull-down circuit to pull down the potential of the first node, so that the output circuit outputs a low-level signal;
  • the second stage it includes a third sub-stage and a fourth sub-stage; in the third sub-stage, the first clock signal is written into the first node, so that the output circuit outputs a high-potential signal; in the fourth sub-stage Wherein the capacitor bootstrap maintains the potential of the first node, and the output circuit continuously outputs a high potential signal;
  • the second clock signal controls the pull-down circuit to pull down the potential of the first node, so that the output circuit outputs a low-level signal.
  • the potential of the first node is directly controlled by the first control circuit and the tank circuit, and the potential of the first node is indirectly controlled by the pull-down control circuit and the second control circuit using the first pull-down circuit to control the potential of the first node.
  • the first stage I includes a first sub-stage I-1 and a second sub-stage I-2; in the first sub-stage I-1, the potential of the input signal and the second clock signal
  • the potentials are all effective potentials, so that the potential of the third node Q3 is the effective potential, so that the potential of the cascade output terminal CR is the effective potential, and because the potential of the first clock signal is the effective potential, the potential of the first node Q1 is Is the effective potential.
  • the potential of the signal output terminal of the output circuit 160 is the effective potential; in the second sub-phase I-2, the potential of the input signal and the potential of the third sequential signal are both effective potentials, and the first pull-down circuit 140 The first node Q1 and the second voltage terminal VGL are turned on, and the potential of the first node Q1 is pulled down. At this time, the potential of the signal output terminal of the output circuit 160 is an invalid potential.
  • the second phase II includes the third sub-phase II-1 and the second sub-phase II-2; in the third sub-phase II-1, the potential of the input signal is an invalid potential, but the third capacitor C3 prevents the second node Q2
  • the potential of the second node Q2 is still at an invalid potential
  • the potential of the second clock signal is an effective potential
  • the potential of the cascade output terminal CR is still an effective potential
  • the second node Q2 is still an effective potential.
  • the potential of a node Q1 is the effective potential.
  • the potential of the signal output terminal of the output circuit 160 is the effective potential; in the fourth sub-phase II-2, the potential of the third clock signal is the effective potential, the potential of the input signal, and the second The potential of the clock signal is an invalid potential.
  • the second node Q2 is an effective potential, and the potential of the cascade output terminal CR is an invalid potential.
  • the first capacitor C1 prevents the potential of the first node Q1 from suddenly changing, the first node Q1 is still Effective potential. At this time, the potential of the signal output terminal of the output circuit 160 is still the effective potential.
  • the potential of the input signal is an invalid potential
  • the potential of the second node Q2 is an effective potential
  • the potential of the third node Q3 is an invalid potential, so that the potential of the cascade output terminal CR is an invalid potential.
  • the potential of the second clock signal is the effective potential
  • the effective potential of the second node Q2 is written into the control terminal of the first pull-down circuit 140 so that the potential of the first node Q1 is the ineffective potential.
  • the potential of the signal output terminal of the output circuit 160 is Invalid potential.
  • fourth stage IV and the fifth stage V may also be included before the first stage I;
  • the potential of the input signal is an invalid potential.
  • the potential of the third clock signal is an effective potential
  • the potential of the second node Q2 is an effective potential.
  • the potential of the output terminal CR and the signal output of the output circuit 160 are cascaded. The potentials at the terminals are all invalid potentials;
  • the potential of the input signal is an effective potential
  • the potential of the second node Q2 is an ineffective potential
  • the potential of the third node Q3 is also an ineffective potential
  • the cascade output The potential of the terminal CR and the potential of the signal output terminal of the output circuit 160 are both invalid potentials.
  • the embodiment of the present disclosure also provides a gate driving circuit, as shown in FIG. 5, which includes the above-mentioned shift register unit, each clock signal line, a second voltage signal line, and the like.
  • the embodiments of the present disclosure also provide a display device, including the gate driving circuit described above.
  • the display device can be a display, a mobile phone, a tablet computer, a television, a wearable electronic device, a navigation display device, and the like.

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Abstract

一种移位寄存器单元及其控制方法、栅极驱动电路和显示装置，其中，包括直接控制第一节点（Q1）的电位的第一控制电路（110）和储能电路（150）、间接控制第一节点（Q1）的电位的下拉控制电路（120）、第二控制电路（130）和第一下拉电路（140）、以及在第一节点（Q1）的电位的控制下将第一电压端（VDD）提供的第一电压信号输出至信号输出端的输出电路（160）。该移位寄存器单元及其控制方法、和栅极驱动电路，能够实现栅极扫描信号的脉冲宽度的调节，满足多种显示需求。

Description

移位寄存器单元及其控制方法、栅极驱动电路和显示装置
相关申请的交叉引用
本申请主张在2020年5月9日在中国提交的中国专利申请号No.202010385861.1的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种移位寄存器单元及其控制方法、栅极驱动电路和显示装置。
背景技术
在显示行业中，为了降低了显示面板的制作成本，实现显示面板的窄边框设计，越来越多的栅极驱动电路采用阵列基板行驱动(Gate Driver on Array，简称GOA)技术，即将栅极开关电路集成在显示面板的阵列基板上。
相关技术中，采用GOA技术的显示装置存在栅极扫描信号的脉冲宽度调节难度大的问题。
发明内容
本公开实施例提供一种移位寄存器单元及其控制方法、栅极驱动电路和显示装置，以解决相关技术采用GOA技术的显示装置存在栅极扫描信号的脉冲宽度调节难度大的问题。
为了解决上述技术问题，本公开提供技术方案如下：
第一方面，本公开实施例提供一种移位寄存器单元，包括第一控制电路、下拉控制电路、第二控制电路、第一下拉电路、储能电路和输出电路；
所述第一控制电路用于在级联输出端的电位的控制下，将所述第一时钟信号端提供的第一时钟信号写入第一节点；
所述下拉控制电路用于在第二时钟信号端提供的第二时钟信号的控制下，将第二节点的电信号写入所述第一下拉电路的控制端；
所述第二控制电路用于在输入信号端提供的输入信号的控制下，将第三 时钟信号端提供的第三时钟信号写入所述第一下拉电路的控制端；
所述第一下拉电路用于在所述第一下拉电路的控制端的电位的控制下，下拉所述第一节点的电位；
所述储能电路用于控制所述第一节点的电位；
所述输出电路用于在所述第一节点的电位的控制下，将第一电压端提供的第一电压信号输出至信号输出端。
进一步地，所述第一控制电路包括第一晶体管和第二晶体管，所述第一晶体管的控制极与所述级联输出端电连接，所述第一晶体管的第一极与所述第一时钟信号端电连接，所述第一晶体管的第二极与所述第二晶体管的第一极电连接，所述第二晶体管的第二极与所述第一节点电连接，所述第二晶体管的控制极与所述第一时钟信号端电连接。
进一步地，所述第一下拉电路包括第三晶体管，所述第三晶体管的控制极与所述下拉控制电路的输出端电连接，所述第三晶体管的第一极与所述第一节点电连接，所述第三晶体管的第二极与第二电压端电连接。
进一步地，所述下拉控制电路包括第四晶体管，所述第四晶体管的控制极与所述第二时钟信号端电连接，所述第四晶体管的第一极与所述第二节点电连接，所述第四晶体管的第二极与所述第一下拉电路的控制端电连接。
进一步地，所述输出电路包括第五晶体管和第六晶体管；
所述第五晶体管的第一极与所述第一电压端电连接，所述第五晶体管的第二极与所述第六晶体管的第一极电连接，所述第五晶体管的控制极与所述第一节点电连接；
所述第六晶体管的控制极与所述下拉控制电路的输出端电连接，所述第六晶体管的第二极与第二电压端电连接。
进一步地，所述第二控制电路包括第七晶体管，所述第七晶体管的控制极与所述输入信号端电连接，所述第七晶体管的第一极与所述第三时钟信号端电连接，所述第七晶体管的第二极与所述第一下拉电路的控制端电连接。
进一步地，所述储能电路包括电容，所述电容的一端与所述第一电压端电连接，所述电容的另一端与所述第一节点电连接。
进一步地，所述移位寄存器还包括输入电路、第三控制电路、反相电路 和级联电路；
所述输入电路用于在所述第三时钟信号的控制下，将所述输入信号端提供的输入信号写入所述第三控制电路的控制端；
所述第三控制电路用于在所述输入信号的控制下，将所述第二时钟信号端提供的第二时钟信号写入第三节点；
所述反相电路用于向所述第二节点写入与所述第三节点电位相反的电信号；
所述级联电路用于在所述第三节点的电位的控制下，将所述第一电压端提供的第一电压信号写入所述级联输出端。
进一步地，所述输入电路包括第八晶体管，所述第八晶体管的控制极与所述第三时钟信号端电连接，所述第八晶体管的第一极与所述输入信号端电连接，所述第八晶体管的第二极与所述第三控制电路的控制极电连接。
进一步地，所述第三控制电路包括第九晶体管和第十晶体管；
所述第九晶体管的控制极与所述输入电路的输出端电连接，所述第九晶体管的第一极与所述第二时序信号端电连接，所述第九晶体管的第二极与所述第十晶体管的第一极电连接；
所述第十晶体管的控制极与所述第二时序信号端电连接，所述第十晶体管的第二极与第三节点电连接。
进一步地，所述反相电路包括第十一晶体管、第十二晶体管、第十三晶体管和第十四晶体管；
所述第十一晶体管的控制极与第一电压端电连接，所述第十一晶体管的第一极与所述第三时序信号端电连接，所述第十一晶体管的第二极与所述第十二晶体管的控制极电连接；
所述第十二晶体管的第一极与所述第一电压端电连接，所述第十二晶体管的第二极与所述第二节点电连接；
所述第十三晶体管的控制极与输入信号端电连接，所述第十三晶体管的第一极与所述第十一晶体管的第二极电连接，所述第十三晶体管的第二极与第二电压端电连接；
所述第十四晶体管的控制极与所述输入信号端电连接，所述第十四晶体 管的第一极与所述第二节点电连接，所述第十四晶体管的第二极与所述第二电压端电连接。
进一步地，所述级联电路包括第十五晶体管和第十六晶体管；
所述第十五晶体管的控制极与第三节点电连接，所述第十五晶体管的第一极与第一电压端电连接，所述第十五晶体管的第二极与所述级联输出端电连接；
所述第十六晶体管的控制极与第二节点电连接，所述第十六晶体管的第一极与所述第十五晶体管的第二极电连接，所述第十六晶体管的第二极与第二电压端电连接。
进一步地，所述移位寄存器还包括复位电路；
所述复位电路用于在复位信号线提供的复位信号的控制下上拉所述第二节点的电位。
进一步地，所述复位电路包括第十七晶体管，所述第十七晶体管的控制极与所述复位信号线电连接，所述第十七晶体管的第一极与所述第一电压端电连接，所述第十七晶体管的第二极与所述第二节点电连接。
第二方面，本公开实施例还提供一种移位寄存器单元的驱动方法，应用于如上所述的移位寄存器单元，所述方法包括：
第一阶段，包括交替的第一子阶段和第二子阶段；在第一子阶段中，第一时钟信号写入所述第一节点，使得所述输出电路输出高电位信号；在第二子阶段中，输入信号控制所述第一下拉电路下拉所述第一节点的电位，使得所述输出电路输出低电位信号；
在第二阶段，包括第三子阶段和第四子阶段；在第三子阶段中，第一时钟信号写入所述第一节点，使得所述输出电路输出高电位信号；在第四子阶段中，所述电容自举保持所述第一节点的电位，所述输出电路持续输出高电位信号；
第三阶段，第二时钟信号控制所述下拉电路下拉所述第一节点的电位，使得所述输出电路输出低电位信号。
第三方面，本公开实施例还提供一种栅极驱动电路，包括如上所述的移位寄存器单元。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对本公开实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为本公开一实施例提供的移位寄存器单元的部分结构示意图；
图2为图1对应的电路图；
图3为本公开另一实施例提供的移位寄存器单元的电路图；
图4为图3中各信号的时序图；
图5为本公开一实施例提供的栅极驱动电路连接示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
需要说明的是，本申请实施例中提到的晶体管，可以是P型晶体管，此时第一极为漏极，第二极为源极；也可以是N型晶体管，此时第一极为源极，第二极为漏极。上述晶体管可以均为同型晶体管，也可以分别为不同的晶体管，此处不作限定。另外，本申请实施例中提到的有效电位为能够使相连的晶体管的第一极与第二极相导通的电位，例如：晶体管为N型晶体管，则有效电位为高电位，无效电位为低电位。
本公开实施例提供一种移位寄存器单元，如图1所示，包括第一控制电路110、下拉控制电路120、第二控制电路130、第一下拉电路140、储能电路150和输出电路160；
所述第一控制电路110用于在级联输出端CR的电位的控制下，将所述第一时钟信号端CLK1提供的第一时钟信号写入第一节点Q1；
所述下拉控制电路120用于在第二时钟信号端CLK2提供的第二时钟信 号的控制下，将第二节点Q2的电信号写入所述第一下拉电路140的控制端；
所述第二控制电路130用于在输入信号端STU提供的输入信号的控制下，将第三时钟信号端CLK3提供的第三时钟信号写入所述第一下拉电路140的控制端；
所述第一下拉电路140用于在所述第一下拉电路140的控制端的电位的控制下，下拉所述第一节点Q1的电位；
所述储能电路150用于控制所述第一节点Q1的电位；
所述输出电路160用于在所述第一节点Q1的电位的控制下，将第一电压端VDD提供的第一电压信号输出至信号输出端。
本公开实施例中，通过第一控制电路和储能电路直接控制第一节点的电位，又通过下拉控制电路、第二控制电路利用第一下拉电路控制间接控制第一节点的电位，从而实现对第一节点的电位的多样化控制，进而通过控制第一节点的电位来改变输出电路输出的栅极扫描信号的脉冲宽度，实现栅极扫描信号的脉冲宽度的调节。因此，本公开提供的技术方案能够实现栅极扫描信号的脉冲宽度的调节，满足多种显示需求。
上述第一控制电路110的控制端与级联输出端CR电连接，所述第一控制电路110的输入端与第一时钟信号端CLK1电连接，所述第一控制电路110的输出端与第一节点Q1电连接。在级联输出端CR输出的级联信号的控制下，控制第一时钟信号端CLK1与第一节点Q1之间导通，从而将第一时钟信号端CLK1提供的第一时钟信号写入第一节点Q1。
上述下拉控制电路120的控制端与第二时钟信号端CLK2电连接，所述下拉控制电路120的输入端与第二节点Q2电连接，所述下拉控制电路120的输出端与所述第一下拉电路140的控制端电连接。在第二时钟信号端CLK2提供的第二时钟信号的控制下，控制第二节点Q2与第一下拉电路140的控制端之间导通，从而第二节点Q2的电信号写入第一下拉电路140的控制端。
上述第二控制电路130的控制端与输入信号端STU电连接，所述第二控制电路130的输入端与第三时钟信号端电连接，所述第二控制电路130的输出端分别与所述第一下拉电路140的控制端和所述输出电路160电连接。在输入信号端STU提供的输入信号的控制下，控制第三时钟信号端与第一下拉 电路140的控制端之间导通，从而第三时钟信号端提供的第三时钟信号写入第一下拉电路140的控制端。
上述第一下拉电路140的输入端与所述第一节点Q1电连接，所述第一下拉电路140的输出端与第二电压端VGL电连接。在第一下拉电路140的控制端的电位的控制下，控制第一节点Q1与第二电压端VGL导通，从而实现下拉第一节点Q1的电位。
上述储能电路150的一端与第一电压端VDD电连接，储能电路150的另一端与第一节点Q1电连接，用于防止第一节点Q1的电位发生突变。
上述输出电路160的第一控制端与所述第一节点Q1电连接，所述输出电路160的第二控制端与第二控制电路130的输出端电连接，所述输出电路160的输入端与第一电压端VDD电连接，所述输出电路160的信号输出端可以与像素驱动电路中的栅线电连接。在第一节点Q1的电位的控制下，控制第一电压端VDD与输出电路160的信号输出端之间导通，从而输出电路160的信号输出端输出第一电压端VDD提供的第一电压信号；在第二控制电路130的输出端的电位的控制下，控制第二电压端VGL与输出电路160的信号输出端之间导通，从而输出电路160的信号输出端输出第二电压端VGL提供的第二电压信号。
本实施例中，第一电压端VDD持续提供电位为有效电位的第一电压信号。
进一步地，如图2所示，所述第一控制电路110包括第一晶体管T1和第二晶体管T2，所述第一晶体管T1的控制极与所述级联输出端CR电连接，所述第一晶体管T1的第一极与所述第一时钟信号端CLK1电连接，所述第一晶体管T1的第二极与所述第二晶体管T2的第一极电连接，所述第二晶体管T2的第二极与所述第一节点Q1电连接，所述第二晶体管T2的控制极与所述第一时钟信号端CLK1电连接。
在级联输出端CR提供的级联信号的电位为有效电位且第一时钟信号的电位也为有效电位时，使得第一晶体管T1的第一极和第二晶体管T2的第二极导通、第二晶体管T2的第一极和第二晶体管T2的第二极导通，第一时钟信号直接写入第一节点Q1，此时第一节点Q1的电位即为有效电位，使得输出电路160输出第一电压端VDD提供的第一电压信号。
进一步地，如图2所示，所述第一下拉电路140包括第三晶体管T3，所述第三晶体管T3的控制极与所述下拉控制电路120的输出端电连接，所述第三晶体管T3的第一极与所述第一节点Q1电连接，所述第三晶体管T3的第二极与第二电压端VGL电连接。
本实施例中，第二电压端VGL持续提供电位为无效电位的第二电压信号。
在第三晶体管T3的控制极的电位为有效电位时，第三晶体管T3的第一极和第三晶体管T3的第二极导通，此时第一节点Q1与第二电压端VGL连接，从而下拉第一节点Q1的电位，从而能够使得输出电路160停止输出第一电压信号。
进一步地，如图2所示，所述下拉控制电路120包括第四晶体管T4，所述第四晶体管T4的控制极与所述第二时钟信号端CLK2电连接，所述第四晶体管T4的第一极与所述第二节点Q2电连接，所述第四晶体管T4的第二极与所述第一下拉电路140的控制端电连接。
在第二时钟信号的电位为有效电位且第二节点Q2的电位也为有效电位时，使得第四晶体管T4的第一极和第四晶体管T4的第二极导通，将第二节点Q2的有效电位直接写入第一下拉电路140140的控制极，使得第一节点Q1与第二电压端VGL导通，从而下拉第一节点Q1的电位，从而能够使得输出电路160停止输出第一电压信号。
进一步地，如图2所示，所述输出电路160包括第五晶体管T5和第六晶体管T6；
所述第五晶体管T5的第一极与所述第一电压端VDD电连接，所述第五晶体管T5的第二极与所述第六晶体管T6的第一极电连接，所述第五晶体管T5的控制极与所述第一节点Q1电连接；
所述第六晶体管T6的控制极与所述下拉控制电路120的控制端电连接，所述第六晶体管T6的第二极与第二电压端VGL电连接。
在第一节点Q1的电位为有效电位的情况下，下拉控制电路120的第一极和下拉控制电路120的第二极必然断开，即下拉控制电路120的控制端的电位为无效电位，又由于第六晶体管T6的控制极与下拉控制电路120的控制端电连接，因此第六晶体管T6的控制极的电位为无效电位，第六晶体管T6 的第一极与第六晶体管T6的第二极之间断开。此时，第五晶体管T5在第一节点Q1的有效电位的控制下将第一电压端VDD的第一电压信号进行输出。
在第六晶体管T6的控制极的电位为有效电位的情况下，由于第六晶体管T6的控制极与下拉控制电路120的控制端电连接，因此下拉控制电路120的第一极与下拉控制电路120的第二极导通，下拉控制电路120下拉第一节点Q1的电位，使得第五晶体管T5的第一极和第五晶体管T5的第二极断开，第六晶体管T6的第一极和第六晶体管T6的第二极导通，使得输出电路160的信号输出端输出第二电压信号。
进一步地，如图2所示，所述第二控制电路130包括第七晶体管T7，所述第七晶体管T7的控制极与所述输入信号端STU电连接，所述第七晶体管T7的第一极与所述第三时钟信号端电连接，所述第七晶体管T7的第二极与所述第一下拉电路140的控制端电连接。
在输入信号的电位为有效电位且第三时钟信号的电位也为有效电位时，使得第七晶体管T7的第一极和第七晶体管T7的第二极导通，将第三时钟信号的有效电位直接写入第一下拉电路140140的控制极，使得第一节点Q1与第二电压端VGL导通，从而下拉第一节点Q1的电位，从而能够使得输出电路160停止输出第一电压信号。
进一步地，如图2所示，所述储能电路150包括第一电容C1，所述第一电容C1的一端与所述第一电压端VDD电连接，所述第一电容C1的另一端与所述第一节点Q1电连接。
第一电容C1在第一下拉电路140的第一极与第一下拉电路140的第二极断开且第一时钟信号的电位从有效电位变为无效电位时，为了防止第一节点Q1的电流突变而发生自举，使得第一节点Q1保持有效电位，进而使得输出电路160继续输出第一电压信号。
进一步地，如图3所示，所述移位寄存器还包括输入电路310、第三控制电路320、反相电路330和级联电路340；
所述输入电路310用于在所述第三时钟信号的控制下，将所述输入信号端STU提供的输入信号写入所述第三控制电路320的控制端；
所述第三控制电路320用于在所述输入信号的控制下，将所述第二时钟 信号端CLK2提供的第二时钟信号写入第三节点Q3；
所述反相电路330用于向所述第二节点Q2写入与所述第三节点Q3电位相反的电信号；
所述级联电路340用于在所述第三节点Q3的电位的控制下，将所述第一电压端VDD提供的第一电压信号写入所述级联输出端CR。
本实施例中，上述输入电路310的控制端与第三时钟信号端电连接，输入电路310的第一端与输入信号端STU电连接，输入电路310的第二极与第三控制电路320的控制端电连接。在第三时钟信号的电位为有效电位的控制下，将输入信号写入输入电路310的第一端。
上述第三控制电路320的控制端与输入电路310的输出端电连接，第三控制电路320的输入端与第二时钟信号端CLK2电连接，第三控制电路320的输出端与第三节点Q3电连接。在输入信号的电位为有效电位的控制下，将第二时钟信号写入第三节点Q3。
上述反相电路330的第一控制端与第一电压端VDD电连接，反相电路330的第二控制端与输入信号端STU电连接，反相电路330的第一输入端与第三时钟信号端电连接，反相电路330的第二输入端与第一电压端VDD电连接，反相电路330的输出端与第二节点Q2电连接。反相电路330用于始终控制第二节点Q2的电位与第三节点Q3的电位相反。
上述级联电路340的第一控制端与第三节点Q3电连接，级联电路340的第二控制端与第二节点Q2电连接，级联电路340的输入端与第一电压端VDD电连接，级联电路340的级联输出端CR与第一控制电路110的控制端电连接。在第三节点Q3的电位为有效电位且第二节点Q2的电位为无效电位时，控制级联电路340的级联输出端CR与第一电压端VDD导通，级联电路340的级联输出端CR输出第一电压信号；在第三节点Q3的电位为无效电位且第二节点Q2的电位为有效电位时，控制级联电路340的级联输出端CR与第二电压端VGL导通，级联电路340的级联输出端CR输出第二电压信号。
进一步地，如图3所示，所述输入电路310包括第八晶体管T8，所述第八晶体管T8的控制极与所述第三时钟信号端电连接，所述第八晶体管T8的第一极与所述输入信号端STU电连接，所述第八晶体管T8的第二极与所述 第三控制电路320的控制极电连接。
在第三时钟信号的电位为有效电位时，使得第八晶体管T8的第一极和第八晶体管T8的第二极导通，从而将输入信号写入第三控制电路320的控制端。
进一步地，如图3所示，所述第三控制电路320包括第九晶体管T9和第十晶体管T10；
所述第九晶体管T9的控制极与所述输入电路310的输出端电连接，所述第九晶体管T9的第一极与所述第二时序信号端电连接，所述第九晶体管T9的第二极与所述第十晶体管T10的第一极电连接；
所述第十晶体管T10的控制极与所述第二时序信号端电连接，所述第十晶体管T10的第二极与第三节点Q3电连接。
在输入信号的电位为有效电位且第二时钟信号的电位为有效电位时，使得第九晶体管T9的第一极与第九晶体管T9的第二极导通、第十晶体管T10的第一极和第十晶体管T10的第二极导通，将第二时钟信号的有效电位写入第三节点Q3。
进一步地，如图3所示，所述反相电路330包括第十一晶体管T11、第十二晶体管T12、第十三晶体管T13和第十四晶体管T14；
所述第十一晶体管T11的控制极与第一电压端VDD电连接，所述第十一晶体管T11的第一极与所述第三时序信号端电连接，所述第十一晶体管T11的第二极与所述第十二晶体管T12的控制极电连接；
所述第十二晶体管T12的第一极与所述第一电压端VDD电连接，所述第十二晶体管T12的第二极与所述第二节点Q2电连接；
所述第十三晶体管T13的控制极与输入信号端STU电连接，所述第十三晶体管T13的第一极与所述第十一晶体管T11的第二极电连接，所述第十三晶体管T13的第二极与第二电压端VGL电连接；
所述第十四晶体管T14的控制极与所述输入信号端STU电连接，所述第十四晶体管T14的第一极与所述第二节点Q2电连接，所述第十四晶体管T14的第二极与所述第二电压端VGL电连接。
第十一晶体管T11的控制极的电位始终处于有效电位，因此第十一晶体管T11的第一极与第十一晶体管T11的第二极电连接，第三时序信号一直写 入第十二晶体管T12的控制极。
在第三时序信号的电位为有效电位时，第十二晶体管T12的第一极与第十二晶体管T12的第二极导通，从而第十二晶体管T12的第二极向第二节点Q2输出第一电压信号。
在输入信号的电位为有效电位时，第十三晶体管T13的第一极和第十三晶体管T13的第二极导通、第十四晶体管T14的第一极与第十四晶体管T14的第二极导通，从而下拉第十二晶体管T12的控制极的电位和第十二晶体管T12的第二极的电位，此时第二节点Q2电位与第二电压信号的电位相同。
另外，还可以包括第二电容C2，第二电容的一端与第一电压端VDD电连接，第二电容的另一端与第三节点Q3电连接。
在输入信号的电位为有效电位时，使得第三控制电路320的控制端得到有效电位，在第二时钟信号的电位为有效电位时，第二时钟信号写入第三节点Q3，此时第三节点Q3为有效电位；在第二时钟信号的电位为非有效电位时，第二电容C2防止第三节点Q3的电位突变，为第三节点Q3提供有效电位，第三节点Q3依旧为有效电位。然而，输入信号的电位为有效电位时，第十三晶体管T13会下拉第十二晶体管T12的控制端的电位，第十四晶体管T14会下拉第二节点Q2的电位，此时第二节点Q2的电位为无效电位，与第三节点Q3的电位相反。
在输入信号的电位为无效电位时，第十二晶体管T12的第一极和第十二晶体管T12的第二极导通，第一电压信号写入第二节点Q2，第二节点Q2的电位为有效电位。然而，第三控制电路320的控制端的电位为无效电位，第三节点Q3为无效电位，此时第二节点Q2的电位为无效电位，与第三节点Q3的电位相反。
进一步地，如图3所示，所述级联电路340包括第十五晶体管T15和第十六晶体管T16；
所述第十五晶体管T15的控制极与第三节点Q3电连接，所述第十五晶体管T15的第一极与第一电压端VDD电连接，所述第十五晶体管T15的第二极与所述级联输出端CR电连接；
所述第十六晶体管T16的控制极与第二节点Q2电连接，所述第十六晶 体管T16的第一极与所述第十五晶体管T15的第二极电连接，所述第十六晶体管T16的第二极与第二电压端VGL电连接。
在第三节点Q3的电位为有效电位时，第十五晶体管T15的第一极与第十五晶体管T15的第二极导通，从而第一电压信号写入级联输出端CR，级联输出端CR处于有效电位，进而使得第一控制电路110的控制端得到有效电位。此时，第二节点Q2的电位为无效电位，第十六晶体管T16的第一极和第十六晶体管T16的第二极断开，且为第一下拉电路140的控制端提供无效电位。
在第二节点Q2的电位为有效电位时，第十六晶体管T16的第一极与第十六晶体管T16的第二极导通，从而第二电压信号写入级联输出端CR，级联输出端CR处于无效电位，进而使得第一控制电路110的控制端得到无效电位。此时，第三节点Q3的电位为无效电位，第十五晶体管T15的第一极和第十五晶体管T15的第二极断开。
进一步地，如图3所示，所述移位寄存器还包括复位电路350；
所述复位电路350用于在复位信号线TST提供的复位信号的控制下上拉所述第二节点Q2的电位。
上述复位信号线TST在每一帧结束后提供一段电位为有效电位的复位信号，使得第二节点Q2与第一电压信号电连接，从而第二节点Q2的电位为有效电位，进而实现下拉级联输出端CR的电位和下拉第一节点Q1的电位。
进一步地，如图3所示，所述复位电路350包括第十七晶体管T17，所述第十七晶体管T17的控制极与所述复位信号线TST电连接，所述第十七晶体管T17的第一极与所述第一电压端VDD电连接，所述第十七晶体管T17的第二极与所述第二节点Q2电连接。
在复位信号线TST提供的复位信号的电位为有效电位时，第十七晶体管T17的第一极和第十七晶体管T17的第二极导通，从而第一电压信号写入第二节点Q2，从而使得第二节点Q2的有效电位能够下拉级联输出端CR的电位和下拉第一节点Q1的电位。
进一步地，如图3所示，移位寄存器单元还可以包括第二下拉电路360，用于在第二节点Q2的电位的控制下下拉第三节点Q3的电位。
第二下拉电路360的控制端与第二节点Q2电连接，第二下拉电路360的输入端与第三节点Q3电连接，所述第二下拉电路360的输出端与第二电压端VGL电连接。在第二节点Q2的电位为有效电位时，导通第三节点Q3与第二电压端VGL，从而下拉第三节点Q3的电位。
进一步地，如图3所示，第二下拉电路360包括第十八晶体管T18，第十八晶体管T18的控制极与第二节点Q2电连接，第十八晶体管T18的第一极与第三节点Q3电连接，第十八晶体管T18的第二极与第二电压端VGL电连接。
在第二节点Q2的电位为有效电位时，第十八晶体管T18的第一极与第十八晶体管T18的第二极导通，从而第二电压信号写入第三节点Q3，使得第三节点Q3的电位为无效电位。
本公开实施例还提供一种移位寄存器单元的驱动方法，应用于如上所述的移位寄存器单元，所述方法包括：
第一阶段，包括交替的第一子阶段和第二子阶段；在第一子阶段中，第一时钟信号写入所述第一节点，使得所述输出电路输出高电位信号；在第二子阶段中，输入信号控制所述第一下拉电路下拉所述第一节点的电位，使得所述输出电路输出低电位信号；
在第二阶段，包括第三子阶段和第四子阶段；在第三子阶段中，第一时钟信号写入所述第一节点，使得所述输出电路输出高电位信号；在第四子阶段中，所述电容自举保持所述第一节点的电位，所述输出电路持续输出高电位信号；
第三阶段，第二时钟信号控制所述下拉电路下拉所述第一节点的电位，使得所述输出电路输出低电位信号。
本公开实施例中，通过第一控制电路和储能电路直接控制第一节点的电位，又通过下拉控制电路、第二控制电路利用第一下拉电路控制间接控制第一节点的电位，从而实现对第一节点的电位的多样化控制，进而通过控制第一节点的电位来改变输出电路输出的栅极扫描信号的脉冲宽度，实现栅极扫描信号的脉冲宽度的调节。因此，本公开提供的技术方案能够实现栅极扫描信号的脉冲宽度的调节，满足多种显示需求。
结合图3和图4所示，第一阶段Ⅰ包括第一子阶段Ⅰ-1和第二子阶段Ⅰ-2；在第一子阶段Ⅰ-1中，输入信号的电位和第二时钟信号的电位均为有效电位，使得第三节点Q3的电位为有效电位，进而使得级联输出端CR的电位为有效电位，又由于第一时钟信号的电位为有效电位，从而使得第一节点Q1的电位为有效电位，此时输出电路160的信号输出端的电位为有效电位；在第二子阶段Ⅰ-2中，输入信号的电位和第三时序信号的电位均为有效电位，第一下拉电路140将第一节点Q1与第二电压端VGL导通，下拉第一节点Q1的电位，此时输出电路160的信号输出端的电位为无效电位。
第二阶段Ⅱ包括第三子阶段Ⅱ-1和第二子阶段Ⅱ-2；在第三子阶段Ⅱ-1中，输入信号的电位为无效电位，但是由于第三电容C3防止第二节点Q2的电位突变，第二节点Q2仍为无效电位，第二时钟信号的电位为有效电位，级联输出端CR的电位仍然为有效电位，又由于第一时钟信号的电位为有效电位，从而使得第一节点Q1的电位为有效电位，此时输出电路160的信号输出端的电位为有效电位；在第四子阶段Ⅱ-2中，第三时钟信号的电位为有效电位、输入信号的电位和第二时钟信号的电位为无效电位，此时第二节点Q2为有效电位、级联输出端CR的电位为无效电位，但是由于第一电容C1防止第一节点Q1的电位突变，第一节点Q1仍为有效电位，此时输出电路160的信号输出端的电位仍为有效电位。
在第三阶段Ⅲ中，输入信号的电位为无效电位，第二节点Q2的电位为有效电位、第三节点Q3的电位为无效电位，使得级联输出端CR的电位为无效电位，又由于第二时钟信号的电位为有效电位，第二节点Q2的有效电位写入第一下拉电路140的控制端，使得第一节点Q1的电位为无效电位，此时输出电路160的信号输出端的电位为无效电位。
进一步地，在第一阶段Ⅰ之前还可以包括第四阶段Ⅳ和第五阶段Ⅴ；
在第四阶段中，输入信号的电位为无效电位，在第三时钟信号的电位为有效电位时，第二节点Q2的电位为有效电位，级联输出端CR的电位和输出电路160的信号输出端的电位均为无效电位；
在第五阶段中，输入信号的电位为有效电位，第二节点Q2的电位为无效电位，但是由于第二时钟信号的电位为无效电位，第三节点Q3的电位也 为无效电位，级联输出端CR的电位和输出电路160的信号输出端的电位均为无效电位。
本公开实施例还提供一种栅极驱动电路，如图5所示，包括如上所述的移位寄存器单元、以及各时钟信号线、第二电压信号线等。
本公开实施例还提供一种显示装置，包括如上所述的栅极驱动电路。
显示装置可以是显示器、手机、平板电脑、电视机、可穿戴电子设备、导航显示设备等。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
上面结合附图对本公开的实施例进行了描述，但是本公开并不局限于上述的具体实施方式，上述的具体实施方式仅仅是示意性的，而不是限制性的，本领域的普通技术人员在本公开的启示下，在不脱离本公开宗旨和权利要求所保护的范围情况下，还可做出很多形式，均属于本公开的保护之内。

Claims (17)

  1. 一种移位寄存器单元，其特征在于，包括第一控制电路、下拉控制电路、第二控制电路、第一下拉电路、储能电路和输出电路；
    所述第一控制电路用于在级联输出端的电位的控制下，将第一时钟信号端提供的第一时钟信号写入第一节点；
    所述下拉控制电路用于在第二时钟信号端提供的第二时钟信号的控制下，将第二节点的电信号写入所述第一下拉电路的控制端；
    所述第二控制电路用于在输入信号端提供的输入信号的控制下，将第三时钟信号端提供的第三时钟信号写入所述第一下拉电路的控制端；
    所述第一下拉电路用于在所述第一下拉电路的控制端的电位的控制下，下拉所述第一节点的电位；
    所述储能电路用于控制所述第一节点的电位；
    所述输出电路用于在所述第一节点的电位的控制下，将第一电压端提供的第一电压信号输出至信号输出端。
  2. 根据权利要求1所述的移位寄存器单元，其特征在于，所述第一控制电路包括第一晶体管和第二晶体管，所述第一晶体管的控制极与所述级联输出端电连接，所述第一晶体管的第一极与所述第一时钟信号端电连接，所述第一晶体管的第二极与所述第二晶体管的第一极电连接，所述第二晶体管的第二极与所述第一节点电连接，所述第二晶体管的控制极与所述第一时钟信号端电连接。
  3. 根据权利要求1所述的移位寄存器单元，其特征在于，所述第一下拉电路包括第三晶体管，所述第三晶体管的控制极与所述下拉控制电路的输出端电连接，所述第三晶体管的第一极与所述第一节点电连接，所述第三晶体管的第二极与第二电压端电连接。
  4. 根据权利要求1所述的移位寄存器单元，其特征在于，所述下拉控制电路包括第四晶体管，所述第四晶体管的控制极与所述第二时钟信号端电连接，所述第四晶体管的第一极与所述第二节点电连接，所述第四晶体管的第二极与所述第一下拉电路的控制端电连接。
  5. 根据权利要求1所述的移位寄存器单元，其特征在于，所述输出电路包括第五晶体管和第六晶体管；
    所述第五晶体管的第一极与所述第一电压端电连接，所述第五晶体管的第二极与所述第六晶体管的第一极电连接，所述第五晶体管的控制极与所述第一节点电连接；
    所述第六晶体管的控制极与所述下拉控制电路的控制端电连接，所述第六晶体管的第二极与第二电压端电连接。
  6. 根据权利要求1所述的移位寄存器单元，其特征在于，所述第二控制电路包括第七晶体管，所述第七晶体管的控制极与所述输入信号端电连接，所述第七晶体管的第一极与所述第三时钟信号端电连接，所述第七晶体管的第二极与所述第一下拉电路的控制端电连接。
  7. 根据权利要求1所述的移位寄存器单元，其特征在于，所述储能电路包括电容，所述电容的一端与所述第一电压端电连接，所述电容的另一端与所述第一节点电连接。
  8. 根据权利要求1-7中任一项所述的移位寄存器单元，其特征在于，所述移位寄存器还包括输入电路、第三控制电路、反相电路和级联电路；
    所述输入电路用于在所述第三时钟信号的控制下，将所述输入信号端提供的输入信号写入所述第三控制电路的控制端；
    所述第三控制电路用于在所述输入信号的控制下，将所述第二时钟信号端提供的第二时钟信号写入第三节点；
    所述反相电路用于向所述第二节点写入与所述第三节点电位相反的电信号；
    所述级联电路用于在所述第三节点的电位的控制下，将所述第一电压端提供的第一电压信号写入所述级联输出端。
  9. 根据权利要求8所述的移位寄存器单元，其特征在于，所述输入电路包括第八晶体管，所述第八晶体管的控制极与所述第三时钟信号端电连接，所述第八晶体管的第一极与所述输入信号端电连接，所述第八晶体管的第二极与所述第三控制电路的控制极电连接。
  10. 根据权利要求8所述的移位寄存器单元，其特征在于，所述第三控 制电路包括第九晶体管和第十晶体管；
    所述第九晶体管的控制极与所述输入电路的输出端电连接，所述第九晶体管的第一极与第二时序信号端电连接，所述第九晶体管的第二极与所述第十晶体管的第一极电连接；
    所述第十晶体管的控制极与所述第二时序信号端电连接，所述第十晶体管的第二极与第三节点电连接。
  11. 根据权利要求8所述的移位寄存器单元，其特征在于，所述反相电路包括第十一晶体管、第十二晶体管、第十三晶体管和第十四晶体管；
    所述第十一晶体管的控制极与第一电压端电连接，所述第十一晶体管的第一极与第三时序信号端电连接，所述第十一晶体管的第二极与所述第十二晶体管的控制极电连接；
    所述第十二晶体管的第一极与所述第一电压端电连接，所述第十二晶体管的第二极与所述第二节点电连接；
    所述第十三晶体管的控制极与输入信号端电连接，所述第十三晶体管的第一极与所述第十一晶体管的第二极电连接，所述第十三晶体管的第二极与第二电压端电连接；
    所述第十四晶体管的控制极与所述输入信号端电连接，所述第十四晶体管的第一极与所述第二节点电连接，所述第十四晶体管的第二极与所述第二电压端电连接。
  12. 根据权利要求8所述的移位寄存器单元，其特征在于，所述级联电路包括第十五晶体管和第十六晶体管；
    所述第十五晶体管的控制极与第三节点电连接，所述第十五晶体管的第一极与第一电压端电连接，所述第十五晶体管的第二极与所述级联输出端电连接；
    所述第十六晶体管的控制极与第二节点电连接，所述第十六晶体管的第一极与所述第十五晶体管的第二极电连接，所述第十六晶体管的第二极与第二电压端电连接。
  13. 根据权利要求8所述的移位寄存器单元，其特征在于，所述移位寄存器还包括复位电路；
    所述复位电路用于在复位信号线提供的复位信号的控制下上拉所述第二节点的电位。
  14. 根据权利要求13所述的移位寄存器单元，其特征在于，所述复位电路包括第十七晶体管，所述第十七晶体管的控制极与所述复位信号线电连接，所述第十七晶体管的第一极与所述第一电压端电连接，所述第十七晶体管的第二极与所述第二节点电连接。
  15. 一种移位寄存器单元的驱动方法，其特征在于，应用于如权利要求1-14中任一项所述的移位寄存器单元，所述方法包括：
    第一阶段，包括交替的第一子阶段和第二子阶段；在第一子阶段中，第一时钟信号写入所述第一节点，使得所述输出电路输出高电位信号；在第二子阶段中，输入信号控制所述第一下拉电路下拉所述第一节点的电位，使得所述输出电路输出低电位信号；
    在第二阶段，包括第三子阶段和第四子阶段；在第三子阶段中，第一时钟信号写入所述第一节点，使得所述输出电路输出高电位信号；在第四子阶段中，所述电容自举保持所述第一节点的电位，所述输出电路持续输出高电位信号；
    第三阶段，第二时钟信号控制所述下拉电路下拉所述第一节点的电位，使得所述输出电路输出低电位信号。
  16. 一种栅极驱动电路，其特征在于，包括如权利要求1-14中任一项所述的移位寄存器单元。
  17. 一种显示装置，其特征在于，包括如权利要求16所述的栅极驱动电路。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024108544A1 (zh) * 2022-11-25 2024-05-30 京东方科技集团股份有限公司 驱动电路、驱动方法、显示基板和显示装置

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111445833B (zh) * 2020-05-09 2022-09-13 合肥京东方卓印科技有限公司 移位寄存器单元及其控制方法、和栅极驱动电路
CN111933083B (zh) * 2020-08-21 2023-04-07 京东方科技集团股份有限公司 移位寄存器单元、驱动方法和显示装置
CN114203081B (zh) * 2020-09-02 2023-12-22 京东方科技集团股份有限公司 栅极驱动单元、驱动方法、栅极驱动电路和显示装置
CN113192463B (zh) * 2021-05-11 2022-11-04 合肥京东方卓印科技有限公司 发光控制移位寄存器、栅极驱动电路、显示装置及方法
CN113539185B (zh) * 2021-07-29 2022-12-23 合肥京东方卓印科技有限公司 显示装置、栅极驱动电路、移位寄存单元及其驱动方法
US20240185936A1 (en) * 2021-08-20 2024-06-06 Boe Technology Group Co., Ltd. Shift register and driving method thereof, gate driving circuit, and display device

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104299583A (zh) * 2014-09-26 2015-01-21 京东方科技集团股份有限公司 一种移位寄存器及其驱动方法、驱动电路和显示装置
KR20170078978A (ko) * 2015-12-29 2017-07-10 엘지디스플레이 주식회사 게이트 쉬프트 레지스터와 이를 포함한 유기발광 표시장치 및 그 구동방법
CN108520724A (zh) * 2018-04-18 2018-09-11 京东方科技集团股份有限公司 移位寄存器单元及驱动方法、栅极驱动电路和显示装置
CN108806584A (zh) * 2018-07-27 2018-11-13 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
CN109935269A (zh) * 2018-05-31 2019-06-25 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
CN110060645A (zh) * 2019-05-07 2019-07-26 京东方科技集团股份有限公司 一种移位寄存器及其驱动方法、栅极驱动电路、显示装置
CN110491329A (zh) * 2019-09-25 2019-11-22 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动电路和显示装置
CN111445833A (zh) * 2020-05-09 2020-07-24 合肥京东方卓印科技有限公司 移位寄存器单元及其控制方法、和栅极驱动电路

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20100083370A (ko) * 2009-01-13 2010-07-22 삼성전자주식회사 게이트 구동회로 및 이를 갖는 표시장치
CN103198781B (zh) * 2013-03-01 2015-04-29 合肥京东方光电科技有限公司 移位寄存器单元、栅极驱动装置及显示装置
KR102167138B1 (ko) * 2014-09-05 2020-10-16 엘지디스플레이 주식회사 쉬프트 레지스터 및 그를 이용한 표시 장치
CN104616617B (zh) * 2015-03-09 2017-03-22 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动电路、显示装置
CN104835465B (zh) * 2015-05-14 2018-07-20 昆山龙腾光电有限公司 移位寄存器、栅极驱动电路及液晶显示面板
CN105185294B (zh) * 2015-10-23 2017-11-14 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、移位寄存器和显示装置
CN105304057B (zh) * 2015-12-09 2018-11-30 京东方科技集团股份有限公司 一种移位寄存器及其驱动方法、栅极驱动电路
CN105741802B (zh) * 2016-03-28 2018-01-30 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
CN105957556A (zh) * 2016-05-11 2016-09-21 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路及其驱动方法、显示装置
CN109979396B (zh) * 2018-02-26 2021-12-17 重庆京东方光电科技有限公司 栅极驱动电路、触控显示装置及驱动方法
CN108564914B (zh) * 2018-04-24 2021-08-17 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路和显示装置
CN110264948B (zh) * 2019-06-25 2022-04-01 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路及显示装置

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104299583A (zh) * 2014-09-26 2015-01-21 京东方科技集团股份有限公司 一种移位寄存器及其驱动方法、驱动电路和显示装置
KR20170078978A (ko) * 2015-12-29 2017-07-10 엘지디스플레이 주식회사 게이트 쉬프트 레지스터와 이를 포함한 유기발광 표시장치 및 그 구동방법
CN108520724A (zh) * 2018-04-18 2018-09-11 京东方科技集团股份有限公司 移位寄存器单元及驱动方法、栅极驱动电路和显示装置
CN109935269A (zh) * 2018-05-31 2019-06-25 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
CN108806584A (zh) * 2018-07-27 2018-11-13 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
CN110060645A (zh) * 2019-05-07 2019-07-26 京东方科技集团股份有限公司 一种移位寄存器及其驱动方法、栅极驱动电路、显示装置
CN110491329A (zh) * 2019-09-25 2019-11-22 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动电路和显示装置
CN111445833A (zh) * 2020-05-09 2020-07-24 合肥京东方卓印科技有限公司 移位寄存器单元及其控制方法、和栅极驱动电路

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024108544A1 (zh) * 2022-11-25 2024-05-30 京东方科技集团股份有限公司 驱动电路、驱动方法、显示基板和显示装置

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