WO2024108544A1 - 驱动电路、驱动方法、显示基板和显示装置 - Google Patents

驱动电路、驱动方法、显示基板和显示装置 Download PDF

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Publication number
WO2024108544A1
WO2024108544A1 PCT/CN2022/134332 CN2022134332W WO2024108544A1 WO 2024108544 A1 WO2024108544 A1 WO 2024108544A1 CN 2022134332 W CN2022134332 W CN 2022134332W WO 2024108544 A1 WO2024108544 A1 WO 2024108544A1
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Prior art keywords
transistor
node
electrically connected
control
electrode
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PCT/CN2022/134332
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English (en)
French (fr)
Inventor
赵冬辉
徐攀
韩影
张星
罗程远
吕广爽
姚星
周丹丹
刘苗
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/134332 priority Critical patent/WO2024108544A1/zh
Priority to CN202280004651.0A priority patent/CN118556262A/zh
Publication of WO2024108544A1 publication Critical patent/WO2024108544A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a driving circuit, a driving method, a display substrate and a display device.
  • the transistor used for resetting directly resets the potential of the first node through a turn-off voltage (the turn-off voltage may be, for example, a low voltage) signal. Since the threshold voltage of the transistor (the transistor may be, for example, an oxide transistor) is prone to negative drift, when the transistor used for resetting needs to be turned off, the transistor cannot be completely turned off. At this time, there is a path between the low voltage line and the first node, which may cause leakage and cause the potential of the first node to be pulled down, thereby causing the output of the driving circuit to be abnormal.
  • the turn-off voltage may be, for example, a low voltage
  • an embodiment of the present disclosure provides a driving circuit, including a driving output circuit, a first reset circuit, and a first isolation circuit;
  • the drive output circuit is electrically connected to the first node and the drive signal output terminal respectively, and the drive circuit is also electrically connected to the first voltage line or the first clock signal line, and is used to control the connection between the drive signal output terminal and the first voltage line or the first clock signal line under the control of the potential of the first node;
  • the first reset circuit is electrically connected to the first reset line, the first clock signal line and the first control node respectively, and is used to control the first clock signal line to write the first clock signal to the first control node under the control of the first reset signal provided by the first reset line;
  • the first isolation circuit is electrically connected to the second clock signal line, the first control node and the first node respectively, and is used to control the connection between the first control node and the first node under the control of the second clock signal provided by the second clock signal line.
  • the first reset circuit includes a first transistor
  • a gate of the first transistor is electrically connected to a first reset line, a first electrode of the first transistor is electrically connected to a first clock signal line, and a second electrode of the first transistor is electrically connected to a first control node.
  • the first transistor is an oxide thin film transistor; the first high voltage time and the second high voltage time do not overlap;
  • the first high voltage time is the time during which the potential of the first clock signal is a high voltage
  • the second high voltage time is the time during which the potential of the second clock signal is a high voltage.
  • the driving circuit described in at least one embodiment of the present disclosure further includes a second control node control circuit
  • the second control node control circuit is respectively connected to the first clock signal line, the first voltage line, the second control node, the third node and the second clock signal line, and is used to control the connection between the second control node and the first voltage line under the control of the first clock signal, and to control the connection between the third node and the second clock signal line under the control of the potential of the second control node.
  • the second control node control circuit is further used to control the potential of the second control node according to the potential of the third node.
  • the driving circuit described in at least one embodiment of the present disclosure further includes a cascade output circuit and a cascade reset circuit;
  • the cascade output circuit is electrically connected to the first node, the carry output terminal and the first voltage line respectively, and is used to control the connection between the carry output terminal and the first voltage line under the control of the potential of the first node;
  • the cascade reset circuit is electrically connected to the second node, the carry output terminal and the second voltage line respectively, and is used to control the connection between the carry output terminal and the second voltage line under the control of the potential of the second node.
  • the cascade reset circuit includes a second transistor and a third transistor
  • the gate of the second transistor is electrically connected to the second node, the first electrode of the second transistor is electrically connected to the carry output terminal, and the second electrode of the second transistor is electrically connected to the fourth node;
  • a gate of the third transistor is electrically connected to the second node, a first electrode of the third transistor is electrically connected to the fourth node, and a second electrode of the third transistor is electrically connected to a second voltage line.
  • the driving circuit described in at least one embodiment of the present disclosure further includes a first control circuit
  • the first control circuit is electrically connected to the first node, the third voltage line and the fourth node respectively, and is used to control the connection between the third voltage line and the fourth node under the control of the potential of the first node.
  • the first control circuit includes a fourth transistor
  • a gate of the fourth transistor is electrically connected to the first node, a first electrode of the fourth transistor is electrically connected to the third voltage line, and a second electrode of the fourth transistor is electrically connected to the fourth node.
  • the driving circuit described in at least one embodiment of the present disclosure further includes a driving output reset circuit and a second reset circuit;
  • the output reset circuit is electrically connected to the second node, the drive signal output terminal and the fourth voltage line respectively, and is used to connect the drive signal output terminal to the fourth voltage line under the control of the potential of the second node;
  • the second reset circuit is electrically connected to the first node, the second voltage line and the second node respectively, and is used to control the connection between the second voltage line and the second node under the control of the potential of the first node.
  • the transistor included in the output reset circuit is an oxide transistor, and the voltage value of the second voltage signal provided by the second voltage line is smaller than the voltage value of the first voltage signal provided by the first voltage line.
  • the output reset circuit includes a fifth transistor and a first capacitor, and the second reset circuit includes a sixth transistor;
  • the gate of the fifth transistor is electrically connected to the second node, the first electrode of the fifth transistor is electrically connected to the drive signal output terminal, and the second electrode of the fifth transistor is electrically connected to the fourth voltage line;
  • the first end of the first capacitor is electrically connected to the second node, and the second end of the first capacitor is electrically connected to the fourth voltage line;
  • a gate of the sixth transistor is electrically connected to the first node, a first electrode of the sixth transistor is electrically connected to a second voltage line, and a second electrode of the sixth transistor is electrically connected to the second node.
  • the driving circuit described in at least one embodiment of the present disclosure further includes a second control circuit
  • the second control circuit is electrically connected to the first control node, the second clock signal line, the second voltage line and the second control node, respectively, and is used to control the connection between the first control node and the second voltage line under the control of the potential of the second control node and the second clock signal provided by the second clock signal line.
  • the driving circuit described in at least one embodiment of the present disclosure further includes a third control circuit
  • the third control circuit is electrically connected to the second clock signal line, the input line and the first control node respectively, and is used to control the connection between the input line and the first control node under the control of the second clock signal.
  • the driving circuit described in at least one embodiment of the present disclosure further includes a fourth control circuit
  • the fourth control circuit is electrically connected to the first node, the first control node and the third voltage line respectively, and is used to control the connection between the first control node and the third voltage line under the control of the potential of the first node.
  • the second control node control circuit is also electrically connected to the input line, and is used to control the writing of the first clock signal into the second control node under the control of the input signal provided by the input line.
  • the second control node control circuit includes a seventh transistor and an eighth transistor;
  • the gate of the seventh transistor is electrically connected to the input line, the first electrode of the seventh transistor is electrically connected to the first clock signal line, and the second electrode of the seventh transistor is electrically connected to the first electrode of the eighth transistor;
  • a gate of the eighth transistor is electrically connected to the input line, and a second electrode of the eighth transistor is electrically connected to the second control node.
  • the driving circuit described in at least one embodiment of the present disclosure further includes a third reset circuit
  • the third reset circuit is electrically connected to the second reset line, the third voltage line and the second node respectively, and is used to control the connection between the third voltage line and the second node under the control of the second reset signal provided by the second reset line.
  • the third reset circuit includes a ninth transistor and a tenth transistor
  • the gate of the ninth transistor is electrically connected to the second reset line, the first electrode of the ninth transistor is electrically connected to the third voltage line, and the second electrode of the ninth transistor is electrically connected to the first electrode of the tenth transistor;
  • a gate of the tenth transistor is electrically connected to the second reset line, and a second electrode of the tenth transistor is electrically connected to the second node.
  • the driving circuit described in at least one embodiment of the present disclosure further includes a second isolation circuit
  • the second isolation circuit is electrically connected to the second clock signal line, the third node and the second node respectively, and is used to control the connection between the third node and the second node under the control of the second clock signal provided by the second clock signal line.
  • the third control circuit includes an eleventh transistor
  • the second control circuit includes a twelfth transistor and a thirteenth transistor
  • the fourth control circuit includes a fourteenth transistor
  • the gate of the eleventh transistor is electrically connected to the second clock signal line, the first electrode of the eleventh transistor is electrically connected to the input line, and the second electrode of the eleventh transistor is electrically connected to the first control node;
  • the gate of the fourteenth transistor is electrically connected to the first node, the first electrode of the fourteenth transistor is electrically connected to the third voltage, and the second electrode of the fourteenth transistor is electrically connected to the first control node;
  • the gate of the twelfth transistor is electrically connected to the second clock signal line, the first electrode of the twelfth transistor is electrically connected to the first control node, and the second electrode of the twelfth transistor is electrically connected to the first electrode of the thirteenth transistor; the gate of the thirteenth transistor is electrically connected to the second control node, and the second electrode of the thirteenth transistor is electrically connected to the second voltage line; or, the gate of the twelfth transistor is electrically connected to the second control node, the first electrode of the twelfth transistor is electrically connected to the first control node, and the second electrode of the twelfth transistor is electrically connected to the first electrode of the thirteenth transistor; the gate of the thirteenth transistor is electrically connected to the second clock signal line, and the second electrode of the thirteenth transistor is electrically connected to the second voltage line.
  • the driving output circuit includes a fifteenth transistor and a second capacitor, and the first isolation circuit includes a sixteenth transistor;
  • the gate of the fifteenth transistor is electrically connected to the first node, the first electrode of the fifteenth transistor is electrically connected to the first voltage line or the first clock signal line, and the second electrode of the fifteenth transistor is electrically connected to the driving signal output terminal;
  • a first end of the second capacitor is electrically connected to the first node, and a second end of the second capacitor is electrically connected to the drive signal output terminal;
  • the control electrode of the sixteenth transistor is electrically connected to the second clock signal line, the first electrode of the sixteenth transistor is electrically connected to the first control node, and the second electrode of the sixteenth transistor is electrically connected to the first node.
  • the second control node control circuit includes a seventeenth transistor, a third capacitor and an eighteenth transistor;
  • a gate of the seventeenth transistor is electrically connected to the first clock signal line, a first electrode of the seventeenth transistor is electrically connected to the first voltage line, and a second electrode of the seventeenth transistor is electrically connected to the second control node;
  • the first end of the third capacitor is electrically connected to the second control node, and the second end of the third capacitor is electrically connected to the third node;
  • a gate of the eighteenth transistor is electrically connected to the second control node, a first electrode of the eighteenth transistor is electrically connected to the second clock signal line, and a second electrode of the eighteenth transistor is electrically connected to the third node.
  • the cascade output circuit includes a nineteenth transistor
  • the gate of the nineteenth transistor is electrically connected to the first node, the first electrode of the nineteenth transistor is electrically connected to the first voltage line, and the second electrode of the nineteenth transistor is electrically connected to the cascade output terminal.
  • the cascade output circuit further includes a fourth capacitor
  • a first end of the fourth capacitor is electrically connected to the first node, and a second end of the fourth capacitor is electrically connected to the cascade output end.
  • the second isolation circuit includes a twentieth transistor
  • a gate of the twentieth transistor is electrically connected to the second clock signal line, a first electrode of the twentieth transistor is electrically connected to the third node, and a second electrode of the twentieth transistor is electrically connected to the second node.
  • the driving circuit described in at least one embodiment of the present disclosure further includes a twenty-first transistor
  • a gate of the twenty-first transistor is electrically connected to the first high voltage line, a first electrode of the twenty-first transistor is electrically connected to a second electrode of the sixteenth transistor, and a second electrode of the twenty-first transistor is electrically connected to the first node.
  • an embodiment of the present disclosure further provides a driving method, which is applied to the above-mentioned driving circuit, wherein a display period includes a first stage, a second stage and a third stage which are arranged in sequence, and the driving method includes:
  • the first reset circuit controls the first clock signal line to write the first clock signal to the first control node under the control of the first reset signal provided by the first reset line, and when the second clock signal line provides a high voltage signal, the first isolation circuit controls the first control node to be connected to the first node under the control of the second clock signal provided by the second clock signal line;
  • the first isolation circuit controls the first control node to be connected to the first node under the control of the second clock signal;
  • the drive output circuit controls the drive signal output terminal to be connected to the first voltage line under the control of the potential of the first node;
  • the first isolation circuit controls the first control node to be connected to the first node under the control of the second clock signal.
  • an embodiment of the present disclosure provides a display substrate, comprising the above-mentioned driving circuit.
  • the display substrate described in at least one embodiment of the present disclosure further includes a plurality of columns of DC signal lines; the display substrate includes a display area and a peripheral area, and the DC signal lines and the driving circuit are arranged in the peripheral area;
  • At least one column of the multiple columns of DC signal lines is arranged on a side of the drive circuit away from the display area, and the DC signal lines other than the at least one column of DC signal lines are arranged on a side of the drive circuit close to the display area.
  • an embodiment of the present disclosure provides a display device, comprising the above-mentioned display substrate.
  • FIG1 is a structural diagram of a driving circuit according to an embodiment of the present disclosure.
  • FIG2 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG3 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG4 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG5 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG6 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG7 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG8 is a timing diagram of operation of at least one embodiment of the driving circuit shown in FIG7 ;
  • FIG9 is a simulation operation timing diagram of at least one embodiment of the driving circuit shown in FIG7 when the threshold voltage of the oxide transistor is 4V;
  • FIG. 10 is a simulation operation timing diagram of at least one embodiment of the driving circuit shown in FIG. 7 when the threshold voltage of the oxide transistor is -2.5V;
  • FIG11 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG12 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG13 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG14 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG15 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG16 is a timing diagram of operation of at least one embodiment of the driving circuit shown in FIG15 ;
  • FIG17 is a simulation operation timing diagram of at least one embodiment of the driving circuit shown in FIG15;
  • FIG18 is a layout diagram of at least one embodiment of the driving circuit shown in FIG13;
  • FIG. 19A is an enlarged view of a portion of FIG. 18 ;
  • FIG19B is an enlarged view of a portion of FIG18;
  • FIG20 is a layout diagram of the semiconductor layer in FIG18.
  • FIG21 is a layout of the gate metal layer in FIG18.
  • FIG. 22 is a layout diagram of the source/drain metal layer in FIG. 18 .
  • the transistors used in all embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics.
  • one of the electrodes is called the first electrode and the other is called the second electrode.
  • the first electrode when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.
  • the driving circuit described in the embodiment of the present disclosure includes a driving output circuit, a first reset circuit and a first isolation circuit;
  • the drive output circuit is electrically connected to the first node and the drive signal output terminal respectively, and the drive circuit is also electrically connected to the first voltage line or the first clock signal line, and is used to control the connection between the drive signal output terminal and the first voltage line or the first clock signal line under the control of the potential of the first node;
  • the first reset circuit is electrically connected to the first reset line, the first clock signal line and the first control node respectively, and is used to control the first clock signal line to write the first clock signal to the first control node under the control of the first reset signal provided by the first reset line;
  • the first isolation circuit is electrically connected to the second clock signal line, the first control node and the first node respectively, and is used to control the connection between the first control node and the first node under the control of the second clock signal provided by the second clock signal line.
  • the driving circuit described in the embodiment of the present disclosure is provided with a first reset circuit and a first isolation circuit.
  • the first reset circuit under the control of a reset signal, controls the writing of a first clock signal into a first control node.
  • the first isolation circuit under the control of a second clock signal, controls the connection between the first control node and the first node.
  • the potential of the first control node is reset by the first clock signal.
  • the first isolation circuit under the control of the second clock signal, controls the connection between the first control node and the first node, thereby resetting the potential of the first node. Since the first clock signal is a periodic signal, the low voltage time is short and the leakage current is small.
  • the first reset line may be a reset line RST, but is not limited thereto.
  • the driving circuit described in the embodiment of the present disclosure includes a driving output circuit 11 , a first reset circuit 12 and a first isolation circuit 13 ;
  • the drive output circuit 11 is electrically connected to the first node Q, the drive signal output terminal O1 and the first voltage line V1 respectively, and is used to control the connection between the drive signal output terminal O1 and the first voltage line V1 under the control of the potential of the first node Q;
  • the first reset circuit 12 is electrically connected to the reset line RST, the first clock signal line CKB and the first control node PQ respectively, and is used to control the first clock signal line CKB to write the first clock signal to the first control node PQ under the control of the reset signal provided by the reset line RST;
  • the first isolation circuit 13 is electrically connected to the second clock signal line CKA, the first control node PQ and the first node Q respectively, and is used to control the connection between the first control node PQ and the first node Q under the control of the second clock signal provided by the second clock signal line CKA.
  • the driving circuit may be an oxide internal compensation PWM (pulse width modulation) circuit.
  • the driving circuit may use an oxide transistor, but is not limited thereto.
  • the driving circuit described in the embodiment of the present disclosure is provided with a first reset circuit 12 and a first isolation circuit 13.
  • the first reset circuit 12 controls the writing of the first clock signal into the first control node PQ under the control of the reset signal.
  • the first isolation circuit 13 controls the connection between the first control node PQ and the first node Q under the control of the second clock signal.
  • the potential of the first control node PQ is reset by the first clock signal.
  • the first isolation circuit 13 controls the connection between the first control node PQ and the first node Q under the control of the second clock signal, thereby resetting the potential of the first node Q. Since the first clock signal is a periodic signal, the low voltage time is short and the leakage current is small.
  • a transistor for resetting directly resets the potential of a first node through a low voltage signal. Since the threshold voltage of an oxide transistor is prone to negative drift, when the transistor for resetting needs to be turned off, the transistor cannot be completely turned off. At this time, there is a path between the low voltage line and the first node, which will cause leakage and cause the potential of the first node to be pulled down. Based on this, an embodiment of the present disclosure resets the potential of a first control node through a first clock signal, and controls the connection between the first control node and the first node under the control of a second clock signal through a first isolation circuit to reset the potential of the first node.
  • the first reset circuit includes a first transistor
  • a gate of the first transistor is electrically connected to a first reset line, a first electrode of the first transistor is electrically connected to a first clock signal line, and a second electrode of the first transistor is electrically connected to a first control node.
  • the first transistor is an oxide thin film transistor; the first high voltage time and the second high voltage time do not overlap;
  • the first high voltage time is the time during which the potential of the first clock signal is a high voltage
  • the second high voltage time is the time during which the potential of the second clock signal is a high voltage.
  • the driving circuit may further include a second control node control circuit
  • the second control node control circuit is respectively connected to the first clock signal line, the first voltage line, the second control node, the third node and the second clock signal line, and is used to control the connection between the second control node and the first voltage line under the control of the first clock signal, and to control the connection between the third node and the second clock signal line under the control of the potential of the second control node, and to control the potential of the second control node according to the potential of the third node.
  • the driving circuit may further include a second control node control circuit, which controls the potential of the second control node according to the second clock signal under the control of the first clock signal.
  • the driving circuit may further include a second control node control circuit 21 ;
  • the second control node control circuit 21 is electrically connected to the first clock signal line CKB, the first voltage line V1, the second control node PQB, the third node N3 and the second clock signal line CKA, respectively, and is used to control the connection between the second control node PQB and the first voltage line V1 under the control of the first clock signal, and to control the connection between the third node N3 and the second clock signal line CKA under the control of the potential of the second control node PQB.
  • the second control node control circuit 21 may control the potential of the second control node PQB according to the potential of the third node N3.
  • the second control node control circuit 21 may include a capacitor, a first end of the capacitor is electrically connected to the third node N3, and a second end of the capacitor is electrically connected to the second clock signal line CKA, so as to control the potential of the second control node PQB according to the potential of the third node N3.
  • the first voltage line may be a first high voltage line, but is not limited thereto.
  • the driving circuit described in at least one embodiment of the present disclosure further includes a cascade output circuit and a cascade reset circuit (T12 and T13);
  • the cascade output circuit is electrically connected to the first node, the carry output terminal and the first voltage line respectively, and is used to control the connection between the carry output terminal and the first voltage line under the control of the potential of the first node;
  • the cascade reset circuit is electrically connected to the second node, the carry output terminal and the second voltage line respectively, and is used to control the connection between the carry output terminal and the second voltage line under the control of the potential of the second node.
  • the driving circuit further includes a cascade output circuit and a cascade reset circuit, which notify the carry output terminal to output a carry signal through the cascade output circuit and the cascade reset circuit.
  • the carry signal is used for cascading to enhance the driving capability of the driving circuit.
  • the driving circuit according to at least one embodiment of the present disclosure further includes a cascade output circuit 31 and a cascade reset circuit 32;
  • the cascade output circuit 31 is electrically connected to the first node Q, the carry output terminal CR and the first voltage line V1 respectively, and is used to control the connection between the carry output terminal C4 and the first voltage line V1 under the control of the potential of the first node Q;
  • the cascade reset circuit 32 is electrically connected to the second node QB, the carry output terminal CR and the second voltage line V2 respectively, and is used to control the connection between the carry output terminal CR and the second voltage line V2 under the control of the potential of the second node QB.
  • the first voltage line V1 may be a first high voltage line
  • the second voltage line V2 may be a second low voltage line, but the present invention is not limited thereto.
  • the cascade reset circuit includes a second transistor and a third transistor
  • the gate of the second transistor is electrically connected to the second node, the first electrode of the second transistor is electrically connected to the carry output terminal, and the second electrode of the second transistor is electrically connected to the fourth node;
  • a gate of the third transistor is electrically connected to the second node, a first electrode of the third transistor is electrically connected to the fourth node, and a second electrode of the third transistor is electrically connected to a second voltage line.
  • the driving circuit described in at least one embodiment of the present disclosure further includes a first control circuit
  • the first control circuit is electrically connected to the first node, the third voltage line and the fourth node respectively, and is used to control the connection between the third voltage line and the fourth node under the control of the potential of the first node.
  • the third voltage line may be a second high voltage line, but is not limited thereto.
  • the driving circuit described in at least one embodiment of the present disclosure may also include a first control circuit, which controls the connection between the fourth node and the third voltage line under the control of the potential of the first node to prevent the potential of the carry signal provided by the carry output terminal from being reduced due to leakage.
  • the driving circuit according to at least one embodiment of the present disclosure further includes a first control circuit 41 ;
  • the first control circuit 41 is electrically connected to the first node Q, the third voltage line V3 and the fourth node N4 respectively, and is used to control the connection between the third voltage line V3 and the fourth node N4 under the control of the potential of the first node Q;
  • the cascade reset circuit 32 is electrically connected to the fourth node N4.
  • the first control circuit includes a fourth transistor
  • a gate of the fourth transistor is electrically connected to the first node, a first electrode of the fourth transistor is electrically connected to the third voltage line, and a second electrode of the fourth transistor is electrically connected to the fourth node.
  • the driving circuit further includes a driving output reset circuit 51 and a second reset circuit 52;
  • the output reset circuit 51 is electrically connected to the second node QB, the drive signal output terminal O1 and the fourth voltage line V4 respectively, and is used to connect the drive signal output terminal O1 and the fourth voltage line V4 under the control of the potential of the second node QB;
  • the second reset circuit 52 is electrically connected to the first node Q, the second voltage line V2 and the second node QB respectively, and is used to control the connection between the second voltage line V2 and the second node QB under the control of the potential of the first node Q.
  • the fourth voltage line may be a first low voltage line, and the second voltage line may be a second low voltage line, but the present invention is not limited thereto.
  • the second reset circuit 52 controls the connection between the second node QB and the second voltage line V2 under the control of the potential of the first node Q
  • the output reset circuit 51 controls the connection between the driving signal output terminal O1 and the fourth voltage line V4 under the control of the potential of the second node QB.
  • the transistor included in the output reset circuit is an oxide transistor, and the voltage value of the second voltage signal provided by the second voltage line is less than the voltage value of the first voltage signal provided by the first voltage line, so as to avoid output leakage when the threshold voltage of the transistor included in the output reset circuit drifts negatively.
  • the output reset circuit includes a fifth transistor and a first capacitor, and the second reset circuit includes a sixth transistor;
  • the gate of the fifth transistor is electrically connected to the second node, the first electrode of the fifth transistor is electrically connected to the drive signal output terminal, and the second electrode of the fifth transistor is electrically connected to the fourth voltage line;
  • the first end of the first capacitor is electrically connected to the second node, and the second end of the first capacitor is electrically connected to the fourth voltage line;
  • a gate of the sixth transistor is electrically connected to the first node, a first electrode of the sixth transistor is electrically connected to a second voltage line, and a second electrode of the sixth transistor is electrically connected to the second node.
  • the driving circuit described in at least one embodiment of the present disclosure may further include a second control circuit
  • the second control circuit is electrically connected to the first control node, the second clock signal line, the second voltage line and the second control node, respectively, and is used to control the connection between the first control node and the second voltage line under the control of the potential of the second control node and the second clock signal provided by the second clock signal line.
  • the driving circuit may include a second control circuit, which controls the connection between the first control node and the second voltage line under the control of the potential of the second control node and the second clock signal provided by the second clock signal line.
  • the driving circuit described in at least one embodiment of the present disclosure may further include a third control circuit
  • the third control circuit is electrically connected to the second clock signal line, the input line and the first control node respectively, and is used to control the connection between the input line and the first control node under the control of the second clock signal.
  • the driving circuit may include a third control circuit, and the third control circuit controls the input line to be connected to the first control node under the control of the second clock signal.
  • the driving circuit described in at least one embodiment of the present disclosure may further include a fourth control circuit
  • the fourth control circuit is electrically connected to the first node, the first control node and the third voltage line respectively, and is used to control the connection between the first control node and the third voltage line under the control of the potential of the first node.
  • the driving circuit may include a fourth control circuit; the fourth control circuit controls the connection between the first control node and the third voltage line under the control of the potential of the first node.
  • the second control node control circuit is also electrically connected to the input line, and is used to control the writing of the first clock signal into the second control node under the control of the input signal provided by the input line.
  • the second control node control circuit may write the first clock signal into the second control node under the control of the input signal.
  • the second control node control circuit includes a seventh transistor and an eighth transistor;
  • the gate of the seventh transistor is electrically connected to the input line, the first electrode of the seventh transistor is electrically connected to the first clock signal line, and the second electrode of the seventh transistor is electrically connected to the first electrode of the eighth transistor;
  • a gate of the eighth transistor is electrically connected to the input line, and a second electrode of the eighth transistor is electrically connected to the second control node.
  • the driving circuit described in at least one embodiment of the present disclosure further includes a third reset circuit
  • the third reset circuit is electrically connected to the second reset line, the third voltage line and the second node respectively, and is used to control the connection between the third voltage line and the second node under the control of the second reset signal provided by the second reset line.
  • the first reset line and the second reset line may be the same, or the first reset line and the second reset line may be different.
  • the second reset line may be a reset line RST, but is not limited thereto.
  • the third voltage line may be a second high voltage line, but is not limited thereto.
  • the driving circuit described in at least one embodiment of the present disclosure may further include a third reset circuit. Under the control of a reset signal, the third reset circuit controls the connection between the second node and the third voltage line to reset the potential of the second node.
  • the third reset circuit includes a ninth transistor and a tenth transistor
  • the gate of the ninth transistor is electrically connected to the second reset line, the first electrode of the ninth transistor is electrically connected to the third voltage line, and the second electrode of the ninth transistor is electrically connected to the first electrode of the tenth transistor;
  • a gate of the tenth transistor is electrically connected to the second reset line, and a second electrode of the tenth transistor is electrically connected to the second node.
  • the driving circuit described in at least one embodiment of the present disclosure further includes a second isolation circuit
  • the second isolation circuit is electrically connected to the second clock signal line, the third node and the second node respectively, and is used to control the connection between the third node and the second node under the control of the second clock signal provided by the second clock signal line.
  • the driving circuit may further include a second isolation circuit, and the second isolation circuit controls the connection between the third node and the second node under the control of the second clock signal.
  • the driving circuit described in at least one embodiment of the present disclosure further includes a second control circuit 602 , a third control circuit 603 , a fourth control circuit 604 , a third reset circuit 61 and a second isolation circuit 62 ;
  • the second control circuit 602 is electrically connected to the first control node PQ, the second clock signal line CKA, the second voltage line V2 and the second control node PQB, respectively, and is used to control the connection between the first control node PQ and the second voltage line V2 under the control of the potential of the second control node PQB and the second clock signal provided by the second clock signal line CKA;
  • the third control circuit 603 is electrically connected to the second clock signal line CKA, the input line STU and the first control node PQ respectively, and is used to control the input line STU to be connected to the first control node PQ under the control of the second clock signal CKA;
  • the fourth control circuit 604 is electrically connected to the first node Q, the first control node PQ and the third voltage line V3 respectively, and is used to control the connection between the first control node PQ and the third voltage line V3 under the control of the potential of the first node Q;
  • the second control node control circuit 21 is also electrically connected to the input line STU and the first clock signal line CKB respectively, and is used to control the first clock signal provided by the first clock signal line CKB to be written into the second control node PQB under the control of the input signal provided by the input line STU;
  • the third reset circuit 61 is electrically connected to the reset line RST, the third voltage line V3 and the second node QB respectively, and is used to control the connection between the third voltage line V3 and the second node QB under the control of the reset signal provided by the reset line RST;
  • the second isolation circuit 62 is electrically connected to the second clock signal line CKA, the third node N3 and the second node QB respectively, and is used to control the connection between the third node N3 and the second node QB under the control of the second clock signal provided by the second clock signal line CKA.
  • the third control circuit includes an eleventh transistor
  • the second control circuit includes a twelfth transistor and a thirteenth transistor
  • the fourth control circuit includes a fourteenth transistor
  • the gate of the eleventh transistor is electrically connected to the second clock signal line, the first electrode of the eleventh transistor is electrically connected to the input line, and the second electrode of the eleventh transistor is electrically connected to the first control node;
  • the gate of the fourteenth transistor is electrically connected to the first node, the first electrode of the fourteenth transistor is electrically connected to the third voltage line, and the second electrode of the fourteenth transistor is electrically connected to the first control node;
  • the gate of the twelfth transistor is electrically connected to the second clock signal line, the first electrode of the twelfth transistor is electrically connected to the first control node, and the second electrode of the twelfth transistor is electrically connected to the first electrode of the thirteenth transistor; the gate of the thirteenth transistor is electrically connected to the second control node, and the second electrode of the thirteenth transistor is electrically connected to the second voltage line; or, the gate of the twelfth transistor is electrically connected to the second control node, the first electrode of the twelfth transistor is electrically connected to the first control node, and the second electrode of the twelfth transistor is electrically connected to the first electrode of the thirteenth transistor; the gate of the thirteenth transistor is electrically connected to the second clock signal line, and the second electrode of the thirteenth transistor is electrically connected to the second voltage line.
  • the driving output circuit includes a fifteenth transistor and a second capacitor, and the first isolation circuit includes a sixteenth transistor;
  • the gate of the fifteenth transistor is electrically connected to the first node, the first electrode of the fifteenth transistor is electrically connected to the first voltage line, and the second electrode of the fifteenth transistor is electrically connected to the driving signal output terminal;
  • a first end of the second capacitor is electrically connected to the first node, and a second end of the second capacitor is electrically connected to the drive signal output terminal;
  • the control electrode of the sixteenth transistor is electrically connected to the second clock signal line, the first electrode of the sixteenth transistor is electrically connected to the first control node, and the second electrode of the sixteenth transistor is electrically connected to the first node.
  • the second control node control circuit includes a seventeenth transistor, a third capacitor and an eighteenth transistor;
  • the gate of the seventeenth transistor is electrically connected to the first clock signal line, the first electrode of the seventeenth transistor is electrically connected to the first voltage line, and the second electrode of the seventeenth transistor is electrically connected to the second control node;
  • the first end of the third capacitor is electrically connected to the second control node, and the second end of the third capacitor is electrically connected to the third node;
  • a gate of the eighteenth transistor is electrically connected to the second control node, a first electrode of the eighteenth transistor is electrically connected to the second clock signal line, and a second electrode of the eighteenth transistor is electrically connected to the third node.
  • the cascade output circuit includes a nineteenth transistor
  • the gate of the nineteenth transistor is electrically connected to the first node, the first electrode of the nineteenth transistor is electrically connected to the first voltage line, and the second electrode of the nineteenth transistor is electrically connected to the cascade output terminal.
  • the cascade output circuit further includes a fourth capacitor
  • the first end of the fourth capacitor is electrically connected to the first node, and the second end of the fourth capacitor is electrically connected to the cascade output end.
  • the second isolation circuit includes a twentieth transistor
  • a gate of the twentieth transistor is electrically connected to the second clock signal line, a first electrode of the twentieth transistor is electrically connected to the third node, and a second electrode of the twentieth transistor is electrically connected to the second node.
  • the first reset circuit 12 includes a first transistor T1;
  • the gate of the first transistor T1 is electrically connected to the reset line RST, the source of the first transistor T1 is electrically connected to the first clock signal line CKB, and the drain of the first transistor T1 is electrically connected to the first control node PQ;
  • the cascade reset circuit 32 includes a second transistor T2 and a third transistor T3;
  • the gate of the second transistor T2 is electrically connected to the second node QB, the source of the second transistor T2 is electrically connected to the carry output terminal CR, and the drain of the second transistor T2 is electrically connected to the fourth node N4;
  • the gate of the third transistor T3 is electrically connected to the second node QB, the source of the third transistor T3 is electrically connected to the fourth node N4, and the drain of the third transistor T3 is electrically connected to the second low voltage line VGL2;
  • the first control circuit 41 includes a fourth transistor T4;
  • the gate of the fourth transistor T4 is electrically connected to the first node Q, the source of the fourth transistor T4 is electrically connected to the second high voltage line VGH2, and the drain of the fourth transistor T4 is electrically connected to the fourth node N4;
  • the output reset circuit 51 includes a fifth transistor T5 and a first capacitor C1, and the second reset circuit 52 includes a sixth transistor T6;
  • the gate of the fifth transistor T5 is electrically connected to the second node QB, the source of the fifth transistor T5 is electrically connected to the driving signal output terminal O1, and the drain of the fifth transistor T5 is electrically connected to the first low voltage line VGL;
  • a first end of the first capacitor C1 is electrically connected to the second node QB, and a second end of the first capacitor C1 is electrically connected to the first low voltage line VGL;
  • the gate of the sixth transistor T6 is electrically connected to the first node Q, the source of the sixth transistor T6 is electrically connected to the second low voltage line VGL2, and the drain of the sixth transistor T6 is electrically connected to the second node QB;
  • the second control node control circuit 21 includes a seventh transistor T7 and an eighth transistor T8;
  • the gate of the seventh transistor T7 is electrically connected to the input line STU, the source of the seventh transistor T7 is electrically connected to the first clock signal line CKB, and the drain of the seventh transistor T7 is electrically connected to the source of the eighth transistor T8;
  • the gate of the eighth transistor T8 is electrically connected to the input line STU, and the drain of the eighth transistor T8 is electrically connected to the second control node PQB;
  • the third reset circuit 61 includes a ninth transistor T9 and a tenth transistor T10;
  • the gate of the ninth transistor T9 is electrically connected to the reset line RST, the source of the ninth transistor T9 is electrically connected to the second high voltage line VGH2, and the drain of the ninth transistor T9 is electrically connected to the source of the tenth transistor T10;
  • a gate of the tenth transistor T10 is electrically connected to the reset line RST, and a drain of the tenth transistor T10 is electrically connected to the second node QB;
  • the third control circuit 603 includes an eleventh transistor T11, the second control circuit 602 includes a twelfth transistor T12 and a thirteenth transistor T13, and the fourth control circuit 604 includes a fourteenth transistor T14;
  • the gate of the eleventh transistor T11 is electrically connected to the second clock signal line CKA, the source of the eleventh transistor T11 is electrically connected to the input line STU, and the drain of the eleventh transistor T11 is electrically connected to the first control node PQ;
  • the gate of the fourteenth transistor T14 is electrically connected to the first node Q, the source of the fourteenth transistor T14 is electrically connected to the second high voltage line VGH2, and the drain of the fourteenth transistor T14 is electrically connected to the first control node PQ;
  • the gate of the twelfth transistor T12 is electrically connected to the second clock signal line CKA, the source of the twelfth transistor T12 is electrically connected to the first control node PQ, and the drain of the twelfth transistor T12 is electrically connected to the source of the thirteenth transistor T13;
  • the gate of the thirteenth transistor T13 is electrically connected to the second control node PQB, and the drain of the thirteenth transistor T13 is electrically connected to the second low voltage line VGL2;
  • the driving output circuit 11 includes a fifteenth transistor T15 and a second capacitor C2, and the first isolation circuit 13 includes a sixteenth transistor T16;
  • the gate of the fifteenth transistor T15 is electrically connected to the first node Q, the source of the fifteenth transistor T15 is electrically connected to the first high voltage line VGH, and the drain of the fifteenth transistor T15 is electrically connected to the driving signal output terminal O1;
  • a first end of the second capacitor C2 is electrically connected to the first node Q, and a second end of the second capacitor C2 is electrically connected to the drive signal output terminal O1;
  • the gate of the sixteenth transistor T16 is electrically connected to the second clock signal line CKA, the source of the sixteenth transistor T16 is electrically connected to the first control node PQ, and the drain of the sixteenth transistor is electrically connected to the first node Q;
  • the second control node control circuit 21 further includes a seventeenth transistor T17, a third capacitor C3 and an eighteenth transistor T18;
  • the gate of the seventeenth transistor T17 is electrically connected to the first clock signal line CKB, the source of the seventeenth transistor T17 is electrically connected to the first high voltage line VGH, and the drain of the seventeenth transistor T17 is electrically connected to the second control node PQB;
  • a first end of the third capacitor C3 is electrically connected to the second control node PQB, and a second end of the third capacitor C3 is electrically connected to the third node N3;
  • the gate of the eighteenth transistor T18 is electrically connected to the second control node PQB, the source of the eighteenth transistor T18 is electrically connected to the second clock signal line CKA, and the drain of the eighteenth transistor T18 is electrically connected to the third node N3;
  • the cascade output circuit 31 includes a nineteenth transistor T19;
  • the gate of the nineteenth transistor T19 is electrically connected to the first node Q, the source of the nineteenth transistor T19 is electrically connected to the first high voltage line VGH, and the drain of the nineteenth transistor T19 is electrically connected to the cascade output terminal CR;
  • the cascade output circuit 31 further includes a fourth capacitor C4;
  • a first end of the fourth capacitor C4 is electrically connected to the first node Q, and a second end of the fourth capacitor C4 is electrically connected to the cascade output terminal CR;
  • the second isolation circuit 62 includes a twentieth transistor T20;
  • a gate of the twentieth transistor T20 is electrically connected to the second clock signal line CKA, a source of the twentieth transistor T20 is electrically connected to the third node N3, and a drain of the twentieth transistor T20 is electrically connected to the second node QB.
  • all transistors are n-type transistors, and all transistors are oxide transistors, but the present invention is not limited thereto.
  • C4 is provided to increase the anti-interference capability.
  • the second control node control circuit includes a seventh transistor T7 , an eighth transistor T8 , a seventeenth transistor T17 , a third capacitor C3 , and an eighteenth transistor T18 ;
  • the drain of T17 is electrically connected to the gate of T13 included in the second control circuit, and the drain of T18 is electrically connected to T20;
  • the drain of T18 is electrically connected to the second node QB through T20 , and the drain of T18 is electrically connected to the gate of T2 , the gate of T3 , and the electrode of T5 .
  • the transistor included in the driving circuit is an n-type transistor, but the present invention is not limited thereto; in a specific implementation, the transistor included in the driving circuit may also be a p-type transistor.
  • the driving cycle includes a first stage S1 , a second stage S2 , and a third stage S3 which are arranged successively;
  • RST provides a high voltage signal
  • T1 is turned on, and for PQ, when CKB outputs a high voltage signal, the potential of PQ is pulled high, but since the potential of the second clock signal provided by CKA is a low voltage, T16 is turned off, so the potential of the first node Q will not be pulled high;
  • T16 is turned on, and at this time, the potentials of PQ and Q are both pulled low, so that the potential of the first node Q is reset, and the potential of PQ changes periodically with the potential of the first clock signal provided by CKB, the low voltage time is short, and the leakage is small.
  • the potential of PQ is reset by T1 to further reduce the risk of leakage;
  • RST provides a high voltage signal
  • T9 and T10 are turned on
  • QB is connected to VGH2
  • VGH2 since VGH2 keeps outputting the second high voltage signal for a long time, there is no need to worry about leakage.
  • CKB outputs a high voltage
  • T17 is turned on
  • the potential of PQB is a high voltage. Due to the existence of C3, the potential of PQB can be kept at a high voltage.
  • CKA outputs a high voltage signal
  • the potential of PQB will be further raised due to bootstrapping, and will change periodically with the change of the potential of the second clock signal provided by CKA.
  • STU provides a high voltage signal
  • RST provides a low voltage signal
  • CKA provides a high voltage signal
  • T11, T16, T15 and T19 are turned on
  • the potential of PQ and the potential of Q are high voltage
  • CR and O1 both output high voltage signals
  • T7 and T8 are turned on
  • the potential of PQB changes with the potential change of the first clock signal provided by CKB
  • T6 is turned on
  • QB is connected to VGL2;
  • STU provides a low voltage signal.
  • CKA outputs a high voltage signal
  • T11 is turned on
  • PQ is connected to STU
  • the potential of PQ is a low voltage
  • T16 is turned on
  • PQ is connected to Q, so that the potential of the first node Q is a low voltage.
  • CKA outputs a high voltage signal
  • the potential of PQB is bootstrapped and pulled up, and at the same time T20 is turned on, the potential of QB is a high voltage to turn on T5 and T2, CR outputs a second low voltage signal, and O1 outputs a low voltage signal.
  • At least one embodiment of the driving circuit shown in FIG. 7 may output a driving signal through its driving signal output terminal as a compensation control signal.
  • the potential of the first low voltage signal output by VGL may be -6V, and the potential of the second low voltage signal output by VGL2 may be -8V. Then, when O1 outputs a high voltage signal, the gate-source voltage of T11 is -2V, thereby avoiding output leakage when the threshold voltage of T11 drifts negatively.
  • the duty cycle of the first clock signal provided by CKA and the duty cycle of the second clock signal provided by CKB may be 25%, and the phase of the second clock signal may be half a cycle apart from the phase of the first clock signal, but is not limited thereto.
  • FIG9 is a simulation operation timing diagram of at least one embodiment of the driving circuit shown in FIG7 when the threshold voltage of the oxide transistor is 4V;
  • FIG. 10 is a simulation operation timing diagram of at least one embodiment of the driving circuit shown in FIG. 7 when the threshold voltage of the oxide transistor is ⁇ 2.5V.
  • At least one embodiment of the driving circuit shown in FIG. 7 can operate normally.
  • the difference between at least one embodiment of the driving circuit shown in FIG. 11 and at least one embodiment of the driving circuit shown in FIG. 7 is that the gate of T12 is electrically connected to PQB, and the gate of T13 is electrically connected to the second clock signal line CKB.
  • the difference between at least one embodiment of the driving circuit shown in FIG13 and at least one embodiment of the driving circuit shown in FIG7 is that T7 and T9 are not provided.
  • the difference between at least one embodiment of the driving circuit shown in FIG. 14 and at least one embodiment of the driving circuit shown in FIG. 7 is that: it further includes a twenty-first transistor T21;
  • the gate of the 21st transistor T21 is electrically connected to the first high voltage line VGH, the source of the 21st transistor T21 is electrically connected to the drain of T16, and the drain of the 21st transistor T21 is electrically connected to the first node Q;
  • the twenty-first transistor T2 is a normally-on transistor.
  • the difference between at least one embodiment of the driving circuit shown in FIG. 15 and at least one embodiment of the driving circuit shown in FIG. 7 is that the source of T15 is electrically connected to the first clock signal line CKB.
  • Fig. 16 is a timing diagram of operation of at least one embodiment of the driving circuit shown in Fig. 15.
  • Fig. 17 is a timing diagram of simulation operation of at least one embodiment of the driving circuit shown in Fig. 15.
  • At least one embodiment of the driving circuit shown in FIG. 15 can provide a gate driving signal for a pixel unit, but the present invention is not limited thereto.
  • the driving output circuit may include at least two transistors for output.
  • the driving output circuit may also include at least one output transistor, the source of the output transistor is electrically connected to the corresponding output clock signal terminal, and the drain of the output transistor is electrically connected to the corresponding driving signal output terminal.
  • the driving circuit described in at least one embodiment of the present disclosure may include at least two driving signal output terminals, and corresponding gate driving signals can be output to the at least two driving signal output terminals.
  • the at least two driving signal output terminals respectively provide corresponding gate driving signals for at least two rows of pixel units.
  • the driving method described in the embodiment of the present disclosure is applied to the above-mentioned driving circuit, and the display period includes a first stage, a second stage and a third stage which are arranged in sequence.
  • the driving method includes:
  • the first reset circuit controls the first clock signal line to write the first clock signal to the first control node under the control of the first reset signal provided by the first reset line, and when the second clock signal line provides a high voltage signal, the first isolation circuit controls the first control node to be connected to the first node under the control of the second clock signal provided by the second clock signal line;
  • the first isolation circuit controls the first control node to be connected to the first node under the control of the second clock signal;
  • the drive output circuit controls the drive signal output terminal to be connected to the first voltage line under the control of the potential of the first node;
  • the first isolation circuit controls the first control node to be connected to the first node under the control of the second clock signal.
  • the display substrate described in at least one embodiment of the present disclosure includes the above-mentioned driving circuit.
  • the display substrate further includes a plurality of columns of DC signal lines; the display substrate includes a display area and a peripheral area, and the DC signal lines and the driving circuit are arranged in the peripheral area;
  • At least one column of the multiple columns of DC signal lines is arranged on a side of the drive circuit away from the display area, and the DC signal lines other than the at least one column of DC signal lines are arranged on a side of the drive circuit close to the display area.
  • Fig. 18 is a layout diagram of at least one embodiment of the driving circuit shown in Fig. 13.
  • Fig. 19A and Fig. 19B are enlarged views of a portion of Fig. 18.
  • Fig. 20 is a layout diagram of the semiconductor layer in Fig. 18,
  • Fig. 21 is a layout diagram of the gate metal layer in Fig. 18, and
  • Fig. 22 is a layout diagram of the source-drain metal layer in Fig. 18.
  • CKA, CKB, STU, RST, VGH, and VGH2 extend in the vertical direction, and VGL1 and VGL2 extend in the vertical direction;
  • CKA, CKB, STU, RST, VGH and VGH2 are arranged on a side of the driving circuit away from the display area, and VGL1 and VGL2 are arranged on a side of the driving circuit close to the display area.
  • the plate of the fourth capacitor C4 extends in the vertical direction, and the area of the plate of the fourth capacitor C4 is larger than the area of the plate of the first capacitor C1, the area of the plate of the fourth capacitor C4 is larger than the area of the plate of C2, and the area of the plate of the fourth capacitor C4 is larger than the area of the plate of C3.
  • the display device described in the embodiment of the present disclosure includes the above-mentioned display substrate.
  • the display device provided in the embodiments of the present disclosure may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or the like.

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Abstract

提供了一种驱动电路、驱动方法、显示基板和显示装置。驱动电路，包括驱动输出电路(11)、第一复位电路(12)和第一隔离电路(13)；驱动输出电路(11)在第一节点(Q)的电位的控制下，控制驱动信号输出端(O1)与第一电压线(V1)或第一时钟信号线(CKB)之间连通；第一复位电路(12)在第一复位信号的控制下，控制第一时钟信号线(CKB)写入第一时钟信号至第一控制节点(PQ)；第一隔离电路(13)在第二时钟信号的控制下，控制第一控制节点(PQ)与第一节点(Q)之间连通。设置第一复位电路(12)和第一隔离电路(13)，通过第一时钟信号对第一控制节点(Q)的电位进行复位，再通过第一隔离电路(12)在第二时钟信号的控制下，控制第一控制节点(PQ)与第一节点(Q)连通，对第一节点(Q)的电位进行复位，由于第一时钟信号是周期性的信号，低压时间较短，漏电较小。

Description

驱动电路、驱动方法、显示基板和显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种驱动电路、驱动方法、显示基板和显示装置。
背景技术
在相关技术中，在驱动电路中，用于复位的晶体管通过关断电压(所述关断电压例如可以为低电压)信号直接对第一节点的电位进行复位，由于晶体管(所述晶体管例如可以为氧化物晶体管)的阈值电压容易负漂而导致在用于复位的晶体管需要关断时，该晶体管不能完全关断，此时在低电压线与第一节点之间有一条通路，会造成漏电而导致第一节点的电位被拉低，从而会使得驱动电路输出异常。
发明内容
在一个方面中，本公开实施例提供一种驱动电路，包括驱动输出电路、第一复位电路和第一隔离电路；
所述驱动输出电路分别与第一节点和驱动信号输出端电连接，所述驱动电路还和第一电压线或第一时钟信号线电连接，用于在所述第一节点的电位的控制下，控制所述驱动信号输出端与所述第一电压线或所述第一时钟信号线之间连通；
所述第一复位电路分别与第一复位线、第一时钟信号线和第一控制节点电连接，用于在所述第一复位线提供的第一复位信号的控制下，控制第一时钟信号线写入第一时钟信号至所述第一控制节点；
所述第一隔离电路分别与第二时钟信号线、第一控制节点和第一节点电连接，用于在所述第二时钟信号线提供的第二时钟信号的控制下，控制所述第一控制节点与所述第一节点之间连通。
可选的，所述第一复位电路包括第一晶体管；
所述第一晶体管的栅极与第一复位线电连接，所述第一晶体管的第一极 与第一时钟信号线电连接，所述第一晶体管的第二极与第一控制节点电连接。
可选的，所述第一晶体管为氧化物薄膜晶体管；第一高电压时间与第二高电压时间不交叠；
所述第一高电压时间为所述第一时钟信号的电位为高电压的时间；
所述第二高电压时间为所述第二时钟信号的电位为高电压的时间。
可选的，本公开至少一实施例所述的驱动电路还包括第二控制节点控制电路；
所述第二控制节点控制电路分别与第一时钟信号线、第一电压线、第二控制节点、第三节点和第二时钟信号线，用于在所述第一时钟信号的控制下，控制第二控制节点与第一电压线之间连通，并在所述第二控制节点的电位的控制下，控制所述第三节点与所述第二时钟信号线之间连通。
可选的，所述第二控制节点控制电路还用于根据所述第三节点的电位控制所述第二控制节点的电位。
可选的，本公开至少一实施例所述的驱动电路还包括级联输出电路和级联复位电路；
所述级联输出电路分别与第一节点、进位输出端和第一电压线电连接，用于在所述第一节点的电位的控制下，控制所述进位输出端与第一电压线之间连通；
所述级联复位电路分别与第二节点、进位输出端和第二电压线电连接，用于在所述第二节点的电位的控制下，控制所述进位输出端与所述第二电压线之间连通。
可选的，所述级联复位电路包括第二晶体管和第三晶体管；
所述第二晶体管的栅极与所述第二节点电连接，所述第二晶体管的第一极与所述进位输出端电连接，所述第二晶体管的第二极与第四节点电连接；
所述第三晶体管的栅极与所述第二节点电连接，所述第三晶体管的第一极与所述第四节点电连接，所述第三晶体管的第二极与第二电压线电连接。
可选的，本公开至少一实施例所述的驱动电路还包括第一控制电路；
所述第一控制电路分别与第一节点、第三电压线和所述第四节点电连接，用于在所述第一节点的电位的控制下，控制所述第三电压线与所述第四节点 之间连通。
可选的，所述第一控制电路包括第四晶体管；
所述第四晶体管的栅极与第一节点电连接，所述第四晶体管的第一极与第三电压线电连接，所述第四晶体管的第二极与第四节点电连接。
可选的，本公开至少一实施例所述的驱动电路还包括驱动输出复位电路和第二复位电路；
所述输出复位电路分别与第二节点、驱动信号输出端和第四电压线电连接，用于在所述第二节点的电位的控制下，将所述驱动信号输出端与所述第四电压线之间连通；
所述第二复位电路分别与第一节点、第二电压线和第二节点电连接，用于在所述第一节点的电位的控制下，控制所述第二电压线与所述第二节点之间连通。
可选的，所述输出复位电路包括的晶体管为氧化物晶体管，第二电压线提供的第二电压信号的电压值小于第一电压线提供的第一电压信号的电压值。
可选的，所述输出复位电路包括第五晶体管和第一电容，所述第二复位电路包括第六晶体管；
所述第五晶体管的栅极与所述第二节点电连接，所述第五晶体管的第一极与所述驱动信号输出端电连接，所述第五晶体管的第二极与所述第四电压线电连接；
所述第一电容的第一端与第二节点电连接，所述第一电容的第二端与第四电压线电连接；
所述第六晶体管的栅极与所述第一节点电连接，所述第六晶体管的第一极与第二电压线电连接，所述第六晶体管的第二极与所述第二节点电连接。
可选的，本公开至少一实施例所述的驱动电路还包括第二控制电路；
所述第二控制电路分别与第一控制节点、第二时钟信号线、第二电压线和第二控制节点电连接，用于在所述第二控制节点的电位和所述第二时钟信号线提供的第二时钟信号的控制下，控制所述第一控制节点与第二电压线之间连通。
可选的，本公开至少一实施例所述的驱动电路还包括第三控制电路；
所述第三控制电路分别与第二时钟信号线、输入线和第一控制节点电连接，用于在所述第二时钟信号的控制下，控制所述输入线与所述第一控制节点之间连通。
可选的，本公开至少一实施例所述的驱动电路还包括第四控制电路；
所述第四控制电路分别与第一节点、第一控制节点和第三电压线电连接，用于在所述第一节点的电位的控制下，控制所述第一控制节点与第三电压线之间连通。
可选的，所述第二控制节点控制电路还与输入线电连接，用于在所述输入线提供的输入信号的控制下，控制将第一时钟信号写入第二控制节点。
可选的，所述第二控制节点控制电路包括第七晶体管和第八晶体管；
所述第七晶体管的栅极与所述输入线电连接，所述第七晶体管的第一极与所述第一时钟信号线电连接，所述第七晶体管的第二极与所述第八晶体管的第一极电连接；
所述第八晶体管的栅极与所述输入线电连接，所述第八晶体管的第二极与所述第二控制节点电连接。
可选的，本公开至少一实施例所述的驱动电路还包括第三复位电路；
所述第三复位电路分别与第二复位线、第三电压线和第二节点电连接，用于在所述第二复位线提供的第二复位信号的控制下，控制所述第三电压线与第二节点之间连通。
可选的，所述第三复位电路包括第九晶体管和第十晶体管；
所述第九晶体管的栅极与所述第二复位线电连接，所述第九晶体管的第一极与第三电压线电连接，所述第九晶体管的第二极与所述第十晶体管的第一极电连接；
所述第十晶体管的栅极与所述第二复位线电连接，所述第十晶体管的第二极与所述第二节点电连接。
可选的，本公开至少一实施例所述的驱动电路还包括第二隔离电路；
所述第二隔离电路分别与第二时钟信号线、第三节点和第二节点电连接，用于在所述第二时钟信号线提供的第二时钟信号的控制下，控制所述第三节点与所述第二节点之间连通。
可选的，所述第三控制电路包括第十一晶体管，所述第二控制电路包括第十二晶体管和第十三晶体管，所述第四控制电路包括第十四晶体管；
所述第十一晶体管的栅极与第二时钟信号线电连接，所述第十一晶体管的第一极与输入线电连接，所述第十一晶体管的第二极与第一控制节点电连接；
所述第十四晶体管的栅极与第一节点电连接，所述第十四晶体管的第一极与第三电压电连接，所述第十四晶体管的第二极与第一控制节点电连接；
所述第十二晶体管的栅极与第二时钟信号线电连接，所述第十二晶体管的第一极与第一控制节点电连接，所述第十二晶体管的第二极与所述第十三晶体管的第一极电连接；所述第十三晶体管的栅极与第二控制节点电连接，所述第十三晶体管的第二极与第二电压线电连接；或者，所述第十二晶体管的栅极与所述第二控制节点电连接，所述第十二晶体管的第一极与第一控制节点电连接，所述第十二晶体管的第二极与所述第十三晶体管的第一极电连接；所述第十三晶体管的栅极与第二时钟信号线电连接，所述第十三晶体管的第二极与第二电压线电连接。
可选的，所述驱动输出电路包括第十五晶体管和第二电容，所述第一隔离电路包括第十六晶体管；
所述第十五晶体管的栅极与第一节点电连接，所述第十五晶体管的第一极与第一电压线或所述第一时钟信号线电连接，所述第十五晶体管的第二极与驱动信号输出端电连接；
所述第二电容的第一端与第一节点电连接，所述第二电容的第二端与所述驱动信号输出端电连接；
所述第十六晶体管的控制极与第二时钟信号线电连接，所述第十六晶体管的第一极与第一控制节点电连接，所述第十六晶体管的第二极与第一节点电连接。
可选的，所述第二控制节点控制电路包括第十七晶体管、第三电容和第十八晶体管；
所述第十七晶体管的栅极与第一时钟信号线电连接，所述第十七晶体管的第一极与第一电压线电连接，所述第十七晶体管的第二极与第二控制节点 电连接；
所述第三电容的第一端与第二控制节点电连接，所述第三电容的第二端与所述第三节点电连接；
所述第十八晶体管的栅极与所述第二控制节点电连接，所述第十八晶体管的第一极与第二时钟信号线电连接，所述第十八晶体管的第二极与第三节点电连接。
可选的，所述级联输出电路包括第十九晶体管；
所述第十九晶体管的栅极与第一节点电连接，所述第十九晶体管的第一极与第一电压线电连接，所述第十九晶体管的第二极与级联输出端电连接。
可选的，所述级联输出电路还包括第四电容；
所述第四电容的第一端与第一节点电连接，所述第四电容的第二端与级联输出端电连接。
可选的，所述第二隔离电路包括第二十晶体管；
所述第二十晶体管的栅极与第二时钟信号线电连接，所述第二十晶体管的第一极与第三节点电连接，所述第二十晶体管的第二极与第二节点电连接。
可选的，本公开至少一实施例所述的驱动电路还包括第二十一晶体管；
所述第二十一晶体管的栅极与第一高电压线电连接，所述第二十一晶体管的第一极与第十六晶体管的第二极电连接，所述第二十一晶体管的第二极与第一节点电连接。
在第二个方面中，本公开实施例还提供一种驱动方法，应用于上述的驱动电路，显示周期包括先后设置的第一阶段、第二阶段和第三阶段，所述驱动方法包括：
在第一阶段，所述第一复位电路在第一复位线提供的第一复位信号的控制下，控制第一时钟信号线写入第一时钟信号至所述第一控制节点，当第二时钟信号线提供高电压信号时，第一隔离电路在第二时钟信号线提供的第二时钟信号的控制下，控制所述第一控制节点与所述第一节点之间连通；
在第二阶段，当第二时钟信号线提供高电压信号时，第一隔离电路在第二时钟信号的控制下，控制所述第一控制节点与所述第一节点之间连通；驱动输出电路在所述第一节点的电位的控制下，控制驱动信号输出端与第一电 压线之间连通；
在第三阶段，当第二时钟信号线提供高电压信号时，第一隔离电路在第二时钟信号的控制下，控制所述第一控制节点与所述第一节点之间连通。
在第三个方面中，本公开实施例提供一种显示基板，包括上述的驱动电路。
可选的，本公开至少一实施例所述的显示基板还包括多列直流信号线；所述显示基板包括显示区域和周边区域，所述直流信号线和所述驱动电路设置于周边区域；
所述多列直流信号线中的至少一列直流信号线设置于所述驱动电路远离所述显示区域的一侧，所述多列直流信号线中的除了该至少一列直流信号线之外的直流信号线设置于所述驱动电路靠近所述显示区域的一侧。
在第四个方面中，本公开实施例提供一种显示装置，包括上述的显示基板。
附图说明
图1是本公开实施例所述的驱动电路的结构图；
图2是本公开至少一实施例所述的驱动电路的结构图；
图3是本公开至少一实施例所述的驱动电路的结构图；
图4是本公开至少一实施例所述的驱动电路的结构图；
图5是本公开至少一实施例所述的驱动电路的结构图；
图6是本公开至少一实施例所述的驱动电路的结构图；
图7是本公开至少一实施例所述的驱动电路的电路图；
图8是图7所示的驱动电路的至少一实施例的工作时序图；
图9是当氧化物晶体管的阈值电压为4V时，图7所示的驱动电路的至少一实施例的仿真工作时序图；
图10是当氧化物晶体管的阈值电压为-2.5V时，图7所示的驱动电路的至少一实施例的仿真工作时序图；
图11是本公开至少一实施例所述的驱动电路的电路图；
图12是本公开至少一实施例所述的驱动电路的电路图；
图13是本公开至少一实施例所述的驱动电路的电路图；
图14是本公开至少一实施例所述的驱动电路的电路图；
图15是本公开至少一实施例所述的驱动电路的电路图；
图16是图15所示的驱动电路的至少一实施例的工作时序图；
图17是图15所示的驱动电路的至少一实施例的仿真工作时序图；
图18是图13所示的驱动电路的至少一实施例的布局图；
图19A是图18的一部分的放大图；
图19B是图18的一部分的放大图；
图20是图18中的半导体层的布局图；
图21是图18中的栅金属层的布局；
图22的图18中的源漏金属层的布局图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除栅极之外的两极，将其中一极称为第一极，另一极称为第二极。
在实际操作时，当所述晶体管为薄膜晶体管或场效应管时，所述第一极可以为漏极，所述第二极可以为源极；或者，所述第一极可以为源极，所述第二极可以为漏极。
本公开实施例所述的驱动电路包括驱动输出电路、第一复位电路和第一隔离电路；
所述驱动输出电路分别与第一节点和驱动信号输出端电连接，所述驱动电路还和第一电压线或第一时钟信号线电连接，用于在所述第一节点的电位的控制下，控制所述驱动信号输出端与所述第一电压线或所述第一时钟信号线之间连通；
所述第一复位电路分别与第一复位线、第一时钟信号线和第一控制节点电连接，用于在所述第一复位线提供的第一复位信号的控制下，控制第一时钟信号线写入第一时钟信号至所述第一控制节点；
所述第一隔离电路分别与第二时钟信号线、第一控制节点和第一节点电连接，用于在所述第二时钟信号线提供的第二时钟信号的控制下，控制所述第一控制节点与所述第一节点之间连通。
本公开实施例所述的驱动电路设置第一复位电路和第一隔离电路，第一复位电路在复位信号的控制下，控制将第一时钟信号写入第一控制节点，第一隔离电路在第二时钟信号的控制下，控制第一控制节点与第一节点之间连通，通过第一时钟信号对第一控制节点的电位进行复位，之后再通过第一隔离电路在第二时钟信号的控制下，控制第一控制节点与第一节点之间连通，进而对第一节点的电位进行复位，由于第一时钟信号是周期性的信号，低压时间较短，漏电较小。
在本公开至少一实施例中，所述第一复位线可以为复位线RST，但不以此为限。
如图1所示，本公开实施例所述的驱动电路包括驱动输出电路11、第一复位电路12和第一隔离电路13；
所述驱动输出电路11分别与第一节点Q、驱动信号输出端O1和第一电压线V1电连接，用于在所述第一节点Q的电位的控制下，控制所述驱动信号输出端O1与所述第一电压线V1之间连通；
所述第一复位电路12分别与复位线RST、第一时钟信号线CKB和第一控制节点PQ电连接，用于在所述复位线RST提供的复位信号的控制下，控制第一时钟信号线CKB写入第一时钟信号至所述第一控制节点PQ；
所述第一隔离电路13分别与第二时钟信号线CKA、第一控制节点PQ和第一节点Q电连接，用于在所述第二时钟信号线CKA提供的第二时钟信号的控制下，控制所述第一控制节点PQ与所述第一节点Q之间连通。
在本公开至少一实施例中，所述驱动电路可以为氧化物内部补偿PWM(脉冲宽度调制)电路。
在本公开至少一实施例中，所述驱动电路可以采用氧化物晶体管，但不 以此为限。
本公开实施例所述的驱动电路设置第一复位电路12和第一隔离电路13，第一复位电路12在复位信号的控制下，控制将第一时钟信号写入第一控制节点PQ，第一隔离电路13在第二时钟信号的控制下，控制第一控制节点PQ与第一节点Q之间连通，通过第一时钟信号对第一控制节点PQ的电位进行复位，之后再通过第一隔离电路13在第二时钟信号的控制下，控制第一控制节点PQ与第一节点Q之间连通，进而对第一节点Q的电位进行复位，由于第一时钟信号是周期性的信号，低压时间较短，漏电较小。
在相关技术中，用于复位的晶体管通过低电压信号直接对第一节点的电位进行复位，由于氧化物晶体管的阈值电压容易负漂而导致在用于复位的晶体管需要关断时，该晶体管不能完全关断，此时在低电压线与第一节点之间有一条通路，会造成漏电而导致第一节点的电位被拉低，基于此本公开实施例通过第一时钟信号对第一控制节点的电位进行复位，在通过第一隔离电路在第二时钟信号的控制下，控制第一控制节点与第一节点之间连通，以对第一节点的电位进行复位。
可选的，所述第一复位电路包括第一晶体管；
所述第一晶体管的栅极与第一复位线电连接，所述第一晶体管的第一极与第一时钟信号线电连接，所述第一晶体管的第二极与第一控制节点电连接。
在本公开至少一实施例中，所述第一晶体管为氧化物薄膜晶体管；第一高电压时间与第二高电压时间不交叠；
所述第一高电压时间为所述第一时钟信号的电位为高电压的时间；
所述第二高电压时间为所述第二时钟信号的电位为高电压的时间。
本公开至少一实施例所述的驱动电路还可以包括第二控制节点控制电路；
所述第二控制节点控制电路分别与第一时钟信号线、第一电压线、第二控制节点、第三节点和第二时钟信号线，用于在所述第一时钟信号的控制下，控制第二控制节点与第一电压线之间连通，并在所述第二控制节点的电位的控制下，控制所述第三节点与所述第二时钟信号线之间连通，并根据所述第三节点的电位控制所述第二控制节点的电位。
在具体实施时，所述驱动电路还可以包括第二控制节点控制电路，第二 控制节点控制电路在第一时钟信号的控制下，根据第二时钟信号，控制第二控制节点的电位。
如图2所示，在图1所示的驱动电路的实施例的基础上，本公开至少一实施例所述的驱动电路还可以包括第二控制节点控制电路21；
所述第二控制节点控制电路21分别与第一时钟信号线CKB、第一电压线V1、第二控制节点PQB、第三节点N3和第二时钟信号线CKA电连接，用于在所述第一时钟信号的控制下，控制第二控制节点PQB与第一电压线V1之间连通，并在所述第二控制节点PQB的电位的控制下，控制所述第三节点N3与所述第二时钟信号线CKA之间连通。
在本公开至少一实施例中，所述第二控制节点控制电路21可以根据所述第三节点N3的电位控制所述第二控制节点PQB的电位。此时，所述第二控制节点控制电路21可以包括一电容，该电容的第一端与第三节点N3电连接，该电容的第二端与第二时钟信号线CKA电连接，以能根据第三节点N3的电位控制第二控制节点PQB的电位。
在本公开至少一实施例中，第一电压线可以为第一高电压线，但不以此为限。
本公开至少一实施例所述的驱动电路还包括级联输出电路和级联复位电路(T12和T13)；
所述级联输出电路分别与第一节点、进位输出端和第一电压线电连接，用于在所述第一节点的电位的控制下，控制所述进位输出端与第一电压线之间连通；
所述级联复位电路分别与第二节点、进位输出端和第二电压线电连接，用于在所述第二节点的电位的控制下，控制所述进位输出端与所述第二电压线之间连通。
在具体实施时，所述驱动电路还包括级联输出电路和级联复位电路，通过级联输出电路和级联复位电路通知进位输出端输出进位信号，该进位信号用于级联，以提升驱动电路的驱动能力。
如图3所示，在图2所示的驱动电路的至少一实施例的基础上，本公开至少一实施例所述的驱动电路还包括级联输出电路31和级联复位电路32；
所述级联输出电路31分别与第一节点Q、进位输出端CR和第一电压线V1电连接，用于在所述第一节点Q的电位的控制下，控制所述进位输出端C4与第一电压线V1之间连通；
所述级联复位电路32分别与第二节点QB、进位输出端CR和第二电压线V2电连接，用于在所述第二节点QB的电位的控制下，控制所述进位输出端CR与所述第二电压线V2之间连通。
在本公开至少一实施例中，第一电压线V1可以为第一高电压线，第二电压线V2可以为第二低电压线，但不以此为限。
可选的，所述级联复位电路包括第二晶体管和第三晶体管；
所述第二晶体管的栅极与所述第二节点电连接，所述第二晶体管的第一极与所述进位输出端电连接，所述第二晶体管的第二极与第四节点电连接；
所述第三晶体管的栅极与所述第二节点电连接，所述第三晶体管的第一极与所述第四节点电连接，所述第三晶体管的第二极与第二电压线电连接。
本公开至少一实施例所述的驱动电路还包括第一控制电路；
所述第一控制电路分别与第一节点、第三电压线和所述第四节点电连接，用于在所述第一节点的电位的控制下，控制所述第三电压线与所述第四节点之间连通。
在本公开至少一实施例中，所述第三电压线可以为第二高电压线，但不以此为限。
在具体实施时，本公开至少一实施例所述的驱动电路还可以包括第一控制电路，第一控制电路在第一节点的电位的控制下，控制第四节点与第三电压线之间连通，以防止进位输出端提供的进位信号的电位由于漏电而降低。
如图4所示，在图3所示的驱动电路的至少一实施例的基础上，本公开至少一实施例所述的驱动电路还包括第一控制电路41；
所述第一控制电路分别41与第一节点Q、第三电压线V3和所述第四节点N4电连接，用于在所述第一节点Q的电位的控制下，控制所述第三电压线V3与所述第四节点N4之间连通；
所述级联复位电路32与所述第四节点N4电连接。
可选的，所述第一控制电路包括第四晶体管；
所述第四晶体管的栅极与第一节点电连接，所述第四晶体管的第一极与第三电压线电连接，所述第四晶体管的第二极与第四节点电连接。
如图5所示，在图4所示的驱动电路的至少一实施例的基础上，所述的驱动电路还包括驱动输出复位电路51和第二复位电路52；
所述输出复位电路51分别与第二节点QB、驱动信号输出端O1和第四电压线V4电连接，用于在所述第二节点QB的电位的控制下，将所述驱动信号输出端O1与所述第四电压线V4之间连通；
所述第二复位电路52分别与第一节点Q、第二电压线V2和第二节点QB电连接，用于在所述第一节点Q的电位的控制下，控制所述第二电压线V2与所述第二节点QB之间连通。
在本公开至少一实施例中，第四电压线可以为第一低电压线，第二电压线可以为第二低电压线，但不以此为限。
本公开图5所示的驱动电路的至少一实施例在工作时，第二复位电路52在第一节点Q的电位的控制下，控制第二节点QB与第二电压线V2之间连通，输出复位电路51在第二节点QB的电位的控制下，控制驱动信号输出端O1与第四电压线V4之间连通。
可选的，所述输出复位电路包括的晶体管为氧化物晶体管，第二电压线提供的第二电压信号的电压值小于第一电压线提供的第一电压信号的电压值，以避免当输出复位电路包括的晶体管的阈值电压负漂时输出漏电。
可选的，所述输出复位电路包括第五晶体管和第一电容，所述第二复位电路包括第六晶体管；
所述第五晶体管的栅极与所述第二节点电连接，所述第五晶体管的第一极与所述驱动信号输出端电连接，所述第五晶体管的第二极与所述第四电压线电连接；
所述第一电容的第一端与第二节点电连接，所述第一电容的第二端与第四电压线电连接；
所述第六晶体管的栅极与所述第一节点电连接，所述第六晶体管的第一极与第二电压线电连接，所述第六晶体管的第二极与所述第二节点电连接。
可选的，本公开至少一实施例所述的驱动电路还可以包括第二控制电路；
所述第二控制电路分别与第一控制节点、第二时钟信号线、第二电压线和第二控制节点电连接，用于在所述第二控制节点的电位和所述第二时钟信号线提供的第二时钟信号的控制下，控制所述第一控制节点与第二电压线之间连通。
在具体实施时，所述驱动电路可以包括第二控制电路，第二控制电路在所述第二控制节点的电位和所述第二时钟信号线提供的第二时钟信号的控制下，控制所述第一控制节点与第二电压线之间连通
本公开至少一实施例所述的驱动电路还可以包括第三控制电路；
所述第三控制电路分别与第二时钟信号线、输入线和第一控制节点电连接，用于在所述第二时钟信号的控制下，控制所述输入线与所述第一控制节点之间连通。
在具体实施时，所述驱动电路可以包括第三控制电路，第三控制电路在第二时钟信号的控制下，控制输入线与第一控制节点之间连通。
本公开至少一实施例所述的驱动电路还可以包括第四控制电路；
所述第四控制电路分别与第一节点、第一控制节点和第三电压线电连接，用于在所述第一节点的电位的控制下，控制所述第一控制节点与第三电压线之间连通。
在具体实施时，所述驱动电路可以包括第四控制电路；第四控制电路在第一节点的电位的控制下，控制第一控制节点与第三电压线之间连通。
在本公开至少一实施例中，所述第二控制节点控制电路还与输入线电连接，用于在所述输入线提供的输入信号的控制下，控制将第一时钟信号写入第二控制节点。
在具体实施时，所述第二控制节点控制电路可以在输入信号的控制下，将第一时钟信号写入第二控制节点。
可选的，所述第二控制节点控制电路包括第七晶体管和第八晶体管；
所述第七晶体管的栅极与所述输入线电连接，所述第七晶体管的第一极与所述第一时钟信号线电连接，所述第七晶体管的第二极与所述第八晶体管的第一极电连接；
所述第八晶体管的栅极与所述输入线电连接，所述第八晶体管的第二极 与所述第二控制节点电连接。
本公开至少一实施例所述的驱动电路还包括第三复位电路；
所述第三复位电路分别与第二复位线、第三电压线和第二节点电连接，用于在所述第二复位线提供的第二复位信号的控制下，控制所述第三电压线与第二节点之间连通。
在本公开至少一实施例中，第一复位线和第二复位线可以相同，或者，第一复位线和第二复位线也可以不同。
在本公开至少一实施例中，所述第二复位线可以为复位线RST，但不以此为限。
可选的，所述第三电压线可以为第二高电压线，但不以此为限。
在具体实施时，本公开至少一实施例所述的驱动电路还可以包括第三复位电路，第三复位电路在复位信号的控制下，控制第二节点与第三电压线之间连通，以对第二节点的电位进行复位。
可选的，所述第三复位电路包括第九晶体管和第十晶体管；
所述第九晶体管的栅极与所述第二复位线电连接，所述第九晶体管的第一极与第三电压线电连接，所述第九晶体管的第二极与所述第十晶体管的第一极电连接；
所述第十晶体管的栅极与所述第二复位线电连接，所述第十晶体管的第二极与所述第二节点电连接。
本公开至少一实施例所述的驱动电路还包括第二隔离电路；
所述第二隔离电路分别与第二时钟信号线、第三节点和第二节点电连接，用于在所述第二时钟信号线提供的第二时钟信号的控制下，控制所述第三节点与所述第二节点之间连通。
在具体实施时，所述驱动电路还可以包括第二隔离电路，第二隔离电路在第二时钟信号的控制下，控制第三节点与第二节点之间连通。
如图6所示，在图5所示的驱动电路的至少一实施例的基础上，本公开至少一实施例所述的驱动电路还包括第二控制电路602、第三控制电路603、第四控制电路604、第三复位电路61和第二隔离电路62；
所述第二控制电路602分别与第一控制节点PQ、第二时钟信号线CKA、 第二电压线V2和第二控制节点PQB电连接，用于在所述第二控制节点PQB的电位和所述第二时钟信号线CKA提供的第二时钟信号的控制下，控制所述第一控制节点PQ与第二电压线V2之间连通；
所述第三控制电路603分别与第二时钟信号线CKA、输入线STU和第一控制节点PQ电连接，用于在所述第二时钟信号CKA的控制下，控制所述输入线STU与所述第一控制节点PQ之间连通；
所述第四控制电路604分别与第一节点Q、第一控制节点PQ和第三电压线V3电连接，用于在所述第一节点Q的电位的控制下，控制所述第一控制节点PQ与第三电压线V3之间连通；
所述第二控制节点控制电路21还分别与输入线STU和第一时钟信号线CKB电连接，用于在所述输入线STU提供的输入信号的控制下，控制将所述第一时钟信号线CKB提供的第一时钟信号写入第二控制节点PQB；
所述第三复位电路61分别与复位线RST、第三电压线V3和第二节点QB电连接，用于在所述复位线RST提供的复位信号的控制下，控制所述第三电压线V3与第二节点QB之间连通；
所述第二隔离电路62分别与第二时钟信号线CKA、第三节点N3和第二节点QB电连接，用于在所述第二时钟信号线CKA提供的第二时钟信号的控制下，控制所述第三节点N3与所述第二节点QB之间连通。
可选的，所述第三控制电路包括第十一晶体管，所述第二控制电路包括第十二晶体管和第十三晶体管，所述第四控制电路包括第十四晶体管；
所述第十一晶体管的栅极与第二时钟信号线电连接，所述第十一晶体管的第一极与输入线电连接，所述第十一晶体管的第二极与第一控制节点电连接；
所述第十四晶体管的栅极与第一节点电连接，所述第十四晶体管的第一极与第三电压线电连接，所述第十四晶体管的第二极与第一控制节点电连接；
所述第十二晶体管的栅极与第二时钟信号线电连接，所述第十二晶体管的第一极与第一控制节点电连接，所述第十二晶体管的第二极与所述第十三晶体管的第一极电连接；所述第十三晶体管的栅极与第二控制节点电连接，所述第十三晶体管的第二极与第二电压线电连接；或者，所述第十二晶体管 的栅极与所述第二控制节点电连接，所述第十二晶体管的第一极与第一控制节点电连接，所述第十二晶体管的第二极与所述第十三晶体管的第一极电连接；所述第十三晶体管的栅极与第二时钟信号线电连接，所述第十三晶体管的第二极与第二电压线电连接。
可选的，所述驱动输出电路包括第十五晶体管和第二电容，所述第一隔离电路包括第十六晶体管；
所述第十五晶体管的栅极与第一节点电连接，所述第十五晶体管的第一极与第一电压线电连接，所述第十五晶体管的第二极与驱动信号输出端电连接；
所述第二电容的第一端与第一节点电连接，所述第二电容的第二端与所述驱动信号输出端电连接；
所述第十六晶体管的控制极与第二时钟信号线电连接，所述第十六晶体管的第一极与第一控制节点电连接，所述第十六晶体管的第二极与第一节点电连接。
可选的，所述第二控制节点控制电路包括第十七晶体管、第三电容和第十八晶体管；
所述第十七晶体管的栅极与第一时钟信号线电连接，所述第十七晶体管的第一极与第一电压线电连接，所述第十七晶体管的第二极与第二控制节点电连接；
所述第三电容的第一端与第二控制节点电连接，所述第三电容的第二端与所述第三节点电连接；
所述第十八晶体管的栅极与所述第二控制节点电连接，所述第十八晶体管的第一极与第二时钟信号线电连接，所述第十八晶体管的第二极与第三节点电连接。
可选的，所述级联输出电路包括第十九晶体管；
所述第十九晶体管的栅极与第一节点电连接，所述第十九晶体管的第一极与第一电压线电连接，所述第十九晶体管的第二极与级联输出端电连接。
在本公开至少一实施例中，所述级联输出电路还包括第四电容；
所述第四电容的第一端与第一节点电连接，所述第四电容的第二端与级 联输出端电连接。
可选的，所述第二隔离电路包括第二十晶体管；
所述第二十晶体管的栅极与第二时钟信号线电连接，所述第二十晶体管的第一极与第三节点电连接，所述第二十晶体管的第二极与第二节点电连接。
如图7所示，在图6所示的驱动电路的至少一实施例的基础上，所述第一复位电路12包括第一晶体管T1；
所述第一晶体管T1的栅极与复位线RST电连接，所述第一晶体管T1的源极与第一时钟信号线CKB电连接，所述第一晶体管T1的漏极与第一控制节点PQ电连接；
所述级联复位电路32包括第二晶体管T2和第三晶体管T3；
所述第二晶体管T2的栅极与所述第二节点QB电连接，所述第二晶体管T2的源极与所述进位输出端CR电连接，所述第二晶体管T2的漏极与第四节点N4电连接；
所述第三晶体管T3的栅极与所述第二节点QB电连接，所述第三晶体管T3的源极与所述第四节点N4电连接，所述第三晶体管T3的漏极与第二低电压线VGL2电连接；
所述第一控制电路41包括第四晶体管T4；
所述第四晶体管T4的栅极与第一节点Q电连接，所述第四晶体管T4的源极与第二高电压线VGH2电连接，所述第四晶体管T4的漏极与第四节点N4电连接；
所述输出复位电路51包括第五晶体管T5和第一电容C1，所述第二复位电路52包括第六晶体管T6；
所述第五晶体管T5的栅极与所述第二节点QB电连接，所述第五晶体管T5的源极与所述驱动信号输出端O1电连接，所述第五晶体管T5的漏极与所述第一低电压线VGL电连接；
所述第一电容C1的第一端与第二节点QB电连接，所述第一电容C1的第二端与第一低电压线VGL电连接；
所述第六晶体管T6的栅极与所述第一节点Q电连接，所述第六晶体管T6的源极与第二低电压线VGL2电连接，所述第六晶体管T6的漏极与所述 第二节点QB电连接；
所述第二控制节点控制电路21包括第七晶体管T7和第八晶体管T8；
所述第七晶体管T7的栅极与所述输入线STU电连接，所述第七晶体管T7的源极与所述第一时钟信号线CKB电连接，所述第七晶体管T7的漏极与所述第八晶体管T8的源极电连接；
所述第八晶体管T8的栅极与所述输入线STU电连接，所述第八晶体管T8的漏极与所述第二控制节点PQB电连接；
所述第三复位电路61包括第九晶体管T9和第十晶体管T10；
所述第九晶体管T9的栅极与所述复位线RST电连接，所述第九晶体管T9的源极与第二高电压线VGH2电连接，所述第九晶体管T9的漏极与所述第十晶体管T10的源极电连接；
所述第十晶体管T10的栅极与所述复位线RST电连接，所述第十晶体管T10的漏极与所述第二节点QB电连接；
所述第三控制电路603包括第十一晶体管T11，所述第二控制电路602包括第十二晶体管T12和第十三晶体管T13，所述第四控制电路604包括第十四晶体管T14；
所述第十一晶体管T11的栅极与第二时钟信号线CKA电连接，所述第十一晶体管T11的源极与输入线STU电连接，所述第十一晶体管T11的漏极与第一控制节点PQ电连接；
所述第十四晶体管T14的栅极与第一节点Q电连接，所述第十四晶体管T14的源极与第二高电压线VGH2电连接，所述第十四晶体管T14的漏极与第一控制节点PQ电连接；
所述第十二晶体管T12的栅极与第二时钟信号线CKA电连接，所述第十二晶体管T12的源极与第一控制节点PQ电连接，所述第十二晶体管T12的漏极与所述第十三晶体管T13的源极电连接；
所述第十三晶体管T13的栅极与第二控制节点PQB电连接，所述第十三晶体管T13的漏极与第二低电压线VGL2电连接；
所述驱动输出电路11包括第十五晶体管T15和第二电容C2，所述第一隔离电路13包括第十六晶体管T16；
所述第十五晶体管T15的栅极与第一节点Q电连接，所述第十五晶体管T15的源极与第一高电压线VGH电连接，所述第十五晶体管T15的漏极与驱动信号输出端O1电连接；
所述第二电容C2的第一端与第一节点Q电连接，所述第二电容C2的第二端与所述驱动信号输出端O1电连接；
所述第十六晶体管T16的栅极与第二时钟信号线CKA电连接，所述第十六晶体管T16的源极与第一控制节点PQ电连接，所述第十六晶体管的漏极与第一节点Q电连接；
所述第二控制节点控制电路21还包括第十七晶体管T17、第三电容C3和第十八晶体管T18；
所述第十七晶体管T17的栅极与第一时钟信号线CKB电连接，所述第十七晶体管T17的源极与第一高电压线VGH电连接，所述第十七晶体管T17的漏极与第二控制节点PQB电连接；
所述第三电容C3的第一端与第二控制节点PQB电连接，所述第三电容C3的第二端与所述第三节点N3电连接；
所述第十八晶体管T18的栅极与所述第二控制节点PQB电连接，所述第十八晶体管T18的源极与第二时钟信号线CKA电连接，所述第十八晶体管T18的漏极与第三节点N3电连接；
所述级联输出电路31包括第十九晶体管T19；
所述第十九晶体管T19的栅极与第一节点Q电连接，所述第十九晶体管T19的源极与第一高电压线VGH电连接，所述第十九晶体管T19的漏极与级联输出端CR电连接；
所述级联输出电路31还包括第四电容C4；
所述第四电容C4的第一端与第一节点Q电连接，所述第四电容C4的第二端与级联输出端CR电连接；
所述第二隔离电路62包括第二十晶体管T20；
所述第二十晶体管T20的栅极与第二时钟信号线CKA电连接，所述第二十晶体管T20的源极与第三节点N3电连接，所述第二十晶体管T20的漏极与第二节点QB电连接。
在图7所示的驱动电路的至少一实施例中，所有晶体管都为n型晶体管，所有晶体管都为氧化物晶体管，但不以此为限。
在图7所示的驱动电路的至少一实施例中，设置有C4，以增加抗干扰能力。
在图7所示的驱动电路的至少一实施例中，所述第二控制节点控制电路包括第七晶体管T7、第八晶体管T8、第十七晶体管T17、第三电容C3和第十八晶体管T18；
T17的漏极与第二控制电路包括的T13的栅极电连接，T18的漏极与T20电连接；
T18的漏极通过T20与第二节点QB电连接，T18的漏极与T2的栅极、T3的栅极和T5的电极电性连接。
在本公开至少一实施例中，驱动电路包括的晶体管为n型晶体管，但不以此为限；在具体实施时，驱动电路包括的晶体管还可以为p型晶体管。
如图8所示，本公开图7所示的驱动电路的至少一实施例在工作时，驱动周期包括先后设置的第一阶段S1、第二阶段S2和第三阶段S3；
在第一阶段S1，RST提供高电压信号，T1打开，对于PQ来说，当CKB输出高电压信号时，PQ的电位被拉高，但是由于CKA提供的第二时钟信号的电位为低电压，T16关闭，因此第一节点Q的电位不会被拉高；当CKB输出低电压信号，CKA输出高电压信号时，T16打开，此时PQ的电位和Q的电位都被拉低，实现了对第一节点Q的电位进行复位，PQ的电位随着CKB提供的第一时钟信号的电位周期性变化，低压时间较短，漏电较小，同时控制由T1控制对PQ的电位进行复位，以进一步降低漏电风险；
在第一阶段S1，RST提供高电压信号，T9和T10打开，QB与VGH2之间连通，由于VGH2长期保持输出第二高电压信号，不担心漏电问题；当CKB输出高电压时，T17打开，PQB的电位为高电压，由于C3的存在，PQB的电位可以保持为高电压，当CKA输出高电压信号时，PQB的电位会由于自举而进一步抬高，并随着CKA提供的第二时钟信号的电位的变化而周期性变化；
在第二阶段S2，STU提供高电压信号，RST提供低电压信号，当CKA 提供高电压信号时，T11、T16、T15和T19打开，PQ的电位和Q的电位为高电压，CR和O1都输出高电压信号，T7和T8打开，PQB的电位随着CKB提供的第一时钟信号的电位变化而变化，T6打开，QB与VGL2之间连通；
在第三阶段S3，STU提供低电压信号，当CKA输出高电压信号时，T11打开，PQ与STU之间连通，PQ的电位为低电压，T16打开，PQ与Q之间连通，以使得第一节点Q的电位为低电压；当CKA输出高电压信号时，PQB的电位自举拉升，同时T20打开，QB的电位为高电压，以打开T5和T2，CR输出第二低电压信号，O1输出低电压信号。
如图8所示，图7所示的驱动电路的至少一实施例通过其驱动信号输出端输出的驱动信号可以为补偿控制信号
在图7所示的驱动电路的至少一实施例中，VGL输出的第一低电压信号的电位可以为-6V，VGL2输出的第二低电压信号的电位可以为-8V，则在O1输出高电压信号时，T11的栅源电压为-2V，避免T11的阈值电压负漂时输出漏电。
如图8所示，CKA提供的第一时钟信号的占空比和CKB提供的第二时钟信号的占空比可以为25％，第二时钟信号的相位与第一时钟信号的相位可以相隔半个周期，但不以此为限。
图9是当氧化物晶体管的阈值电压为4V时，图7所示的驱动电路的至少一实施例的仿真工作时序图；
图10是当氧化物晶体管的阈值电压为-2.5V时，图7所示的驱动电路的至少一实施例的仿真工作时序图。
如图10所示，当氧化物晶体管的阈值电压为-2.5V时，图7所示的驱动电路的至少一实施例能够正常工作。
图11所示的驱动电路的至少一实施例与图7所示的驱动电路的至少一实施例的区别在于：T12的栅极与PQB电连接，T13的栅极与第二时钟信号线CKB电连接。
图12所示的驱动电路的至少一实施例与图7所示的驱动电路的至少一实施例的区别在于：不设置有C4。
图13所示的驱动电路的至少一实施例与图7所示的驱动电路的至少一实 施例的区别在于：不设置有T7和T9。
图14所示的驱动电路的至少一实施例与图7所示的驱动电路的至少一实施例的区别在于：还包括第二十一晶体管T21；
所述第二十一晶体管T21的栅极与第一高电压线VGH电连接，所述第二十一晶体管T21的源极与T16的漏极电连接，所述第二十一晶体管T21的漏极第一节点Q电连接；
所述第二十一晶体管T2为常开晶体管。
图15所示的驱动电路的至少一实施例与图7所示的驱动电路的至少一实施例的区别在于：T15的源极与第一时钟信号线CKB电连接。
图16是图15所示的驱动电路的至少一实施例的工作时序图。图17是图15所示的驱动电路的至少一实施例的仿真工作时序图。
图15所示的驱动电路的至少一实施例可以为像素单元提供栅极驱动信号，但不以此为限。
在图15所示的驱动电路的至少一实施例中，驱动输出电路可以包括至少两个用于输出的晶体管，例如，驱动输出电路除了可以包括第十五晶体管之外，还可以包括至少一个输出晶体管，所述输出晶体管的源极与相应的输出时钟信号端电连接，所述输出晶体管的漏极与相应的驱动信号输出端电连接，此时，本公开至少一实施例所述的驱动电路可以包括至少两个驱动信号输出端，可以输出相应的栅极驱动信号至所述至少两个驱动信号输出端，所述至少两个驱动信号输出端分别为至少两行像素单元提供相应的栅极驱动信号。
本公开实施例所述的驱动方法，应用于上述的驱动电路，显示周期包括先后设置的第一阶段、第二阶段和第三阶段，所述驱动方法包括：
在第一阶段，所述第一复位电路在第一复位线提供的第一复位信号的控制下，控制第一时钟信号线写入第一时钟信号至所述第一控制节点，当第二时钟信号线提供高电压信号时，第一隔离电路在第二时钟信号线提供的第二时钟信号的控制下，控制所述第一控制节点与所述第一节点之间连通；
在第二阶段，当第二时钟信号线提供高电压信号时，第一隔离电路在第二时钟信号的控制下，控制所述第一控制节点与所述第一节点之间连通；驱动输出电路在所述第一节点的电位的控制下，控制驱动信号输出端与第一电 压线之间连通；
在第三阶段，当第二时钟信号线提供高电压信号时，第一隔离电路在第二时钟信号的控制下，控制所述第一控制节点与所述第一节点之间连通。
本公开至少一实施例所述的显示基板包括上述的驱动电路。
本公开至少一实施例所述的显示基板还包括多列直流信号线；所述显示基板包括显示区域和周边区域，所述直流信号线和所述驱动电路设置于周边区域；
所述多列直流信号线中的至少一列直流信号线设置于所述驱动电路远离所述显示区域的一侧，所述多列直流信号线中的除了该至少一列直流信号线之外的直流信号线设置于所述驱动电路靠近所述显示区域的一侧。
图18是图13所示的驱动电路的至少一实施例的布局图。图19A和图19B是图18的一部分的放大图。图20是图18中的半导体层的布局图，图21是图18中的栅金属层的布局，图22的图18中的源漏金属层的布局图。
如图18所示，CKA、CKB、STU、RST、VGH和VGH2沿竖直方向延伸，VGL1和VGL2沿竖直方向延伸；
CKA、CKB、STU、RST、VGH和VGH2设置于驱动电路远离显示区域的一侧，VGL1和VGL2设置于驱动电路靠近显示区域的一侧。
如图18所示，第四电容C4的极板沿竖直方向延伸，并第四电容C4的极板的面积大于第一电容C1的极板的面积，第四电容C4的极板的面积大于C2的极板的面积，第四电容C4的极板的面积大于C3的极板的面积。
本公开实施例所述的显示装置包括上述的显示基板。
本公开实施例所提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (31)

  1. 一种驱动电路，包括驱动输出电路、第一复位电路和第一隔离电路；
    所述驱动输出电路分别与第一节点和驱动信号输出端电连接，所述驱动电路还和第一电压线或第一时钟信号线电连接，用于在所述第一节点的电位的控制下，控制所述驱动信号输出端与所述第一电压线或所述第一时钟信号线之间连通；
    所述第一复位电路分别与第一复位线、第一时钟信号线和第一控制节点电连接，用于在所述第一复位线提供的第一复位信号的控制下，控制第一时钟信号线写入第一时钟信号至所述第一控制节点；
    所述第一隔离电路分别与第二时钟信号线、第一控制节点和第一节点电连接，用于在所述第二时钟信号线提供的第二时钟信号的控制下，控制所述第一控制节点与所述第一节点之间连通。
  2. 如权利要求1所述的驱动电路，其中，所述第一复位电路包括第一晶体管；
    所述第一晶体管的栅极与第一复位线电连接，所述第一晶体管的第一极与第一时钟信号线电连接，所述第一晶体管的第二极与第一控制节点电连接。
  3. 如权利要求2所述的驱动电路，其中，所述第一晶体管为氧化物薄膜晶体管；第一高电压时间与第二高电压时间不交叠；
    所述第一高电压时间为所述第一时钟信号的电位为高电压的时间；
    所述第二高电压时间为所述第二时钟信号的电位为高电压的时间。
  4. 如权利要求1至3中任一权利要求所述的驱动电路，其中，还包括第二控制节点控制电路；
    所述第二控制节点控制电路分别与第一时钟信号线、第一电压线、第二控制节点、第三节点和第二时钟信号线，用于在所述第一时钟信号的控制下，控制第二控制节点与第一电压线之间连通，并在所述第二控制节点的电位的控制下，控制所述第三节点与所述第二时钟信号线之间连通。
  5. 如权利要求4所述的驱动电路，其中，所述第二控制节点控制电路还用于根据所述第三节点的电位控制所述第二控制节点的电位。
  6. 如权利要求1至3中任一权利要求所述的驱动电路，其中，还包括级联输出电路和级联复位电路；
    所述级联输出电路分别与第一节点、进位输出端和第一电压线电连接，用于在所述第一节点的电位的控制下，控制所述进位输出端与第一电压线之间连通；
    所述级联复位电路分别与第二节点、进位输出端和第二电压线电连接，用于在所述第二节点的电位的控制下，控制所述进位输出端与所述第二电压线之间连通。
  7. 如权利要求6所述的驱动电路，其中，所述级联复位电路包括第二晶体管和第三晶体管；
    所述第二晶体管的栅极与所述第二节点电连接，所述第二晶体管的第一极与所述进位输出端电连接，所述第二晶体管的第二极与第四节点电连接；
    所述第三晶体管的栅极与所述第二节点电连接，所述第三晶体管的第一极与所述第四节点电连接，所述第三晶体管的第二极与第二电压线电连接。
  8. 如权利要求7所述的驱动电路，其中，还包括第一控制电路；
    所述第一控制电路分别与第一节点、第三电压线和所述第四节点电连接，用于在所述第一节点的电位的控制下，控制所述第三电压线与所述第四节点之间连通。
  9. 如权利要求8所述的驱动电路，其中，所述第一控制电路包括第四晶体管；
    所述第四晶体管的栅极与第一节点电连接，所述第四晶体管的第一极与第三电压线电连接，所述第四晶体管的第二极与第四节点电连接。
  10. 如权利要求1至3中任一权利要求所述的驱动电路，其中，还包括驱动输出复位电路和第二复位电路；
    所述输出复位电路分别与第二节点、驱动信号输出端和第四电压线电连接，用于在所述第二节点的电位的控制下，将所述驱动信号输出端与所述第四电压线之间连通；
    所述第二复位电路分别与第一节点、第二电压线和第二节点电连接，用于在所述第一节点的电位的控制下，控制所述第二电压线与所述第二节点之 间连通。
  11. 如权利要求10所述的驱动电路，其中，所述输出复位电路包括的晶体管为氧化物晶体管，第二电压线提供的第二电压信号的电压值小于第一电压线提供的第一电压信号的电压值。
  12. 如权利要求10所述的驱动电路，其中，所述输出复位电路包括第五晶体管和第一电容，所述第二复位电路包括第六晶体管；
    所述第五晶体管的栅极与所述第二节点电连接，所述第五晶体管的第一极与所述驱动信号输出端电连接，所述第五晶体管的第二极与所述第四电压线电连接；
    所述第一电容的第一端与第二节点电连接，所述第一电容的第二端与第四电压线电连接；
    所述第六晶体管的栅极与所述第一节点电连接，所述第六晶体管的第一极与第二电压线电连接，所述第六晶体管的第二极与所述第二节点电连接。
  13. 如权利要求1至3中任一权利要求所述的驱动电路，其中，还包括第二控制电路；
    所述第二控制电路分别与第一控制节点、第二时钟信号线、第二电压线和第二控制节点电连接，用于在所述第二控制节点的电位和所述第二时钟信号线提供的第二时钟信号的控制下，控制所述第一控制节点与第二电压线之间连通。
  14. 如权利要求13所述的驱动电路，其中，还包括第三控制电路；
    所述第三控制电路分别与第二时钟信号线、输入线和第一控制节点电连接，用于在所述第二时钟信号的控制下，控制所述输入线与所述第一控制节点之间连通。
  15. 如权利要求14所述的驱动电路，其中，还包括第四控制电路；
    所述第四控制电路分别与第一节点、第一控制节点和第三电压线电连接，用于在所述第一节点的电位的控制下，控制所述第一控制节点与第三电压线之间连通。
  16. 如权利要求4所述的驱动电路，其中，所述第二控制节点控制电路还与输入线电连接，用于在所述输入线提供的输入信号的控制下，控制将第 一时钟信号写入第二控制节点。
  17. 如权利要求16所述的驱动电路，其中，所述第二控制节点控制电路包括第七晶体管和第八晶体管；
    所述第七晶体管的栅极与所述输入线电连接，所述第七晶体管的第一极与所述第一时钟信号线电连接，所述第七晶体管的第二极与所述第八晶体管的第一极电连接；
    所述第八晶体管的栅极与所述输入线电连接，所述第八晶体管的第二极与所述第二控制节点电连接。
  18. 如权利要求10所述的驱动电路，其中，还包括第三复位电路；
    所述第三复位电路分别与第二复位线、第三电压线和第二节点电连接，用于在所述第二复位线提供的第二复位信号的控制下，控制所述第三电压线与第二节点之间连通。
  19. 如权利要求18所述的驱动电路，其中，所述第三复位电路包括第九晶体管和第十晶体管；
    所述第九晶体管的栅极与所述第二复位线电连接，所述第九晶体管的第一极与第三电压线电连接，所述第九晶体管的第二极与所述第十晶体管的第一极电连接；
    所述第十晶体管的栅极与所述第二复位线电连接，所述第十晶体管的第二极与所述第二节点电连接。
  20. 如权利要求4所述的驱动电路，其中，还包括第二隔离电路；
    所述第二隔离电路分别与第二时钟信号线、第三节点和第二节点电连接，用于在所述第二时钟信号线提供的第二时钟信号的控制下，控制所述第三节点与所述第二节点之间连通。
  21. 如权利要求15所述的驱动电路，其中，所述第三控制电路包括第十一晶体管，所述第二控制电路包括第十二晶体管和第十三晶体管，所述第四控制电路包括第十四晶体管；
    所述第十一晶体管的栅极与第二时钟信号线电连接，所述第十一晶体管的第一极与输入线电连接，所述第十一晶体管的第二极与第一控制节点电连接；
    所述第十四晶体管的栅极与第一节点电连接，所述第十四晶体管的第一极与第三电压电连接，所述第十四晶体管的第二极与第一控制节点电连接；
    所述第十二晶体管的栅极与第二时钟信号线电连接，所述第十二晶体管的第一极与第一控制节点电连接，所述第十二晶体管的第二极与所述第十三晶体管的第一极电连接；所述第十三晶体管的栅极与第二控制节点电连接，所述第十三晶体管的第二极与第二电压线电连接；或者，所述第十二晶体管的栅极与所述第二控制节点电连接，所述第十二晶体管的第一极与第一控制节点电连接，所述第十二晶体管的第二极与所述第十三晶体管的第一极电连接；所述第十三晶体管的栅极与第二时钟信号线电连接，所述第十三晶体管的第二极与第二电压线电连接。
  22. 如权利要求1所述的驱动电路，其中，所述驱动输出电路包括第十五晶体管和第二电容，所述第一隔离电路包括第十六晶体管；
    所述第十五晶体管的栅极与第一节点电连接，所述第十五晶体管的第一极与第一电压线或所述第一时钟信号线电连接，所述第十五晶体管的第二极与驱动信号输出端电连接；
    所述第二电容的第一端与第一节点电连接，所述第二电容的第二端与所述驱动信号输出端电连接；
    所述第十六晶体管的控制极与第二时钟信号线电连接，所述第十六晶体管的第一极与第一控制节点电连接，所述第十六晶体管的第二极与第一节点电连接。
  23. 如权利要求5所述的驱动电路，其中，所述第二控制节点控制电路包括第十七晶体管、第三电容和第十八晶体管；
    所述第十七晶体管的栅极与第一时钟信号线电连接，所述第十七晶体管的第一极与第一电压线电连接，所述第十七晶体管的第二极与第二控制节点电连接；
    所述第三电容的第一端与第二控制节点电连接，所述第三电容的第二端与所述第三节点电连接；
    所述第十八晶体管的栅极与所述第二控制节点电连接，所述第十八晶体管的第一极与第二时钟信号线电连接，所述第十八晶体管的第二极与第三节 点电连接。
  24. 如权利要求6所述的驱动电路，其中，所述级联输出电路包括第十九晶体管；
    所述第十九晶体管的栅极与第一节点电连接，所述第十九晶体管的第一极与第一电压线电连接，所述第十九晶体管的第二极与级联输出端电连接。
  25. 如权利要求24所述的驱动电路，其中，所述级联输出电路还包括第四电容；
    所述第四电容的第一端与第一节点电连接，所述第四电容的第二端与级联输出端电连接。
  26. 如权利要求20所述的驱动电路，其中，所述第二隔离电路包括第二十晶体管；
    所述第二十晶体管的栅极与第二时钟信号线电连接，所述第二十晶体管的第一极与第三节点电连接，所述第二十晶体管的第二极与第二节点电连接。
  27. 如权利要求22所述的驱动电路，其中，还包括第二十一晶体管；
    所述第二十一晶体管的栅极与第一高电压线电连接，所述第二十一晶体管的第一极与第十六晶体管的第二极电连接，所述第二十一晶体管的第二极与第一节点电连接。
  28. 一种驱动方法，应用于如权利要求1至27中任一权利要求所述的驱动电路，显示周期包括先后设置的第一阶段、第二阶段和第三阶段，所述驱动方法包括：
    在第一阶段，所述第一复位电路在第一复位线提供的第一复位信号的控制下，控制第一时钟信号线写入第一时钟信号至所述第一控制节点，当第二时钟信号线提供高电压信号时，第一隔离电路在第二时钟信号线提供的第二时钟信号的控制下，控制所述第一控制节点与所述第一节点之间连通；
    在第二阶段，当第二时钟信号线提供高电压信号时，第一隔离电路在第二时钟信号的控制下，控制所述第一控制节点与所述第一节点之间连通；驱动输出电路在所述第一节点的电位的控制下，控制驱动信号输出端与第一电压线之间连通；
    在第三阶段，当第二时钟信号线提供高电压信号时，第一隔离电路在第 二时钟信号的控制下，控制所述第一控制节点与所述第一节点之间连通。
  29. 一种显示基板，包括如权利要求1至27中任一权利要求所述的驱动电路。
  30. 如权利要求29所述的显示基板，其中，还包括多列直流信号线；所述显示基板包括显示区域和周边区域，所述直流信号线和所述驱动电路设置于周边区域；
    所述多列直流信号线中的至少一列直流信号线设置于所述驱动电路远离所述显示区域的一侧，所述多列直流信号线中的除了该至少一列直流信号线之外的直流信号线设置于所述驱动电路靠近所述显示区域的一侧。
  31. 一种显示装置，包括如权利要求29或30所述的显示基板。
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