WO2022082719A1 - 移位寄存器单元、驱动方法、驱动电路和显示装置 - Google Patents

移位寄存器单元、驱动方法、驱动电路和显示装置 Download PDF

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Publication number
WO2022082719A1
WO2022082719A1 PCT/CN2020/123206 CN2020123206W WO2022082719A1 WO 2022082719 A1 WO2022082719 A1 WO 2022082719A1 CN 2020123206 W CN2020123206 W CN 2020123206W WO 2022082719 A1 WO2022082719 A1 WO 2022082719A1
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WIPO (PCT)
Prior art keywords
node
electrically connected
control
transistor
terminal
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PCT/CN2020/123206
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English (en)
French (fr)
Inventor
徐映嵩
张振华
马倩
曹席磊
袁长龙
冯靖伊
黄炜赟
王本莲
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202080002436.8A priority Critical patent/CN114945969B/zh
Priority to US17/598,790 priority patent/US11922845B2/en
Priority to PCT/CN2020/123206 priority patent/WO2022082719A1/zh
Publication of WO2022082719A1 publication Critical patent/WO2022082719A1/zh
Priority to US18/423,236 priority patent/US20240161673A1/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a shift register unit, a driving method, a driving circuit and a display device.
  • the relevant shift register unit cannot provide both the gate driving signal and the light-emitting control signal, and cannot conveniently provide the waveform of a specific pixel operation. Also, the related shift register unit cannot turn on the first output transistor in the output circuit sufficiently, so that the output waveform of the driving voltage signal terminal is depleted by the threshold voltage of the first output transistor.
  • an embodiment of the present disclosure provides a shift register unit, including a first node potential adjustment circuit, a first tank circuit, a second node control circuit, a second tank circuit, a third node control circuit, a first node control circuit and an output circuit; wherein,
  • the first node control circuit is respectively electrically connected to the input terminal, the first clock signal terminal, the first isolation node, the fourth node and the first voltage terminal, and is used for controlling the first clock signal provided at the first clock signal terminal controlling to write the input signal provided by the input terminal into the first isolation node, and under the control of the potential of the fourth node, controlling to write the first voltage signal provided by the first voltage terminal to the first isolation node;
  • the first node potential adjustment circuit is respectively electrically connected to the adjustment clock signal terminal and the first node, and is used for changing the potential of the first node according to the adjustment clock signal provided by the adjustment clock signal terminal under the control of the potential of the first node;
  • the first tank circuit is electrically connected to the first node for maintaining the potential of the first node
  • the third node control circuit is respectively electrically connected to the first clock signal terminal, the second clock signal terminal, the first isolation node, the third isolation node, the fourth node, the first voltage terminal and the second voltage terminal, and is used for Under the control of the first clock signal, the second clock signal and the potential of the first isolation node, the potential of the third isolation node and the potential of the fourth node are controlled;
  • the second node control circuit is respectively electrically connected to the first isolation node, the first voltage terminal, the second isolation node, the control clock signal terminal and the third node, and is used for the potential of the third node and the control clock signal terminal Under the control of the provided control clock signal, the potential of the second isolation node is controlled, and under the control of the potential of the first isolation node, the first voltage signal provided by the first voltage terminal is controlled to be written into the second isolation node;
  • the second tank circuit is used for maintaining the potential of the second node
  • the output circuit is respectively electrically connected with the first node, the second voltage terminal, the driving voltage signal terminal and the third voltage terminal, and is used for converting the second voltage signal provided by the second voltage terminal under the control of the potential of the first node writing the driving voltage signal output terminal, and is used for writing the third voltage signal provided by the third voltage terminal into the driving voltage signal terminal under the control of the potential of the second node;
  • the first isolated node and the first node are the same node; or, the first isolated node and the first node are different nodes.
  • the first isolation node and the first node are different nodes, the first isolation node and the first node are electrically connected through a first isolation circuit;
  • the control terminal of the first isolation circuit is electrically connected to the control voltage terminal, and the first isolation circuit is used to control the first isolation node and the first isolation node under the control of the control voltage signal provided by the control voltage terminal. communication between nodes.
  • the first isolation circuit includes a first isolation transistor
  • the control electrode of the first isolation transistor is electrically connected to the control voltage terminal, the first electrode of the first isolation transistor is electrically connected to the first isolation node, and the second electrode of the first isolation transistor is electrically connected to the first isolation node.
  • a node is electrically connected.
  • the second isolation node and the second node are the same node; or, the second isolation node and the second node are electrically connected through a second circuit;
  • the control terminal of the second isolation circuit is electrically connected to the control voltage terminal, and the second isolation circuit is used to control the second isolation node and the first isolation node under the control of the control voltage signal provided by the control voltage terminal. Connectivity between two nodes.
  • the second isolation circuit includes a second isolation transistor
  • the control electrode of the second isolation transistor is electrically connected to the control voltage terminal, the first electrode of the second isolation transistor is electrically connected to the second isolation node, and the second electrode of the second isolation transistor is electrically connected to the second isolation node.
  • the two nodes are electrically connected.
  • the third isolation node and the third node are the same node; or, the third isolation node and the third node are electrically connected through a third isolation circuit;
  • the control terminal of the third isolation circuit is electrically connected to the control voltage terminal, and the third isolation circuit is used to control the third isolation node and the third isolation node under the control of the control voltage signal provided by the control voltage terminal. Connectivity between three nodes.
  • the third isolation circuit includes a third isolation transistor
  • the control electrode of the third isolation transistor is electrically connected to the control voltage terminal, the first electrode of the third isolation transistor is electrically connected to the third isolation node, and the second electrode of the third isolation transistor is electrically connected to the third isolation node.
  • the three nodes are electrically connected.
  • control clock signal terminal is the second clock signal terminal; or,
  • the driving voltage signal terminal is a light-emitting control signal terminal
  • the control clock signal terminal is a first clock signal terminal.
  • the adjustment clock signal provided by the adjustment clock signal terminal is the second clock signal, or the adjustment clock signal is a clock signal with an inverse phase to the first clock signal.
  • the driving voltage signal terminal is a gate driving signal output terminal, and the third voltage terminal is an output clock signal terminal; the output clock signal provided by the output clock signal terminal is the inverse of the second clock signal. phase clock signal; or,
  • the driving voltage signal terminal is a light-emitting control signal terminal
  • the third voltage terminal is a first voltage terminal
  • the first node potential adjustment circuit includes an adjustment transistor and an adjustment capacitor, wherein,
  • the control electrode of the adjustment transistor is electrically connected to the first isolation node, the first electrode of the adjustment transistor is electrically connected to the adjustment clock signal terminal, and the second electrode of the adjustment transistor is electrically connected to the first end of the adjustment capacitor electrical connection;
  • the second end of the adjustment capacitor is electrically connected to the first isolation node.
  • the second node control circuit is further electrically connected to the first clock signal terminal, and is further configured to control the potential of the second isolation node under the control of the first clock signal.
  • the second node control circuit includes a first control transistor, a control capacitor, a second control transistor and a third control transistor, wherein,
  • the first end of the control capacitor is electrically connected to the third node, and the second end of the control capacitor is electrically connected to the fifth node;
  • the control electrode of the first control transistor is electrically connected to the third node, the first electrode of the first control transistor is electrically connected to the fifth node, and the second electrode of the first control transistor is electrically connected to the control clock
  • the signal terminal is electrically connected;
  • the control electrode of the second control transistor is electrically connected to the second clock signal terminal, the first electrode of the second control transistor is electrically connected to the fifth node, and the second electrode of the second control transistor is electrically connected to the fifth node.
  • the second isolation node is electrically connected;
  • the control electrode of the third control transistor is electrically connected to the first node, the first electrode of the third control transistor is electrically connected to the first voltage terminal, and the second electrode of the third control transistor is electrically connected to the first voltage terminal.
  • the two isolated nodes are electrically connected.
  • the second node control circuit includes a first control transistor, a control capacitor, a second control transistor, a third control transistor and a node control transistor, wherein,
  • the first end of the control capacitor is electrically connected to the third node, and the second end of the control capacitor is electrically connected to the fifth node;
  • the control electrode of the first control transistor is electrically connected to the third node, the first electrode of the first control transistor is electrically connected to the fifth node, and the second electrode of the first control transistor is electrically connected to the control clock
  • the signal terminal is electrically connected;
  • the control electrode of the second control transistor is electrically connected to the second clock signal terminal, the first electrode of the second control transistor is electrically connected to the fifth node, and the second electrode of the second control transistor is electrically connected to the fifth node.
  • the second isolation node is electrically connected;
  • the control electrode of the third control transistor is electrically connected to the first node, and the first electrode of the third control transistor is electrically connected to the first voltage terminal;
  • the control pole of the node control transistor is electrically connected to the first clock signal terminal, the first pole of the node control transistor is electrically connected to the second pole of the third control transistor, and the second pole of the node control transistor is electrically connected to the second pole of the third control transistor.
  • the second node is electrically connected.
  • the second node control circuit includes a first control transistor, a control capacitor, a second control transistor and a third control transistor, wherein,
  • the first end of the control capacitor is electrically connected to the third node
  • the control electrode of the first control transistor is electrically connected to the third node, the first electrode of the first control transistor is electrically connected to the second end of the control capacitor, and the second electrode of the first control transistor is electrically connected is electrically connected to the second clock signal terminal; the control electrode of the second control transistor is electrically connected to the second clock signal terminal, and the first electrode of the second control transistor is electrically connected to the second isolation node;
  • the control electrode of the third control transistor is electrically connected to the first isolation node, the first electrode of the third control transistor is electrically connected to the first voltage terminal, and the second electrode of the third control transistor is electrically connected to the first voltage terminal.
  • the second isolation node is electrically connected.
  • the third node control circuit includes a fourth control transistor, a fifth control transistor and a sixth control transistor, wherein,
  • the control pole of the fourth control transistor is electrically connected to the first clock signal terminal, the first pole of the fourth control transistor is electrically connected to the second voltage terminal, and the second pole of the fourth control transistor is isolated from the third terminal Node electrical connection;
  • the control electrode of the fifth control transistor is electrically connected to the first isolation node, the first electrode of the fifth control transistor is electrically connected to the first voltage terminal, and the second electrode of the fifth control transistor is electrically connected to the fourth node. connect;
  • the control electrode of the sixth control transistor is electrically connected to the second clock signal terminal, the first electrode of the sixth control transistor is electrically connected to the fourth node, and the second electrode of the sixth control transistor is electrically connected to the fourth node.
  • the third isolation node is electrically connected.
  • the shift register unit further includes a third isolation transistor; the third isolation node is a third node;
  • the second pole of the fourth control transistor is electrically connected to the third node through the third isolation transistor;
  • the control electrode of the third isolation transistor is electrically connected to the control voltage terminal, the first electrode of the third isolation transistor is electrically connected to the second electrode of the fourth control transistor, and the second electrode of the third isolation transistor is electrically connected is electrically connected to the third node.
  • the driving voltage signal terminal is a light-emitting control signal terminal
  • the third voltage terminal is a first voltage terminal
  • the third node control circuit includes a fourth control transistor, a fifth control transistor and a sixth control transistor, wherein,
  • the control pole of the fourth control transistor is electrically connected to the second clock signal terminal, the first pole of the fourth control transistor is electrically connected to the second voltage terminal, and the second pole of the fourth control transistor is isolated from the third terminal Node electrical connection;
  • the control electrode of the fifth control transistor is electrically connected to the first isolation node, the first electrode of the fifth control transistor is electrically connected to the first voltage terminal, and the second electrode of the fifth control transistor is electrically connected to the fourth node. connect;
  • the control electrode of the sixth control transistor is electrically connected to the first clock signal terminal, the first electrode of the sixth control transistor is electrically connected to the fourth node, and the second electrode of the sixth control transistor is electrically connected to the fourth node.
  • the third isolation node is electrically connected.
  • the shift register unit further includes a third isolation transistor; the third isolation node is a third node;
  • the second pole of the fourth control transistor is electrically connected to the third node through the third isolation transistor;
  • the control electrode of the third isolation transistor is electrically connected to the control voltage terminal, the first electrode of the third isolation transistor is electrically connected to the second electrode of the fourth control transistor, and the second electrode of the third isolation transistor is electrically connected is electrically connected to the third node.
  • the first node control circuit includes a seventh control transistor and an eighth control transistor, wherein,
  • the control pole of the seventh control transistor is electrically connected to the first clock signal terminal, the first pole of the seventh control transistor is electrically connected to the input terminal, and the second pole of the seventh control transistor is electrically connected to the first clock signal terminal. an isolated node is electrically connected;
  • the control electrode of the eighth control transistor is electrically connected to the fourth node, the first electrode of the eighth control transistor is electrically connected to the first isolation node, and the second electrode of the eighth control transistor is electrically connected to the first isolation node.
  • a voltage terminal is electrically connected.
  • the output circuit includes a first output transistor and a second output transistor
  • the control electrode of the first output transistor is electrically connected to the first node, the first electrode of the first output transistor is electrically connected to the second voltage terminal, and the second electrode of the first output transistor is electrically connected to the driver
  • the voltage signal terminal is electrically connected;
  • the control electrode of the second output transistor is electrically connected to the second node, the first electrode of the second output transistor is electrically connected to the driving voltage signal terminal, and the second electrode of the second output transistor is electrically connected to the drive voltage signal terminal.
  • the third voltage terminal is electrically connected.
  • the first energy storage circuit includes a first storage capacitor
  • the second energy storage circuit includes a second storage capacitor
  • the first end of the first storage capacitor is electrically connected to the first node, and the second end of the first storage capacitor is electrically connected to the second voltage end;
  • the first terminal of the second storage capacitor is electrically connected to the second node, and the second terminal of the second storage capacitor is electrically connected to the third voltage terminal;
  • the driving voltage signal terminal is a gate driving signal output terminal, and the third voltage terminal is an output clock signal terminal; the output clock signal provided by the output clock signal terminal is a clock signal inverted to the second clock signal ;or,
  • the driving voltage signal terminal is a light-emitting control signal terminal
  • the third voltage terminal is a first voltage terminal
  • an embodiment of the present disclosure further provides a driving method, which is applied to the above-mentioned shift register unit, and the driving method includes:
  • the input signal is controlled to be written into the first isolation node, and under the control of the potential of the fourth node, the first voltage signal is controlled to be written into the first isolation node ;
  • the first node potential adjustment circuit changes the potential of the first node according to the adjustment clock signal under the control of the potential of the first node
  • the third node control circuit controls the potential of the third isolation node and the potential of the fourth node under the control of the first clock signal, the second clock signal and the potential of the first isolation node;
  • the second node control circuit controls the potential of the second isolation node under the control of the potential of the third node and the control clock signal, and controls the first voltage signal to be written into the second isolation node under the control of the potential of the first isolation node. isolated node;
  • the second tank circuit maintains the potential of the second node
  • the output circuit writes the second voltage signal into the driving voltage signal output terminal under the control of the potential of the first node, and the output circuit writes the third voltage signal into the drive voltage signal under the control of the potential of the second node Drive voltage signal terminal.
  • an embodiment of the present disclosure further provides a driving circuit, which includes the above-mentioned shift register unit in multiple stages.
  • the driving circuit is a gate driving circuit
  • the driving voltage signal terminal is the gate driving signal output terminal
  • the third voltage terminal is the output clock signal terminal
  • the output clock signal provided by the output clock signal terminal is the same as that of the third voltage terminal.
  • Two clock signals are inverted clock signals.
  • the driving circuit is a lighting control signal generating circuit; the driving voltage signal terminal is the lighting control signal terminal, and the third voltage terminal is the first voltage terminal.
  • an embodiment of the present disclosure further provides a display device including the above-mentioned driving circuit.
  • FIG. 1 is a structural diagram of a shift register unit according to at least one embodiment of the present disclosure
  • FIG. 2 is a structural diagram of a shift register unit according to at least one embodiment of the present disclosure
  • FIG. 3 is a structural diagram of a shift register unit according to at least one embodiment of the present disclosure.
  • FIG. 4 is a structural diagram of a shift register unit according to at least one embodiment of the present disclosure.
  • FIG. 5 is a structural diagram of a shift register unit according to at least one embodiment of the present disclosure.
  • FIG. 6 is a structural diagram of a shift register unit according to at least one embodiment of the present disclosure.
  • FIG. 7 is a structural diagram of a shift register unit according to at least one embodiment of the present disclosure.
  • FIG. 8 is a structural diagram of a shift register unit according to at least one embodiment of the present disclosure.
  • FIG. 9 is a structural diagram of a shift register unit according to at least one embodiment of the present disclosure.
  • FIG. 10 is a structural diagram of a shift register unit according to at least one embodiment of the present disclosure.
  • FIG. 11 is a structural diagram of a shift register unit according to an embodiment of the present disclosure.
  • 14A is a schematic diagram of a circuit state of the first embodiment of the shift register unit described in the present disclosure during a first time period t1;
  • 14B is a schematic diagram of a circuit state of the first embodiment of the shift register unit according to the present disclosure during the second time period t2;
  • 14C is a schematic diagram of the circuit state of the first embodiment of the shift register unit described in the present disclosure during the third time period t3;
  • 14D is a schematic diagram of a circuit state of the first embodiment of the shift register unit described in the present disclosure during a fourth time period t4;
  • 14E is a schematic diagram of a circuit state of the first embodiment of the shift register unit according to the present disclosure during the fifth time period t5;
  • 14F is a schematic diagram of a circuit state of the first embodiment of the shift register unit described in the present disclosure during a sixth time period t6;
  • 14G is a schematic diagram of a circuit state of the first embodiment of the shift register unit according to the present disclosure in a seventh time period t7;
  • 14H is a schematic diagram of a circuit state of the first embodiment of the shift register unit described in the present disclosure during the eighth time period t8;
  • 15 is a circuit diagram of a second embodiment of the shift register unit described in the present disclosure.
  • 16 is a circuit diagram of a third embodiment of the shift register cell described in the present disclosure.
  • 17 is a circuit diagram of a fourth embodiment of the shift register unit described in the present disclosure.
  • 21 is a circuit diagram of a sixth embodiment of the shift register unit described in the present disclosure.
  • 22 is a circuit diagram of a seventh embodiment of the shift register unit described in the present disclosure.
  • FIG. 23 is a circuit diagram of an eighth embodiment of the shift register unit described in the present disclosure.
  • 24 is a circuit diagram of a ninth embodiment of the shift register unit described in the present disclosure.
  • 25 is a circuit diagram of a tenth embodiment of the shift register unit described in the present disclosure.
  • FIG. 26 is a working timing diagram of the tenth embodiment of the shift register unit described in the present disclosure.
  • 27A is a schematic diagram of a circuit state of the tenth embodiment of the shift register unit according to the present disclosure during the first time period t1;
  • 27B is a schematic diagram of a circuit state of the tenth embodiment of the shift register unit according to the present disclosure during the second time period t2;
  • 27C is a schematic diagram of the circuit state of the tenth embodiment of the shift register unit described in the present disclosure during the third time period t3;
  • 27D is a schematic diagram of a circuit state of the tenth embodiment of the shift register unit according to the present disclosure during the fourth time period t4;
  • 27E is a schematic diagram of a circuit state of the tenth embodiment of the shift register unit according to the present disclosure during the fifth time period t5;
  • 29 is a circuit diagram of a twelfth embodiment of the shift register unit described in the present disclosure.
  • FIG. 30 is a circuit diagram of a thirteenth embodiment of the shift register unit described in the present disclosure.
  • 31 is a circuit diagram of a fourteenth embodiment of the shift register cell described in the present disclosure.
  • 32 is a circuit diagram of a fifteenth embodiment of the shift register unit described in the present disclosure.
  • 33 is a circuit diagram of a sixteenth embodiment of a shift register cell according to the present disclosure.
  • the transistors used in all the embodiments of the present disclosure may be triodes, thin film transistors, field effect transistors, or other devices with the same characteristics.
  • one pole is called the first pole, and the other pole is called the second pole.
  • control electrode when the transistor is a triode, the control electrode may be the base electrode, the first electrode may be the collector electrode, and the second electrode may be the emitter electrode; or the control electrode may be the base electrode electrode, the first electrode can be an emitter electrode, and the second electrode can be a collector electrode.
  • the control electrode when the transistor is a thin film transistor or a field effect transistor, the control electrode may be a gate electrode, the first electrode may be a drain electrode, and the second electrode may be a source electrode;
  • the control electrode may be a gate electrode, the first electrode may be a source electrode, and the second electrode may be a drain electrode.
  • the shift register unit described in at least one embodiment of the present disclosure includes a first node potential adjustment circuit, a first tank circuit, a second node control circuit, a second tank circuit, a third node control circuit, and a first node control circuit and output circuit;
  • the first node control circuit is respectively electrically connected to the input terminal, the first clock signal terminal, the first isolation node, the fourth node and the first voltage terminal, and is used for controlling the first clock signal provided at the first clock signal terminal controlling to write the input signal provided by the input terminal into the first isolation node, and under the control of the potential of the fourth node, controlling to write the first voltage signal provided by the first voltage terminal to the first isolation node;
  • the first node potential adjustment circuit is respectively electrically connected to the adjustment clock signal terminal and the first node, and is used for changing the potential of the first node according to the adjustment clock signal provided by the adjustment clock signal terminal under the control of the potential of the first node;
  • the first tank circuit is electrically connected to the first node for maintaining the potential of the first node
  • the third node control circuit is respectively electrically connected to the first clock signal terminal, the second clock signal terminal, the first isolation node, the third isolation node, the fourth node, the first voltage terminal and the second voltage terminal, and is used for Under the control of the first clock signal, the second clock signal and the potential of the first isolation node, the potential of the third isolation node and the potential of the fourth node are controlled;
  • the second node control circuit is respectively electrically connected to the first isolation node, the first voltage terminal, the second isolation node, the control clock signal terminal and the third node, and is used for the potential of the third node and the control clock signal terminal Under the control of the provided control clock signal, the potential of the second isolation node is controlled, and under the control of the potential of the first isolation node, the first voltage signal provided by the first voltage terminal is controlled to be written into the second isolation node;
  • the second tank circuit is used for maintaining the potential of the second node
  • the output circuit is respectively electrically connected with the first node, the second voltage terminal, the driving voltage signal terminal and the third voltage terminal, and is used for converting the second voltage signal provided by the second voltage terminal under the control of the potential of the first node writing the driving voltage signal output terminal, and is used for writing the third voltage signal provided by the third voltage terminal into the driving voltage signal terminal under the control of the potential of the second node;
  • the first isolated node and the first node are the same node; or, the first isolated node and the first node are different nodes.
  • the shift register unit described in at least one embodiment of the present disclosure can provide both a gate driving signal and a light-emitting control signal, so as to provide a waveform of a specific pixel operation; when the shift register unit provides the light-emitting control signal, the The third voltage terminal may be a first voltage terminal; when the shift register unit provides a gate driving signal, the third voltage terminal may be an output clock signal terminal; the output clock signal terminal provided by the output clock signal terminal is a clock signal inverted to the second clock signal.
  • the first node potential adjustment circuit is electrically connected to the adjustment clock signal terminal and the first node, respectively, for the potential at the first node
  • the potential of the first node is changed according to the adjustment clock signal provided by the adjustment clock signal terminal, so that when the first output transistor in the output circuit needs to be turned on, the potential of the first node can drop to a low enough voltage
  • the output waveform of the driving voltage signal terminal is prevented from being depleted by the threshold voltage of the first output transistor; and the shift register unit according to at least one embodiment of the present disclosure can realize a narrow frame design.
  • the first voltage terminal may be a high voltage terminal
  • the second voltage terminal may be a low voltage terminal, but not limited thereto.
  • the shift register unit described in at least one embodiment of the present disclosure can generate a lighting control signal or a gate driving signal, but cannot generate a lighting control signal and a gate driving signal at the same time; when it is necessary to provide a lighting control signal and a gate driving signal at the same time , two shift register units described in at least one embodiment of the present disclosure need to be used.
  • the first isolation node and the first node are different nodes, the first isolation node and the first node are electrically connected through a first isolation circuit;
  • the control terminal of the first isolation circuit is electrically connected to the control voltage terminal, and the first isolation circuit is used to control the first isolation node and the first isolation node under the control of the control voltage signal provided by the control voltage terminal. communication between nodes.
  • the first isolation node and the first node may be the same node; or,
  • the first isolation node may be electrically connected to the first node through a first isolation circuit, so that when the potential of the first node is pulled too low, a transistor whose source or drain is electrically connected to the first node Threshold voltage drift or performance degradation, thus causing the transistor to be turned on incompletely when it needs to be turned on again, avoiding affecting the performance of the shift register unit.
  • the first isolation circuit may include a first isolation transistor
  • the control electrode of the first isolation transistor is electrically connected to the control voltage terminal, the first electrode of the first isolation transistor is electrically connected to the first isolation node, and the second electrode of the first isolation transistor is electrically connected to the first isolation node.
  • a node is electrically connected.
  • the second isolation node and the second node are the same node; or, the second isolation node and the second node are electrically connected through a second circuit;
  • the control terminal of the second isolation circuit is electrically connected to the control voltage terminal, and the second isolation circuit is used to control the second isolation node and the first isolation node under the control of the control voltage signal provided by the control voltage terminal. Connectivity between two nodes.
  • the second isolation node and the second node may be the same node; or,
  • the second isolation node may be electrically connected to the second node through a second isolation circuit, so that when the potential of the second node is pulled too low, a transistor whose source or drain is electrically connected to the second node Threshold voltage drift or performance degradation, thus causing the transistor to be turned on incompletely when it needs to be turned on again, avoiding affecting the performance of the shift register unit.
  • the third isolation circuit may include a third isolation transistor
  • the control electrode of the third isolation transistor is electrically connected to the control voltage terminal, the first electrode of the third isolation transistor is electrically connected to the third isolation node, and the second electrode of the third isolation transistor is electrically connected to the third isolation node.
  • the three nodes are electrically connected.
  • the third isolation node and the third node are the same node; or, the third isolation node and the third node are electrically connected through a third isolation circuit;
  • the control terminal of the third isolation circuit is electrically connected to the control voltage terminal, and the third isolation circuit is used to control the third isolation node and the third isolation node under the control of the control voltage signal provided by the control voltage terminal. Connectivity between three nodes.
  • the third isolation node and the third node may be the same node; or,
  • the third isolation node may be electrically connected to the third node through a third isolation circuit, so that when the potential of the third node is pulled too low, a transistor whose source or drain is electrically connected to the third node Threshold voltage drift or performance degradation, thus causing the transistor to be turned on incompletely when it needs to be turned on again, avoiding affecting the performance of the shift register unit.
  • the third isolation circuit may include a third isolation transistor
  • the control electrode of the third isolation transistor is electrically connected to the control voltage terminal, the first electrode of the third isolation transistor is electrically connected to the third isolation node, and the second electrode of the third isolation transistor is electrically connected to the third isolation node.
  • the three nodes are electrically connected.
  • control clock signal terminal may be the second clock signal terminal; or,
  • the driving voltage signal terminal is a light-emitting control signal terminal, and the control clock signal terminal may be a first clock signal terminal.
  • the adjustment clock signal provided by the adjustment clock signal terminal is the second clock signal, or the adjustment clock signal is a clock signal with an inverse phase to the first clock signal.
  • the driving voltage signal terminal is a gate driving signal output terminal
  • the third voltage terminal is an output clock signal terminal
  • the output clock signal provided by the output clock signal terminal is the same as that of the output clock signal terminal.
  • the driving voltage signal terminal is a light-emitting control signal terminal
  • the third voltage terminal is a first voltage terminal
  • the shift register unit includes a first node potential adjustment circuit 11 , a first tank circuit 12 , a second node control circuit 13 , a second tank circuit 14 , a Three-node control circuit 15, first node control circuit 16 and output circuit 17; wherein,
  • the first node control circuit 16 is respectively electrically connected to the input terminal I1, the first clock signal terminal CK, the first node N1, the fourth node N4 and the first voltage terminal V1, and is used for the voltage provided by the first clock signal terminal CK. Under the control of the first clock signal, the input signal provided by the input terminal I1 is controlled to be written into the first node N1, and under the control of the potential of the fourth node N4, the first voltage provided by the first voltage terminal V1 is controlled to be written The signal is written to the first node N1;
  • the first node potential adjustment circuit 11 is respectively electrically connected to the second clock signal terminal CB and the first node N1, and is used for, under the control of the potential of the first node N1, according to the first clock signal terminal CB provided by the second clock signal terminal CB. Two clock signals change the potential of the first node N1;
  • the first energy storage circuit 12 is electrically connected to the first node N1 for maintaining the potential of the first node N1;
  • the third node control circuit 15 is respectively connected with the first clock signal terminal CK, the second clock signal terminal CB, the first node N1, the third node N3, the fourth node N4, the first voltage terminal V1 and the second voltage terminal V2. ) is electrically connected for controlling the potential of the third node N3 and the potential of the fourth node N4 under the control of the first clock signal, the second clock signal and the potential of the first node N1;
  • the second node control circuit 13 is electrically connected to the first node N1, the first voltage terminal V1, the second node N2, the second clock signal terminal CB and the third node N3, respectively, for the potential and the third node N3. Under the control of the second clock signal, the potential of the second node N2 is controlled, and under the control of the potential of the first node N1, the first voltage signal provided by the first voltage terminal V1 is controlled to be written into the second node N2;
  • the second energy storage circuit 14 is electrically connected to the second node N2 for maintaining the potential of the second node N2;
  • the output circuit 17 is respectively electrically connected to the first node N1, the second voltage terminal V2, the driving voltage signal terminal O1 and the first voltage terminal V1, and is used to connect the second voltage terminal to the voltage of the first node N1 under the control of the potential of the first node N1.
  • the second voltage signal provided by V2 is written into the driving voltage signal output terminal O1, and is used to write the first voltage signal provided by the first voltage terminal V1 into the driving voltage signal terminal under the control of the potential of the second node N2.
  • the first isolation node and the first node are the same node
  • the second isolation node and the second node are the same node
  • the third isolation node and the third isolation node are the same node.
  • Three nodes are the same node, but not limited thereto.
  • the third voltage terminal is the first voltage terminal
  • the shift register unit shown in FIG. 1 is used to generate a light-emitting control signal
  • the shift register unit shown in FIG. 1 is for light-emitting control A shift register unit in a signal generation circuit.
  • control clock signal terminal is the second clock signal terminal
  • adjustment clock signal terminal is the second clock signal terminal
  • the second node control circuit may be further electrically connected to the first clock signal terminal, and is also used for generating a first clock signal at the first clock signal end. Under the control of the signal, the potential of the second isolation node is controlled.
  • the second node control circuit 13 is also electrically connected to the first clock signal terminal CK, and is also used for the first clock signal Under the control of , the potential of the second node N2 is controlled.
  • the embodiment of the shift register unit shown in FIG. 3 is different from the embodiment of the shift register unit shown in FIG. 1 in that: the control clock signal terminal is the first clock signal terminal CK;
  • the second node control circuit 13 is respectively electrically connected to the first node N1, the first voltage terminal V1, the second node N2, the first clock signal terminal CK and the third node N3, for the potential and the third node N3. Under the control of the first clock signal, the potential of the second node N2 is controlled, and under the control of the potential of the first node N1, the first voltage signal provided by the first voltage terminal V1 is controlled to be written into the second node N2.
  • the difference from the embodiment of the shift register unit shown in FIG. 1 is that the first node N1 and the first isolation node are not the same node;
  • At least one embodiment of the shift register unit further includes a first isolation circuit 41; the first node N1 is electrically connected to the first isolation node N01 through the first isolation circuit 41;
  • the control terminal of the first isolation circuit 41 is electrically connected to the control voltage terminal V0.
  • the first node N1 and the first isolation node are not the same node, and the third node N3 and the third isolation node are not the same node;
  • At least one embodiment of the shift register unit further includes a first isolation circuit 41 and a third isolation circuit 43; the first node N1 is electrically connected to the first isolation node N01 through the first isolation circuit 41; the third node N3 is electrically connected to the third isolation node N03 through the third isolation circuit 43;
  • the control terminal of the first isolation circuit 41 is electrically connected to the control voltage terminal V0, and the control terminal of the third isolation circuit 43 is electrically connected to the control voltage terminal V0.
  • the control voltage terminal may be low voltage terminal
  • the control voltage terminal may be a high voltage terminal
  • At least one embodiment of the shift register unit further includes a second isolation circuit 42;
  • the second isolation node N02 is electrically connected to the second node N2 through the second isolation circuit 42;
  • the control terminal of the second isolation circuit 42 is electrically connected to the control voltage terminal V0.
  • the control voltage terminal may be a low voltage terminal
  • the control voltage terminal may be a high voltage terminal
  • the shift register unit described in at least one embodiment of the present disclosure includes a first node potential adjustment circuit 11 , a first energy storage circuit 12 , a second node control circuit 13 , a second energy storage circuit 14 , a first energy storage circuit 14 , and a second energy storage circuit 14 .
  • the first node control circuit 16 is respectively electrically connected to the input terminal I1, the first clock signal terminal CK, the first node N1, the fourth node N4 and the first voltage terminal V1, and is used for the voltage provided by the first clock signal terminal CK. Under the control of the first clock signal, the input signal provided by the input terminal I1 is controlled to be written into the first node N1, and under the control of the potential of the fourth node N4, the first voltage provided by the first voltage terminal V1 is controlled to be written The signal is written to the first node N1;
  • the first node potential adjustment circuit 11 is respectively electrically connected to the second clock signal terminal CB and the first node N1, and is used for, under the control of the potential of the first node N1, according to the first clock signal terminal CB provided by the second clock signal terminal CB. Two clock signals change the potential of the first node N1;
  • the first energy storage circuit 12 is electrically connected to the first node N1 for maintaining the potential of the first node N1;
  • the third node control circuit 15 is respectively connected with the first clock signal terminal CK, the second clock signal terminal CB, the first node N1, the third node N3, the fourth node N4, the first voltage terminal V1 and the second voltage terminal V2. ) is electrically connected for controlling the potential of the third node N3 and the potential of the fourth node N4 under the control of the first clock signal, the second clock signal and the potential of the first node N1;
  • the second node control circuit 13 is electrically connected to the first node N1, the first voltage terminal V1, the second node N2, the second clock signal terminal CB and the third node N3, respectively, for the potential and the third node N3. Under the control of the second clock signal, the potential of the second node N2 is controlled, and under the control of the potential of the first node N1, the first voltage signal provided by the first voltage terminal V1 is controlled to be written into the second node N2;
  • the second energy storage circuit 14 is electrically connected to the second node N2 for maintaining the potential of the second node N2;
  • the output circuit 17 is respectively electrically connected with the first node N1, the second voltage terminal V2, the driving voltage signal terminal O1 and the output clock signal terminal CBo, and is used for connecting the second voltage terminal under the control of the potential of the first node N1.
  • the second voltage signal provided by V2 is written into the driving voltage signal output terminal O1, and is used to write the output clock signal provided by the output clock signal terminal CBo into the driving voltage signal terminal O1 under the control of the potential of the second node N2.
  • the first isolation node and the first node are the same node
  • the second isolation node and the second node are the same node
  • the third isolation node and the third isolation node are the same node.
  • Three nodes are the same node, but not limited thereto.
  • control clock signal terminal is the second clock signal terminal
  • adjustment clock signal terminal is the second clock signal terminal
  • the shift register unit is used to provide a gate driving signal
  • the shift register unit is a shift register unit in a gate driving circuit
  • the third voltage terminal is an output clock signal terminal
  • the output clock signal provided by the output clock signal terminal is a clock signal with an inverse phase to the second clock signal.
  • the difference from the embodiment of the shift register unit shown in FIG. 7 is that the first node N1 and the first isolation node are not the same node;
  • At least one embodiment of the shift register unit further includes a first isolation circuit 41 ; the first node N1 is electrically connected to the first isolation node N01 through the first isolation circuit 41 .
  • the first node N1 and the first isolation node are not the same node, and the third node N3 and the third isolation node are not the same node;
  • At least one embodiment of the shift register unit further includes a first isolation circuit 41 and a third isolation circuit 43; the first node N1 is electrically connected to the first isolation node N01 through the first isolation circuit 41; the third node N3 is electrically connected to the third isolation node N03 through the third isolation circuit 43;
  • the control terminal of the first isolation circuit 41 is electrically connected to the control voltage terminal V0, and the control terminal of the third isolation circuit 43 is electrically connected to the control voltage terminal V0.
  • the control voltage terminal may be low voltage terminal
  • the control voltage terminal may be a high voltage terminal
  • At least one embodiment of the shift register unit further includes a second isolation circuit 42;
  • the second isolation node N02 is electrically connected to the second node N2 through the second isolation circuit 42;
  • the control electrode of the second isolation circuit 42 is electrically connected to the control voltage terminal V0.
  • the control voltage terminal may be a low voltage terminal
  • the control voltage terminal may be a high voltage terminal
  • the difference from the embodiment of the shift register unit shown in FIG. 10 is that the adjustment clock signal terminal is not the second clock signal terminal CB, but the third clock signal terminal CKo;
  • the first node potential adjustment circuit 11 is electrically connected to the third clock signal terminal CKo and the first node N1, respectively, and is used for, under the control of the potential of the first node N1, according to the first node provided by the third clock signal terminal CKo. Three clock signals change the potential of the first node N1;
  • the third clock signal is inverted from the first clock signal.
  • the first node potential adjustment circuit may include an adjustment transistor and an adjustment capacitor, wherein,
  • the control electrode of the adjustment transistor is electrically connected to the first isolation node, the first electrode of the adjustment transistor is electrically connected to the adjustment clock signal terminal, and the second electrode of the adjustment transistor is electrically connected to the first end of the adjustment capacitor electrical connection;
  • the second end of the adjustment capacitor is electrically connected to the first isolation node.
  • the second node control circuit may include a first control transistor, a control capacitor, a second control transistor and a third control transistor, wherein,
  • the first end of the control capacitor is electrically connected to the third node, and the second end of the control capacitor is electrically connected to the fifth node;
  • the control electrode of the first control transistor is electrically connected to the third node, the first electrode of the first control transistor is electrically connected to the fifth node, and the second electrode of the first control transistor is electrically connected to the control clock
  • the signal terminal is electrically connected;
  • the control electrode of the second control transistor is electrically connected to the second clock signal terminal, the first electrode of the second control transistor is electrically connected to the fifth node, and the second electrode of the second control transistor is electrically connected to the fifth node.
  • the second isolation node is electrically connected;
  • the control electrode of the third control transistor is electrically connected to the first node, the first electrode of the third control transistor is electrically connected to the first voltage terminal, and the second electrode of the third control transistor is electrically connected to the first voltage terminal.
  • the two isolated nodes are electrically connected.
  • the second node control circuit includes a first control transistor, a control capacitor, a second control transistor and a third control transistor, wherein,
  • the first end of the control capacitor is electrically connected to the third node
  • the control electrode of the first control transistor is electrically connected to the third node, the first electrode of the first control transistor is electrically connected to the second end of the control capacitor, and the second electrode of the first control transistor is electrically connected is electrically connected to the second clock signal terminal; the control electrode of the second control transistor is electrically connected to the control clock signal terminal, and the first electrode of the second control transistor is electrically connected to the second isolation node;
  • the control electrode of the third control transistor is electrically connected to the first isolation node, the first electrode of the third control transistor is electrically connected to the first voltage terminal, and the second electrode of the third control transistor is electrically connected to the first voltage terminal.
  • the second isolation node is electrically connected.
  • the second node control circuit is further electrically connected to the first clock signal terminal, and is further configured to control the potential of the second isolation node under the control of the first clock signal.
  • the shift register unit is a shift register unit in a light-emitting control signal generating circuit
  • the second node control circuit includes a first control transistor, a control capacitor, a second control transistor, a third control transistor and a node control transistor ,in,
  • the first end of the control capacitor is electrically connected to the third node, and the second end of the control capacitor is electrically connected to the fifth node;
  • the control electrode of the first control transistor is electrically connected to the third node, the first electrode of the first control transistor is electrically connected to the fifth node, and the second electrode of the first control transistor is electrically connected to the second node.
  • the clock signal terminal is electrically connected;
  • the control electrode of the second control transistor is electrically connected to the second clock signal terminal, the first electrode of the second control transistor is electrically connected to the fifth node, and the second electrode of the second control transistor is electrically connected to the fifth node.
  • the second isolation node is electrically connected;
  • the control electrode of the third control transistor is electrically connected to the first node, and the first electrode of the third control transistor is electrically connected to the first voltage terminal;
  • the control pole of the node control transistor is electrically connected to the first clock signal terminal, the first pole of the node control transistor is electrically connected to the second pole of the third control transistor, and the second pole of the node control transistor is electrically connected to the second pole of the third control transistor.
  • the second node is electrically connected.
  • the third node control circuit includes a fourth control transistor, a fifth control transistor and a sixth control transistor, wherein,
  • the control pole of the fourth control transistor is electrically connected to the first clock signal terminal, the first pole of the fourth control transistor is electrically connected to the second voltage terminal, and the second pole of the fourth control transistor is isolated from the third terminal Node electrical connection;
  • the control electrode of the fifth control transistor is electrically connected to the first isolation node, the first electrode of the fifth control transistor is electrically connected to the first voltage terminal, and the second electrode of the fifth control transistor is electrically connected to the fourth node. connect;
  • the control electrode of the sixth control transistor is electrically connected to the second clock signal terminal, the first electrode of the sixth control transistor is electrically connected to the fourth node, and the second electrode of the sixth control transistor is electrically connected to the fourth node.
  • the third isolation node is electrically connected.
  • the shift register unit may further include a third isolation transistor; the third isolation node is a third node;
  • the second pole of the fourth control transistor is electrically connected to the third node through the third isolation transistor;
  • the control electrode of the third isolation transistor is electrically connected to the control voltage terminal, the first electrode of the third isolation transistor is electrically connected to the second electrode of the fourth control transistor, and the second electrode of the third isolation transistor is electrically connected is electrically connected to the third node.
  • the driving voltage signal terminal is a light-emitting control signal terminal
  • the third voltage terminal is a first voltage terminal
  • the third node control circuit includes a fourth control transistor, a fifth control transistor and a sixth control transistor, wherein,
  • the control pole of the fourth control transistor is electrically connected to the second clock signal terminal, the first pole of the fourth control transistor is electrically connected to the second voltage terminal, and the second pole of the fourth control transistor is isolated from the third terminal Node electrical connection;
  • the control electrode of the fifth control transistor is electrically connected to the first isolation node, the first electrode of the fifth control transistor is electrically connected to the first voltage terminal, and the second electrode of the fifth control transistor is electrically connected to the fourth node. connect;
  • the control electrode of the sixth control transistor is electrically connected to the first clock signal terminal, the first electrode of the sixth control transistor is electrically connected to the fourth node, and the second electrode of the sixth control transistor is electrically connected to the fourth node.
  • the third isolation node is electrically connected.
  • the shift register unit may further include a third isolation transistor; the third isolation node is a third node;
  • the second pole of the fourth control transistor is electrically connected to the third node through the third isolation transistor;
  • the control electrode of the third isolation transistor is electrically connected to the control voltage terminal, the first electrode of the third isolation transistor is electrically connected to the second electrode of the fourth control transistor, and the second electrode of the third isolation transistor is electrically connected is electrically connected to the third node.
  • the first node control circuit includes a seventh control transistor and an eighth control transistor, wherein,
  • the control pole of the seventh control transistor is electrically connected to the first clock signal terminal, the first pole of the seventh control transistor is electrically connected to the input terminal, and the second pole of the seventh control transistor is electrically connected to the first clock signal terminal. an isolated node is electrically connected;
  • the control electrode of the eighth control transistor is electrically connected to the fourth node, the first electrode of the eighth control transistor is electrically connected to the first isolation node, and the second electrode of the eighth control transistor is electrically connected to the first isolation node.
  • a voltage terminal is electrically connected.
  • the output circuit includes a first output transistor and a second output transistor
  • the control electrode of the first output transistor is electrically connected to the first node, the first electrode of the first output transistor is electrically connected to the second voltage terminal, and the second electrode of the first output transistor is electrically connected to the driver
  • the voltage signal terminal is electrically connected;
  • the control electrode of the second output transistor is electrically connected to the second node, the first electrode of the second output transistor is electrically connected to the driving voltage signal terminal, and the second electrode of the second output transistor is electrically connected to the drive voltage signal terminal.
  • the third voltage terminal is electrically connected.
  • the first tank circuit may include a first storage capacitor
  • the second tank circuit may include a second storage capacitor
  • the first end of the first storage capacitor is electrically connected to the first node, and the second end of the first storage capacitor is electrically connected to the second voltage terminal;
  • the first terminal of the second storage capacitor is electrically connected to the second node, and the second terminal of the second storage capacitor is electrically connected to the third voltage terminal.
  • the first node potential adjustment circuit 11 includes an adjustment transistor T10 and an adjustment capacitor C2, wherein,
  • the gate of the adjustment transistor T10 is electrically connected to the first node N1, the source of the adjustment transistor T10 is electrically connected to the second clock signal terminal CB, and the drain of the adjustment transistor T10 is electrically connected to the adjustment capacitor C2 The first end of the electrical connection;
  • the second end of the adjustment capacitor C2 is electrically connected to the first node N1;
  • the second node control circuit 13 includes a first control transistor T11, a control capacitor C1, a second control transistor T8 and a third control transistor T9, wherein,
  • the first end of the control capacitor C1 is electrically connected to the third node N3, and the second end of the control capacitor C1 is electrically connected to the fifth node N5;
  • the gate of the first control transistor T11 is electrically connected to the third node N3, the drain of the first control transistor T11 is electrically connected to the fifth node N5, and the source of the first control transistor T11 electrically connected to the second clock signal terminal CB;
  • the gate of the second control transistor T8 is electrically connected to the second clock signal terminal CB, the source of the second control transistor T8 is electrically connected to the fifth node N5, and the second control transistor T8 is the drain is electrically connected to the second node N2;
  • the gate of the third control transistor T9 is electrically connected to the first node N1, the source of the third control transistor T9 is electrically connected to the high voltage terminal V01, and the drain of the third control transistor T9 is electrically connected to the high voltage terminal V01. the second node N2 is electrically connected;
  • the third node control circuit 15 includes a fourth control transistor T2, a fifth control transistor T5 and a sixth control transistor T6, wherein,
  • the gate of the fourth control transistor T2 is electrically connected to the first clock signal terminal CK, the source of the fourth control transistor T2 is electrically connected to the low voltage terminal V02, and the drain of the fourth control transistor T2 is electrically connected to the first clock signal terminal CK.
  • the gate of the fifth control transistor T5 is electrically connected to the first node N1, the source of the fifth control transistor T5 is electrically connected to the high voltage terminal V01, and the drain of the fifth control transistor T5 is electrically connected to the fourth node N4 electrical connection;
  • the gate of the sixth control transistor T6 is electrically connected to the second clock signal terminal CB, the source of the sixth control transistor T6 is electrically connected to the fourth node N4, and the drain of the sixth control transistor T6 electrically connected to the third node N3;
  • the first node control circuit 16 includes a seventh control transistor T1 and an eighth control transistor T7, wherein,
  • the gate of the seventh control transistor T1 is electrically connected to the first clock signal terminal CK, the source of the seventh control transistor T1 is electrically connected to the input terminal I1, and the drain of the seventh control transistor T1 is electrically connected to the input terminal I1.
  • the first node N1 is electrically connected;
  • the gate of the eighth control transistor T7 is electrically connected to the fourth node N4, the drain of the eighth control transistor T7 is electrically connected to the first node N1, and the source of the eighth control transistor T7 It is electrically connected to the high voltage terminal V01;
  • the output circuit 17 includes a first output transistor T3 and a second output transistor T4;
  • the gate of the first output transistor T3 is electrically connected to the first node N1, the source of the first output transistor T3 is electrically connected to the low voltage terminal V02, and the drain of the first output transistor T3 is electrically connected to the first node N1.
  • the driving voltage signal terminal O1 is electrically connected;
  • the gate of the second output transistor T4 is electrically connected to the second node N2, the drain of the second output transistor T4 is electrically connected to the driving voltage signal terminal O1, and the source of the second output transistor T4 The pole is electrically connected with the high voltage terminal V01;
  • the first energy storage circuit 12 includes a first storage capacitor C4, and the second energy storage circuit 14 includes a second storage capacitor C3;
  • the first terminal of the first storage capacitor C4 is electrically connected to the first node N1, and the second terminal of the first storage capacitor C4 is electrically connected to the low voltage terminal V02;
  • the first terminal of the second storage capacitor C3 is electrically connected to the second node N2, and the second terminal of the second storage capacitor C3 is electrically connected to the high voltage terminal V01.
  • the high voltage terminal may provide a high voltage signal
  • the low voltage terminal may provide a low voltage signal
  • the first embodiment of the shift register unit described in the present disclosure is a shift register unit in a light-emitting control signal generating circuit, which is used for generating a light-emitting control signal.
  • all transistors are p-type thin film transistors, but not limited thereto.
  • the shift register unit when used to generate the light-emitting control signal, the shift register unit may only use two clock signals, but is not limited thereto.
  • the display period when the first embodiment of the shift register unit described in the present disclosure is in operation, the display period includes a first time period t1 , a second time period t2 , a third time period t3 , and a fourth time period t4 , the fifth time period t5, the sixth time period t6, the seventh time period t7 and the eighth time period t8, wherein,
  • CK provides a low voltage signal
  • CB provides a high voltage signal (the potential of the high voltage signal provided by CB is VH)
  • I1 provides a low voltage signal
  • T6 is turned off
  • T8 is turned off
  • T1 Turn on
  • the potential of N1 is a low voltage
  • the potential of N2 is a high voltage
  • T2 is turned on
  • the potential of N3 is a low voltage
  • the potential of N4 is maintained at a high voltage
  • T4 is turned off
  • T3 is turned on
  • O1 outputs a low voltage
  • due to The potential of N1 will not drop low enough, so the low voltage output by O1 has a threshold voltage loss
  • the voltage value of the voltage signal output by O1 is VL-Vth, where Vth is the threshold voltage of T3; VL is the low voltage provided by V02 The voltage value of the signal;
  • the potential of N1 is VL
  • the potential of N2 is VH
  • the potential of N3 is VL
  • the potential of N4 is VH
  • the potential of N5 is VH
  • CK provides a high voltage signal
  • CB provides a low voltage signal (the voltage value of the low voltage signal provided by CB is VL)
  • I1 provides a low voltage signal, as shown in FIG. 14B
  • T1 is turned off
  • T2 is turned off Since the second clock signal provided by CB is reduced from the high voltage signal of t1 to the low voltage signal, the potential of N1 is correspondingly reduced, so that the potential of N1 is a low voltage.
  • the potential of N1 is (VL-VH)C2z/( C2z+C4z)+VL;
  • VH is the voltage value of the high voltage signal
  • VL is the voltage value of the low voltage signal
  • C2z is the capacitance value of C2
  • C4z is the capacitance value of C4
  • T5 and T6 are turned on, and the high voltage signal V01 Write N3, T11 is turned off, T8 and T9 are turned on, so that the potential of N2 is a high voltage
  • the potential of the second clock signal provided by CB is reduced from a high voltage to a low voltage
  • the potential of N1 is further reduced, so that T3 It can be fully opened, O1 outputs low voltage, and the voltage value of the voltage signal output by O1 is VL;
  • the potential of N2 is VH
  • the potential of N3 is VH
  • the potential of N4 is VH
  • the potential of N5 is VH
  • CK provides a low voltage signal
  • CB provides a high voltage signal (the potential of the high voltage signal provided by CB is VH)
  • I1 provides a high voltage signal.
  • T1 is turned on to provide I1 with a high voltage signal.
  • the high voltage signal is written to N1, T5 is turned off, T6 is turned off, N4 is floating, T2 is turned on, the potential of N3 is low voltage, T11 is turned on, so that the potential of N5 is high voltage, T8 is turned off, T9 is turned off, T10 is turned off, T3 is turned off, and T4 is turned off. Due to the parasitic capacitance of the circuit, the signal output by O1 maintains the state of the previous period of time, O1 outputs a low voltage, and the voltage value of the voltage signal output by O1 is VL;
  • the potential of N1 is VH
  • the potential of N2 is maintained at the potential of the previous period
  • the potential of N2 is VH
  • the potential of N3 is VL
  • the potential of N4 is unknown
  • the potential of N5 is VH
  • CK provides a high voltage signal
  • CB provides a low voltage signal (the voltage value of the low voltage signal provided by CB is VL)
  • I1 provides a high voltage signal
  • T1 is turned off
  • T2 is turned off off
  • T9 is turned off
  • T11 is turned on
  • the low voltage signal provided by CB is written into C1 to further reduce the potential of N3 to VL+VL-VH
  • T8 is turned on
  • the low voltage signal provided by CB charges C3 through the turned on T8 , to ensure that the potential of N2 is a low voltage
  • T6 is turned on, the potential of N4 is a low voltage
  • T7 is turned on
  • T10 is turned off
  • the potential of N1 is a high voltage
  • T3 is turned off
  • T4 is turned on
  • O1 outputs a high voltage
  • the potential of N1 is VH
  • the potential of N2 is VL
  • the potential of N4 is approximately equal to VL
  • the potential of N5 is VL
  • CK provides a high voltage signal
  • CB provides a high voltage signal
  • T1 is turned off
  • T2 is turned off
  • T6 is turned off
  • the potential of N1 is maintained high by C4 voltage
  • the potential of N2 is maintained as a low voltage by C3
  • N4 is floating
  • the potential of N3 is a low voltage
  • O1 maintains a high voltage output
  • CK provides a low voltage signal
  • CB provides a high voltage signal
  • I1 provides a high voltage signal
  • T1 and T2 are turned on, the potential of N1 is a high voltage
  • T8 is turned off
  • T9 is turned off
  • the potential of N2 is maintained at a low voltage
  • the potential of N3 is a low voltage
  • N4 is floating
  • T3 is turned off
  • T4 is turned on
  • O1 outputs a high voltage
  • the potential of N1 is VH
  • the potential of N2 is VL
  • the potential of N3 is VL
  • the potential of N4 is unknown
  • the potential of N5 is VH
  • CK provides a high voltage signal
  • CB provides a low voltage signal
  • T1 and T2 are turned off
  • the potential of N1 is maintained at a high voltage, as shown in FIG. 14F
  • T6 is turned on
  • T11 is turned on
  • the signal is written to C1 to further reduce the potential of N3 to VL+VL-VH
  • T8 is turned on.
  • the low-voltage signal provided by CB charges C3 through the turned-on T8 to ensure that the potential of N2 is a low voltage
  • T6 is turned on
  • N4 The potential is low voltage
  • T7 is turned on
  • T3 is turned off
  • T4 is turned on
  • O1 outputs a high voltage
  • the potential of N1 is VH
  • the potential of N2 is VL
  • the potential of N3 is 2VL-VH
  • the potential of N4 is VL
  • the potential of N5 is VL;
  • CK provides a low voltage signal
  • CB provides a high voltage signal
  • I1 provides a low voltage signal.
  • both T1 and T2 are turned on, the potential of N1 is a low voltage, T10 is turned on, and T9 is turned on, T8 is turned off, and the potential of N2 is a high voltage.
  • the voltage value of the voltage signal output by O1 is VL-Vth, where Vth is the threshold voltage of T3;
  • the potential of N1 is VL
  • the potential of N2 is VH
  • the potential of N3 is approximately equal to VL
  • the potential of N4 is VH
  • the potential of N5 is VH
  • CK provides a high voltage signal
  • CB provides a low voltage signal
  • I1 provides a low voltage signal.
  • T1 and T2 are turned off, and T10 is turned on. Since the second clock signal provided by CB is powered by the upper A high-voltage signal for a period of time is converted into a low-voltage signal, and the potential of N1 is pulled lower, so that T3 can be fully turned on; T9 is turned on, T11 is turned off, and the potential of N2 is a high voltage. Since T8 is turned on, the voltage of N3 is turned on. The potential is high voltage, T5 and T6 are turned on, the potential of N4 is high voltage, T3 is turned on, T4 is turned off, and the voltage value of the voltage signal output by O1 is VL;
  • the potential of N1 is VL
  • the potential of N2 is VH
  • the potential of N3 is VH
  • the potential of N4 is VH
  • the potential of N5 is VH.
  • Vth since the value of Vth is small, the difference between VL and VL-Vth cannot be seen in the corresponding timing diagram.
  • the high voltage value of each clock signal may be VH, and the low voltage value of each clock signal may be VL, but not limited thereto.
  • the differences between the second embodiment of the shift register unit described in the present disclosure and the first embodiment of the shift register unit described in the present disclosure are as follows: the position of C1;
  • the first terminal of C1 is electrically connected to the third node N3, the second terminal of C1 is electrically connected to the drain of T11, and N3 is directly electrically connected to the source of T8. .
  • the operation timing diagram of the second embodiment of the shift register unit shown in FIG. 15 may also be shown in FIG. 13 , but it is not limited thereto.
  • the potential of the N3 point is realized according to the second clock signal provided by the CB Jump, the jump value is (VL-VH+VL), because in the previous time period (that is, the third time period t3), the potential of N2 is VH, so the potential of the second clock signal provided by CB is changed by The high level jumps to a low level, and the voltage value is distributed according to the ratio of the capacitance value;
  • the potential of N3 is equal to the potential of N2, and the potential of N2 is equal to [(2VL-VH) ⁇ C1z+VH ⁇ C3z]/(C1z+C3z), where C1z is the capacitance value of C1 , C3z is the capacitance value of C3.
  • C1z is the capacitance value of C1
  • C3z is the capacitance value of C3.
  • the first node potential adjustment circuit 11 includes an adjustment transistor T10 and an adjustment capacitor C2, wherein,
  • the gate of the adjustment transistor T10 is electrically connected to the first node N1, the source of the adjustment transistor T10 is electrically connected to the second clock signal terminal CB, and the drain of the adjustment transistor T10 is electrically connected to the adjustment capacitor C2 The first end of the electrical connection;
  • the second end of the adjustment capacitor C2 is electrically connected to the first node N1;
  • the second node control circuit 13 includes a first control transistor T11, a control capacitor C1, a second control transistor T8, a node control transistor T0 and a third control transistor T9, wherein,
  • the first end of the control capacitor C1 is electrically connected to the third node N3, and the second end of the control capacitor C1 is electrically connected to the fifth node N5;
  • the gate of the first control transistor T11 is electrically connected to the third node N3, the drain of the first control transistor T11 is electrically connected to the fifth node N5, and the source of the first control transistor T11 electrically connected to the second clock signal terminal CB;
  • the gate of the second control transistor T8 is electrically connected to the second clock signal terminal CB, the source of the second control transistor T8 is electrically connected to the fifth node N5, and the second control transistor T8 is the drain is electrically connected to the second node N2;
  • the gate of the third control transistor T9 is electrically connected to the first node N1, and the source of the third control transistor T9 is electrically connected to the high voltage terminal V01;
  • the gate of the node control transistor T0 is electrically connected to the first clock signal terminal CK, the source of the node control transistor T0 is electrically connected to the drain of the third control transistor T9, and the drain of the node control transistor T0 The pole is electrically connected to the second node N2;
  • the third node control circuit 15 includes a fourth control transistor T2, a fifth control transistor T5 and a sixth control transistor T6, wherein,
  • the gate of the fourth control transistor T2 is electrically connected to the first clock signal terminal CK, the source of the fourth control transistor T2 is electrically connected to the low voltage terminal V02, and the drain of the fourth control transistor T2 is electrically connected to the first clock signal terminal CK.
  • the gate of the fifth control transistor T5 is electrically connected to the first node N1, the source of the fifth control transistor T5 is electrically connected to the high voltage terminal V01, and the drain of the fifth control transistor T5 is electrically connected to the fourth node N4 electrical connection;
  • the gate of the sixth control transistor T6 is electrically connected to the second clock signal terminal CB, the source of the sixth control transistor T6 is electrically connected to the fourth node N4, and the drain of the sixth control transistor T6 electrically connected to the third node N3;
  • the first node control circuit 16 includes a seventh control transistor T1 and an eighth control transistor T7, wherein,
  • the gate of the seventh control transistor T1 is electrically connected to the first clock signal terminal CK, the source of the seventh control transistor T1 is electrically connected to the input terminal I1, and the drain of the seventh control transistor T1 is electrically connected to the input terminal I1.
  • the first node N1 is electrically connected;
  • the gate of the eighth control transistor T7 is electrically connected to the fourth node N4, the drain of the eighth control transistor T7 is electrically connected to the first node N1, and the source of the eighth control transistor T7 It is electrically connected to the high voltage terminal V01;
  • the output circuit 17 includes a first output transistor T3 and a second output transistor T4;
  • the gate of the first output transistor T3 is electrically connected to the first node N1, the source of the first output transistor T3 is electrically connected to the low voltage terminal V02, and the drain of the first output transistor T3 is electrically connected to the first node N1.
  • the driving voltage signal terminal O1 is electrically connected;
  • the gate of the second output transistor T4 is electrically connected to the second node N2, the drain of the second output transistor T4 is electrically connected to the driving voltage signal terminal O1, and the source of the second output transistor T4 The pole is electrically connected with the high voltage terminal V01;
  • the first energy storage circuit 12 includes a first storage capacitor C4, and the second energy storage circuit 14 includes a second storage capacitor C3;
  • the first terminal of the first storage capacitor C4 is electrically connected to the first node N1, and the second terminal of the first storage capacitor C4 is electrically connected to the low voltage terminal V02;
  • the first terminal of the second storage capacitor C3 is electrically connected to the second node N2, and the second terminal of the second storage capacitor C3 is electrically connected to the high voltage terminal V01.
  • the high voltage terminal may provide a high voltage signal
  • the low voltage terminal may provide a low voltage signal
  • the third embodiment of the shift register unit described in the present disclosure is a shift register unit in a light-emitting control signal generating circuit, which is used for generating a light-emitting control signal.
  • all transistors are p-type thin film transistors, but not limited thereto.
  • the difference between the third embodiment of the shift register unit described in the present disclosure and the first embodiment described in the present disclosure is that a node control transistor T0 is added.
  • CK provides a high voltage signal, and T0 is turned off;
  • the potential of N1 is a low voltage, T0 is turned on, and T9 is turned on, so the turning on of T0 will not affect the potential of N2;
  • the potential of N1 is a low voltage, T9 is turned on, and T0 is turned off, but since T8 is turned on and the potential of N3 is a high voltage, the potential of N2 can be maintained at a high voltage;
  • the potential of N1 is a high voltage, T0 is turned on, and T9 is turned off, so the opening of T0 will not affect the potential of N2;
  • the potential of N1 is a high voltage, T9 is turned off, and T0 is turned off;
  • the potential of N1 is a high voltage, T0 is turned on, and T9 is turned off, so the opening of T0 will not affect the potential of N2;
  • the potential of N1 is a high voltage, T9 is turned off, and T0 is turned off;
  • the potential of N1 is at a low voltage, T9 is turned on, and T0 is turned off, but since T8 is turned on and the potential of N3 is at a high voltage, the potential of N2 can be maintained at a high voltage.
  • the differences between the fourth embodiment of the shift register unit described in the present disclosure and the third embodiment of the shift register unit described in the present disclosure are as follows: the position of C1;
  • the drain of T2 and the drain of T6 are directly electrically connected to N3, one end of C1 is electrically connected to N3, and the other end of C1 is electrically connected to T11.
  • the first node potential adjustment circuit 11 includes an adjustment transistor T10 and an adjustment capacitor C2, wherein,
  • the gate of the adjustment transistor T10 is electrically connected to the first node N1, the source of the adjustment transistor T10 is electrically connected to the second clock signal terminal CB, and the drain of the adjustment transistor T10 is electrically connected to the adjustment capacitor C1 The first end of the electrical connection;
  • the second end of the adjustment capacitor C1 is electrically connected to the first node N1;
  • the second node control circuit 13 includes a first control transistor T11, a control capacitor C1, a second control transistor T8 and a third control transistor T9, wherein,
  • the first end of the control capacitor C1 is electrically connected to the third node N3, and the second end of the control capacitor C1 is electrically connected to the fifth node N5;
  • the gate of the first control transistor T11 is electrically connected to the third node N3, the drain of the first control transistor T11 is electrically connected to the fifth node N5, and the source of the first control transistor T11 is electrically connected to the first clock signal terminal CK;
  • the gate of the second control transistor T8 is electrically connected to the second clock signal terminal CB, the source of the second control transistor T8 is electrically connected to the fifth node N5, and the second control transistor T8 is the drain is electrically connected to the second node N2;
  • the gate of the third control transistor T9 is electrically connected to the first node N1, the source of the third control transistor T9 is electrically connected to the high voltage terminal V01, and the drain of the third control transistor T9 is electrically connected to the high voltage terminal V01. the second node N2 is electrically connected;
  • the third node control circuit 15 includes a fourth control transistor T2, a fifth control transistor T5 and a sixth control transistor T6, wherein,
  • the gate of the fourth control transistor T2 is electrically connected to the second clock signal terminal CB, the source of the fourth control transistor T2 is electrically connected to the low voltage terminal V02, and the drain of the fourth control transistor T2 is electrically connected to the second clock signal terminal CB.
  • the gate of the fifth control transistor T5 is electrically connected to the first node N1, the source of the fifth control transistor T5 is electrically connected to the high voltage terminal V01, and the drain of the fifth control transistor T5 is electrically connected to the fourth node N4 electrical connection;
  • the gate of the sixth control transistor T6 is electrically connected to the first clock signal terminal CK, the source of the sixth control transistor T6 is electrically connected to the fourth node N4, and the drain of the sixth control transistor T6 electrically connected to the third node N3;
  • the first node control circuit 16 includes a seventh control transistor T1 and an eighth control transistor T7, wherein,
  • the gate of the seventh control transistor T1 is electrically connected to the first clock signal terminal CK, the source of the seventh control transistor T1 is electrically connected to the input terminal I1, and the drain of the seventh control transistor T1 is electrically connected to the input terminal I1.
  • the first node N1 is electrically connected;
  • the gate of the eighth control transistor T7 is electrically connected to the fourth node N4, the drain of the eighth control transistor T7 is electrically connected to the first node N1, and the source of the eighth control transistor T7 It is electrically connected to the high voltage terminal V01;
  • the output circuit 17 includes a first output transistor T3 and a second output transistor T4;
  • the gate of the first output transistor T3 is electrically connected to the first node N1, the source of the first output transistor T3 is electrically connected to the low voltage terminal V02, and the drain of the first output transistor T3 is electrically connected to the first node N1.
  • the driving voltage signal terminal O1 is electrically connected;
  • the gate of the second output transistor T4 is electrically connected to the second node N2, the drain of the second output transistor T4 is electrically connected to the driving voltage signal terminal O1, and the source of the second output transistor T4 The pole is electrically connected with the high voltage terminal V01;
  • the first energy storage circuit 12 includes a first storage capacitor C4, and the second energy storage circuit 14 includes a second storage capacitor C3;
  • the first terminal of the first storage capacitor C4 is electrically connected to the first node N1, and the second terminal of the first storage capacitor C4 is electrically connected to the low voltage terminal V02;
  • the first terminal of the second storage capacitor C3 is electrically connected to the second node N2, and the second terminal of the second storage capacitor C3 is electrically connected to the high voltage terminal V01.
  • the high voltage terminal may provide a high voltage signal
  • the low voltage terminal may provide a low voltage signal
  • the fifth embodiment of the shift register unit described in the present disclosure is a shift register unit in a light-emitting control signal generating circuit, which is used for generating a light-emitting control signal.
  • all transistors are p-type thin film transistors, but not limited thereto.
  • the fifth embodiment of the shift register unit described in the present disclosure is different from the first embodiment of the shift register unit described in the present disclosure as follows: the gate of T2 is electrically connected to CB, and the gate of T6 is electrically connected to CK , the source of T11 is electrically connected to CK.
  • CK provides a low voltage signal
  • CB provides a high voltage signal
  • I1 provides a low voltage signal
  • T1 is turned off
  • T2 is turned on
  • T6 is turned off
  • the potential of N3 is a low voltage
  • the potential of N1 is maintained at a high voltage
  • T11 is turned on
  • T8 is turned off
  • the potential of N2 is maintained at a high voltage
  • O1 continues to output the voltage signal of the previous time period; since T5 and T6 are turned off, N4 is floating at this time;
  • CK provides a high voltage signal
  • CB provides a low voltage signal
  • I1 provides a low voltage signal
  • T1 is turned on
  • T2 is turned off
  • the potential of N1 is low voltage
  • T9 is turned on
  • T5 is turned on
  • T6 is turned on
  • the potential of N3 is high voltage
  • T8 is turned off
  • the potential of N2 is high voltage
  • T11 is turned off
  • T10 is turned on
  • CK provides a low voltage signal
  • CB provides a high voltage signal
  • I1 provides a high voltage signal
  • T1 is turned off
  • T2 is turned on
  • the potential of N3 is low voltage
  • T10 is turned on.
  • CK provides a high voltage signal
  • CB provides a low voltage signal
  • I1 provides a high voltage signal
  • T1 is turned on
  • T2 is turned off
  • the potential of N1 is a high voltage
  • T5 is turned off
  • T9 is turned off
  • T10 is turned off
  • T3 is turned off
  • T6 is turned on
  • T11 is turned on
  • the second clock signal provided by CB jumps from the high voltage signal of the previous period to a low voltage signal
  • the potential of N3 is further pulled down
  • the potential of N4 is also low voltage
  • T8 is turned on
  • the potential of N2 For low voltage, T4 is on, T3 is off, and O1 provides high voltage;
  • CK provides a low voltage signal
  • CB provides a high voltage signal
  • I1 provides a high voltage signal
  • T2 is turned on
  • T1 is turned off
  • the potential of N3 is low voltage
  • T6 is turned off
  • the potential of N1 is maintained at high voltage
  • T5 Closed N4 is floating
  • T8 is closed
  • the potential of N2 is maintained at a low voltage
  • T3 is closed
  • T4 is open
  • O1 outputs a high voltage
  • CK provides a high voltage signal
  • CB provides a low voltage signal
  • I1 provides a high voltage signal
  • T1 is turned off
  • T2 is turned on
  • the potential of N1 is a high voltage
  • T9 is turned off
  • T5 is turned off
  • T6 is turned on
  • T11 is turned on
  • the second clock signal provided by CB jumps from the high voltage signal in the previous period to the low voltage signal
  • the potential of N3 is further pulled down
  • the potential of N4 is also low voltage
  • T8 is turned on
  • the potential of N2 is low voltage
  • T4 Open T3 is closed
  • O1 provides high voltage
  • CK provides a low voltage signal
  • CB provides a high voltage signal
  • I1 provides a low voltage signal
  • T1 is turned off
  • T2 is turned on
  • the potential of N3 is low voltage
  • T6 is turned off
  • the potential of N1 is maintained at high voltage
  • T11 Open T8 is closed
  • T9 is closed
  • the potential of N2 is maintained at a high voltage
  • O1 continues to output a high voltage
  • CK provides a high voltage signal
  • CB provides a low voltage signal
  • I1 provides a low voltage signal
  • T1 is turned on
  • T2 is turned off
  • the potential of N1 is a low voltage
  • T5 and T6 are turned on
  • the potential of N4 and the potential of N3
  • T8 is turned on
  • T9 is turned on
  • the potential of N2 is a high voltage
  • T3 is turned on
  • T4 is turned off
  • O1 outputs a low voltage.
  • the pulse width of the input signal is the same as the pulse width of the light-emitting control signal output by O1, and O1 can be used as the input terminal of the adjacent next-stage shift register unit, but it is not limited thereto.
  • CK provides a low voltage signal
  • CB provides a high voltage signal
  • I1 provides a low voltage signal
  • T1 is turned off
  • T2 is turned on
  • T6 is turned off
  • the potential of N3 is a low voltage
  • the potential of N1 is maintained at a high voltage
  • T11 is turned on
  • T8 is turned off
  • the potential of N2 is maintained at a high voltage
  • O1 continues to output the voltage signal of the previous period; since T5 and T6 are turned off, N4 is floating at this time;
  • CK provides a high voltage signal
  • CB provides a low voltage signal
  • I1 provides a low voltage signal
  • T1 is turned on
  • T2 is turned off
  • the potential of N1 is a low voltage
  • T9 is turned on
  • T5 is turned on
  • T6 is turned on
  • N3 is turned on.
  • the potential is high voltage
  • T8 is off
  • the potential of N2 is high voltage
  • T11 is off
  • T10 is on
  • T3 is on
  • T4 off
  • O1 outputs low voltage
  • T5 is on, T6 is on, and the potential of N4 is high voltage
  • T5 is on
  • T6 is on
  • the potential of N4 is high voltage
  • CK provides a low voltage signal
  • CB provides a high voltage signal
  • I1 provides a high voltage signal
  • T1 is turned off
  • T2 is turned on
  • the potential of N3 is low voltage
  • T10 is turned on.
  • the high voltage signal of the period jumps to a low voltage signal
  • the potential of N1 is further pulled down, so that T3 can be fully turned on, and O1 outputs a low voltage
  • T11 is turned on
  • T8 is turned off
  • T9 is turned on
  • the potential of N2 is a high voltage
  • T5 Turn on, T6 is turned off, and the potential of N4 is a high voltage
  • the voltage value of the voltage signal output by O1 is VL;
  • CK provides a high voltage signal
  • CB provides a low voltage signal
  • I1 provides a high voltage signal
  • T1 is turned on
  • T2 is turned off
  • the potential of N1 is a high voltage
  • T5 is turned off
  • T9 is turned off
  • T10 is turned off
  • T3 is turned off
  • T6 is turned on
  • T11 is turned on
  • the second clock signal provided by CB jumps from the high voltage signal of the previous period to a low voltage signal
  • the potential of N3 is further pulled down
  • the potential of N4 is also low voltage
  • T8 is turned on
  • the potential of N2 For low voltage, T4 is on, T3 is off, and O1 provides high voltage;
  • CK provides a low voltage signal
  • CB provides a high voltage signal
  • I1 provides a high voltage signal
  • T2 is turned on
  • T1 is turned off
  • the potential of N3 is low voltage
  • T6 is turned off
  • the potential of N1 is maintained at high voltage
  • T5 Closed N4 is floating
  • T8 is closed
  • the potential of N2 is maintained at a low voltage
  • T3 is closed
  • T4 is open
  • O1 outputs a high voltage
  • CK provides a high voltage signal
  • CB provides a low voltage signal
  • I1 provides a low voltage signal
  • T1 is turned off
  • T2 is turned on
  • the potential of N1 is a high voltage
  • T9 is turned off
  • T5 is turned off
  • T6 is turned on
  • T11 is turned on
  • the second clock signal provided by CB jumps from the high voltage signal in the previous period to the low voltage signal
  • the potential of N3 is further pulled down
  • the potential of N4 is also low voltage
  • T8 is turned on
  • the potential of N2 is low voltage
  • T4 Open T3 is closed
  • O1 provides high voltage
  • CK provides a low voltage signal
  • CB provides a high voltage signal
  • I1 provides a low voltage signal
  • T1 is turned off
  • T2 is turned on
  • the potential of N3 is low voltage
  • T6 is turned off
  • the potential of N1 is maintained at high voltage
  • T11 Open T8 is closed
  • T9 is closed
  • the potential of N2 is maintained at a high voltage
  • O1 continues to output a high voltage
  • CK provides a high voltage signal
  • CB provides a low voltage signal
  • I1 provides a low voltage signal
  • T1 is turned on
  • T2 is turned off
  • the potential of N1 is a low voltage
  • T5 and T6 are turned on
  • the potential of N4 and the potential of N3
  • T8 is turned on
  • T9 is turned on
  • the potential of N2 is a high voltage
  • T3 is turned on
  • T4 is turned off
  • O1 outputs a low voltage.
  • the pulse width of the input signal is different from the pulse width of the light-emitting control signal output by O1, but not limited thereto.
  • the first isolation circuit 41 includes a first isolation transistor T13;
  • the gate of T13 is connected to the low voltage terminal V02, the source of T13 is electrically connected to N01, and the drain of T13 is electrically connected to N1;
  • the first node potential adjustment circuit 11 includes an adjustment transistor T10 and an adjustment capacitor C2, wherein,
  • the gate of the adjustment transistor T10 is electrically connected to the first node N1, the source of the adjustment transistor T10 is electrically connected to the second clock signal terminal CB, and the drain of the adjustment transistor T10 is electrically connected to the adjustment capacitor C2 The first end of the electrical connection;
  • the second end of the adjustment capacitor C2 is electrically connected to the first node N1;
  • the second node control circuit 13 includes a first control transistor T11, a control capacitor C1, a second control transistor T8 and a third control transistor T9, wherein,
  • the first end of the control capacitor C1 is electrically connected to the third node N3, and the second end of the control capacitor C1 is electrically connected to the fifth node N5;
  • the gate of the first control transistor T11 is electrically connected to the third node N3, the drain of the first control transistor T11 is electrically connected to the fifth node N5, and the source of the first control transistor T11 electrically connected to the second clock signal terminal CB;
  • the gate of the second control transistor T8 is electrically connected to the second clock signal terminal CB, the source of the second control transistor T8 is electrically connected to the fifth node N5, and the second control transistor T8 is the drain is electrically connected to the second node N2;
  • the gate of the third control transistor T9 is electrically connected to the first isolation node N01, the source of the third control transistor T9 is electrically connected to the high voltage terminal V01, and the drain of the third control transistor T9 is electrically connected to the high voltage terminal V01. the second node N2 is electrically connected;
  • the third node control circuit 15 includes a fourth control transistor T2, a third isolation transistor T12, a fifth control transistor T5 and a sixth control transistor T6, wherein,
  • the gate of the fourth control transistor T2 is electrically connected to the first clock signal terminal CK, and the source of the fourth control transistor T2 is electrically connected to the low voltage terminal V02;
  • the gate of the third isolation transistor T12 is electrically connected to the low voltage terminal V02, the source of the third isolation transistor T12 is electrically connected to the drain of the fourth control transistor T2, and the drain of the third isolation transistor T12 is electrically connected electrically connected to the third node N3;
  • the gate of the fifth control transistor T5 is electrically connected to the first isolation node N01, the source of the fifth control transistor T5 is electrically connected to the high voltage terminal V01, and the drain of the fifth control transistor T5 is electrically connected to the fourth Node N4 is electrically connected;
  • the gate of the sixth control transistor T6 is electrically connected to the second clock signal terminal CB, the source of the sixth control transistor T6 is electrically connected to the fourth node N4, and the drain of the sixth control transistor T6 electrically connected to the third node N3;
  • the first node control circuit 16 includes a seventh control transistor T1 and an eighth control transistor T7, wherein,
  • the gate of the seventh control transistor T1 is electrically connected to the first clock signal terminal CK, the source of the seventh control transistor T1 is electrically connected to the input terminal I1, and the drain of the seventh control transistor T1 is electrically connected to the input terminal I1.
  • the first isolation node N01 is electrically connected;
  • the gate of the eighth control transistor T7 is electrically connected to the fourth node N4, the drain of the eighth control transistor T7 is electrically connected to the first isolation node N01, and the source of the eighth control transistor T7 The pole is electrically connected with the high voltage terminal V01;
  • the output circuit 17 includes a first output transistor T3 and a second output transistor T4;
  • the gate of the first output transistor T3 is electrically connected to the first node N1, the source of the first output transistor T3 is electrically connected to the low voltage terminal V02, and the drain of the first output transistor T3 is electrically connected to the first node N1.
  • the driving voltage signal terminal O1 is electrically connected;
  • the gate of the second output transistor T4 is electrically connected to the second node N2, the drain of the second output transistor T4 is electrically connected to the driving voltage signal terminal O1, and the source of the second output transistor T4 The pole is electrically connected with the high voltage terminal V01;
  • the first energy storage circuit 12 includes a first storage capacitor C4, and the second energy storage circuit 14 includes a second storage capacitor C3;
  • the first terminal of the first storage capacitor C4 is electrically connected to the first node N1, and the second terminal of the first storage capacitor C4 is electrically connected to the low voltage terminal V02;
  • the first terminal of the second storage capacitor C3 is electrically connected to the second node N2, and the second terminal of the second storage capacitor C3 is electrically connected to the high voltage terminal V01.
  • the high voltage terminal may provide a high voltage signal
  • the low voltage terminal may provide a low voltage signal
  • control voltage terminal is a low voltage terminal, but not limited thereto.
  • the sixth embodiment of the shift register unit described in the present disclosure is a shift register unit in a light-emitting control signal generating circuit for generating a light-emitting control signal.
  • all transistors are p-type thin film transistors, but not limited thereto.
  • the difference between the sixth embodiment of the shift register unit described in the present disclosure and the second embodiment of the shift register unit described in the present disclosure is that T12 and T13 are added.
  • the purpose of increasing T13 is to prevent the occurrence of DIBL (Drain Induced Barrier Lowering, Drain Induced Barrier Lowering) in the transistor electrically connected to N1 when the potential of N1 is too low decrease), so that the threshold voltage of the transistor electrically connected to N1 is shifted, resulting in the situation that the transistor electrically connected to N1 cannot be turned on or off normally in other working stages;
  • DIBL Drain Induced Barrier Lowering, Drain Induced Barrier Lowering
  • T12 The purpose of adding T12 is to prevent the threshold voltage of the transistor electrically connected to N3 from being shifted, resulting in the situation that the transistor electrically connected to N3 cannot be turned on or off normally in other working stages.
  • FIG. 22 on the basis of the embodiment of the shift register unit described in FIG. 5 , in the seventh embodiment of the shift register unit described in the present disclosure,
  • the first isolation circuit 41 includes a first isolation transistor T13, and the third isolation circuit 43 includes a third isolation transistor T12;
  • the gate of T13 is electrically connected to the low voltage terminal V02, the source of T13 is electrically connected to N01, and the drain of T13 is electrically connected to N1;
  • the gate of T12 is electrically connected to the low voltage terminal V02, the source of T12 is electrically connected to N03, and the drain of T12 is electrically connected to N3;
  • the first node potential adjustment circuit 11 includes an adjustment transistor T10 and an adjustment capacitor C2, wherein,
  • the gate of the adjustment transistor T10 is electrically connected to the first node N1, the source of the adjustment transistor T10 is electrically connected to the second clock signal terminal CB, and the drain of the adjustment transistor T10 is electrically connected to the adjustment capacitor C1 The first end of the electrical connection;
  • the second end of the adjustment capacitor C1 is electrically connected to the first node N1;
  • the second node control circuit 13 includes a first control transistor T11, a control capacitor C1, a second control transistor T8 and a third control transistor T9, wherein,
  • the first end of the control capacitor C1 is electrically connected to the third node N3, and the second end of the control capacitor C1 is electrically connected to the fifth node N5;
  • the gate of the first control transistor T11 is electrically connected to the third node N3, the drain of the first control transistor T11 is electrically connected to the fifth node N5, and the source of the first control transistor T11 electrically connected to the second clock signal terminal CB;
  • the gate of the second control transistor T8 is electrically connected to the second clock signal terminal CB, the source of the second control transistor T8 is electrically connected to the fifth node N5, and the second control transistor T8 is the drain is electrically connected to the second node N2;
  • the gate of the third control transistor T9 is electrically connected to the first isolation node N01, the source of the third control transistor T9 is electrically connected to the high voltage terminal V01, and the drain of the third control transistor T9 is electrically connected to the high voltage terminal V01. the second node N2 is electrically connected;
  • the third node control circuit 15 includes a fourth control transistor T2, a fifth control transistor T5 and a sixth control transistor T6, wherein,
  • the gate of the fourth control transistor T2 is electrically connected to the first clock signal terminal CK, the source of the fourth control transistor T2 is electrically connected to the low voltage terminal V02, and the drain of the fourth control transistor T2 is electrically connected to the first clock signal terminal CK.
  • the gate of the fifth control transistor T5 is electrically connected to the first isolation node N01, the source of the fifth control transistor T5 is electrically connected to the high voltage terminal V01, and the drain of the fifth control transistor T5 is electrically connected to the fourth Node N4 is electrically connected;
  • the gate of the sixth control transistor T6 is electrically connected to the second clock signal terminal CB, the source of the sixth control transistor T6 is electrically connected to the fourth node N4, and the drain of the sixth control transistor T6 electrically connected to the third isolation node N03;
  • the first node control circuit 16 includes a seventh control transistor T1 and an eighth control transistor T7, wherein,
  • the gate of the seventh control transistor T1 is electrically connected to the first clock signal terminal CK, the source of the seventh control transistor T1 is electrically connected to the input terminal I1, and the drain of the seventh control transistor T1 is electrically connected to the input terminal I1.
  • the first isolation node N01 is electrically connected;
  • the gate of the eighth control transistor T7 is electrically connected to the fourth node N4, the drain of the eighth control transistor T7 is electrically connected to the first isolation node N1, and the source of the eighth control transistor T7 The pole is electrically connected with the high voltage terminal V01;
  • the output circuit 17 includes a first output transistor T3 and a second output transistor T4;
  • the gate of the first output transistor T3 is electrically connected to the first node N1, the source of the first output transistor T3 is electrically connected to the low voltage terminal V02, and the drain of the first output transistor T3 is electrically connected to the first node N1.
  • the driving voltage signal terminal O1 is electrically connected;
  • the gate of the second output transistor T4 is electrically connected to the second node N2, the drain of the second output transistor T4 is electrically connected to the driving voltage signal terminal O1, and the source of the second output transistor T4 The pole is electrically connected with the high voltage terminal V01;
  • the first energy storage circuit 12 includes a first storage capacitor C4, and the second energy storage circuit 14 includes a second storage capacitor C3;
  • the first terminal of the first storage capacitor C4 is electrically connected to the first node N1, and the second terminal of the first storage capacitor C4 is electrically connected to the low voltage terminal V02;
  • the first end of the second storage capacitor C3 is electrically connected to the second node N2, and the second end of the second storage capacitor C3 is electrically connected to the high voltage terminal V01.
  • the high voltage terminal may provide a high voltage signal
  • the low voltage terminal may provide a low voltage signal
  • the seventh embodiment of the shift register unit described in the present disclosure is a shift register unit in a light-emitting control signal generating circuit, which is used for generating a light-emitting control signal.
  • all transistors are p-type thin film transistors, but not limited thereto.
  • the difference between the seventh embodiment of the shift register unit described in the present disclosure and the first embodiment of the shift register unit described in the present disclosure is that T13 and T12 are added.
  • the purpose of increasing T13 is to prevent the occurrence of DIBL (Drain Induced Barrier Lowering, drain induced barrier) in the transistor electrically connected to N1 when the potential of N1 is too low. decrease), so that the threshold voltage of the transistor electrically connected to N1 is shifted, resulting in the situation that the transistor electrically connected to N1 cannot be turned on or off normally in other working stages;
  • DIBL Drain Induced Barrier Lowering, drain induced barrier
  • T12 The purpose of adding T12 is to prevent the threshold voltage of the transistor electrically connected to the potential of N3 from shifting, resulting in the situation that the transistor electrically connected to N3 cannot be turned on or off normally in other working stages.
  • the first isolation circuit 41 includes a first isolation transistor T13
  • the third isolation circuit 43 includes a third isolation transistor T12
  • the second isolation circuit 42 includes a second isolation transistor T14;
  • the gate of T13 is electrically connected to the low voltage terminal V02, the source of T13 is electrically connected to N01, and the drain of T13 is electrically connected to N1;
  • the gate of T12 is electrically connected to the low voltage terminal V02, the source of T12 is electrically connected to N03, and the drain of T12 is electrically connected to N3;
  • the gate of T14 is electrically connected to the low voltage terminal V02, the source of T14 is electrically connected to N02, and the drain of T14 is electrically connected to N2;
  • the first node potential adjustment circuit 11 includes an adjustment transistor T10 and an adjustment capacitor C2, wherein,
  • the gate of the adjustment transistor T10 is electrically connected to the first node N1, the source of the adjustment transistor T10 is electrically connected to the second clock signal terminal CB, and the drain of the adjustment transistor T10 is electrically connected to the adjustment capacitor C2 The first end of the electrical connection;
  • the second end of the adjustment capacitor C2 is electrically connected to the first node N1;
  • the second node control circuit 13 includes a first control transistor T11, a control capacitor C1, a second control transistor T8 and a third control transistor T9, wherein,
  • the first end of the control capacitor C1 is electrically connected to the third node N3, and the second end of the control capacitor C1 is electrically connected to the fifth node N5;
  • the gate of the first control transistor T11 is electrically connected to the third node N3, the drain of the first control transistor T11 is electrically connected to the fifth node N5, and the source of the first control transistor T11 electrically connected to the second clock signal terminal CB;
  • the gate of the second control transistor T8 is electrically connected to the second clock signal terminal CB, the source of the second control transistor T8 is electrically connected to the fifth node N5, and the second control transistor T8 is the drain is electrically connected to the second isolation node N02;
  • the gate of the third control transistor T9 is electrically connected to the first isolation node N01, the source of the third control transistor T9 is electrically connected to the high voltage terminal V01, and the drain of the third control transistor T9 is electrically connected to the high voltage terminal V01. the second isolation node N02 is electrically connected;
  • the third node control circuit 15 includes a fourth control transistor T2, a fifth control transistor T5 and a sixth control transistor T6, wherein,
  • the gate of the fourth control transistor T2 is electrically connected to the first clock signal terminal CK, the source of the fourth control transistor T2 is electrically connected to the low voltage terminal V02, and the drain of the fourth control transistor T2 is electrically connected to the first clock signal terminal CK.
  • the gate of the fifth control transistor T5 is electrically connected to the first isolation node N01, the source of the fifth control transistor T5 is electrically connected to the high voltage terminal V01, and the drain of the fifth control transistor T5 is electrically connected to the fourth Node N4 is electrically connected;
  • the gate of the sixth control transistor T6 is electrically connected to the second clock signal terminal CB, the source of the sixth control transistor T6 is electrically connected to the fourth node N4, and the drain of the sixth control transistor T6 electrically connected to the third isolation node N03;
  • the first node control circuit 16 includes a seventh control transistor T1 and an eighth control transistor T7, wherein,
  • the gate of the seventh control transistor T1 is electrically connected to the first clock signal terminal CK, the source of the seventh control transistor T1 is electrically connected to the input terminal I1, and the drain of the seventh control transistor T1 is electrically connected to the input terminal I1.
  • the first isolation node N01 is electrically connected;
  • the gate of the eighth control transistor T7 is electrically connected to the fourth node N4, the drain of the eighth control transistor T7 is electrically connected to the first isolation node N1, and the source of the eighth control transistor T7 The pole is electrically connected with the high voltage terminal V01;
  • the output circuit 17 includes a first output transistor T3 and a second output transistor T4;
  • the gate of the first output transistor T3 is electrically connected to the first node N1, the source of the first output transistor T3 is electrically connected to the low voltage terminal V02, and the drain of the first output transistor T3 is electrically connected to the first node N1.
  • the driving voltage signal terminal O1 is electrically connected;
  • the gate of the second output transistor T4 is electrically connected to the second node N2, the drain of the second output transistor T4 is electrically connected to the driving voltage signal terminal O1, and the source of the second output transistor T4 The pole is electrically connected with the high voltage terminal V01;
  • the first energy storage circuit 12 includes a first storage capacitor C4, and the second energy storage circuit 14 includes a second storage capacitor C3;
  • the first terminal of the first storage capacitor C4 is electrically connected to the first node N1, and the second terminal of the first storage capacitor C4 is electrically connected to the low voltage terminal V02;
  • the first terminal of the second storage capacitor C3 is electrically connected to the second node N2, and the second terminal of the second storage capacitor C3 is electrically connected to the high voltage terminal V01.
  • the high voltage terminal may provide a high voltage signal
  • the low voltage terminal may provide a low voltage signal
  • the eighth embodiment of the shift register unit described in the present disclosure is a shift register unit in a light-emitting control signal generating circuit, which is used for generating a light-emitting control signal.
  • all transistors are p-type thin film transistors, but not limited thereto.
  • the difference between the sixth embodiment of the shift register unit described in the present disclosure and the first embodiment of the shift register unit described in the present disclosure is that T13, T12 and T14 are added.
  • the purpose of adding T13 is to prevent DIBL (Drain Induced Barrier Lowering, drain induced barrier) from occurring in the transistor electrically connected to N1 when the potential of N1 is too low decrease), so that the threshold voltage of the transistor electrically connected to N1 is shifted, resulting in the situation that the transistor electrically connected to N1 cannot be turned on or off normally in other working stages;
  • DIBL Drain Induced Barrier Lowering, drain induced barrier
  • T12 The purpose of adding T12 is to prevent the threshold voltage of the transistor electrically connected to the potential of N3 from shifting, resulting in the situation that the transistor electrically connected to N3 cannot be turned on or off normally during other working stages.
  • T14 The purpose of increasing T14 is to prevent DIBL (Drain Induced Barrier Lowering) of the transistor electrically connected to N2 from occurring when the potential of N2 is too low, so that the threshold voltage of the transistor electrically connected to N2 is shifted. , resulting in the situation that the transistor electrically connected to N2 cannot be turned on or off normally during other working stages.
  • DIBL Drain Induced Barrier Lowering
  • the difference between the ninth embodiment of the shift register unit described in the present disclosure and the seventh embodiment of the shift register unit described in the present disclosure is as follows: the source of T10 is connected to the third clock signal terminal CKo.
  • the third clock signal provided by CKo is an inverted signal of the second clock signal provided by CK.
  • the first node potential adjustment circuit 11 includes an adjustment transistor T10 and an adjustment capacitor C2, wherein,
  • the gate of the adjustment transistor T10 is electrically connected to the first node N1, the source of the adjustment transistor T10 is electrically connected to the second clock signal terminal CB, and the drain of the adjustment transistor T10 is electrically connected to the adjustment capacitor C1 The first end of the electrical connection;
  • the second end of the adjustment capacitor C1 is electrically connected to the first node N1;
  • the second node control circuit 13 includes a first control transistor T11, a control capacitor C1, a second control transistor T8 and a third control transistor T9, wherein,
  • the first end of the control capacitor C1 is electrically connected to the third node N3, and the second end of the control capacitor C1 is electrically connected to the fifth node N5;
  • the gate of the first control transistor T11 is electrically connected to the third node N3, the drain of the first control transistor T11 is electrically connected to the fifth node N5, and the source of the first control transistor T11 electrically connected to the second clock signal terminal CB;
  • the gate of the second control transistor T8 is electrically connected to the second clock signal terminal CB, the source of the second control transistor T8 is electrically connected to the fifth node N5, and the second control transistor T8 is the drain is electrically connected to the second node N2;
  • the gate of the third control transistor T9 is electrically connected to the first node N1, the source of the third control transistor T9 is electrically connected to the high voltage terminal V01, and the drain of the third control transistor T9 is electrically connected to the high voltage terminal V01. the second node N2 is electrically connected;
  • the third node control circuit 15 includes a fourth control transistor T2, a fifth control transistor T5 and a sixth control transistor T6, wherein,
  • the gate of the fourth control transistor T2 is electrically connected to the first clock signal terminal CK, the source of the fourth control transistor T2 is electrically connected to the low voltage terminal V02, and the drain of the fourth control transistor T2 is electrically connected to the first clock signal terminal CK.
  • the gate of the fifth control transistor T5 is electrically connected to the first node N1, the source of the fifth control transistor T5 is electrically connected to the high voltage terminal V01, and the drain of the fifth control transistor T5 is electrically connected to the fourth node N4 electrical connection;
  • the gate of the sixth control transistor T6 is electrically connected to the second clock signal terminal CB, the source of the sixth control transistor T6 is electrically connected to the fourth node N4, and the drain of the sixth control transistor T6 electrically connected to the third node N3;
  • the first node control circuit 16 includes a seventh control transistor T1 and an eighth control transistor T7, wherein,
  • the gate of the seventh control transistor T1 is electrically connected to the first clock signal terminal CK, the source of the seventh control transistor T1 is electrically connected to the input terminal I1, and the drain of the seventh control transistor T1 is electrically connected to the input terminal I1.
  • the first node N1 is electrically connected;
  • the gate of the eighth control transistor T7 is electrically connected to the fourth node N4, the drain of the eighth control transistor T7 is electrically connected to the first node N1, and the source of the eighth control transistor T7 It is electrically connected to the high voltage terminal V01;
  • the output circuit 17 includes a first output transistor T3 and a second output transistor T4;
  • the gate of the first output transistor T3 is electrically connected to the first node N1, the source of the first output transistor T3 is electrically connected to the low voltage terminal V02, and the drain of the first output transistor T3 is electrically connected to the first node N1.
  • the driving voltage signal terminal O1 is electrically connected;
  • the gate of the second output transistor T4 is electrically connected to the second node N2, the drain of the second output transistor T4 is electrically connected to the driving voltage signal terminal O1, and the source of the second output transistor T4
  • the pole is electrically connected with the output clock signal terminal CBo;
  • the first energy storage circuit 12 includes a first storage capacitor C4, and the second energy storage circuit 14 includes a second storage capacitor C3;
  • the first terminal of the first storage capacitor C4 is electrically connected to the first node N1, and the second terminal of the first storage capacitor C4 is electrically connected to the low voltage terminal V02;
  • the first terminal of the second storage capacitor C3 is electrically connected to the second node N2, and the second terminal of the second storage capacitor C3 is electrically connected to the output clock signal terminal CBo.
  • the high voltage terminal may provide a high voltage signal
  • the low voltage terminal may provide a low voltage signal
  • the tenth embodiment of the shift register unit described in the present disclosure is a shift register unit in a gate driving circuit for generating a gate driving signal.
  • all transistors are p-type thin film transistors, but not limited thereto.
  • the second clock signal provided by the CB and the output clock signal provided by the CBo are inverted, but not limited thereto.
  • the pulse width of the gate driving signal provided by the shift register unit is smaller than the pulse width of the light-emitting control signal provided by the shift register unit, but not limited thereto.
  • the display period includes a first time period t1, a second time period t2, a third time period t3, and a fourth time period t4 and the fifth time period t5;
  • CK provides a low voltage signal
  • CB provides a high voltage signal
  • CBo provides a low voltage signal
  • I1 provides a low voltage signal
  • T1 and T2 are turned on, the potential of N1 is a low voltage
  • T9 Turn on, T10 is turned on, the potential of N3 is low voltage
  • T8 is turned off
  • the potential of N2 is high voltage
  • T3 is turned on
  • T4 is turned off
  • O1 outputs VL-Vth, where Vth is the threshold voltage of T3, and VL is provided by the low voltage terminal The voltage value of the voltage signal;
  • the potential of N1 is VL
  • the potential of N2 is VH
  • the potential of N3 is VL
  • the potential of N4 is VH
  • the potential of N5 is VH
  • CK provides a high-voltage signal
  • CB provides a low-voltage signal
  • CBo provides a high-voltage signal
  • I1 provides a low-voltage signal
  • the second clock signal jumps from a high voltage signal in the previous period to a low voltage signal, so the potential of N1 is further pulled down, so that T3 can be fully turned on, T5 is turned on, T6 is turned on, and the potential of N4 and N3 are both high voltages , T8 is turned on, the potential of N2 is a high voltage, T3 is turned on, T4 is turned off, O1 outputs a low voltage, and the voltage value of the voltage signal output by O1 at this time is VL;
  • the potential of N1 is (VL-VH)C2z/(C2z+C4z)+VL
  • the potential of N2 is VH
  • the potential of N3 is VH
  • the potential of N4 is VH
  • the potential of N5 is VH
  • CK provides a low voltage signal
  • CB provides a high voltage signal
  • CBo provides a low voltage signal
  • I1 provides a high voltage signal
  • T1 and T2 are turned on, the potential of N1 is a high voltage, and T5 , T9 and T10 are closed, T6 is closed, the potential of N3 is low voltage, T11 is open, T8 is closed, the potential of N2 is maintained at high voltage, both T3 and T4 are closed, and the voltage signal output by O1 is maintained by the parasitic capacitance of the circuit.
  • the potential of N1 is VH
  • the potential of N2 is VH
  • the potential of N3 is VL
  • the potential of N4 is unknown
  • the potential of N5 is VH
  • CK provides a high voltage signal
  • CB provides a low voltage signal
  • CBo provides a high voltage signal
  • I1 provides a low voltage signal
  • T1 and T2 are turned off, and the potential of N1 remains at a high voltage
  • T11 is turned on, since the second clock signal provided by CB jumps from the high-voltage signal of the previous period to the low-voltage signal
  • T8 is turned on, the potential of N3 and N2 are further pulled down, T3 is turned off, and T4 is turned on.
  • CBo provides high voltage signal
  • O1 outputs high voltage
  • the potential of N1 is VH
  • the potential of N2 is VL
  • the potential of N3 is 2VL-VH
  • the potential of N4 is VL
  • the potential of N4 is VL;
  • CK provides a low voltage signal
  • CB provides a high voltage signal
  • CBo provides a low voltage signal
  • T1 and T2 are turned on
  • the potential of N1 is VL
  • the potential of N3 is VL
  • T6 is turned off
  • T5 is turned on
  • the potential of N4 is VH.
  • the differences between the eleventh embodiment of the shift register unit described in the present disclosure and the tenth embodiment of the shift register unit described in the present disclosure are as follows: the position of C1;
  • the first terminal of C1 is electrically connected to the third node N3
  • the second terminal of C1 is electrically connected to the drain of T11
  • N3 is directly electrically connected to the drain of T8. connect.
  • the operation timing diagram of the eleventh embodiment of the shift register unit shown in FIG. 28 may also be shown in FIG. 26 , but it is not limited thereto.
  • the eleventh embodiment of the shift register unit of the present disclosure as shown in FIG. 28 when the eleventh embodiment of the shift register unit of the present disclosure as shown in FIG. 28 is in operation, in the fourth time period t4, when T11 is turned on, according to the second clock signal provided by CB, the switching of point N3 is realized.
  • the potential jumps, and the jump value is (VL-VH+VL). Since in the previous time period (that is, the third time period t3), the potential of N2 is VH, so with the potential of the second clock signal provided by CB Jump from high level to low level, and distribute the voltage value according to the ratio of the capacitance value;
  • the potential of N3 is equal to the potential of N2, and the potential of N2 is equal to [(2VL-VH) ⁇ C1z+VH ⁇ C3z]/(C1z+C3z), where C1z is the capacitance value of C1 , C3z is the capacitance value of C3.
  • the first isolation circuit 41 includes a first isolation transistor T13;
  • the gate of T13 is connected to the low voltage terminal V02, the source of T13 is electrically connected to N01, and the drain of T13 is electrically connected to N1;
  • the first node potential adjustment circuit 11 includes an adjustment transistor T10 and an adjustment capacitor C2, wherein,
  • the gate of the adjustment transistor T10 is electrically connected to the first node N1, the source of the adjustment transistor T10 is electrically connected to the second clock signal terminal CB, and the drain of the adjustment transistor T10 is electrically connected to the adjustment capacitor C1 The first end of the electrical connection;
  • the second end of the adjustment capacitor C1 is electrically connected to the first node N1;
  • the second node control circuit 13 includes a first control transistor T11, a control capacitor C1, a second control transistor T8 and a third control transistor T9, wherein,
  • the first end of the control capacitor C1 is electrically connected to the third node N3, and the second end of the control capacitor C1 is electrically connected to the drain of the first control transistor T11;
  • the gate of the first control transistor T11 is electrically connected to the third node N3, and the source of the first control transistor T11 is electrically connected to the second clock signal terminal CB;
  • the gate of the second control transistor T8 is electrically connected to the second clock signal terminal CB, the source of the second control transistor T8 is electrically connected to the third node N3, and the second control transistor T8 is electrically connected to the third node N3. the drain is electrically connected to the second node N2;
  • the gate of the third control transistor T9 is electrically connected to the first isolation node N01, the source of the third control transistor T9 is electrically connected to the high voltage terminal V01, and the drain of the third control transistor T9 is electrically connected to the high voltage terminal V01. the second node N2 is electrically connected;
  • the third node control circuit 15 includes a fourth control transistor T2, a third isolation transistor T12, a fifth control transistor T5 and a sixth control transistor T6, wherein,
  • the gate of the fourth control transistor T2 is electrically connected to the first clock signal terminal CK, and the source of the fourth control transistor T2 is electrically connected to the low voltage terminal V02;
  • the gate of the third isolation transistor T12 is electrically connected to the low voltage terminal V02, the source of the third isolation transistor T12 is electrically connected to the drain of the fourth control transistor T2, and the drain of the third isolation transistor T12 is electrically connected electrically connected to the third node N3;
  • the gate of the fifth control transistor T5 is electrically connected to the first isolation node N01, the source of the fifth control transistor T5 is electrically connected to the high voltage terminal V01, and the drain of the fifth control transistor T5 is electrically connected to the fourth Node N4 is electrically connected;
  • the gate of the sixth control transistor T6 is electrically connected to the second clock signal terminal CB, the source of the sixth control transistor T6 is electrically connected to the fourth node N4, and the drain of the sixth control transistor T6 electrically connected to the third node N3;
  • the first node control circuit 16 includes a seventh control transistor T1 and an eighth control transistor T7, wherein,
  • the gate of the seventh control transistor T1 is electrically connected to the first clock signal terminal CK, the source of the seventh control transistor T1 is electrically connected to the input terminal I1, and the drain of the seventh control transistor T1 is electrically connected to the input terminal I1.
  • the first isolation node N01 is electrically connected;
  • the gate of the eighth control transistor T7 is electrically connected to the fourth node N4, the drain of the eighth control transistor T7 is electrically connected to the first isolation node N01, and the source of the eighth control transistor T7 The pole is electrically connected with the high voltage terminal V01;
  • the output circuit 17 includes a first output transistor T3 and a second output transistor T4;
  • the gate of the first output transistor T3 is electrically connected to the first node N1, the source of the first output transistor T3 is electrically connected to the low voltage terminal V02, and the drain of the first output transistor T3 is electrically connected to the first node N1.
  • the driving voltage signal terminal O1 is electrically connected;
  • the gate of the second output transistor T4 is electrically connected to the second node N2, the drain of the second output transistor T4 is electrically connected to the driving voltage signal terminal O1, and the source of the second output transistor T4
  • the pole is electrically connected with the output clock signal terminal CBo;
  • the first energy storage circuit 12 includes a first storage capacitor C4, and the second energy storage circuit 14 includes a second storage capacitor C3;
  • the first terminal of the first storage capacitor C4 is electrically connected to the first node N1, and the second terminal of the first storage capacitor C4 is electrically connected to the low voltage terminal V02;
  • the first terminal of the second storage capacitor C3 is electrically connected to the second node N2, and the second terminal of the second storage capacitor C3 is electrically connected to the high voltage terminal V01.
  • the high voltage terminal may provide a high voltage signal
  • the low voltage terminal may provide a low voltage signal
  • control voltage terminal is a low voltage terminal, but not limited thereto.
  • the twelfth embodiment of the shift register unit described in the present disclosure is a shift register unit in a gate driving circuit for generating a gate driving signal.
  • all transistors are p-type thin film transistors, but not limited thereto.
  • the purpose of adding T11 is to prevent the potential of N1 from being too low when the potential of N1 is further pulled down by T10 that is turned on through CB.
  • the threshold voltage of T1 is shifted to prevent the situation that T1 cannot be fully turned on when T1 needs to be turned on;
  • the purpose of adding T12 is to prevent the threshold voltage of T2 from being shifted due to the low potential of N3 when the potential of N3 is further pulled down through CB by T11 that is turned on. Open situation occurs.
  • the first isolation circuit 41 includes a first isolation transistor T13;
  • the gate of T13 is connected to the low voltage terminal V02, the source of T13 is electrically connected to N01, and the drain of T13 is electrically connected to N1;
  • the first node potential adjustment circuit 11 includes an adjustment transistor T10 and an adjustment capacitor C2, wherein,
  • the gate of the adjustment transistor T10 is electrically connected to the first node N1, the source of the adjustment transistor T10 is electrically connected to the second clock signal terminal CB, and the drain of the adjustment transistor T10 is electrically connected to the adjustment capacitor C1 The first end of the electrical connection;
  • the second end of the adjustment capacitor C1 is electrically connected to the first node N1;
  • the second node control circuit 13 includes a first control transistor T11, a control capacitor C1, a second control transistor T8 and a third control transistor T9, wherein,
  • the first end of the control capacitor C1 is electrically connected to the third node N3, and the second end of the control capacitor C1 is electrically connected to the fifth node N5;
  • the gate of the first control transistor T11 is electrically connected to the third node N3, the drain of the first control transistor T11 is electrically connected to the fifth node N5, and the source of the first control transistor T11 electrically connected to the second clock signal terminal CB;
  • the gate of the second control transistor T8 is electrically connected to the second clock signal terminal CB, the source of the second control transistor T8 is electrically connected to the fifth node N5, and the second control transistor T8 is the drain is electrically connected to the second node N2;
  • the gate of the third control transistor T9 is electrically connected to the first isolation node N01, the source of the third control transistor T9 is electrically connected to the high voltage terminal V01, and the drain of the third control transistor T9 is electrically connected to the high voltage terminal V01. the second node N2 is electrically connected;
  • the third node control circuit 15 includes a fourth control transistor T2, a third isolation transistor T12, a fifth control transistor T5 and a sixth control transistor T6, wherein,
  • the gate of the fourth control transistor T2 is electrically connected to the first clock signal terminal CK, and the source of the fourth control transistor T2 is electrically connected to the low voltage terminal V02;
  • the gate of the third isolation transistor T12 is electrically connected to the low voltage terminal V02, the source of the third isolation transistor T12 is electrically connected to the drain of the fourth control transistor T2, and the drain of the third isolation transistor T12 is electrically connected electrically connected to the third node N3;
  • the gate of the fifth control transistor T5 is electrically connected to the first isolation node N01, the source of the fifth control transistor T5 is electrically connected to the high voltage terminal V01, and the drain of the fifth control transistor T5 is electrically connected to the fourth Node N4 is electrically connected;
  • the gate of the sixth control transistor T6 is electrically connected to the second clock signal terminal CB, the source of the sixth control transistor T6 is electrically connected to the fourth node N4, and the drain of the sixth control transistor T6 electrically connected to the third node N3;
  • the first node control circuit 16 includes a seventh control transistor T1 and an eighth control transistor T7, wherein,
  • the gate of the seventh control transistor T1 is electrically connected to the first clock signal terminal CK, the source of the seventh control transistor T1 is electrically connected to the input terminal I1, and the drain of the seventh control transistor T1 is electrically connected to the input terminal I1.
  • the first isolation node N01 is electrically connected;
  • the gate of the eighth control transistor T7 is electrically connected to the fourth node N4, the drain of the eighth control transistor T7 is electrically connected to the first isolation node N01, and the source of the eighth control transistor T7 The pole is electrically connected with the high voltage terminal V01;
  • the output circuit 17 includes a first output transistor T3 and a second output transistor T4;
  • the gate of the first output transistor T3 is electrically connected to the first node N1, the source of the first output transistor T3 is electrically connected to the low voltage terminal V02, and the drain of the first output transistor T3 is electrically connected to the first node N1.
  • the driving voltage signal terminal O1 is electrically connected;
  • the gate of the second output transistor T4 is electrically connected to the second node N2, the drain of the second output transistor T4 is electrically connected to the driving voltage signal terminal O1, and the source of the second output transistor T4 The pole is electrically connected with the high voltage terminal V01;
  • the first energy storage circuit 12 includes a first storage capacitor C4, and the second energy storage circuit 14 includes a second storage capacitor C3;
  • the first terminal of the first storage capacitor C4 is electrically connected to the first node N1, and the second terminal of the first storage capacitor C4 is electrically connected to the low voltage terminal V02;
  • the first terminal of the second storage capacitor C3 is electrically connected to the second node N2, and the second terminal of the second storage capacitor C3 is electrically connected to the output clock signal terminal CBo.
  • the high voltage terminal may provide a high voltage signal
  • the low voltage terminal may provide a low voltage signal
  • control voltage terminal is a low voltage terminal, but not limited thereto.
  • the thirteenth embodiment of the shift register unit described in the present disclosure is a shift register unit in a gate driving circuit for generating a gate driving signal.
  • all transistors are p-type thin film transistors, but not limited thereto.
  • the difference between the thirteenth embodiment of the shift register unit described in the present disclosure and the tenth embodiment of the shift register unit described in the present disclosure is that T13 and T12 are added.
  • the purpose of increasing T13 is to prevent the occurrence of DIBL (Drain Induced Barrier Lowering, drain induced potential) in the transistor electrically connected to N1 when the potential of N1 is too low barrier lowering), so that the threshold voltage of the transistor electrically connected to N1 is shifted, resulting in the situation that the transistor electrically connected to N1 cannot be turned on or off normally in other working stages;
  • DIBL Drain Induced Barrier Lowering, drain induced potential
  • T12 The purpose of adding T12 is to prevent the threshold voltage of the transistor electrically connected to the potential of N3 from shifting, resulting in the situation that the transistor electrically connected to N3 cannot be turned on or off normally in other working stages.
  • the first isolation circuit 41 includes a first isolation transistor T13, and the third isolation circuit 43 includes a third isolation transistor T12;
  • the gate of T13 is electrically connected to the low voltage terminal V02, the source of T13 is electrically connected to N01, and the drain of T13 is electrically connected to N1;
  • the gate of T12 is electrically connected to the low voltage terminal V02, the source of T12 is electrically connected to N03, and the drain of T12 is electrically connected to N3;
  • the first node potential adjustment circuit 11 includes an adjustment transistor T10 and an adjustment capacitor C2, wherein,
  • the gate of the adjustment transistor T10 is electrically connected to the first node N1, the source of the adjustment transistor T10 is electrically connected to the second clock signal terminal CB, and the drain of the adjustment transistor T10 is electrically connected to the adjustment capacitor C1 The first end of the electrical connection;
  • the second end of the adjustment capacitor C1 is electrically connected to the first node N1;
  • the second node control circuit 13 includes a first control transistor T11, a control capacitor C1, a second control transistor T8 and a third control transistor T9, wherein,
  • the first end of the control capacitor C1 is electrically connected to the third node N3, and the second end of the control capacitor C1 is electrically connected to the fifth node N5;
  • the gate of the first control transistor T11 is electrically connected to the third node N3, the drain of the first control transistor T11 is electrically connected to the fifth node N5, and the source of the first control transistor T11 electrically connected to the second clock signal terminal CB;
  • the gate of the second control transistor T8 is electrically connected to the second clock signal terminal CB, the source of the second control transistor T8 is electrically connected to the fifth node N5, and the second control transistor T8 is the drain is electrically connected to the second node N2;
  • the gate of the third control transistor T9 is electrically connected to the first isolation node N01, the source of the third control transistor T9 is electrically connected to the high voltage terminal V01, and the drain of the third control transistor T9 is electrically connected to the high voltage terminal V01. the second node N2 is electrically connected;
  • the third node control circuit 15 includes a fourth control transistor T2, a fifth control transistor T5 and a sixth control transistor T6, wherein,
  • the gate of the fourth control transistor T2 is electrically connected to the first clock signal terminal CK, the source of the fourth control transistor T2 is electrically connected to the low voltage terminal V02, and the drain of the fourth control transistor T2 is electrically connected to the first clock signal terminal CK.
  • the gate of the fifth control transistor T5 is electrically connected to the first isolation node N01, the source of the fifth control transistor T5 is electrically connected to the high voltage terminal V01, and the drain of the fifth control transistor T5 is electrically connected to the fourth Node N4 is electrically connected;
  • the gate of the sixth control transistor T6 is electrically connected to the second clock signal terminal CB, the source of the sixth control transistor T6 is electrically connected to the fourth node N4, and the drain of the sixth control transistor T6 electrically connected to the third isolation node N03;
  • the first node control circuit 16 includes a seventh control transistor T1 and an eighth control transistor T7, wherein,
  • the gate of the seventh control transistor T1 is electrically connected to the first clock signal terminal CK, the source of the seventh control transistor T1 is electrically connected to the input terminal I1, and the drain of the seventh control transistor T1 is electrically connected to the input terminal I1.
  • the first isolation node N01 is electrically connected;
  • the gate of the eighth control transistor T7 is electrically connected to the fourth node N4, the drain of the eighth control transistor T7 is electrically connected to the first isolation node N1, and the source of the eighth control transistor T7 The pole is electrically connected with the high voltage terminal V01;
  • the output circuit 17 includes a first output transistor T3 and a second output transistor T4;
  • the gate of the first output transistor T3 is electrically connected to the first node N1, the source of the first output transistor T3 is electrically connected to the low voltage terminal V02, and the drain of the first output transistor T3 is electrically connected to the first node N1.
  • the driving voltage signal terminal O1 is electrically connected;
  • the gate of the second output transistor T4 is electrically connected to the second node N2, the drain of the second output transistor T4 is electrically connected to the driving voltage signal terminal O1, and the source of the second output transistor T4 The pole is electrically connected with the high voltage terminal V01;
  • the first energy storage circuit 12 includes a first storage capacitor C4, and the second energy storage circuit 14 includes a second storage capacitor C3;
  • the first terminal of the first storage capacitor C4 is electrically connected to the first node N1, and the second terminal of the first storage capacitor C4 is electrically connected to the low voltage terminal V02;
  • the first terminal of the second storage capacitor C3 is electrically connected to the second node N2, and the second terminal of the second storage capacitor C3 is electrically connected to the output clock signal terminal CBo.
  • the high voltage terminal may provide a high voltage signal
  • the low voltage terminal may provide a low voltage signal
  • the fourteenth embodiment of the shift register unit described in the present disclosure is a shift register unit in a gate driving circuit for generating a gate driving signal.
  • all transistors are p-type thin film transistors, but not limited thereto.
  • the difference between the fourteenth embodiment of the shift register unit described in the present disclosure and the tenth embodiment of the shift register unit described in the present disclosure is that T13 and T12 are added.
  • the purpose of increasing T13 is to prevent the occurrence of DIBL (Drain Induced Barrier Lowering, drain induced potential) in the transistor electrically connected to N1 when the potential of N1 is too low barrier lowering), so that the threshold voltage of the transistor electrically connected to N1 is shifted, resulting in the situation that the transistor electrically connected to N1 cannot be turned on or off normally in other working stages;
  • DIBL Drain Induced Barrier Lowering, drain induced potential
  • T12 The purpose of adding T12 is to prevent the threshold voltage of the transistor electrically connected to the potential of N3 from shifting, resulting in the situation that the transistor electrically connected to N3 cannot be turned on or off normally in other working stages.
  • the first isolation circuit 41 includes a first isolation transistor T13
  • the third isolation circuit 43 includes a third isolation transistor T12
  • the second isolation circuit 42 includes a second isolation transistor T14;
  • the gate of T13 is electrically connected to the low voltage terminal V02, the source of T13 is electrically connected to N01, and the drain of T13 is electrically connected to N1;
  • the gate of T12 is electrically connected to the low voltage terminal V02, the source of T12 is electrically connected to N03, and the drain of T12 is electrically connected to N3;
  • the gate of T14 is electrically connected to the low voltage terminal V02, the source of T14 is electrically connected to N02, and the drain of T14 is electrically connected to N2;
  • the first node potential adjustment circuit 11 includes an adjustment transistor T10 and an adjustment capacitor C2, wherein,
  • the gate of the adjustment transistor T10 is electrically connected to the first node N1, the source of the adjustment transistor T10 is electrically connected to the second clock signal terminal CB, and the drain of the adjustment transistor T10 is electrically connected to the adjustment capacitor C1 The first end of the electrical connection;
  • the second end of the adjustment capacitor C1 is electrically connected to the first node N1;
  • the second node control circuit 13 includes a first control transistor T11, a control capacitor C1, a second control transistor T8 and a third control transistor T9, wherein,
  • the first end of the control capacitor C1 is electrically connected to the third node N3, and the second end of the control capacitor C1 is electrically connected to the fifth node N5;
  • the gate of the first control transistor T11 is electrically connected to the third node N3, the drain of the first control transistor T11 is electrically connected to the fifth node N5, and the source of the first control transistor T11 electrically connected to the second clock signal terminal CB;
  • the gate of the second control transistor T8 is electrically connected to the second clock signal terminal CB, the source of the second control transistor T8 is electrically connected to the fifth node N5, and the second control transistor T8 is the drain is electrically connected to the second isolation node N02;
  • the gate of the third control transistor T9 is electrically connected to the first isolation node N01, the source of the third control transistor T9 is electrically connected to the high voltage terminal V01, and the drain of the third control transistor T9 is electrically connected to the high voltage terminal V01. the second isolation node N02 is electrically connected;
  • the third node control circuit 15 includes a fourth control transistor T2, a fifth control transistor T5 and a sixth control transistor T6, wherein,
  • the gate of the fourth control transistor T2 is electrically connected to the first clock signal terminal CK, the source of the fourth control transistor T2 is electrically connected to the low voltage terminal V02, and the drain of the fourth control transistor T2 is electrically connected to the first clock signal terminal CK.
  • the gate of the fifth control transistor T5 is electrically connected to the first isolation node N01, the source of the fifth control transistor T5 is electrically connected to the high voltage terminal V01, and the drain of the fifth control transistor T5 is electrically connected to the fourth Node N4 is electrically connected;
  • the gate of the sixth control transistor T6 is electrically connected to the second clock signal terminal CB, the source of the sixth control transistor T6 is electrically connected to the fourth node N4, and the drain of the sixth control transistor T6 electrically connected to the third isolation node N03;
  • the first node control circuit 16 includes a seventh control transistor T1 and an eighth control transistor T7, wherein,
  • the gate of the seventh control transistor T1 is electrically connected to the first clock signal terminal CK, the source of the seventh control transistor T1 is electrically connected to the input terminal I1, and the drain of the seventh control transistor T1 is electrically connected to the input terminal I1.
  • the first isolation node N01 is electrically connected;
  • the gate of the eighth control transistor T7 is electrically connected to the fourth node N4, the drain of the eighth control transistor T7 is electrically connected to the first isolation node N1, and the source of the eighth control transistor T7 The pole is electrically connected with the high voltage terminal V01;
  • the output circuit 17 includes a first output transistor T3 and a second output transistor T4;
  • the gate of the first output transistor T3 is electrically connected to the first node N1, the source of the first output transistor T3 is electrically connected to the low voltage terminal V02, and the drain of the first output transistor T3 is electrically connected to the first node N1.
  • the driving voltage signal terminal O1 is electrically connected;
  • the gate of the second output transistor T4 is electrically connected to the second node N2, the drain of the second output transistor T4 is electrically connected to the driving voltage signal terminal O1, and the source of the second output transistor T4 The pole is electrically connected with the high voltage terminal V01;
  • the first energy storage circuit 12 includes a first storage capacitor C4, and the second energy storage circuit 14 includes a second storage capacitor C3;
  • the first terminal of the first storage capacitor C4 is electrically connected to the first node N1, and the second terminal of the first storage capacitor C4 is electrically connected to the low voltage terminal V02;
  • the first terminal of the second storage capacitor C3 is electrically connected to the second node N2, and the second terminal of the second storage capacitor C3 is electrically connected to the output clock signal terminal CBo.
  • the high voltage terminal may provide a high voltage signal
  • the low voltage terminal may provide a low voltage signal
  • the fifteenth embodiment of the shift register unit described in the present disclosure is a shift register unit in a gate driving circuit for generating a gate driving signal.
  • all transistors are p-type thin film transistors, but not limited thereto.
  • the difference between the fifteenth embodiment of the shift register unit described in the present disclosure and the tenth embodiment of the shift register unit described in the present disclosure is that T13, T12 and T14 are added.
  • the purpose of increasing T13 is to prevent DIBL (Drain Induced Barrier Lowering, Drain Induced Barrier Lowering) from occurring in the transistor electrically connected to N1 when the potential of N1 is too low barrier lowering), so that the threshold voltage of the transistor electrically connected to N1 is shifted, resulting in the situation that the transistor electrically connected to N1 cannot be turned on or off normally in other working stages;
  • DIBL Drain Induced Barrier Lowering, Drain Induced Barrier Lowering
  • T12 The purpose of adding T12 is to prevent the threshold voltage of the transistor electrically connected to the potential of N3 from shifting, resulting in the situation that the transistor electrically connected to N3 cannot be turned on or off normally during other working stages.
  • T14 The purpose of increasing T14 is to prevent DIBL (Drain Induced Barrier Lowering) of the transistor electrically connected to N2 from occurring when the potential of N2 is too low, so that the threshold voltage of the transistor electrically connected to N2 is shifted. , resulting in the situation that the transistor electrically connected to N2 cannot be turned on or off normally during other working stages.
  • DIBL Drain Induced Barrier Lowering
  • the difference between the sixteenth embodiment of the shift register unit described in the present disclosure and the fifteenth embodiment of the shift register unit described in the present disclosure is: the source of T10 and the third clock signal Terminal CKo is electrically connected.
  • the third clock signal provided by CKo may be inverted from the first clock signal provided by CK.
  • the first to sixteenth embodiments of the shift register unit described above in the present disclosure are at least one embodiment of the shift register unit described in the present disclosure.
  • the driving method described in at least one embodiment of the present disclosure is applied to the above-mentioned shift register unit, and the driving method includes:
  • the input signal is controlled to be written into the first isolation node, and under the control of the potential of the fourth node, the first voltage signal is controlled to be written into the first isolation node ;
  • the first node potential adjustment circuit changes the potential of the first node according to the adjustment clock signal under the control of the potential of the first node
  • the third node control circuit controls the potential of the third isolation node and the potential of the fourth node under the control of the first clock signal, the second clock signal and the potential of the first isolation node;
  • the second node control circuit controls the potential of the second isolation node under the control of the potential of the third node and the control clock signal, and controls the first voltage signal to be written into the second isolation node under the control of the potential of the first isolation node. isolated node;
  • the second tank circuit maintains the potential of the second node
  • the output circuit writes the second voltage signal into the driving voltage signal output terminal under the control of the potential of the first node, and the output circuit writes the third voltage signal into the drive voltage signal under the control of the potential of the second node Drive voltage signal terminal.
  • the shift register unit described in at least one embodiment of the present disclosure can provide both a gate driving signal and a light-emitting control signal, so as to provide a waveform of a specific pixel operation;
  • the third voltage terminal may be a first voltage terminal;
  • the shift register unit provides a gate driving signal, the third voltage terminal may be an output clock a signal terminal; the output clock signal provided by the output clock signal terminal is a clock signal inverted to the second clock signal.
  • the first node potential adjustment circuit is electrically connected to the adjustment clock signal terminal and the first node, respectively, and under the control of the potential of the first node, according to
  • the adjustment clock signal provided by the adjustment clock signal terminal changes the potential of the first node, so that when the first output transistor in the output circuit needs to be turned on, the potential of the first node can drop to a low enough voltage so that the first node can be turned on.
  • An output transistor is fully turned on to avoid the problem of reducing the output waveform of the driving voltage signal terminal by the threshold voltage loss of the first output transistor.
  • the driving voltage signal terminal is a gate driving signal output terminal
  • the third voltage terminal is an output clock signal terminal
  • the output clock signal provided by the output clock signal terminal is the same as the second clock signal an inverted clock signal
  • the driving voltage signal terminal is a light-emitting control signal terminal
  • the third voltage terminal is a first voltage terminal
  • the driving circuit according to at least one embodiment of the present disclosure includes multiple stages of the above-mentioned shift register unit.
  • the input terminal of the shift register unit of the driving circuit is electrically connected to the driving voltage signal output terminal of the adjacent upper-stage shift register unit;
  • the first clock signal connected to the odd-numbered stage shift register unit is the second clock signal connected to the even-numbered stage shift register unit, and the odd-numbered stage shift register unit is connected to the second clock signal.
  • the accessed second clock signal is the first clock signal accessed by the even-numbered shift register unit, but not limited to this;
  • the output clock signal connected to the odd-numbered stage shift register unit is the third clock signal connected to the even-numbered stage shift register unit, and the odd-numbered stage shift register unit is connected to the third clock signal.
  • the third clock signal is an output clock signal connected to the even-numbered shift register units, but not limited to this.
  • the driving circuit is a gate driving circuit
  • the driving voltage signal terminal is the gate driving signal output terminal
  • the third voltage terminal is the output clock signal terminal
  • the output clock signal provided by the output clock signal terminal is the same as that of the third voltage terminal.
  • Two clock signals are inverted clock signals.
  • the driving circuit is a lighting control signal generating circuit; the driving voltage signal terminal is the lighting control signal terminal, and the third voltage terminal is the first voltage terminal.
  • the display device includes the above-mentioned driving circuit.
  • the display device provided by at least one embodiment of the present disclosure may be any product or component with a display function, such as a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • a display function such as a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, and a navigator.

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Abstract

提供了一种移位寄存器单元、驱动方法、驱动电路和显示装置。移位寄存器单元包括第一节点电位调节电路（11）、第一储能电路（12）、第二节点控制电路（13）、第二储能电路（14）、第三节点控制电路（15）、第一节点控制电路（16）和输出电路（17）；第一节点电位调节电路（11）在第一节点（N1）的电位的控制下，根据调节时钟信号（CK）改变第一节点（N1）的电位；第一储能电路（12）用于维持第一节点（N1）的电位；第三节点控制电路（15）控制第三隔离节点（N03）的电位和第四节点（N4）的电位；第二节点控制电路（13）控制第二隔离节点（N02）的电位。移位寄存器既可以提供栅极驱动信号，又可以提供发光控制信号，以提供特定像素工作的波形。

Description

移位寄存器单元、驱动方法、驱动电路和显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种移位寄存器单元、驱动方法、驱动电路和显示装置。
背景技术
相关的移位寄存器单元不能既能够提供栅极驱动信号，又能够提供发光控制信号，不能方便的提供特定像素工作的波形。并且，相关的移位寄存器单元不能使得输出电路中的第一输出晶体管充分打开，使得驱动电压信号端的输出波形受到第一输出晶体管的阈值电压损耗。
发明内容
在一个方面中，本公开实施例提供了一种移位寄存器单元，包括第一节点电位调节电路、第一储能电路、第二节点控制电路、第二储能电路、第三节点控制电路、第一节点控制电路和输出电路；其中，
所述第一节点控制电路分别与输入端、第一时钟信号端、第一隔离节点、第四节点和第一电压端电连接，用于在第一时钟信号端提供的第一时钟信号的控制下，控制将输入端提供的输入信号写入第一隔离节点，并在第四节点的电位的控制下，控制将所述第一电压端提供的第一电压信号写入至第一隔离节点；
所述第一节点电位调节电路分别与调节时钟信号端和第一节点电连接，用于在第一节点的电位的控制下，根据调节时钟信号端提供的调节时钟信号改变第一节点的电位；
所述第一储能电路与所述第一节点电连接，用于维持所述第一节点的电位；
所述第三节点控制电路分别与第一时钟信号端、第二时钟信号端、第一隔离节点、第三隔离节点、第四节点、第一电压端和第二电压端电连接，用于在第一时钟信号、第二时钟信号和第一隔离节点的电位的控制下，控制所 述第三隔离节点的电位和所述第四节点的电位；
所述第二节点控制电路分别与第一隔离节点、第一电压端、第二隔离节点、控制时钟信号端和第三节点电连接，用于在第三节点的电位和所述控制时钟信号端提供的控制时钟信号的控制下，控制第二隔离节点的电位，并在第一隔离节点的电位的控制下，控制第一电压端提供的第一电压信号写入第二隔离节点；
所述第二储能电路用于维持所述第二节点的电位；
所述输出电路分别与第一节点、第二电压端、驱动电压信号端和第三电压端电连接，用于在第一节点的电位的控制下，将第二电压端提供的第二电压信号写入驱动电压信号输出端，并用于在第二节点的电位的控制下，将第三电压端提供的第三电压信号写入所述驱动电压信号端；
所述第一隔离节点与所述第一节点为同一节点；或者，所述第一隔离节点与所述第一节点为不同的节点。
可选的，当所述第一隔离节点与所述第一节点为不同的节点时，所述第一隔离节点与所述第一节点之间通过第一隔离电路电连接；
所述第一隔离电路的控制端与控制电压端电连接，所述第一隔离电路用于在所述控制电压端提供的控制电压信号的控制下，控制所述第一隔离节点与所述第一节点之间连通。
可选的，所述第一隔离电路包括第一隔离晶体管；
所述第一隔离晶体管的控制极与控制电压端电连接，所述第一隔离晶体管的第一极与所述第一隔离节点电连接，所述第一隔离晶体管的第二极与所述第一节点电连接。
可选的，所述第二隔离节点与所述第二节点为同一节点；或者，所述第二隔离节点与所述第二节点之间通过第二电路电连接；
所述第二隔离电路的控制端与控制电压端电连接，所述第二隔离电路用于在所述控制电压端提供的控制电压信号的控制下，控制所述第二隔离节点与所述第二节点之间连通。
可选的，所述第二隔离电路包括第二隔离晶体管；
所述第二隔离晶体管的控制极与控制电压端电连接，所述第二隔离晶体 管的第一极与所述第二隔离节点电连接，所述第二隔离晶体管的第二极与所述第二节点电连接。
可选的，所述第三隔离节点与所述第三节点为同一节点；或者，所述第三隔离节点与所述第三节点之间通过第三隔离电路电连接；
所述第三隔离电路的控制端与控制电压端电连接，所述第三隔离电路用于在所述控制电压端提供的控制电压信号的控制下，控制所述第三隔离节点与所述第三节点之间连通。
可选的，所述第三隔离电路包括第三隔离晶体管；
所述第三隔离晶体管的控制极与控制电压端电连接，所述第三隔离晶体管的第一极与所述第三隔离节点电连接，所述第三隔离晶体管的第二极与所述第三节点电连接。
可选的，所述控制时钟信号端为第二时钟信号端；或者，
所述驱动电压信号端为发光控制信号端，所述控制时钟信号端为第一时钟信号端。
可选的，所述调节时钟信号端提供的调节时钟信号为所述第二时钟信号，或者，所述调节时钟信号为与所述第一时钟信号反相的时钟信号。
可选的，所述驱动电压信号端为栅极驱动信号输出端，所述第三电压端为输出时钟信号端；所述输出时钟信号端提供的输出时钟信号为与所述第二时钟信号反相的时钟信号；或者，
所述驱动电压信号端为发光控制信号端，所述第三电压端为第一电压端。
可选的，所述第一节点电位调节电路包括调节晶体管和调节电容，其中，
所述调节晶体管的控制极与所述第一隔离节点电连接，所述调节晶体管的第一极与调节时钟信号端电连接，所述调节晶体管的第二极与所述调节电容的第一端电连接；
所述调节电容的第二端与所述第一隔离节点电连接。
可选的，所述第二节点控制电路还与第一时钟信号端电连接，还用于在第一时钟信号的控制下，控制所述第二隔离节点的电位。
可选的，第二节点控制电路包括第一控制晶体管、控制电容、第二控制晶体管和第三控制晶体管，其中，
所述控制电容的第一端与所述第三节点电连接，所述控制电容的第二端与第五节点电连接；
所述第一控制晶体管的控制极与所述第三节点电连接，所述第一控制晶体管的第一极与所述第五节点电连接，所述第一控制晶体管的第二极与控制时钟信号端电连接；
所述第二控制晶体管的控制极与所述第二时钟信号端电连接，所述第二控制晶体管的第一极与所述第五节点电连接，所述第二控制晶体管的第二极与第二隔离节点电连接；
所述第三控制晶体管的控制极与所述第一节点电连接，所述第三控制晶体管的第一极与第一电压端电连接，所述第三控制晶体管的第二极与所述第二隔离节点电连接。
可选的，第二节点控制电路包括第一控制晶体管、控制电容、第二控制晶体管、第三控制晶体管和节点控制晶体管，其中，
所述控制电容的第一端与所述第三节点电连接，所述控制电容的第二端与第五节点电连接；
所述第一控制晶体管的控制极与所述第三节点电连接，所述第一控制晶体管的第一极与所述第五节点电连接，所述第一控制晶体管的第二极与控制时钟信号端电连接；
所述第二控制晶体管的控制极与所述第二时钟信号端电连接，所述第二控制晶体管的第一极与所述第五节点电连接，所述第二控制晶体管的第二极与第二隔离节点电连接；
所述第三控制晶体管的控制极与所述第一节点电连接，所述第三控制晶体管的第一极与第一电压端电连接；
所述节点控制晶体管的控制极与第一时钟信号端电连接，所述节点控制晶体管的第一极与所述第三控制晶体管的第二极电连接，所述节点控制晶体管的第二极与第二节点电连接。
可选的，第二节点控制电路包括第一控制晶体管、控制电容、第二控制晶体管和第三控制晶体管，其中，
所述控制电容的第一端与所述第三节点电连接；
所述第一控制晶体管的控制极与所述第三节点电连接，所述第一控制晶体管的第一极与所述控制电容的第二端电连接，所述第一控制晶体管的第二极与第二时钟信号端电连接；所述第二控制晶体管的控制极与所述第二时钟信号端电连接，所述第二控制晶体管的第一极与所述第二隔离节点电连接；
所述第三控制晶体管的控制极与所述第一隔离节点电连接，所述第三控制晶体管的第一极与第一电压端电连接，所述第三控制晶体管的第二极与所述第二隔离节点电连接。
可选的，所述第三节点控制电路包括第四控制晶体管、第五控制晶体管和第六控制晶体管，其中，
所述第四控制晶体管的控制极与第一时钟信号端电连接，所述第四控制晶体管的第一极与第二电压端电连接，所述第四控制晶体管的第二极与第三隔离节点电连接；
所述第五控制晶体管的控制极与第一隔离节点电连接，所述第五控制晶体管的第一极与第一电压端电连接，所述第五控制晶体管的第二极与第四节点电连接；
所述第六控制晶体管的控制极与第二时钟信号端电连接，所述第六控制晶体管的第一极与所述第四节点电连接，所述第六控制晶体管的第二极与所述第三隔离节点电连接。
可选的，本公开至少一实施例所述的移位寄存器单元还包括第三隔离晶体管；所述第三隔离节点为第三节点；
所述第四控制晶体管的第二极通过所述第三隔离晶体管与所述第三节点电连接；
所述第三隔离晶体管的控制极与控制电压端电连接，所述第三隔离晶体管的第一极与所述第四控制晶体管的第二极电连接，所述第三隔离晶体管的第二极与所述第三节点电连接。
可选的，所述驱动电压信号端为发光控制信号端，所述第三电压端为第一电压端；
所述第三节点控制电路包括第四控制晶体管、第五控制晶体管和第六控制晶体管，其中，
所述第四控制晶体管的控制极与第二时钟信号端电连接，所述第四控制晶体管的第一极与第二电压端电连接，所述第四控制晶体管的第二极与第三隔离节点电连接；
所述第五控制晶体管的控制极与第一隔离节点电连接，所述第五控制晶体管的第一极与第一电压端电连接，所述第五控制晶体管的第二极与第四节点电连接；
所述第六控制晶体管的控制极与第一时钟信号端电连接，所述第六控制晶体管的第一极与所述第四节点电连接，所述第六控制晶体管的第二极与所述第三隔离节点电连接。
可选的，本公开至少一实施例所述的移位寄存器单元还包括第三隔离晶体管；所述第三隔离节点为第三节点；
所述第四控制晶体管的第二极通过所述第三隔离晶体管与所述第三节点电连接；
所述第三隔离晶体管的控制极与控制电压端电连接，所述第三隔离晶体管的第一极与所述第四控制晶体管的第二极电连接，所述第三隔离晶体管的第二极与所述第三节点电连接。
可选的，所述第一节点控制电路包括第七控制晶体管和第八控制晶体管，其中，
所述第七控制晶体管的控制极与第一时钟信号端电连接，所述第七控制晶体管的第一极与所述输入端电连接，所述第七控制晶体管的第二极与所述第一隔离节点电连接；
所述第八控制晶体管的控制极与所述第四节点电连接，所述第八控制晶体管的第一极与所述第一隔离节点电连接，所述第八控制晶体管的第二极与第一电压端电连接。
可选的，所述输出电路包括第一输出晶体管和第二输出晶体管；
所述第一输出晶体管的控制极与所述第一节点电连接，所述第一输出晶体管的第一极与第二电压端电连接，所述第一输出晶体管的第二极与所述驱动电压信号端电连接；
所述第二输出晶体管的控制极与所述第二节点电连接，所述第二输出晶 体管的第一极与所述驱动电压信号端电连接，所述第二输出晶体管的第二极与所述第三电压端电连接。
可选的，所述第一储能电路包括第一存储电容，所述第二储能电路包括第二存储电容；
所述第一存储电容的第一端与所述第一节点电连接，所述第一存储电容的第二端与第二电压端电连接；
所述第二存储电容的第一端与所述第二节点电连接，所述第二存储电容的第二端与第三电压端电连接；
所述驱动电压信号端为栅极驱动信号输出端，所述第三电压端为输出时钟信号端；所述输出时钟信号端提供的输出时钟信号为与所述第二时钟信号反相的时钟信号；或者，
所述驱动电压信号端为发光控制信号端，所述第三电压端为第一电压端。
在第二个方面中，本公开实施例还提供了一种驱动方法，应用于上述的移位寄存器单元，所述驱动方法包括：
所述第一节点控制电路第一时钟信号的控制下，控制将输入信号写入第一隔离节点，并在第四节点的电位的控制下，控制将第一电压信号写入至第一隔离节点；
所述第一节点电位调节电路在第一节点的电位的控制下，根据调节时钟信号改变第一节点的电位；
所述第一储能电路所述第一节点的电位；
所述第三节点控制电路在第一时钟信号、第二时钟信号和第一隔离节点的电位的控制下，控制所述第三隔离节点的电位和所述第四节点的电位；
所述第二节点控制电路在第三节点的电位和控制时钟信号的控制下，控制第二隔离节点的电位，并在第一隔离节点的电位的控制下，控制第一电压信号写入第二隔离节点；
所述第二储能电路维持所述第二节点的电位；
所述输出电路在第一节点的电位的控制下，将第二电压信号写入驱动电压信号输出端，所述输出电路在第二节点的电位的控制下，将第三电压信号写入所述驱动电压信号端。
在第三个方面中，本公开实施例还提供了一种驱动电路，包括多级上述的移位寄存器单元。
可选的，所述驱动电路为栅极驱动电路，驱动电压信号端为栅极驱动信号输出端，第三电压端为输出时钟信号端；所述输出时钟信号端提供的输出时钟信号为与第二时钟信号反相的时钟信号。
可选的，所述驱动电路为发光控制信号生成电路；驱动电压信号端为发光控制信号端，第三电压端为第一电压端。
在第四个方面中，本公开实施例还提供了一种显示装置，包括上述的驱动电路。
附图说明
图1是本公开至少一实施例所述的移位寄存器单元的结构图；
图2是本公开至少一实施例所述的移位寄存器单元的结构图；
图3是本公开至少一实施例所述的移位寄存器单元的结构图；
图4是本公开至少一实施例所述的移位寄存器单元的结构图；
图5是本公开至少一实施例所述的移位寄存器单元的结构图；
图6是本公开至少一实施例所述的移位寄存器单元的结构图；
图7是本公开至少一实施例所述的移位寄存器单元的结构图；
图8是本公开至少一实施例所述的移位寄存器单元的结构图；
图9是本公开至少一实施例所述的移位寄存器单元的结构图；
图10是本公开至少一实施例所述的移位寄存器单元的结构图；
图11是本公开实施例所述的移位寄存器单元的结构图；
图12是本公开所述的移位寄存器单元的第一实施例的电路图；
图13是本公开所述的移位寄存器单元的第一实施例的工作时序图；
图14A是本公开所述的移位寄存器单元的第一实施例在第一时间段t1的电路状态示意图；
图14B是本公开所述的移位寄存器单元的第一实施例在第二时间段t2的电路状态示意图；
图14C是本公开所述的移位寄存器单元的第一实施例在第三时间段t3的 电路状态示意图；
图14D是本公开所述的移位寄存器单元的第一实施例在第四时间段t4的电路状态示意图；
图14E是本公开所述的移位寄存器单元的第一实施例在第五时间段t5的电路状态示意图；
图14F是本公开所述的移位寄存器单元的第一实施例在第六时间段t6的电路状态示意图；
图14G是本公开所述的移位寄存器单元的第一实施例在第七时间段t7的电路状态示意图；
图14H是本公开所述的移位寄存器单元的第一实施例在第八时间段t8的电路状态示意图；
图15是本公开所述的移位寄存器单元的第二实施例的电路图；
图16是本公开所述的移位寄存器单元的第三实施例的电路图；
图17是本公开所述的移位寄存器单元的第四实施例的电路图；
图18是本公开所述的移位寄存器单元的第五实施例的电路图；
图19是本公开所述的移位寄存器单元的第五实施例的第一工作时序图；
图20是本公开所述的移位寄存器单元的第五实施例的的第二工作时序图；
图21是本公开所述的移位寄存器单元的第六实施例的电路图；
图22是本公开所述的移位寄存器单元的第七实施例的电路图；
图23是本公开所述的移位寄存器单元的第八实施例的电路图；
图24是本公开所述的移位寄存器单元的第九实施例的电路图；
图25是本公开所述的移位寄存器单元的第十实施例的电路图；
图26是本公开所述的移位寄存器单元的第十实施例的工作时序图；
图27A是本公开所述的移位寄存器单元的第十实施例在第一时间段t1的电路状态示意图；
图27B是本公开所述的移位寄存器单元的第十实施例在第二时间段t2的电路状态示意图；
图27C是本公开所述的移位寄存器单元的第十实施例在第三时间段t3的 电路状态示意图；
图27D是本公开所述的移位寄存器单元的第十实施例在第四时间段t4的电路状态示意图；
图27E是本公开所述的移位寄存器单元的第十实施例在第五时间段t5的电路状态示意图；
图28是本公开所述的移位寄存器单元的第十一实施例的电路图；
图29是本公开所述的移位寄存器单元的第十二实施例的电路图；
图30是本公开所述的移位寄存器单元的第十三实施例的电路图；
图31是本公开所述的移位寄存器单元的第十四实施例的电路图；
图32是本公开所述的移位寄存器单元的第十五实施例的电路图；
图33是本公开所述的移位寄存器单元的第十六实施例的电路图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为三极管、薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除控制极之外的两极，将其中一极称为第一极，另一极称为第二极。
在实际操作时，当所述晶体管为三极管时，所述控制极可以为基极，所述第一极可以为集电极，所述第二极可以发射极；或者，所述控制极可以为基极，所述第一极可以为发射极，所述第二极可以集电极。
在实际操作时，当所述晶体管为薄膜晶体管或场效应管时，所述控制极可以为栅极，所述第一极可以为漏极，所述第二极可以为源极；或者，所述控制极可以为栅极，所述第一极可以为源极，所述第二极可以为漏极。
本公开至少一实施例所述的移位寄存器单元包括第一节点电位调节电路、第一储能电路、第二节点控制电路、第二储能电路、第三节点控制电路、第一节点控制电路和输出电路；其中，
所述第一节点控制电路分别与输入端、第一时钟信号端、第一隔离节点、第四节点和第一电压端电连接，用于在第一时钟信号端提供的第一时钟信号的控制下，控制将输入端提供的输入信号写入第一隔离节点，并在第四节点的电位的控制下，控制将所述第一电压端提供的第一电压信号写入至第一隔离节点；
所述第一节点电位调节电路分别与调节时钟信号端和第一节点电连接，用于在第一节点的电位的控制下，根据调节时钟信号端提供的调节时钟信号改变第一节点的电位；
所述第一储能电路与所述第一节点电连接，用于维持所述第一节点的电位；
所述第三节点控制电路分别与第一时钟信号端、第二时钟信号端、第一隔离节点、第三隔离节点、第四节点、第一电压端和第二电压端电连接，用于在第一时钟信号、第二时钟信号和第一隔离节点的电位的控制下，控制所述第三隔离节点的电位和所述第四节点的电位；
所述第二节点控制电路分别与第一隔离节点、第一电压端、第二隔离节点、控制时钟信号端和第三节点电连接，用于在第三节点的电位和所述控制时钟信号端提供的控制时钟信号的控制下，控制第二隔离节点的电位，并在第一隔离节点的电位的控制下，控制第一电压端提供的第一电压信号写入第二隔离节点；
所述第二储能电路用于维持所述第二节点的电位；
所述输出电路分别与第一节点、第二电压端、驱动电压信号端和第三电压端电连接，用于在第一节点的电位的控制下，将第二电压端提供的第二电压信号写入驱动电压信号输出端，并用于在第二节点的电位的控制下，将第三电压端提供的第三电压信号写入所述驱动电压信号端；
所述第一隔离节点与所述第一节点为同一节点；或者，所述第一隔离节点与所述第一节点为不同的节点。
本公开至少一实施例所述的移位寄存器单元既可以提供栅极驱动信号，又可以提供发光控制信号，以提供特定像素工作的波形；在所述移位寄存器单元提供发光控制信号时，所述第三电压端可以为第一电压端；在所述移位 寄存器单元提供栅极驱动信号时，所述第三电压端可以为输出时钟信号端；所述输出时钟信号端提供的输出时钟信号为与所述第二时钟信号反相的时钟信号。并且，本公开至少一实施例所述的移位寄存器单元在工作时，所述第一节点电位调节电路分别与调节时钟信号端和所述第一节点电连接，用于在第一节点的电位的控制下，根据调节时钟信号端提供的调节时钟信号改变第一节点的电位，以使得需要使得输出电路中的第一输出晶体管打开时，所述第一节点的电位可以下降至够低电压，以使得所述第一输出晶体管充分打开，避免驱动电压信号端的输出波形受到第一输出晶体管的阈值电压损耗问题；并本公开至少一实施例所述的移位寄存器单元可以实现窄边框设计。
在本公开至少一实施例中，所述第一电压端可以为高电压端，所述第二电压端可以为低电压端，但不以此为限。
本公开至少一实施例所述的移位寄存器单元能够生成发光控制信号或栅极驱动信号，但是不能同时生成发光控制信号和栅极驱动信号；当需要同时提供发光控制信号和栅极驱动信号时，需要采用两个本公开至少一实施例所述的移位寄存器单元。
可选的，当所述第一隔离节点与所述第一节点为不同的节点时，所述第一隔离节点与所述第一节点之间通过第一隔离电路电连接；
所述第一隔离电路的控制端与控制电压端电连接，所述第一隔离电路用于在所述控制电压端提供的控制电压信号的控制下，控制所述第一隔离节点与所述第一节点之间连通。
在本公开至少一实施例中，所述第一隔离节点和第一节点可以为同一节点；或者，
所述第一隔离节点可以通过第一隔离电路与第一节点电连接，从而使得当第一节点的电位被拉到过低时，使得源极或漏极与所述第一节点电连接的晶体管的阈值电压漂移或性能退化，从而导致该晶体管再次需要打开时打开不完全，避免影响移位寄存器单元的性能。
在具体实施时，所述第一隔离电路可以包括第一隔离晶体管；
所述第一隔离晶体管的控制极与控制电压端电连接，所述第一隔离晶体管的第一极与所述第一隔离节点电连接，所述第一隔离晶体管的第二极与所 述第一节点电连接。
可选的，所述第二隔离节点与所述第二节点为同一节点；或者，所述第二隔离节点与所述第二节点之间通过第二电路电连接；
所述第二隔离电路的控制端与控制电压端电连接，所述第二隔离电路用于在所述控制电压端提供的控制电压信号的控制下，控制所述第二隔离节点与所述第二节点之间连通。
在本公开至少一实施例中，所述第二隔离节点和第二节点可以为同一节点；或者，
所述第二隔离节点可以通过第二隔离电路与第二节点电连接，从而使得当第二节点的电位被拉到过低时，使得源极或漏极与所述第二节点电连接的晶体管的阈值电压漂移或性能退化，从而导致该晶体管再次需要打开时打开不完全，避免影响移位寄存器单元的性能。
在具体实施时，所述第三隔离电路可以包括第三隔离晶体管；
所述第三隔离晶体管的控制极与控制电压端电连接，所述第三隔离晶体管的第一极与所述第三隔离节点电连接，所述第三隔离晶体管的第二极与所述第三节点电连接。
可选的，所述第三隔离节点与所述第三节点为同一节点；或者，所述第三隔离节点与所述第三节点之间通过第三隔离电路电连接；
所述第三隔离电路的控制端与控制电压端电连接，所述第三隔离电路用于在所述控制电压端提供的控制电压信号的控制下，控制所述第三隔离节点与所述第三节点之间连通。
在本公开至少一实施例中，所述第三隔离节点和第三节点可以为同一节点；或者，
所述第三隔离节点可以通过第三隔离电路与第三节点电连接，从而使得当第三节点的电位被拉到过低时，使得源极或漏极与所述第三节点电连接的晶体管的阈值电压漂移或性能退化，从而导致该晶体管再次需要打开时打开不完全，避免影响移位寄存器单元的性能。
在具体实施时，所述第三隔离电路可以包括第三隔离晶体管；
所述第三隔离晶体管的控制极与控制电压端电连接，所述第三隔离晶体 管的第一极与所述第三隔离节点电连接，所述第三隔离晶体管的第二极与所述第三节点电连接。
可选的，所述控制时钟信号端可以为第二时钟信号端；或者，
所述驱动电压信号端为发光控制信号端，所述控制时钟信号端可以为第一时钟信号端。
在具体实施时，所述调节时钟信号端提供的调节时钟信号为所述第二时钟信号，或者，所述调节时钟信号为与所述第一时钟信号反相的时钟信号。
在本公开至少一实施例中，所述驱动电压信号端为栅极驱动信号输出端，所述第三电压端为输出时钟信号端；所述输出时钟信号端提供的输出时钟信号为与所述第二时钟信号反相的时钟信号；或者，
所述驱动电压信号端为发光控制信号端，所述第三电压端为第一电压端。
如图1所示，本公开至少一实施例所述的移位寄存器单元包括第一节点电位调节电路11、第一储能电路12、第二节点控制电路13、第二储能电路14、第三节点控制电路15、第一节点控制电路16和输出电路17；其中，
所述第一节点控制电路16分别与输入端I1、第一时钟信号端CK、第一节点N1、第四节点N4和第一电压端V1电连接，用于在第一时钟信号端CK提供的第一时钟信号的控制下，控制将输入端I1提供的输入信号写入第一节点N1，并在第四节点N4的电位的控制下，控制将所述第一电压端V1提供的第一电压信号写入至第一节点N1；
所述第一节点电位调节电路11分别与第二时钟信号端CB和所述第一节点N1电连接，用于在第一节点N1的电位的控制下，根据第二时钟信号端CB提供的第二时钟信号改变第一节点N1的电位；
所述第一储能电路12与所述第一节点N1电连接，用于维持所述第一节点N1的电位；
所述第三节点控制电路15分别与第一时钟信号端CK、第二时钟信号端CB、第一节点N1、第三节点N3、第四节点N4、第一电压端V1和第二电压端V2)电连接，用于在第一时钟信号、第二时钟信号和第一节点N1的电位的控制下，控制所述第三节点N3的电位和所述第四节点N4的电位；
所述第二节点控制电路13分别与第一节点N1、第一电压端V1、第二节 点N2、第二时钟信号端CB和第三节点N3电连接，用于在第三节点N3的电位和第二时钟信号的控制下，控制第二节点N2的电位，并在第一节点N1的电位的控制下，控制第一电压端V1提供的第一电压信号写入第二节点N2；
所述第二储能电路14与第二节点N2电连接，用于维持所述第二节点N2的电位；
所述输出电路17分别与第一节点N1、第二电压端V2、驱动电压信号端O1和第一电压端V1电连接，用于在第一节点N1的电位的控制下，将第二电压端V2提供的第二电压信号写入驱动电压信号输出端O1，并用于在第二节点N2的电位的控制下，将第一电压端V1提供的第一电压信号写入所述驱动电压信号端。
在图1所示的移位寄存器单元中，所述第一隔离节点与所述第一节点为同一节点，所述第二隔离节点与第二节点为同一节点，所述第三隔离节点与第三节点为同一节点，但不以此为限。
在图1所示的移位寄存器单元中，第三电压端为第一电压端，图1所示的移位寄存器单元用于生成发光控制信号，图1所示的移位寄存器单元为发光控制信号生成电路中的移位寄存器单元。
在图1所示的移位寄存器单元中，控制时钟信号端为第二时钟信号端，调节时钟信号端为第二时钟信号端。
在具体实施时，当所述移位寄存器单元为发光控制生成电路中的移位寄存器单元时，所述第二节点控制电路可以还与第一时钟信号端电连接，还用于在第一时钟信号的控制下，控制所述第二隔离节点的电位。
如图2所示，在图1所示的移位寄存器单元的实施例的基础上，所述第二节点控制电路13还与第一时钟信号端CK电连接，还用于在第一时钟信号的控制下，控制第二节点N2的电位。
如图3所示，图3所示的移位寄存器单元的实施例与图1所示的移位寄存器单元的实施例不同的是：所述控制时钟信号端为第一时钟信号端CK；
所述第二节点控制电路13分别与第一节点N1、第一电压端V1、第二节点N2、第一时钟信号端CK和第三节点N3电连接，用于在第三节点N3的电位和第一时钟信号的控制下，控制第二节点N2的电位，并在第一节点N1 的电位的控制下，控制第一电压端V1提供的第一电压信号写入第二节点N2。
如图4所示，与图1所示的移位寄存器单元的实施例不同的是：第一节点N1和第一隔离节点并非同一节点；
所述移位寄存器单元的至少一实施例还包括第一隔离电路41；第一节点N1通过所述第一隔离电路41与第一隔离节点N01电连接；
所述第一隔离电路41的控制端与控制电压端V0电连接。
如图5所示，与图1所示的移位寄存器单元的实施例不同的是：
所述第一节点N1与第一隔离节点并非同一节点，所述第三节点N3与第三隔离节点并非同一节点；
所述移位寄存器单元的至少一实施例还包括第一隔离电路41和第三隔离电路43；第一节点N1通过所述第一隔离电路41与第一隔离节点N01电连接；第三节点N3通过所述第三隔离电路43与第三隔离节点N03电连接；
所述第一隔离电路41的控制端与控制电压端V0电连接，所述第三隔离电路43的控制端与所述控制电压端V0电连接。
在具体实施时，当所述第一隔离电路41包括的第一隔离晶体管为p型晶体管，所述第三隔离电路43包括的第三隔离晶体管为p型晶体管时，所述控制电压端可以为低电压端；
当所述第一隔离电路41包括的第一隔离晶体管为n型晶体管，所述第三隔离电路43包括的第三隔离晶体管为n型晶体管时，所述控制电压端可以为高电压端；
但不以此为限。
如图6所示，与图5所示的移位寄存器单元的实施例不同的是：
所述移位寄存器单元的至少一实施例还包括第二隔离电路42；
第二隔离节点N02通过第二隔离电路42与所述第二节点N2电连接；
所述第二隔离电路42的控制端与所述控制电压端V0电连接。
在具体实施时，当所述第二隔离电路42包括的第二隔离晶体管为p型晶体管，所述控制电压端可以为低电压端；
当所述第二隔离电路41包括的第二隔离晶体管为n型晶体管，所述控制电压端可以为高电压端；
但不以此为限。
如图7所示，本公开至少一实施例所述的移位寄存器单元包括第一节点电位调节电路11、第一储能电路12、第二节点控制电路13、第二储能电路14、第三节点控制电路15、第一节点控制电路16和输出电路17；其中，
所述第一节点控制电路16分别与输入端I1、第一时钟信号端CK、第一节点N1、第四节点N4和第一电压端V1电连接，用于在第一时钟信号端CK提供的第一时钟信号的控制下，控制将输入端I1提供的输入信号写入第一节点N1，并在第四节点N4的电位的控制下，控制将所述第一电压端V1提供的第一电压信号写入至第一节点N1；
所述第一节点电位调节电路11分别与第二时钟信号端CB和所述第一节点N1电连接，用于在第一节点N1的电位的控制下，根据第二时钟信号端CB提供的第二时钟信号改变第一节点N1的电位；
所述第一储能电路12与所述第一节点N1电连接，用于维持所述第一节点N1的电位；
所述第三节点控制电路15分别与第一时钟信号端CK、第二时钟信号端CB、第一节点N1、第三节点N3、第四节点N4、第一电压端V1和第二电压端V2)电连接，用于在第一时钟信号、第二时钟信号和第一节点N1的电位的控制下，控制所述第三节点N3的电位和所述第四节点N4的电位；
所述第二节点控制电路13分别与第一节点N1、第一电压端V1、第二节点N2、第二时钟信号端CB和第三节点N3电连接，用于在第三节点N3的电位和第二时钟信号的控制下，控制第二节点N2的电位，并在第一节点N1的电位的控制下，控制第一电压端V1提供的第一电压信号写入第二节点N2；
所述第二储能电路14与第二节点N2电连接，用于维持所述第二节点N2的电位；
所述输出电路17分别与第一节点N1、第二电压端V2、驱动电压信号端O1和输出时钟信号端CBo电连接，用于在第一节点N1的电位的控制下，将第二电压端V2提供的第二电压信号写入驱动电压信号输出端O1，并用于在第二节点N2的电位的控制下，将输出时钟信号端CBo提供的输出时钟信号写入所述驱动电压信号端O1。
在图7所示的移位寄存器单元中，所述第一隔离节点与所述第一节点为同一节点，所述第二隔离节点与第二节点为同一节点，所述第三隔离节点与第三节点为同一节点，但不以此为限。
在图7所示的移位寄存器单元中，控制时钟信号端为第二时钟信号端，调节时钟信号端为第二时钟信号端。
在图7所示的移位寄存器单元中，所述移位寄存器单元用于提供栅极驱动信号，所述移位寄存器单元为栅极驱动电路中的移位寄存器单元，所述第三电压端为输出时钟信号端；所述输出时钟信号端提供的输出时钟信号为与所述第二时钟信号反相的时钟信号。
如图8所示，与图7所示的移位寄存器单元的实施例不同的是：第一节点N1和第一隔离节点并非同一节点；
所述移位寄存器单元的至少一实施例还包括第一隔离电路41；第一节点N1通过所述第一隔离电路41与第一隔离节点N01电连接。
如图9所示，与图7所示的移位寄存器单元的实施例不同的是：
所述第一节点N1与第一隔离节点并非同一节点，所述第三节点N3与第三隔离节点并非同一节点；
所述移位寄存器单元的至少一实施例还包括第一隔离电路41和第三隔离电路43；第一节点N1通过所述第一隔离电路41与第一隔离节点N01电连接；第三节点N3通过所述第三隔离电路43与第三隔离节点N03电连接；
所述第一隔离电路41的控制端与控制电压端V0电连接，所述第三隔离电路43的控制端与所述控制电压端V0电连接。
在具体实施时，当所述第一隔离电路41包括的第一隔离晶体管为p型晶体管，所述第三隔离电路43包括的第三隔离晶体管为p型晶体管时，所述控制电压端可以为低电压端；
当所述第一隔离电路41包括的第一隔离晶体管为n型晶体管，所述第三隔离电路43包括的第三隔离晶体管为n型晶体管时，所述控制电压端可以为高电压端；
但不以此为限。
如图10所示，与图9所示的移位寄存器单元的实施例不同的是：
所述移位寄存器单元的至少一实施例还包括第二隔离电路42；
第二隔离节点N02通过第二隔离电路42与所述第二节点N2电连接；
所述第二隔离电路42的控制极与所述控制电压端V0电连接。
在具体实施时，当所述第二隔离电路42包括的第二隔离晶体管为p型晶体管，所述控制电压端可以为低电压端；
当所述第二隔离电路41包括的第二隔离晶体管为n型晶体管，所述控制电压端可以为高电压端；
如图11所示，与图10所示的移位寄存器单元的实施例不同的是：所述调节时钟信号端并非第二时钟信号端CB，而是第三时钟信号端CKo；
所述第一节点电位调节电路11分别与第三时钟信号端CKo和所述第一节点N1电连接，用于在第一节点N1的电位的控制下，根据第三时钟信号端CKo提供的第三时钟信号改变第一节点N1的电位；
所述第三时钟信号与所述第一时钟信号反相。
在本公开至少一实施例中，所述第一节点电位调节电路可以包括调节晶体管和调节电容，其中，
所述调节晶体管的控制极与所述第一隔离节点电连接，所述调节晶体管的第一极与调节时钟信号端电连接，所述调节晶体管的第二极与所述调节电容的第一端电连接；
所述调节电容的第二端与所述第一隔离节点电连接。
可选的，第二节点控制电路可以包括第一控制晶体管、控制电容、第二控制晶体管和第三控制晶体管，其中，
所述控制电容的第一端与所述第三节点电连接，所述控制电容的第二端与第五节点电连接；
所述第一控制晶体管的控制极与所述第三节点电连接，所述第一控制晶体管的第一极与所述第五节点电连接，所述第一控制晶体管的第二极与控制时钟信号端电连接；
所述第二控制晶体管的控制极与所述第二时钟信号端电连接，所述第二控制晶体管的第一极与所述第五节点电连接，所述第二控制晶体管的第二极与第二隔离节点电连接；
所述第三控制晶体管的控制极与所述第一节点电连接，所述第三控制晶体管的第一极与第一电压端电连接，所述第三控制晶体管的第二极与所述第二隔离节点电连接。
可选的，第二节点控制电路包括第一控制晶体管、控制电容、第二控制晶体管和第三控制晶体管，其中，
所述控制电容的第一端与所述第三节点电连接；
所述第一控制晶体管的控制极与所述第三节点电连接，所述第一控制晶体管的第一极与所述控制电容的第二端电连接，所述第一控制晶体管的第二极与第二时钟信号端电连接；所述第二控制晶体管的控制极与所述控制时钟信号端电连接，所述第二控制晶体管的第一极与所述第二隔离节点电连接；
所述第三控制晶体管的控制极与所述第一隔离节点电连接，所述第三控制晶体管的第一极与第一电压端电连接，所述第三控制晶体管的第二极与所述第二隔离节点电连接。
在具体实施时，所述第二节点控制电路还与第一时钟信号端电连接，还用于在第一时钟信号的控制下，控制所述第二隔离节点的电位。
可选的，所述移位寄存器单元为发光控制信号生成电路中的移位寄存器单元；第二节点控制电路包括第一控制晶体管、控制电容、第二控制晶体管、第三控制晶体管和节点控制晶体管，其中，
所述控制电容的第一端与所述第三节点电连接，所述控制电容的第二端与第五节点电连接；
所述第一控制晶体管的控制极与所述第三节点电连接，所述第一控制晶体管的第一极与所述第五节点电连接，所述第一控制晶体管的第二极与第二时钟信号端电连接；
所述第二控制晶体管的控制极与所述第二时钟信号端电连接，所述第二控制晶体管的第一极与所述第五节点电连接，所述第二控制晶体管的第二极与第二隔离节点电连接；
所述第三控制晶体管的控制极与所述第一节点电连接，所述第三控制晶体管的第一极与第一电压端电连接；
所述节点控制晶体管的控制极与第一时钟信号端电连接，所述节点控制 晶体管的第一极与所述第三控制晶体管的第二极电连接，所述节点控制晶体管的第二极与第二节点电连接。
在具体实施时，所述第三节点控制电路包括第四控制晶体管、第五控制晶体管和第六控制晶体管，其中，
所述第四控制晶体管的控制极与第一时钟信号端电连接，所述第四控制晶体管的第一极与第二电压端电连接，所述第四控制晶体管的第二极与第三隔离节点电连接；
所述第五控制晶体管的控制极与第一隔离节点电连接，所述第五控制晶体管的第一极与第一电压端电连接，所述第五控制晶体管的第二极与第四节点电连接；
所述第六控制晶体管的控制极与第二时钟信号端电连接，所述第六控制晶体管的第一极与所述第四节点电连接，所述第六控制晶体管的第二极与所述第三隔离节点电连接。
在本公开至少一实施例中，所述的移位寄存器单元还可以包括第三隔离晶体管；所述第三隔离节点为第三节点；
所述第四控制晶体管的第二极通过所述第三隔离晶体管与所述第三节点电连接；
所述第三隔离晶体管的控制极与控制电压端电连接，所述第三隔离晶体管的第一极与所述第四控制晶体管的第二极电连接，所述第三隔离晶体管的第二极与所述第三节点电连接。
可选的，所述驱动电压信号端为发光控制信号端，所述第三电压端为第一电压端；
所述第三节点控制电路包括第四控制晶体管、第五控制晶体管和第六控制晶体管，其中，
所述第四控制晶体管的控制极与第二时钟信号端电连接，所述第四控制晶体管的第一极与第二电压端电连接，所述第四控制晶体管的第二极与第三隔离节点电连接；
所述第五控制晶体管的控制极与第一隔离节点电连接，所述第五控制晶体管的第一极与第一电压端电连接，所述第五控制晶体管的第二极与第四节 点电连接；
所述第六控制晶体管的控制极与第一时钟信号端电连接，所述第六控制晶体管的第一极与所述第四节点电连接，所述第六控制晶体管的第二极与所述第三隔离节点电连接。
在本公开至少一实施例中，所述的移位寄存器单元还可以包括第三隔离晶体管；所述第三隔离节点为第三节点；
所述第四控制晶体管的第二极通过所述第三隔离晶体管与所述第三节点电连接；
所述第三隔离晶体管的控制极与控制电压端电连接，所述第三隔离晶体管的第一极与所述第四控制晶体管的第二极电连接，所述第三隔离晶体管的第二极与所述第三节点电连接。
可选的，所述第一节点控制电路包括第七控制晶体管和第八控制晶体管，其中，
所述第七控制晶体管的控制极与第一时钟信号端电连接，所述第七控制晶体管的第一极与所述输入端电连接，所述第七控制晶体管的第二极与所述第一隔离节点电连接；
所述第八控制晶体管的控制极与所述第四节点电连接，所述第八控制晶体管的第一极与所述第一隔离节点电连接，所述第八控制晶体管的第二极与第一电压端电连接。
可选的，所述输出电路包括第一输出晶体管和第二输出晶体管；
所述第一输出晶体管的控制极与所述第一节点电连接，所述第一输出晶体管的第一极与第二电压端电连接，所述第一输出晶体管的第二极与所述驱动电压信号端电连接；
所述第二输出晶体管的控制极与所述第二节点电连接，所述第二输出晶体管的第一极与所述驱动电压信号端电连接，所述第二输出晶体管的第二极与所述第三电压端电连接。
在具体实施时，所述第一储能电路可以包括第一存储电容，所述第二储能电路可以包括第二存储电容；
所述第一存储电容的第一端与所述第一节点电连接，所述第一存储电容 的第二端与第二电压端电连接；
所述第二存储电容的第一端与所述第二节点电连接，所述第二存储电容的第二端与第三电压端电连接。
如图12所示，在图1所述的移位寄存器单元的实施例的基础上，在本公开所述的移位寄存器单元的第一实施例中，
所述第一节点电位调节电路11包括调节晶体管T10和调节电容C2，其中，
所述调节晶体管T10的栅极与所述第一节点N1电连接，所述调节晶体管T10的源极与第二时钟信号端CB电连接，所述调节晶体管T10的漏极与所述调节电容C2的第一端电连接；
所述调节电容C2的第二端与所述第一节点N1电连接；
第二节点控制电路13包括第一控制晶体管T11、控制电容C1、第二控制晶体管T8和第三控制晶体管T9，其中，
所述控制电容C1的第一端与所述第三节点N3电连接，所述控制电容C1的第二端与第五节点N5电连接；
所述第一控制晶体管T11的栅极与所述第三节点N3电连接，所述第一控制晶体管T11的漏极与所述第五节点N5电连接，所述第一控制晶体管T11的源极与第二时钟信号端CB电连接；
所述第二控制晶体管T8的栅极与所述第二时钟信号端CB电连接，所述第二控制晶体管T8的源极与所述第五节点N5电连接，所述第二控制晶体管T8的漏极与第二节点N2电连接；
所述第三控制晶体管T9的栅极与所述第一节点N1电连接，所述第三控制晶体管T9的源极与高电压端V01电连接，所述第三控制晶体管T9的漏极与所述第二节点N2电连接；
所述第三节点控制电路15包括第四控制晶体管T2、第五控制晶体管T5和第六控制晶体管T6，其中，
所述第四控制晶体管T2的栅极与第一时钟信号端CK电连接，所述第四控制晶体管T2的源极与低电压端V02电连接，所述第四控制晶体管T2的漏极与第三节点N3电连接；
所述第五控制晶体管T5的栅极与第一节点N1电连接，所述第五控制晶体管T5的源极与高电压端V01电连接，所述第五控制晶体管T5的漏极与第四节点N4电连接；
所述第六控制晶体管T6的栅极与第二时钟信号端CB电连接，所述第六控制晶体管T6的源极与所述第四节点N4电连接，所述第六控制晶体管T6的漏极与所述第三节点N3电连接；
所述第一节点控制电路16包括第七控制晶体管T1和第八控制晶体管T7，其中，
所述第七控制晶体管T1的栅极与第一时钟信号端CK电连接，所述第七控制晶体管T1的源极与所述输入端I1电连接，所述第七控制晶体管T1的漏极与所述第一节点N1电连接；
所述第八控制晶体管T7的栅极与所述第四节点N4电连接，所述第八控制晶体管T7的漏极与所述第一节点N1电连接，所述第八控制晶体管T7的源极与高电压端V01电连接；
所述输出电路17包括第一输出晶体管T3和第二输出晶体管T4；
所述第一输出晶体管T3的栅极与所述第一节点N1电连接，所述第一输出晶体管T3的源极与低电压端V02电连接，所述第一输出晶体管T3的漏极与所述驱动电压信号端O1电连接；
所述第二输出晶体管T4的栅极与所述第二节点N2电连接，所述第二输出晶体管T4的漏极与所述驱动电压信号端O1电连接，所述第二输出晶体管T4的源极与高电压端V01电连接；
所述第一储能电路12包括第一存储电容C4，所述第二储能电路14包括第二存储电容C3；
所述第一存储电容C4的第一端与所述第一节点N1电连接，所述第一存储电容C4的第二端与低电压端V02电连接；
所述第二存储电容C3的第一端与所述第二节点N2电连接，所述第二存储电容C3的第二端与所述高电压端V01电连接。
在本公开至少一实施例中，所述高电压端可以提供高电压信号，所述低电压端可以提供低电压信号。
本公开所述的移位寄存器单元的第一实施例为发光控制信号生成电路中的移位寄存器单元，用于生成发光控制信号。
在本公开所述的移位寄存器单元的第一实施例中，所有的晶体管都为p型薄膜晶体管，但不以此为限。
在本公开至少一实施例中，当所述移位寄存器单元用于生成发光控制信号时，所述移位寄存器单元可以仅使用两个时钟信号，但不以此为限。
本公开所述的移位寄存器单元的第一实施例在工作时，由于C2和C4能够使得CB提供的第二时钟信号由高电压信号跳变为低电压信号时，使得N1的电位变得不特别低，能够改善T1的阈值电压偏移的情况。
如图13所示，本公开所述的移位寄存器单元的第一实施例在工作时，显示周期包括第一时间段t1、第二时间段t2、第三时间段t3、第四时间段t4、第五时间段t5、第六时间段t6、第七时间段t7和第八时间段t8，其中，
在第一时间段t1，CK提供低电压信号，CB提供高电压信号(CB提供的高电压信号的电位为VH)，I1提供低电压信号，如图14A所示，T6关闭，T8关闭，T1打开，N1的电位为低电压，N2的电位为高电压，T2打开，N3的电位为低电压，N4的电位维持为高电压，T4关断，T3打开，O1输出低电压；此时，由于N1的电位不会降到足够低，因此O1输出的低电压具有阈值电压损耗，O1输出的电压信号的电压值为VL-Vth，其中，Vth为T3的阈值电压；VL为V02提供的低电压信号的电压值；
在第一时间段t1，N1的电位为VL，N2的电位为VH，N3的电位为VL，N4的电位为VH，N5的电位为VH；
在第二时间段t2，CK提供高电压信号，CB提供低电压信号(CB提供的低电压信号的电压值为VL)，I1提供低电压信号，如图14B所示，T1关断，T2关断，由于CB提供的第二时钟信号由t1的高电压信号降低为低电压信号，相应降低N1的电位，使得N1的电位为低电压，此时N1的电位为(VL-VH)C2z/(C2z+C4z)+VL；其中，VH为高电压信号的电压值，VL为低电压信号的电压值，C2z为C2的电容值，C4z为C4的电容值；T5和T6打开，高电压信号V01写入N3，T11关断，T8和T9打开，以使得N2的电位为高电压，并由于CB提供的第二时钟信号的电位由高电压降低至低电压，从而进一步 降低N1的电位，使得T3能够完全打开，O1输出低电压，O1输出的电压信号的电压值为VL；
在第二时间段t2，N2的电位为VH，N3的电位为VH，N4的电位为VH，N5的电位为VH；
在第三时间段t3，CK提供低电压信号，CB提供高电压信号(CB提供的高电压信号的电位为VH)，I1提供高电压信号，如图14C所示，T1打开，以将I1提供的高电压信号写入N1，T5关断，T6关断，N4浮置，T2打开，N3的电位为低电压，T11打开，以使得N5的电位为高电压，T8关断，T9关断，T10关断，T3关断，T4关断，由于有电路的寄生电容，O1输出的信号保持前一时间段的状态，O1输出低电压，O1输出的电压信号的电压值为VL；
在第三时间段t3，N1的电位为VH，N2的电位为维持为前一时段的电位，N2的电位为VH，N3的电位为VL，N4的电位未知，N5的电位为VH；
在第四时间段t4，CK提供高电压信号，CB提供低电压信号(CB提供的低电压信号的电压值为VL)，I1提供高电压信号，如图14D所示，T1关断，T2关断，T9关断，T11打开，CB提供的低电压信号写入C1，以将N3的电位进一步降低为VL+VL-VH，并T8打开，CB提供的低电压信号通过打开的T8为C3充电，以保证N2的电位为低电压；T6打开，N4的电位为低电压，T7打开，T10关断，N1的电位为高电压，T3关断，T4打开，O1输出高电压；
在第四时间段t4，N1的电位为VH，N2的电位为VL，N4的电位约等于VL，N5的电位为VL；
在第四时间段t4与第五时间段t5之间的时间段，CK提供高电压信号，CB提供高电压信号，T1关断，T2关断，T6关断，N1的电位被C4维持为高电压，N2的电位被C3维持为低电压，N4浮置，N3的电位为低电压，O1维持输出高电压；
在第五时间段t5，CK提供低电压信号，CB提供高电压信号，I1提供高电压信号，如图14E所示，T1和T2打开，N1的电位为高电压，T8关断,T9关断，N2的电位维持为低电压，N3的电位为低电压，N4浮置，T3关断， T4打开，O1输出高电压；
在第五时间段t5，N1的电位为VH，N2的电位为VL，N3的电位为VL，N4的电位未知，N5的电位为VH；
在第六时间段t6，CK提供高电压信号，CB提供低电压信号，T1和T2关闭，N1的电位维持为高电压，如图14F所示，T6打开，T11打开，并CB提供的低电压信号写入C1，以将N3的电位进一步降低为VL+VL-VH，并T8打开，CB提供的低电压信号通过打开的T8为C3充电，以保证N2的电位为低电压；T6打开，N4的电位为低电压，T7打开，T3关闭，T4打开，O1输出高电压；
在第六时间段t6，N1的电位为VH，N2的电位为VL，N3的电位为2VL-VH，N4的电位为VL，N5的电位为VL；
在第七时间段t7，CK提供低电压信号，CB提供高电压信号，I1提供低电压信号，如图14G所示，T1和T2都打开，N1的电位为低电压，T10打开，T9打开，T8关断，N2的电位为高电压，此时由于N1的电位不足够低，因此O1输出的电压信号的电压值为VL-Vth，其中，Vth为T3的阈值电压；
在第七时间段t7，N1的电位为VL，N2的电位为VH，N3的电位约等于VL，N4的电位为VH，N5的电位为VH；
在第八时间段t8，CK提供高电压信号，CB提供低电压信号，I1提供低电压信号，如图14H所示，T1和T2关断，T10打开，由于CB提供的第二时钟信号由上一时间段的高电压信号转换为低电压信号，N1的电位被拉到更低，以使得T3能够完全打开；T9打开，T11关断，N2的电位为高电压，由于T8打开，则N3的电位为高电压，T5和T6打开，N4的电位为高电压，T3打开，T4关闭，O1输出的电压信号的电压值为VL；
在第八时间段t8，N1的电位为VL，N2的电位为VH，N3的电位为VH，N4的电位为VH，N5的电位为VH。
在本公开至少一实施例中，由于Vth的值较小，因此在相应的时序图中看不出VL与VL-Vth的区别。
并且，在本公开至少一实施例中，各时钟信号的高电压值可以为VH，各时钟信号的低电压值可以为VL，但不以此为限。
如图15所示，本公开所述的移位寄存器单元的第二实施例与本公开所述的移位寄存器单元的第一实施例的区别如下：C1的位置；
而在所述移位寄存器单元的第二实施例中，C1的第一端与第三节点N3电连接，C1的第二端与T11的漏极电连接，N3直接与T8的源极电连接。
所述移位寄存器单元的图15所示的第二实施例工作时序图也可以如图13所示，但不以此为限。
本公开如图15所示的移位寄存器单元的第二实施例的工作过程与所述移位寄存器单元的第一实施例的工作过程大致相同，区别在于：
当T11打开时，根据CB提供的第二时钟信号，以控制N3的电位，而没有通过第二时钟信号向C3充电的过程；
具体的，本公开如图15所示的移位寄存器单元的第二实施例在工作时，在第四时间段t4，当T11打开时，根据CB提供的第二时钟信号，实现N3点的电位跳变，跳变值为(VL-VH+VL)，由于在前一时间段(也即第三时间段t3)，N2的电位为VH，所以随着CB提供的第二时钟信号的电位由高电平跳变为低电平，根据电容值比例分配电压值；
在第四时间段t4，T8打开，N3的电位等于N2的电位，N2的电位等于[(2VL-VH)×C1z+VH×C3z]/(C1z+C3z)，其中，C1z为C1的电容值，C3z为C3的电容值。如图16所示，在图2所述的移位寄存器单元的实施例的基础上，在本公开所述的移位寄存器单元的第三实施例中，
所述第一节点电位调节电路11包括调节晶体管T10和调节电容C2，其中，
所述调节晶体管T10的栅极与所述第一节点N1电连接，所述调节晶体管T10的源极与第二时钟信号端CB电连接，所述调节晶体管T10的漏极与所述调节电容C2的第一端电连接；
所述调节电容C2的第二端与所述第一节点N1电连接；
第二节点控制电路13包括第一控制晶体管T11、控制电容C1、第二控制晶体管T8、节点控制晶体管T0和第三控制晶体管T9，其中，
所述控制电容C1的第一端与所述第三节点N3电连接，所述控制电容C1的第二端与第五节点N5电连接；
所述第一控制晶体管T11的栅极与所述第三节点N3电连接，所述第一控制晶体管T11的漏极与所述第五节点N5电连接，所述第一控制晶体管T11的源极与第二时钟信号端CB电连接；
所述第二控制晶体管T8的栅极与所述第二时钟信号端CB电连接，所述第二控制晶体管T8的源极与所述第五节点N5电连接，所述第二控制晶体管T8的漏极与第二节点N2电连接；
所述第三控制晶体管T9的栅极与所述第一节点N1电连接，所述第三控制晶体管T9的源极与高电压端V01电连接；
所述节点控制晶体管T0的栅极与第一时钟信号端CK电连接，所述节点控制晶体管T0的源极与所述第三控制晶体管T9的漏极电连接，所述节点控制晶体管T0的漏极与所述第二节点N2电连接；
所述第三节点控制电路15包括第四控制晶体管T2、第五控制晶体管T5和第六控制晶体管T6，其中，
所述第四控制晶体管T2的栅极与第一时钟信号端CK电连接，所述第四控制晶体管T2的源极与低电压端V02电连接，所述第四控制晶体管T2的漏极与第三节点N3电连接；
所述第五控制晶体管T5的栅极与第一节点N1电连接，所述第五控制晶体管T5的源极与高电压端V01电连接，所述第五控制晶体管T5的漏极与第四节点N4电连接；
所述第六控制晶体管T6的栅极与第二时钟信号端CB电连接，所述第六控制晶体管T6的源极与所述第四节点N4电连接，所述第六控制晶体管T6的漏极与所述第三节点N3电连接；
所述第一节点控制电路16包括第七控制晶体管T1和第八控制晶体管T7，其中，
所述第七控制晶体管T1的栅极与第一时钟信号端CK电连接，所述第七控制晶体管T1的源极与所述输入端I1电连接，所述第七控制晶体管T1的漏极与所述第一节点N1电连接；
所述第八控制晶体管T7的栅极与所述第四节点N4电连接，所述第八控制晶体管T7的漏极与所述第一节点N1电连接，所述第八控制晶体管T7的 源极与高电压端V01电连接；
所述输出电路17包括第一输出晶体管T3和第二输出晶体管T4；
所述第一输出晶体管T3的栅极与所述第一节点N1电连接，所述第一输出晶体管T3的源极与低电压端V02电连接，所述第一输出晶体管T3的漏极与所述驱动电压信号端O1电连接；
所述第二输出晶体管T4的栅极与所述第二节点N2电连接，所述第二输出晶体管T4的漏极与所述驱动电压信号端O1电连接，所述第二输出晶体管T4的源极与高电压端V01电连接；
所述第一储能电路12包括第一存储电容C4，所述第二储能电路14包括第二存储电容C3；
所述第一存储电容C4的第一端与所述第一节点N1电连接，所述第一存储电容C4的第二端与低电压端V02电连接；
所述第二存储电容C3的第一端与所述第二节点N2电连接，所述第二存储电容C3的第二端与所述高电压端V01电连接。
在本公开至少一实施例中，所述高电压端可以提供高电压信号，所述低电压端可以提供低电压信号。
本公开所述的移位寄存器单元的第三实施例为发光控制信号生成电路中的移位寄存器单元，用于生成发光控制信号。
在本公开所述的移位寄存器单元的第三实施例中，所有的晶体管都为p型薄膜晶体管，但不以此为限。
本公开所述的移位寄存器单元的第三实施例与本公开所述的第一实施例的区别在于：增加了节点控制晶体管T0。
本公开所述的移位寄存器单元的第三实施例在工作时，在第一时间段t1、第三时间段t3、第五时间段t5和第七时间段t7，CK提供低电压信号，T0打开；
在第二时间段t2、第四时间段t4、第六时间段t6和第八时间段t8，CK提供高电压信号，T0关闭；
在第一时间段t1，N1的电位为低电压，T0打开，T9打开，则T0打开不会对N2的电位产生影响；
在第二时间段t2，N1的电位为低电压，T9打开，T0关闭，但是由于T8打开，并N3的电位为高电压，则N2的电位可以维持为高电压；
在第三时间段t3，N1的电位为高电压，T0打开，T9关闭，则T0打开不会对N2的电位产生影响；
在第四时间段t4，N1的电位为高电压，T9关闭，T0关闭；
在第五时间段t5，N1的电位为高电压，T0打开，T9关闭，则T0打开不会对N2的电位产生影响；
在第六时间段t6，N1的电位为高电压，T9关闭，T0关闭；
在第七时间段t7，N1的电位低电压，T9打开，T0打开；
在第八时间段t8，N1的电位为低电压，T9打开，T0关闭，但是由于T8打开，并N3的电位为高电压，则N2的电位可以维持为高电压。如图17所示，本公开所述的移位寄存器单元的第四实施例与本公开所述的移位寄存器单元的第三实施例的区别如下：C1的位置；
如图17所示，T2的漏极和T6的漏极直接与N3电连接，C1的一端与N3电连接，C1的另一端与T11电连接。
如图18所示，在图3所述的移位寄存器单元的实施例的基础上，在本公开所述的移位寄存器单元的第五实施例中，
所述第一节点电位调节电路11包括调节晶体管T10和调节电容C2，其中，
所述调节晶体管T10的栅极与所述第一节点N1电连接，所述调节晶体管T10的源极与第二时钟信号端CB电连接，所述调节晶体管T10的漏极与所述调节电容C1的第一端电连接；
所述调节电容C1的第二端与所述第一节点N1电连接；
第二节点控制电路13包括第一控制晶体管T11、控制电容C1、第二控制晶体管T8和第三控制晶体管T9，其中，
所述控制电容C1的第一端与所述第三节点N3电连接，所述控制电容C1的第二端与第五节点N5电连接；
所述第一控制晶体管T11的栅极与所述第三节点N3电连接，所述第一控制晶体管T11的漏极与所述第五节点N5电连接，所述第一控制晶体管T11 的源极与第一时钟信号端CK电连接；
所述第二控制晶体管T8的栅极与所述第二时钟信号端CB电连接，所述第二控制晶体管T8的源极与所述第五节点N5电连接，所述第二控制晶体管T8的漏极与第二节点N2电连接；
所述第三控制晶体管T9的栅极与所述第一节点N1电连接，所述第三控制晶体管T9的源极与高电压端V01电连接，所述第三控制晶体管T9的漏极与所述第二节点N2电连接；
所述第三节点控制电路15包括第四控制晶体管T2、第五控制晶体管T5和第六控制晶体管T6，其中，
所述第四控制晶体管T2的栅极与第二时钟信号端CB电连接，所述第四控制晶体管T2的源极与低电压端V02电连接，所述第四控制晶体管T2的漏极与第三节点N3电连接；
所述第五控制晶体管T5的栅极与第一节点N1电连接，所述第五控制晶体管T5的源极与高电压端V01电连接，所述第五控制晶体管T5的漏极与第四节点N4电连接；
所述第六控制晶体管T6的栅极与第一时钟信号端CK电连接，所述第六控制晶体管T6的源极与所述第四节点N4电连接，所述第六控制晶体管T6的漏极与所述第三节点N3电连接；
所述第一节点控制电路16包括第七控制晶体管T1和第八控制晶体管T7，其中，
所述第七控制晶体管T1的栅极与第一时钟信号端CK电连接，所述第七控制晶体管T1的源极与所述输入端I1电连接，所述第七控制晶体管T1的漏极与所述第一节点N1电连接；
所述第八控制晶体管T7的栅极与所述第四节点N4电连接，所述第八控制晶体管T7的漏极与所述第一节点N1电连接，所述第八控制晶体管T7的源极与高电压端V01电连接；
所述输出电路17包括第一输出晶体管T3和第二输出晶体管T4；
所述第一输出晶体管T3的栅极与所述第一节点N1电连接，所述第一输出晶体管T3的源极与低电压端V02电连接，所述第一输出晶体管T3的漏极 与所述驱动电压信号端O1电连接；
所述第二输出晶体管T4的栅极与所述第二节点N2电连接，所述第二输出晶体管T4的漏极与所述驱动电压信号端O1电连接，所述第二输出晶体管T4的源极与高电压端V01电连接；
所述第一储能电路12包括第一存储电容C4，所述第二储能电路14包括第二存储电容C3；
所述第一存储电容C4的第一端与所述第一节点N1电连接，所述第一存储电容C4的第二端与低电压端V02电连接；
所述第二存储电容C3的第一端与所述第二节点N2电连接，所述第二存储电容C3的第二端与所述高电压端V01电连接。
在本公开至少一实施例中，所述高电压端可以提供高电压信号，所述低电压端可以提供低电压信号。
本公开所述的移位寄存器单元的第五实施例为发光控制信号生成电路中的移位寄存器单元，用于生成发光控制信号。
在本公开所述的移位寄存器单元的第五实施例中，所有的晶体管都为p型薄膜晶体管，但不以此为限。
本公开所述的移位寄存器单元的第五实施例与本公开所述的移位寄存器单元的第一实施例的区别如下：T2的栅极与CB电连接，T6的栅极与CK电连接，T11的源极与CK电连接。
如图19所示，在第一种情况下，本公开所述的移位寄存器单元的第五实施例在工作时，
在第一时间段t1，CK提供低电压信号，CB提供高电压信号，I1提供低电压信号，T1关断，T2打开，T6关断，N3的电位为低电压，N1的电位维持为高电压，T11打开，T8关断，N2的电位维持为高电压，O1继续输出上一时间段的电压信号；由于T5和T6关断，此时N4浮置(floating)；在第二时间段t2，CK提供高电压信号，CB提供低电压信号，I1提供低电压信号，T1打开，T2关断，N1的电位为低电压，T9打开，T5打开，T6打开，N3的电位为高电压，T8关闭，N2的电位为高电压，T11关闭，T10打开，T3打开，T4关断，O1输出低电压；T5打开，T6打开，N4的电位为高电压；
在第三时间段t3，CK提供低电压信号，CB提供高电压信号，I1提供高电压信号，T1关闭，T2打开，N3的电位为低电压，T10打开，由于CK提供的电压信号由上一时段的高电压信号跳变为低电压信号，则N1的电位被进一步拉低，使得T3能够完全打开，O1输出低电压；T11打开，T8关断，T9打开，N2的电位为高电压；T5打开，T6关闭，N4的电位为高电压；此时，由于T3完全打开，则O1输出的电压信号的电压值为VL；
在第四时间段t4，CK提供高电压信号，CB提供低电压信号，I1提供高电压信号，T1打开，T2关闭，N1的电位为高电压，T5关闭，T9关闭，T10关闭，T3关闭，T6打开，T11打开，CB提供的第二时钟信号由上一时段的高电压信号跳变为低电压信号，N3的电位被进一步拉低，N4的电位也为低电压，T8打开，N2的电位为低电压，T4打开，T3关闭，O1提供高电压；
在第五时间段t5，CK提供低电压信号，CB提供高电压信号，I1提供高电压信号，T2打开，T1关闭，N3的电位为低电压，T6关闭，N1的电位维持为高电压，T5关闭，N4浮置，T8关闭，N2的电位维持为低电压，T3关闭，T4打开，O1输出高电压；
在第六时间段t6，CK提供高电压信号，CB提供低电压信号，I1提供高电压信号，T1关闭，T2打开，N1的电位为高电压，T9关闭，T5关闭，T6打开，T11打开，由于CB提供的第二时钟信号由上一时段的高电压信号跳变为低电压信号，N3的电位被进一步拉低，N4的电位也为低电压，T8打开，N2的电位为低电压，T4打开，T3关闭，O1提供高电压；
在第七时间段t7，CK提供低电压信号，CB提供高电压信号，I1提供低电压信号，T1关闭，T2打开，N3的电位为低电压，T6关闭，N1的电位维持为高电压，T11打开，T8关闭，T9关闭，N2的电位维持为高电压，O1继续输出高电压；
在第八时间段t8，CK提供高电压信号，CB提供低电压信号，I1提供低电压信号，T1打开，T2关闭，N1的电位为低电压，T5和T6打开，N4的电位和N3的电位为高电压，T8打开，T9打开，N2的电位为高电压，T3打开，T4关闭，O1输出低电压。
如图19所示，输入信号的脉宽与O1输出的发光控制信号的脉宽相同， O1可以作为相邻下一级移位寄存器单元的输入端，但不以此为限。
如图20所示，在第二种情况下，本公开所述的移位寄存器单元的第五实施例在工作时，
在第一时间段t1，CK提供低电压信号，CB提供高电压信号，I1提供低电压信号，T1关断，T2打开，T6关断，N3的电位为低电压，N1的电位维持为高电压，T11打开，T8关断，N2的电位维持为高电压，O1继续输出上一时间段的电压信号；由于T5和T6关断，此时N4浮置；
在第二时间段t2，CK提供高电压信号，CB提供低电压信号，I1提供低电压信号，T1打开，T2关断，N1的电位为低电压，T9打开，T5打开，T6打开，N3的电位为高电压，T8关闭，N2的电位为高电压，T11关闭，T10打开，T3打开，T4关断，O1输出低电压；T5打开，T6打开，N4的电位为高电压；
在第三时间段t3，CK提供低电压信号，CB提供高电压信号，I1提供高电压信号，T1关闭，T2打开，N3的电位为低电压，T10打开，由于CK提供的电压信号由上一时段的高电压信号跳变为低电压信号，则N1的电位被进一步拉低，使得T3能够完全打开，O1输出低电压；T11打开，T8关断，T9打开，N2的电位为高电压；T5打开，T6关闭，N4的电位为高电压；此时由于N1完全打开，则O1输出的电压信号的电压值为VL；
在第四时间段t4，CK提供高电压信号，CB提供低电压信号，I1提供高电压信号，T1打开，T2关闭，N1的电位为高电压，T5关闭，T9关闭，T10关闭，T3关闭，T6打开，T11打开，CB提供的第二时钟信号由上一时段的高电压信号跳变为低电压信号，N3的电位被进一步拉低，N4的电位也为低电压，T8打开，N2的电位为低电压，T4打开，T3关闭，O1提供高电压；
在第五时间段t5，CK提供低电压信号，CB提供高电压信号，I1提供高电压信号，T2打开，T1关闭，N3的电位为低电压，T6关闭，N1的电位维持为高电压，T5关闭，N4浮置，T8关闭，N2的电位维持为低电压，T3关闭，T4打开，O1输出高电压；
在第六时间段t6，CK提供高电压信号，CB提供低电压信号，I1提供低电压信号，T1关闭，T2打开，N1的电位为高电压，T9关闭，T5关闭，T6 打开，T11打开，由于CB提供的第二时钟信号由上一时段的高电压信号跳变为低电压信号，N3的电位被进一步拉低，N4的电位也为低电压，T8打开，N2的电位为低电压，T4打开，T3关闭，O1提供高电压；
在第七时间段t7，CK提供低电压信号，CB提供高电压信号，I1提供低电压信号，T1关闭，T2打开，N3的电位为低电压，T6关闭，N1的电位维持为高电压，T11打开，T8关闭，T9关闭，N2的电位维持为高电压，O1继续输出高电压；
在第八时间段t8，CK提供高电压信号，CB提供低电压信号，I1提供低电压信号，T1打开，T2关闭，N1的电位为低电压，T5和T6打开，N4的电位和N3的电位为高电压，T8打开，T9打开，N2的电位为高电压，T3打开，T4关闭，O1输出低电压。
如图20所示，输入信号的脉宽与O1输出的发光控制信号的脉宽不相同，但不以此为限。
如图21所示，在图4所述的移位寄存器单元的实施例的基础上，在本公开所述的移位寄存器单元的第六实施例中，
所述第一隔离电路41包括第一隔离晶体管T13；
T13的栅极与低电压端V02连接，T13的源极与N01电连接，T13的漏极与N1电连接；
所述第一节点电位调节电路11包括调节晶体管T10和调节电容C2，其中，
所述调节晶体管T10的栅极与所述第一节点N1电连接，所述调节晶体管T10的源极与第二时钟信号端CB电连接，所述调节晶体管T10的漏极与所述调节电容C2的第一端电连接；
所述调节电容C2的第二端与所述第一节点N1电连接；
第二节点控制电路13包括第一控制晶体管T11、控制电容C1、第二控制晶体管T8和第三控制晶体管T9，其中，
所述控制电容C1的第一端与所述第三节点N3电连接，所述控制电容C1的第二端与第五节点N5电连接；
所述第一控制晶体管T11的栅极与所述第三节点N3电连接，所述第一 控制晶体管T11的漏极与所述第五节点N5电连接，所述第一控制晶体管T11的源极与第二时钟信号端CB电连接；
所述第二控制晶体管T8的栅极与所述第二时钟信号端CB电连接，所述第二控制晶体管T8的源极与所述第五节点N5电连接，所述第二控制晶体管T8的漏极与第二节点N2电连接；
所述第三控制晶体管T9的栅极与所述第一隔离节点N01电连接，所述第三控制晶体管T9的源极与高电压端V01电连接，所述第三控制晶体管T9的漏极与所述第二节点N2电连接；
所述第三节点控制电路15包括第四控制晶体管T2、第三隔离晶体管T12、第五控制晶体管T5和第六控制晶体管T6，其中，
所述第四控制晶体管T2的栅极与第一时钟信号端CK电连接，所述第四控制晶体管T2的源极与低电压端V02电连接；
所述第三隔离晶体管T12的栅极与低电压端V02电连接，第三隔离晶体管T12的源极与所述第四控制晶体管T2的漏极电连接，所述第三隔离晶体管T12的漏极与第三节点N3电连接；
所述第五控制晶体管T5的栅极与第一隔离节点N01电连接，所述第五控制晶体管T5的源极与高电压端V01电连接，所述第五控制晶体管T5的漏极与第四节点N4电连接；
所述第六控制晶体管T6的栅极与第二时钟信号端CB电连接，所述第六控制晶体管T6的源极与所述第四节点N4电连接，所述第六控制晶体管T6的漏极与所述第三节点N3电连接；
所述第一节点控制电路16包括第七控制晶体管T1和第八控制晶体管T7，其中，
所述第七控制晶体管T1的栅极与第一时钟信号端CK电连接，所述第七控制晶体管T1的源极与所述输入端I1电连接，所述第七控制晶体管T1的漏极与所述第一隔离节点N01电连接；
所述第八控制晶体管T7的栅极与所述第四节点N4电连接，所述第八控制晶体管T7的漏极与所述第一隔离节点N01电连接，所述第八控制晶体管T7的源极与高电压端V01电连接；
所述输出电路17包括第一输出晶体管T3和第二输出晶体管T4；
所述第一输出晶体管T3的栅极与所述第一节点N1电连接，所述第一输出晶体管T3的源极与低电压端V02电连接，所述第一输出晶体管T3的漏极与所述驱动电压信号端O1电连接；
所述第二输出晶体管T4的栅极与所述第二节点N2电连接，所述第二输出晶体管T4的漏极与所述驱动电压信号端O1电连接，所述第二输出晶体管T4的源极与高电压端V01电连接；
所述第一储能电路12包括第一存储电容C4，所述第二储能电路14包括第二存储电容C3；
所述第一存储电容C4的第一端与所述第一节点N1电连接，所述第一存储电容C4的第二端与低电压端V02电连接；
所述第二存储电容C3的第一端与所述第二节点N2电连接，所述第二存储电容C3的第二端与所述高电压端V01电连接。
在本公开至少一实施例中，所述高电压端可以提供高电压信号，所述低电压端可以提供低电压信号。
在本公开至少一实施例中，所述控制电压端为低电压端，但不以此为限。
本公开所述的移位寄存器单元的第六实施例为发光控制信号生成电路中的移位寄存器单元，用于生成发光控制信号。
在本公开所述的移位寄存器单元的第六实施例中，所有的晶体管都为p型薄膜晶体管，但不以此为限。
在本公开所述的移位寄存器单元的第六实施例与在本公开所述的移位寄存器单元的第二实施例的区别在于：增加了T12和T13。
在本公开所述的移位寄存器单元的第六实施例中，增加T13的目的在于：防止当N1的电位过低而导致与N1电连接的晶体管发生DIBL(Drain Induced Barrier Lowering，漏致势垒降低)，从而使得与N1电连接的晶体管的阈值电压发生偏移，导致在其他工作阶段，与N1电连接的晶体管无法正常打开或关闭的情况发生；
增加T12的目的在于，防止当N3的电位电连接的晶体管的阈值电压发生偏移，导致在其他工作阶段，与N3电连接的晶体管无法正常打开或关闭 的情况发生。如图22所示，在图5所述的移位寄存器单元的实施例的基础上，在本公开所述的移位寄存器单元的第七实施例中，
所述第一隔离电路41包括第一隔离晶体管T13，所述第三隔离电路43包括第三隔离晶体管T12；
T13的栅极与低电压端V02电连接，T13的源极与N01电连接，T13的漏极与N1电连接；
T12的栅极与低电压端V02电连接，T12的源极与N03电连接，T12的漏极与N3电连接；
所述第一节点电位调节电路11包括调节晶体管T10和调节电容C2，其中，
所述调节晶体管T10的栅极与所述第一节点N1电连接，所述调节晶体管T10的源极与第二时钟信号端CB电连接，所述调节晶体管T10的漏极与所述调节电容C1的第一端电连接；
所述调节电容C1的第二端与所述第一节点N1电连接；
第二节点控制电路13包括第一控制晶体管T11、控制电容C1、第二控制晶体管T8和第三控制晶体管T9，其中，
所述控制电容C1的第一端与所述第三节点N3电连接，所述控制电容C1的第二端与第五节点N5电连接；
所述第一控制晶体管T11的栅极与所述第三节点N3电连接，所述第一控制晶体管T11的漏极与所述第五节点N5电连接，所述第一控制晶体管T11的源极与第二时钟信号端CB电连接；
所述第二控制晶体管T8的栅极与所述第二时钟信号端CB电连接，所述第二控制晶体管T8的源极与所述第五节点N5电连接，所述第二控制晶体管T8的漏极与第二节点N2电连接；
所述第三控制晶体管T9的栅极与所述第一隔离节点N01电连接，所述第三控制晶体管T9的源极与高电压端V01电连接，所述第三控制晶体管T9的漏极与所述第二节点N2电连接；
所述第三节点控制电路15包括第四控制晶体管T2、第五控制晶体管T5和第六控制晶体管T6，其中，
所述第四控制晶体管T2的栅极与第一时钟信号端CK电连接，所述第四控制晶体管T2的源极与低电压端V02电连接，所述第四控制晶体管T2的漏极与第三节点N3电连接；
所述第五控制晶体管T5的栅极与第一隔离节点N01电连接，所述第五控制晶体管T5的源极与高电压端V01电连接，所述第五控制晶体管T5的漏极与第四节点N4电连接；
所述第六控制晶体管T6的栅极与第二时钟信号端CB电连接，所述第六控制晶体管T6的源极与所述第四节点N4电连接，所述第六控制晶体管T6的漏极与所述第三隔离节点N03电连接；
所述第一节点控制电路16包括第七控制晶体管T1和第八控制晶体管T7，其中，
所述第七控制晶体管T1的栅极与第一时钟信号端CK电连接，所述第七控制晶体管T1的源极与所述输入端I1电连接，所述第七控制晶体管T1的漏极与所述第一隔离节点N01电连接；
所述第八控制晶体管T7的栅极与所述第四节点N4电连接，所述第八控制晶体管T7的漏极与所述第一隔离节点N1电连接，所述第八控制晶体管T7的源极与高电压端V01电连接；
所述输出电路17包括第一输出晶体管T3和第二输出晶体管T4；
所述第一输出晶体管T3的栅极与所述第一节点N1电连接，所述第一输出晶体管T3的源极与低电压端V02电连接，所述第一输出晶体管T3的漏极与所述驱动电压信号端O1电连接；
所述第二输出晶体管T4的栅极与所述第二节点N2电连接，所述第二输出晶体管T4的漏极与所述驱动电压信号端O1电连接，所述第二输出晶体管T4的源极与高电压端V01电连接；
所述第一储能电路12包括第一存储电容C4，所述第二储能电路14包括第二存储电容C3；
所述第一存储电容C4的第一端与所述第一节点N1电连接，所述第一存储电容C4的第二端与低电压端V02电连接；
所述第二存储电容C3的第一端与所述第二节点N2电连接，所述第二存 储电容C3的第二端与所述高电压端V01电连接。
在本公开至少一实施例中，所述高电压端可以提供高电压信号，所述低电压端可以提供低电压信号。
本公开所述的移位寄存器单元的第七实施例为发光控制信号生成电路中的移位寄存器单元，用于生成发光控制信号。
在本公开所述的移位寄存器单元的第七实施例中，所有的晶体管都为p型薄膜晶体管，但不以此为限。
在本公开所述的移位寄存器单元的第七实施例与在本公开所述的移位寄存器单元的第一实施例的区别在于：增加了T13和T12。
在本公开所述的移位寄存器单元的第七实施例中，增加T13的目的在于：防止当N1的电位过低而导致与N1电连接的晶体管发生DIBL(Drain Induced Barrier Lowering，漏致势垒降低)，从而使得与N1电连接的晶体管的阈值电压发生偏移，导致在其他工作阶段，与N1电连接的晶体管无法正常打开或关闭的情况发生；
增加T12的目的在于，防止当N3的电位电连接的晶体管的阈值电压发生偏移，导致在其他工作阶段，与N3电连接的晶体管无法正常打开或关闭的情况发生。
如图23所示，在图6所述的移位寄存器单元的实施例的基础上，在本公开所述的移位寄存器单元的第八实施例中，
所述第一隔离电路41包括第一隔离晶体管T13，所述第三隔离电路43包括第三隔离晶体管T12；所述第二隔离电路42包括第二隔离晶体管T14；
T13的栅极与低电压端V02电连接，T13的源极与N01电连接，T13的漏极与N1电连接；
T12的栅极与低电压端V02电连接，T12的源极与N03电连接，T12的漏极与N3电连接；
T14的栅极与低电压端V02电连接，T14的源极与N02电连接，T14的漏极与N2电连接；
所述第一节点电位调节电路11包括调节晶体管T10和调节电容C2，其中，
所述调节晶体管T10的栅极与所述第一节点N1电连接，所述调节晶体管T10的源极与第二时钟信号端CB电连接，所述调节晶体管T10的漏极与所述调节电容C2的第一端电连接；
所述调节电容C2的第二端与所述第一节点N1电连接；
第二节点控制电路13包括第一控制晶体管T11、控制电容C1、第二控制晶体管T8和第三控制晶体管T9，其中，
所述控制电容C1的第一端与所述第三节点N3电连接，所述控制电容C1的第二端与第五节点N5电连接；
所述第一控制晶体管T11的栅极与所述第三节点N3电连接，所述第一控制晶体管T11的漏极与所述第五节点N5电连接，所述第一控制晶体管T11的源极与第二时钟信号端CB电连接；
所述第二控制晶体管T8的栅极与所述第二时钟信号端CB电连接，所述第二控制晶体管T8的源极与所述第五节点N5电连接，所述第二控制晶体管T8的漏极与第二隔离节点N02电连接；
所述第三控制晶体管T9的栅极与所述第一隔离节点N01电连接，所述第三控制晶体管T9的源极与高电压端V01电连接，所述第三控制晶体管T9的漏极与所述第二隔离节点N02电连接；
所述第三节点控制电路15包括第四控制晶体管T2、第五控制晶体管T5和第六控制晶体管T6，其中，
所述第四控制晶体管T2的栅极与第一时钟信号端CK电连接，所述第四控制晶体管T2的源极与低电压端V02电连接，所述第四控制晶体管T2的漏极与第三节点N3电连接；
所述第五控制晶体管T5的栅极与第一隔离节点N01电连接，所述第五控制晶体管T5的源极与高电压端V01电连接，所述第五控制晶体管T5的漏极与第四节点N4电连接；
所述第六控制晶体管T6的栅极与第二时钟信号端CB电连接，所述第六控制晶体管T6的源极与所述第四节点N4电连接，所述第六控制晶体管T6的漏极与所述第三隔离节点N03电连接；
所述第一节点控制电路16包括第七控制晶体管T1和第八控制晶体管T7， 其中，
所述第七控制晶体管T1的栅极与第一时钟信号端CK电连接，所述第七控制晶体管T1的源极与所述输入端I1电连接，所述第七控制晶体管T1的漏极与所述第一隔离节点N01电连接；
所述第八控制晶体管T7的栅极与所述第四节点N4电连接，所述第八控制晶体管T7的漏极与所述第一隔离节点N1电连接，所述第八控制晶体管T7的源极与高电压端V01电连接；
所述输出电路17包括第一输出晶体管T3和第二输出晶体管T4；
所述第一输出晶体管T3的栅极与所述第一节点N1电连接，所述第一输出晶体管T3的源极与低电压端V02电连接，所述第一输出晶体管T3的漏极与所述驱动电压信号端O1电连接；
所述第二输出晶体管T4的栅极与所述第二节点N2电连接，所述第二输出晶体管T4的漏极与所述驱动电压信号端O1电连接，所述第二输出晶体管T4的源极与高电压端V01电连接；
所述第一储能电路12包括第一存储电容C4，所述第二储能电路14包括第二存储电容C3；
所述第一存储电容C4的第一端与所述第一节点N1电连接，所述第一存储电容C4的第二端与低电压端V02电连接；
所述第二存储电容C3的第一端与所述第二节点N2电连接，所述第二存储电容C3的第二端与所述高电压端V01电连接。
在本公开至少一实施例中，所述高电压端可以提供高电压信号，所述低电压端可以提供低电压信号。
本公开所述的移位寄存器单元的第八实施例为发光控制信号生成电路中的移位寄存器单元，用于生成发光控制信号。
在本公开所述的移位寄存器单元的第八实施例中，所有的晶体管都为p型薄膜晶体管，但不以此为限。
在本公开所述的移位寄存器单元的第六实施例与在本公开所述的移位寄存器单元的第一实施例的区别在于：增加了T13、T12和T14。
在本公开所述的移位寄存器单元的第八实施例中，增加T13的目的在于： 防止当N1的电位过低而导致与N1电连接的晶体管发生DIBL(Drain Induced Barrier Lowering，漏致势垒降低)，从而使得与N1电连接的晶体管的阈值电压发生偏移，导致在其他工作阶段，与N1电连接的晶体管无法正常打开或关闭的情况发生；
增加T12的目的在于，防止当N3的电位电连接的晶体管的阈值电压发生偏移，导致在其他工作阶段，与N3电连接的晶体管无法正常打开或关闭的情况发生
增加T14的目的在于，防止当N2的电位过低而导致与N2电连接的晶体管发生DIBL(Drain Induced Barrier Lowering，漏致势垒降低)，从而使得与N2电连接的晶体管的阈值电压发生偏移，导致在其他工作阶段，与N2电连接的晶体管无法正常打开或关闭的情况发生。
如图24所示，本公开所述的移位寄存器单元的第九实施例与本公开所述的移位寄存器单元的第七实施例的区别如下：T10的源极接入第三时钟信号端CKo。
在本公开至少一实施例中，CKo提供的第三时钟信号是CK提供的第二时钟信号的反相信号。
如图25所示，在图7所述的移位寄存器单元的实施例的基础上，在本公开所述的移位寄存器单元的第十实施例中，
所述第一节点电位调节电路11包括调节晶体管T10和调节电容C2，其中，
所述调节晶体管T10的栅极与所述第一节点N1电连接，所述调节晶体管T10的源极与第二时钟信号端CB电连接，所述调节晶体管T10的漏极与所述调节电容C1的第一端电连接；
所述调节电容C1的第二端与所述第一节点N1电连接；
第二节点控制电路13包括第一控制晶体管T11、控制电容C1、第二控制晶体管T8和第三控制晶体管T9，其中，
所述控制电容C1的第一端与所述第三节点N3电连接，所述控制电容C1的第二端与第五节点N5电连接；
所述第一控制晶体管T11的栅极与所述第三节点N3电连接，所述第一 控制晶体管T11的漏极与所述第五节点N5电连接，所述第一控制晶体管T11的源极与第二时钟信号端CB电连接；
所述第二控制晶体管T8的栅极与所述第二时钟信号端CB电连接，所述第二控制晶体管T8的源极与所述第五节点N5电连接，所述第二控制晶体管T8的漏极与第二节点N2电连接；
所述第三控制晶体管T9的栅极与所述第一节点N1电连接，所述第三控制晶体管T9的源极与高电压端V01电连接，所述第三控制晶体管T9的漏极与所述第二节点N2电连接；
所述第三节点控制电路15包括第四控制晶体管T2、第五控制晶体管T5和第六控制晶体管T6，其中，
所述第四控制晶体管T2的栅极与第一时钟信号端CK电连接，所述第四控制晶体管T2的源极与低电压端V02电连接，所述第四控制晶体管T2的漏极与第三节点N3电连接；
所述第五控制晶体管T5的栅极与第一节点N1电连接，所述第五控制晶体管T5的源极与高电压端V01电连接，所述第五控制晶体管T5的漏极与第四节点N4电连接；
所述第六控制晶体管T6的栅极与第二时钟信号端CB电连接，所述第六控制晶体管T6的源极与所述第四节点N4电连接，所述第六控制晶体管T6的漏极与所述第三节点N3电连接；
所述第一节点控制电路16包括第七控制晶体管T1和第八控制晶体管T7，其中，
所述第七控制晶体管T1的栅极与第一时钟信号端CK电连接，所述第七控制晶体管T1的源极与所述输入端I1电连接，所述第七控制晶体管T1的漏极与所述第一节点N1电连接；
所述第八控制晶体管T7的栅极与所述第四节点N4电连接，所述第八控制晶体管T7的漏极与所述第一节点N1电连接，所述第八控制晶体管T7的源极与高电压端V01电连接；
所述输出电路17包括第一输出晶体管T3和第二输出晶体管T4；
所述第一输出晶体管T3的栅极与所述第一节点N1电连接，所述第一输 出晶体管T3的源极与低电压端V02电连接，所述第一输出晶体管T3的漏极与所述驱动电压信号端O1电连接；
所述第二输出晶体管T4的栅极与所述第二节点N2电连接，所述第二输出晶体管T4的漏极与所述驱动电压信号端O1电连接，所述第二输出晶体管T4的源极与输出时钟信号端CBo电连接；
所述第一储能电路12包括第一存储电容C4，所述第二储能电路14包括第二存储电容C3；
所述第一存储电容C4的第一端与所述第一节点N1电连接，所述第一存储电容C4的第二端与低电压端V02电连接；
所述第二存储电容C3的第一端与所述第二节点N2电连接，所述第二存储电容C3的第二端与所述输出时钟信号端CBo电连接。
在本公开至少一实施例中，所述高电压端可以提供高电压信号，所述低电压端可以提供低电压信号。
本公开所述的移位寄存器单元的第十实施例为栅极驱动电路中的移位寄存器单元，用于生成栅极驱动信号。
在本公开所述的移位寄存器单元的第十实施例中，所有的晶体管都为p型薄膜晶体管，但不以此为限。
在本公开至少一实施例中，CB提供的第二时钟信号与CBo提供的输出时钟信号反相，但不以此为限。
在本公开至少一实施例中，所述移位寄存器单元提供的栅极驱动信号的脉宽比所述移位寄存器单元提供的发光控制信号的脉宽小，但不以此为限。
并且，在本公开至少一实施例中，当所述移位寄存器单元用于生成栅极驱动信号时，需要采用四个时钟信号。
如图26所示，本公开所述的移位寄存器单元的第十实施例在工作时，显示周期包括第一时间段t1、第二时间段t2、第三时间段t3、第四时间段t4和第五时间段t5；
在第一时间段t1，CK提供低电压信号，CB提供高电压信号，CBo提供低电压信号，I1提供低电压信号，如图27A所示，T1和T2打开，N1的电位为低电压，T9打开，T10打开，N3的电位为低电压，T8关断，N2的电位 为高电压，T3打开，T4关闭，O1输出VL-Vth，其中,Vth为T3的阈值电压，VL为低电压端提供的电压信号的电压值；
在第一时间段t1，N1的电位为VL，N2的电位为VH，N3的电位为VL，N4的电位为VH，N5的电位为VH；
在第二时间段t2，CK提供高电压信号，CB提供低电压信号，CBo提供高电压信号，I1提供低电压信号，如图27B所示，T1和T2关闭，T10打开，由于CB提供的第二时钟信号由上一时段的高电压信号跳变为低电压信号，因此N1的电位被进一步拉低，使得T3能够完全打开，T5打开，T6打开，N4的电位和N3的电位都为高电压，T8打开，N2的电位为高电压，T3打开，T4关闭，O1输出低电压，此时O1输出的电压信号的电压值为VL；
在第二时间段t2，N1的电位为(VL-VH)C2z/(C2z+C4z)+VL，N2的电位为VH，N3的电位为VH，N4的电位为VH，N5的电位为VH；
在第三时间段t3，CK提供低电压信号，CB提供高电压信号，CBo提供低电压信号，I1提供高电压信号，如图27C所示，T1和T2打开，N1的电位为高电压，T5、T9和T10关闭，T6关闭，N3的电位为低电压，T11打开，T8关闭，N2的电位维持为高电压，T3和T4都关闭，O1输出的电压信号由电路的寄生电容维持为上一时段的电压信号；此时由于T5和T6都关闭，则N4浮置，N4的电位未知；
在第三时间段t3，N1的电位为VH，N2的电位为VH，N3的电位为VL，N4的电位未知，N5的电位为VH；
在第四时间段t4，CK提供高电压信号,CB提供低电压信号，CBo提供高电压信号，I1提供低电压信号，如图27D所示，T1和T2关断，N1的电位保持为高电压，T11打开，由于CB提供的第二时钟信号由上一时段的高电压信号跳变为低电压信号，并T8打开，则进一步拉低N3的电位和N2的电位，T3关闭，T4打开，此时CBo提供高电压信号，O1输出高电压；
在第四时间段t4，N1的电位为VH，N2的电位为VL，N3的电位为2VL-VH，N4的电位为VL，N4的电位为VL；
在第五时间段t5，CK提供低电压信号，CB提供高电压信号，CBo提供低电压信号，如图27E所示，T1和T2打开，N1的电位为VL，N3的电位为 VL，T6关闭，T5打开，N4的电位为VH，此时由前一时段的状态决定O1输出低电压信号，并O1输出的低电压信号的电压值为VL，此时由于T3的栅极电位、T3的源极电位和T3的漏极电位都为VL，则T3的栅源电压等于0，T3的栅源电压大于T3的阈值电压，因此此时T3不导通，O1输出的电压信号由电路的寄生电容保持为低电压信号；
在第五时间段t5以及之后的若干个时间段，N2的为电位保持为高电压，则T4始终处于截止状态，可以提高O1输出的低电压信号的稳定状态。
如图28所示，本公开所述的移位寄存器单元的第十一实施例与本公开所述的移位寄存器单元的第十实施例的区别如下：C1的位置；
而在所述移位寄存器单元的第十一实施例中，C1的第一端与第三节点N3电连接，C1的第二端与T11的漏极电连接，N3直接与T8的漏极电连接。
所述移位寄存器单元的图28所示的第十一实施例工作时序图也可以如图26所示，但不以此为限。
本公开如图28所示的移位寄存器单元的第十一实施例的工作过程与所述移位寄存器单元的第十实施例的工作过程大致相同，区别在于：
当T11打开时，根据CB提供的第二时钟信号，以控制N3的电位，而没有通过第二时钟信号向C3充电的过程；
具体的，本公开如图28所示的移位寄存器单元的第十一实施例在工作时，在第四时间段t4，当T11打开时，根据CB提供的第二时钟信号，实现N3点的电位跳变，跳变值为(VL-VH+VL)，由于在前一时间段(也即第三时间段t3)，N2的电位为VH，所以随着CB提供的第二时钟信号的电位由高电平跳变为低电平，根据电容值比例分配电压值；
在第四时间段t4，T8打开，N3的电位等于N2的电位，N2的电位等于[(2VL-VH)×C1z+VH×C3z]/(C1z+C3z)，其中，C1z为C1的电容值，C3z为C3的电容值。
如图29所示，在图8所述的移位寄存器单元的实施例的基础上，在本公开所述的移位寄存器单元的第十二实施例中，
所述第一隔离电路41包括第一隔离晶体管T13；
T13的栅极与低电压端V02连接，T13的源极与N01电连接，T13的漏 极与N1电连接；
所述第一节点电位调节电路11包括调节晶体管T10和调节电容C2，其中，
所述调节晶体管T10的栅极与所述第一节点N1电连接，所述调节晶体管T10的源极与第二时钟信号端CB电连接，所述调节晶体管T10的漏极与所述调节电容C1的第一端电连接；
所述调节电容C1的第二端与所述第一节点N1电连接；
第二节点控制电路13包括第一控制晶体管T11、控制电容C1、第二控制晶体管T8和第三控制晶体管T9，其中，
所述控制电容C1的第一端与所述第三节点N3电连接，所述控制电容C1的第二端与所述第一控制晶体管T11的漏极电连接；
所述第一控制晶体管T11的栅极与所述第三节点N3电连接，所述第一控制晶体管T11的源极与第二时钟信号端CB电连接；
所述第二控制晶体管T8的栅极与所述第二时钟信号端CB电连接，所述第二控制晶体管T8的源极与所述第三节点N3电连接，所述第二控制晶体管T8的漏极与第二节点N2电连接；
所述第三控制晶体管T9的栅极与所述第一隔离节点N01电连接，所述第三控制晶体管T9的源极与高电压端V01电连接，所述第三控制晶体管T9的漏极与所述第二节点N2电连接；
所述第三节点控制电路15包括第四控制晶体管T2、第三隔离晶体管T12、第五控制晶体管T5和第六控制晶体管T6，其中，
所述第四控制晶体管T2的栅极与第一时钟信号端CK电连接，所述第四控制晶体管T2的源极与低电压端V02电连接；
所述第三隔离晶体管T12的栅极与低电压端V02电连接，第三隔离晶体管T12的源极与所述第四控制晶体管T2的漏极电连接，所述第三隔离晶体管T12的漏极与第三节点N3电连接；
所述第五控制晶体管T5的栅极与第一隔离节点N01电连接，所述第五控制晶体管T5的源极与高电压端V01电连接，所述第五控制晶体管T5的漏极与第四节点N4电连接；
所述第六控制晶体管T6的栅极与第二时钟信号端CB电连接，所述第六控制晶体管T6的源极与所述第四节点N4电连接，所述第六控制晶体管T6的漏极与所述第三节点N3电连接；
所述第一节点控制电路16包括第七控制晶体管T1和第八控制晶体管T7，其中，
所述第七控制晶体管T1的栅极与第一时钟信号端CK电连接，所述第七控制晶体管T1的源极与所述输入端I1电连接，所述第七控制晶体管T1的漏极与所述第一隔离节点N01电连接；
所述第八控制晶体管T7的栅极与所述第四节点N4电连接，所述第八控制晶体管T7的漏极与所述第一隔离节点N01电连接，所述第八控制晶体管T7的源极与高电压端V01电连接；
所述输出电路17包括第一输出晶体管T3和第二输出晶体管T4；
所述第一输出晶体管T3的栅极与所述第一节点N1电连接，所述第一输出晶体管T3的源极与低电压端V02电连接，所述第一输出晶体管T3的漏极与所述驱动电压信号端O1电连接；
所述第二输出晶体管T4的栅极与所述第二节点N2电连接，所述第二输出晶体管T4的漏极与所述驱动电压信号端O1电连接，所述第二输出晶体管T4的源极与输出时钟信号端CBo电连接；
所述第一储能电路12包括第一存储电容C4，所述第二储能电路14包括第二存储电容C3；
所述第一存储电容C4的第一端与所述第一节点N1电连接，所述第一存储电容C4的第二端与低电压端V02电连接；
所述第二存储电容C3的第一端与所述第二节点N2电连接，所述第二存储电容C3的第二端与所述高电压端V01电连接。
在本公开至少一实施例中，所述高电压端可以提供高电压信号，所述低电压端可以提供低电压信号。
在本公开至少一实施例中，所述控制电压端为低电压端，但不以此为限。
本公开所述的移位寄存器单元的第十二实施例为栅极驱动电路中的移位寄存器单元，用于生成栅极驱动信号。
在本公开所述的移位寄存器单元的第十二实施例中，所有的晶体管都为p型薄膜晶体管，但不以此为限。
在本公开所述的移位寄存器单元的第十二实施例与在本公开所述的移位寄存器单元的第十一实施例的区别在于：增加了T13和T12。
在本公开所述的移位寄存器单元的第六实施例中，增加T11的目的在于：防止当N1的电位被导通的T10通过CB进一步拉低时，由于N1的电位过低，而导致的T1的阈值电压偏移，防止在需要T1打开时，T1不能完全打开的情况发生；
增加T12的目的在于，防止当N3的电位被导通的T11通过CB进一步拉低时，由于N3的电位过低，而导致的T2的阈值电压偏移，防止在需要T2打开时，T2不能完全打开的情况发生。
如图30所示，在图8所述的移位寄存器单元的实施例的基础上，在本公开所述的移位寄存器单元的第十三实施例中，
所述第一隔离电路41包括第一隔离晶体管T13；
T13的栅极与低电压端V02连接，T13的源极与N01电连接，T13的漏极与N1电连接；
所述第一节点电位调节电路11包括调节晶体管T10和调节电容C2，其中，
所述调节晶体管T10的栅极与所述第一节点N1电连接，所述调节晶体管T10的源极与第二时钟信号端CB电连接，所述调节晶体管T10的漏极与所述调节电容C1的第一端电连接；
所述调节电容C1的第二端与所述第一节点N1电连接；
第二节点控制电路13包括第一控制晶体管T11、控制电容C1、第二控制晶体管T8和第三控制晶体管T9，其中，
所述控制电容C1的第一端与所述第三节点N3电连接，所述控制电容C1的第二端与第五节点N5电连接；
所述第一控制晶体管T11的栅极与所述第三节点N3电连接，所述第一控制晶体管T11的漏极与所述第五节点N5电连接，所述第一控制晶体管T11的源极与第二时钟信号端CB电连接；
所述第二控制晶体管T8的栅极与所述第二时钟信号端CB电连接，所述第二控制晶体管T8的源极与所述第五节点N5电连接，所述第二控制晶体管T8的漏极与第二节点N2电连接；
所述第三控制晶体管T9的栅极与所述第一隔离节点N01电连接，所述第三控制晶体管T9的源极与高电压端V01电连接，所述第三控制晶体管T9的漏极与所述第二节点N2电连接；
所述第三节点控制电路15包括第四控制晶体管T2、第三隔离晶体管T12、第五控制晶体管T5和第六控制晶体管T6，其中，
所述第四控制晶体管T2的栅极与第一时钟信号端CK电连接，所述第四控制晶体管T2的源极与低电压端V02电连接；
所述第三隔离晶体管T12的栅极与低电压端V02电连接，第三隔离晶体管T12的源极与所述第四控制晶体管T2的漏极电连接，所述第三隔离晶体管T12的漏极与第三节点N3电连接；
所述第五控制晶体管T5的栅极与第一隔离节点N01电连接，所述第五控制晶体管T5的源极与高电压端V01电连接，所述第五控制晶体管T5的漏极与第四节点N4电连接；
所述第六控制晶体管T6的栅极与第二时钟信号端CB电连接，所述第六控制晶体管T6的源极与所述第四节点N4电连接，所述第六控制晶体管T6的漏极与所述第三节点N3电连接；
所述第一节点控制电路16包括第七控制晶体管T1和第八控制晶体管T7，其中，
所述第七控制晶体管T1的栅极与第一时钟信号端CK电连接，所述第七控制晶体管T1的源极与所述输入端I1电连接，所述第七控制晶体管T1的漏极与所述第一隔离节点N01电连接；
所述第八控制晶体管T7的栅极与所述第四节点N4电连接，所述第八控制晶体管T7的漏极与所述第一隔离节点N01电连接，所述第八控制晶体管T7的源极与高电压端V01电连接；
所述输出电路17包括第一输出晶体管T3和第二输出晶体管T4；
所述第一输出晶体管T3的栅极与所述第一节点N1电连接，所述第一输 出晶体管T3的源极与低电压端V02电连接，所述第一输出晶体管T3的漏极与所述驱动电压信号端O1电连接；
所述第二输出晶体管T4的栅极与所述第二节点N2电连接，所述第二输出晶体管T4的漏极与所述驱动电压信号端O1电连接，所述第二输出晶体管T4的源极与高电压端V01电连接；
所述第一储能电路12包括第一存储电容C4，所述第二储能电路14包括第二存储电容C3；
所述第一存储电容C4的第一端与所述第一节点N1电连接，所述第一存储电容C4的第二端与低电压端V02电连接；
所述第二存储电容C3的第一端与所述第二节点N2电连接，所述第二存储电容C3的第二端与所述输出时钟信号端CBo电连接。
在本公开至少一实施例中，所述高电压端可以提供高电压信号，所述低电压端可以提供低电压信号。
在本公开至少一实施例中，所述控制电压端为低电压端，但不以此为限。
本公开所述的移位寄存器单元的第十三实施例为栅极驱动电路中的移位寄存器单元，用于生成栅极驱动信号。
在本公开所述的移位寄存器单元的第十三实施例中，所有的晶体管都为p型薄膜晶体管，但不以此为限。
在本公开所述的移位寄存器单元的第十三实施例与在本公开所述的移位寄存器单元的第十实施例的区别在于：增加了T13和T12。
在本公开所述的移位寄存器单元的第十三实施例中，增加T13的目的在于：防止当N1的电位过低而导致与N1电连接的晶体管发生DIBL(Drain Induced Barrier Lowering，漏致势垒降低)，从而使得与N1电连接的晶体管的阈值电压发生偏移，导致在其他工作阶段，与N1电连接的晶体管无法正常打开或关闭的情况发生；
增加T12的目的在于，防止当N3的电位电连接的晶体管的阈值电压发生偏移，导致在其他工作阶段，与N3电连接的晶体管无法正常打开或关闭的情况发生。
如图31所示，在图9所述的移位寄存器单元的实施例的基础上，在本公 开所述的移位寄存器单元的第十四实施例中，
所述第一隔离电路41包括第一隔离晶体管T13，所述第三隔离电路43包括第三隔离晶体管T12；
T13的栅极与低电压端V02电连接，T13的源极与N01电连接，T13的漏极与N1电连接；
T12的栅极与低电压端V02电连接，T12的源极与N03电连接，T12的漏极与N3电连接；
所述第一节点电位调节电路11包括调节晶体管T10和调节电容C2，其中，
所述调节晶体管T10的栅极与所述第一节点N1电连接，所述调节晶体管T10的源极与第二时钟信号端CB电连接，所述调节晶体管T10的漏极与所述调节电容C1的第一端电连接；
所述调节电容C1的第二端与所述第一节点N1电连接；
第二节点控制电路13包括第一控制晶体管T11、控制电容C1、第二控制晶体管T8和第三控制晶体管T9，其中，
所述控制电容C1的第一端与所述第三节点N3电连接，所述控制电容C1的第二端与第五节点N5电连接；
所述第一控制晶体管T11的栅极与所述第三节点N3电连接，所述第一控制晶体管T11的漏极与所述第五节点N5电连接，所述第一控制晶体管T11的源极与第二时钟信号端CB电连接；
所述第二控制晶体管T8的栅极与所述第二时钟信号端CB电连接，所述第二控制晶体管T8的源极与所述第五节点N5电连接，所述第二控制晶体管T8的漏极与第二节点N2电连接；
所述第三控制晶体管T9的栅极与所述第一隔离节点N01电连接，所述第三控制晶体管T9的源极与高电压端V01电连接，所述第三控制晶体管T9的漏极与所述第二节点N2电连接；
所述第三节点控制电路15包括第四控制晶体管T2、第五控制晶体管T5和第六控制晶体管T6，其中，
所述第四控制晶体管T2的栅极与第一时钟信号端CK电连接，所述第四 控制晶体管T2的源极与低电压端V02电连接，所述第四控制晶体管T2的漏极与第三节点N3电连接；
所述第五控制晶体管T5的栅极与第一隔离节点N01电连接，所述第五控制晶体管T5的源极与高电压端V01电连接，所述第五控制晶体管T5的漏极与第四节点N4电连接；
所述第六控制晶体管T6的栅极与第二时钟信号端CB电连接，所述第六控制晶体管T6的源极与所述第四节点N4电连接，所述第六控制晶体管T6的漏极与所述第三隔离节点N03电连接；
所述第一节点控制电路16包括第七控制晶体管T1和第八控制晶体管T7，其中，
所述第七控制晶体管T1的栅极与第一时钟信号端CK电连接，所述第七控制晶体管T1的源极与所述输入端I1电连接，所述第七控制晶体管T1的漏极与所述第一隔离节点N01电连接；
所述第八控制晶体管T7的栅极与所述第四节点N4电连接，所述第八控制晶体管T7的漏极与所述第一隔离节点N1电连接，所述第八控制晶体管T7的源极与高电压端V01电连接；
所述输出电路17包括第一输出晶体管T3和第二输出晶体管T4；
所述第一输出晶体管T3的栅极与所述第一节点N1电连接，所述第一输出晶体管T3的源极与低电压端V02电连接，所述第一输出晶体管T3的漏极与所述驱动电压信号端O1电连接；
所述第二输出晶体管T4的栅极与所述第二节点N2电连接，所述第二输出晶体管T4的漏极与所述驱动电压信号端O1电连接，所述第二输出晶体管T4的源极与高电压端V01电连接；
所述第一储能电路12包括第一存储电容C4，所述第二储能电路14包括第二存储电容C3；
所述第一存储电容C4的第一端与所述第一节点N1电连接，所述第一存储电容C4的第二端与低电压端V02电连接；
所述第二存储电容C3的第一端与所述第二节点N2电连接，所述第二存储电容C3的第二端与所述输出时钟信号端CBo电连接。
在本公开至少一实施例中，所述高电压端可以提供高电压信号，所述低电压端可以提供低电压信号。
本公开所述的移位寄存器单元的第十四实施例为栅极驱动电路中的移位寄存器单元，用于生成栅极驱动信号。
在本公开所述的移位寄存器单元的第十四实施例中，所有的晶体管都为p型薄膜晶体管，但不以此为限。
在本公开所述的移位寄存器单元的第十四实施例与在本公开所述的移位寄存器单元的第十实施例的区别在于：增加了T13和T12。
在本公开所述的移位寄存器单元的第十四实施例中，增加T13的目的在于：防止当N1的电位过低而导致与N1电连接的晶体管发生DIBL(Drain Induced Barrier Lowering，漏致势垒降低)，从而使得与N1电连接的晶体管的阈值电压发生偏移，导致在其他工作阶段，与N1电连接的晶体管无法正常打开或关闭的情况发生；
增加T12的目的在于，防止当N3的电位电连接的晶体管的阈值电压发生偏移，导致在其他工作阶段，与N3电连接的晶体管无法正常打开或关闭的情况发生。
如图32所示，在图10所述的移位寄存器单元的实施例的基础上，在本公开所述的移位寄存器单元的第十五实施例中，
所述第一隔离电路41包括第一隔离晶体管T13，所述第三隔离电路43包括第三隔离晶体管T12；所述第二隔离电路42包括第二隔离晶体管T14；
T13的栅极与低电压端V02电连接，T13的源极与N01电连接，T13的漏极与N1电连接；
T12的栅极与低电压端V02电连接，T12的源极与N03电连接，T12的漏极与N3电连接；
T14的栅极与低电压端V02电连接，T14的源极与N02电连接，T14的漏极与N2电连接；
所述第一节点电位调节电路11包括调节晶体管T10和调节电容C2，其中，
所述调节晶体管T10的栅极与所述第一节点N1电连接，所述调节晶体 管T10的源极与第二时钟信号端CB电连接，所述调节晶体管T10的漏极与所述调节电容C1的第一端电连接；
所述调节电容C1的第二端与所述第一节点N1电连接；
第二节点控制电路13包括第一控制晶体管T11、控制电容C1、第二控制晶体管T8和第三控制晶体管T9，其中，
所述控制电容C1的第一端与所述第三节点N3电连接，所述控制电容C1的第二端与第五节点N5电连接；
所述第一控制晶体管T11的栅极与所述第三节点N3电连接，所述第一控制晶体管T11的漏极与所述第五节点N5电连接，所述第一控制晶体管T11的源极与第二时钟信号端CB电连接；
所述第二控制晶体管T8的栅极与所述第二时钟信号端CB电连接，所述第二控制晶体管T8的源极与所述第五节点N5电连接，所述第二控制晶体管T8的漏极与第二隔离节点N02电连接；
所述第三控制晶体管T9的栅极与所述第一隔离节点N01电连接，所述第三控制晶体管T9的源极与高电压端V01电连接，所述第三控制晶体管T9的漏极与所述第二隔离节点N02电连接；
所述第三节点控制电路15包括第四控制晶体管T2、第五控制晶体管T5和第六控制晶体管T6，其中，
所述第四控制晶体管T2的栅极与第一时钟信号端CK电连接，所述第四控制晶体管T2的源极与低电压端V02电连接，所述第四控制晶体管T2的漏极与第三节点N3电连接；
所述第五控制晶体管T5的栅极与第一隔离节点N01电连接，所述第五控制晶体管T5的源极与高电压端V01电连接，所述第五控制晶体管T5的漏极与第四节点N4电连接；
所述第六控制晶体管T6的栅极与第二时钟信号端CB电连接，所述第六控制晶体管T6的源极与所述第四节点N4电连接，所述第六控制晶体管T6的漏极与所述第三隔离节点N03电连接；
所述第一节点控制电路16包括第七控制晶体管T1和第八控制晶体管T7，其中，
所述第七控制晶体管T1的栅极与第一时钟信号端CK电连接，所述第七控制晶体管T1的源极与所述输入端I1电连接，所述第七控制晶体管T1的漏极与所述第一隔离节点N01电连接；
所述第八控制晶体管T7的栅极与所述第四节点N4电连接，所述第八控制晶体管T7的漏极与所述第一隔离节点N1电连接，所述第八控制晶体管T7的源极与高电压端V01电连接；
所述输出电路17包括第一输出晶体管T3和第二输出晶体管T4；
所述第一输出晶体管T3的栅极与所述第一节点N1电连接，所述第一输出晶体管T3的源极与低电压端V02电连接，所述第一输出晶体管T3的漏极与所述驱动电压信号端O1电连接；
所述第二输出晶体管T4的栅极与所述第二节点N2电连接，所述第二输出晶体管T4的漏极与所述驱动电压信号端O1电连接，所述第二输出晶体管T4的源极与高电压端V01电连接；
所述第一储能电路12包括第一存储电容C4，所述第二储能电路14包括第二存储电容C3；
所述第一存储电容C4的第一端与所述第一节点N1电连接，所述第一存储电容C4的第二端与低电压端V02电连接；
所述第二存储电容C3的第一端与所述第二节点N2电连接，所述第二存储电容C3的第二端与所述输出时钟信号端CBo电连接。
在本公开至少一实施例中，所述高电压端可以提供高电压信号，所述低电压端可以提供低电压信号。
本公开所述的移位寄存器单元的第十五实施例为栅极驱动电路中的移位寄存器单元，用于生成栅极驱动信号。
在本公开所述的移位寄存器单元的第十五实施例中，所有的晶体管都为p型薄膜晶体管，但不以此为限。
在本公开所述的移位寄存器单元的第十五实施例与在本公开所述的移位寄存器单元的第十实施例的区别在于：增加了T13、T12和T14。
在本公开所述的移位寄存器单元的第十五实施例中，增加T13的目的在于：防止当N1的电位过低而导致与N1电连接的晶体管发生DIBL(Drain  Induced Barrier Lowering，漏致势垒降低)，从而使得与N1电连接的晶体管的阈值电压发生偏移，导致在其他工作阶段，与N1电连接的晶体管无法正常打开或关闭的情况发生；
增加T12的目的在于，防止当N3的电位电连接的晶体管的阈值电压发生偏移，导致在其他工作阶段，与N3电连接的晶体管无法正常打开或关闭的情况发生
增加T14的目的在于，防止当N2的电位过低而导致与N2电连接的晶体管发生DIBL(Drain Induced Barrier Lowering，漏致势垒降低)，从而使得与N2电连接的晶体管的阈值电压发生偏移，导致在其他工作阶段，与N2电连接的晶体管无法正常打开或关闭的情况发生。
如图33所示，本公开所述的移位寄存器单元的第十六实施例与本公开所述的移位寄存器单元的第十五实施例的区别在于：T10的源极与第三时钟信号端CKo电连接。
在本公开至少一实施例中，CKo提供的第三时钟信号可以与CK提供的第一时钟信号反相。
以上本公开所述的移位寄存器单元的第一实施例至第十六实施例为本公开所述的移位寄存器单元的至少一实施例。
本公开至少一实施例所述的驱动方法应用于上述的移位寄存器单元，所述驱动方法包括：
所述第一节点控制电路第一时钟信号的控制下，控制将输入信号写入第一隔离节点，并在第四节点的电位的控制下，控制将第一电压信号写入至第一隔离节点；
所述第一节点电位调节电路在第一节点的电位的控制下，根据调节时钟信号改变第一节点的电位；
所述第一储能电路所述第一节点的电位；
所述第三节点控制电路在第一时钟信号、第二时钟信号和第一隔离节点的电位的控制下，控制所述第三隔离节点的电位和所述第四节点的电位；
所述第二节点控制电路在第三节点的电位和控制时钟信号的控制下，控制第二隔离节点的电位，并在第一隔离节点的电位的控制下，控制第一电压 信号写入第二隔离节点；
所述第二储能电路维持所述第二节点的电位；
所述输出电路在第一节点的电位的控制下，将第二电压信号写入驱动电压信号输出端，所述输出电路在第二节点的电位的控制下，将第三电压信号写入所述驱动电压信号端。
通过采用本公开至少一实施例所述的驱动方法，本公开至少一实施例所述的移位寄存器单元即可以提供栅极驱动信号，又可以提供发光控制信号，以提供特定像素工作的波形；在所述移位寄存器单元提供发光控制信号时，所述第三电压端可以为第一电压端；在所述移位寄存器单元提供栅极驱动信号时，所述第三电压端可以为输出时钟信号端；所述输出时钟信号端提供的输出时钟信号为与所述第二时钟信号反相的时钟信号。并且，在本公开至少一实施例所述的驱动方法中，所述第一节点电位调节电路分别与调节时钟信号端和所述第一节点电连接，在第一节点的电位的控制下，根据调节时钟信号端提供的调节时钟信号改变第一节点的电位，以使得需要使得输出电路中的第一输出晶体管打开时，所述第一节点的电位可以下降至够低电压，以使得所述第一输出晶体管充分打开，避免降低驱动电压信号端的输出波形受到第一输出晶体管的阈值电压损耗问题。
在具体实施时，所述驱动电压信号端为栅极驱动信号输出端，所述第三电压端为输出时钟信号端；所述输出时钟信号端提供的输出时钟信号为与所述第二时钟信号反相的时钟信号；或者，
所述驱动电压信号端为发光控制信号端，所述第三电压端为第一电压端。
本公开至少一实施例所述的驱动电路包括多级上述的移位寄存器单元。
在本公开至少一实施例中，所述驱动电路的移位寄存器单元的输入端与相邻上一级移位寄存器单元的驱动电压信号输出端电连接；
并且，在本公开至少一实施例所述的驱动电路中，奇数级移位寄存器单元接入的第一时钟信号为偶数级移位寄存器单元接入的第二时钟信号，奇数级移位寄存器单元接入的第二时钟信号为偶数级移位寄存器单元接入的第一时钟信号，但不以此为限；
在本公开至少一实施例所述的驱动电路中，奇数级移位寄存器单元接入 的输出时钟信号为偶数级移位寄存器单元接入的第三时钟信号，奇数级移位寄存器单元接入的第三时钟信号为偶数级移位寄存器单元接入的输出时钟信号，但不以此为限。
可选的，所述驱动电路为栅极驱动电路，驱动电压信号端为栅极驱动信号输出端，第三电压端为输出时钟信号端；所述输出时钟信号端提供的输出时钟信号为与第二时钟信号反相的时钟信号。
可选的，所述驱动电路为发光控制信号生成电路；驱动电压信号端为发光控制信号端，第三电压端为第一电压端。
本公开至少一实施例所述的显示装置包括上述的驱动电路。
本公开至少一实施例所提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (27)

  1. 一种移位寄存器单元，包括第一节点电位调节电路、第一储能电路、第二节点控制电路、第二储能电路、第三节点控制电路、第一节点控制电路和输出电路；其中，
    所述第一节点控制电路分别与输入端、第一时钟信号端、第一隔离节点、第四节点和第一电压端电连接，用于在第一时钟信号端提供的第一时钟信号的控制下，控制将输入端提供的输入信号写入第一隔离节点，并在第四节点的电位的控制下，控制将所述第一电压端提供的第一电压信号写入至第一隔离节点；
    所述第一节点电位调节电路分别与调节时钟信号端和第一节点电连接，用于在第一节点的电位的控制下，根据调节时钟信号端提供的调节时钟信号改变第一节点的电位；
    所述第一储能电路与所述第一节点电连接，用于维持所述第一节点的电位；
    所述第三节点控制电路分别与第一时钟信号端、第二时钟信号端、第一隔离节点、第三隔离节点、第四节点、第一电压端和第二电压端电连接，用于在第一时钟信号、第二时钟信号和第一隔离节点的电位的控制下，控制所述第三隔离节点的电位和所述第四节点的电位；
    所述第二节点控制电路分别与第一隔离节点、第一电压端、第二隔离节点、控制时钟信号端和第三节点电连接，用于在第三节点的电位和所述控制时钟信号端提供的控制时钟信号的控制下，控制第二隔离节点的电位，并在第一隔离节点的电位的控制下，控制第一电压端提供的第一电压信号写入第二隔离节点；
    所述第二储能电路用于维持所述第二节点的电位；
    所述输出电路分别与第一节点、第二电压端、驱动电压信号端和第三电压端电连接，用于在第一节点的电位的控制下，将第二电压端提供的第二电压信号写入驱动电压信号输出端，并用于在第二节点的电位的控制下，将第三电压端提供的第三电压信号写入所述驱动电压信号端；
    所述第一隔离节点与所述第一节点为同一节点；或者，所述第一隔离节点与所述第一节点为不同的节点。
  2. 如权利要求1所述的移位寄存器单元，其中，当所述第一隔离节点与所述第一节点为不同的节点时，所述第一隔离节点与所述第一节点之间通过第一隔离电路电连接；
    所述第一隔离电路的控制端与控制电压端电连接，所述第一隔离电路用于在所述控制电压端提供的控制电压信号的控制下，控制所述第一隔离节点与所述第一节点之间连通。
  3. 如权利要求2所述的移位寄存器单元，其中，所述第一隔离电路包括第一隔离晶体管；
    所述第一隔离晶体管的控制极与控制电压端电连接，所述第一隔离晶体管的第一极与所述第一隔离节点电连接，所述第一隔离晶体管的第二极与所述第一节点电连接。
  4. 如权利要求1所述的移位寄存器单元，其中，所述第二隔离节点与所述第二节点为同一节点；或者，所述第二隔离节点与所述第二节点之间通过第二电路电连接；
    所述第二隔离电路的控制端与控制电压端电连接，所述第二隔离电路用于在所述控制电压端提供的控制电压信号的控制下，控制所述第二隔离节点与所述第二节点之间连通。
  5. 如权利要求4所述的移位寄存器单元，其中，所述第二隔离电路包括第二隔离晶体管；
    所述第二隔离晶体管的控制极与控制电压端电连接，所述第二隔离晶体管的第一极与所述第二隔离节点电连接，所述第二隔离晶体管的第二极与所述第二节点电连接。
  6. 如权利要求1所述的移位寄存器单元，其中，所述第三隔离节点与所述第三节点为同一节点；或者，所述第三隔离节点与所述第三节点之间通过第三隔离电路电连接；
    所述第三隔离电路的控制端与控制电压端电连接，所述第三隔离电路用于在所述控制电压端提供的控制电压信号的控制下，控制所述第三隔离节点 与所述第三节点之间连通。
  7. 如权利要求6所述的移位寄存器单元，其中，所述第三隔离电路包括第三隔离晶体管；
    所述第三隔离晶体管的控制极与控制电压端电连接，所述第三隔离晶体管的第一极与所述第三隔离节点电连接，所述第三隔离晶体管的第二极与所述第三节点电连接。
  8. 如权利要求1所述的移位寄存器单元，其中，所述控制时钟信号端为第二时钟信号端；或者，
    所述驱动电压信号端为发光控制信号端，所述控制时钟信号端为第一时钟信号端。
  9. 如权利要求1所述的移位寄存器单元，其中，所述调节时钟信号端提供的调节时钟信号为所述第二时钟信号，或者，所述调节时钟信号为与所述第一时钟信号反相的时钟信号。
  10. 如权利要求1所述的移位寄存器单元，其中，所述驱动电压信号端为栅极驱动信号输出端，所述第三电压端为输出时钟信号端；所述输出时钟信号端提供的输出时钟信号为与所述第二时钟信号反相的时钟信号；或者，
    所述驱动电压信号端为发光控制信号端，所述第三电压端为第一电压端。
  11. 如权利要求1至10中任一权利要求所述的移位寄存器单元，其中，所述第一节点电位调节电路包括调节晶体管和调节电容，其中，
    所述调节晶体管的控制极与所述第一隔离节点电连接，所述调节晶体管的第一极与调节时钟信号端电连接，所述调节晶体管的第二极与所述调节电容的第一端电连接；
    所述调节电容的第二端与所述第一隔离节点电连接。
  12. 如权利要求1至10中任一权利要求所述的移位寄存器单元，其中，所述第二节点控制电路还与第一时钟信号端电连接，还用于在第一时钟信号的控制下，控制所述第二隔离节点的电位。
  13. 如权利要求1至10中任一权利要求所述的移位寄存器单元，其中，第二节点控制电路包括第一控制晶体管、控制电容、第二控制晶体管和第三控制晶体管，其中，
    所述控制电容的第一端与所述第三节点电连接，所述控制电容的第二端与第五节点电连接；
    所述第一控制晶体管的控制极与所述第三节点电连接，所述第一控制晶体管的第一极与所述第五节点电连接，所述第一控制晶体管的第二极与控制时钟信号端电连接；
    所述第二控制晶体管的控制极与所述第二时钟信号端电连接，所述第二控制晶体管的第一极与所述第五节点电连接，所述第二控制晶体管的第二极与第二隔离节点电连接；
    所述第三控制晶体管的控制极与所述第一节点电连接，所述第三控制晶体管的第一极与第一电压端电连接，所述第三控制晶体管的第二极与所述第二隔离节点电连接。
  14. 如权利要求12所述的移位寄存器单元，其中，第二节点控制电路包括第一控制晶体管、控制电容、第二控制晶体管、第三控制晶体管和节点控制晶体管，其中，
    所述控制电容的第一端与所述第三节点电连接，所述控制电容的第二端与第五节点电连接；
    所述第一控制晶体管的控制极与所述第三节点电连接，所述第一控制晶体管的第一极与所述第五节点电连接，所述第一控制晶体管的第二极与控制时钟信号端电连接；
    所述第二控制晶体管的控制极与所述第二时钟信号端电连接，所述第二控制晶体管的第一极与所述第五节点电连接，所述第二控制晶体管的第二极与第二隔离节点电连接；
    所述第三控制晶体管的控制极与所述第一节点电连接，所述第三控制晶体管的第一极与第一电压端电连接；
    所述节点控制晶体管的控制极与第一时钟信号端电连接，所述节点控制晶体管的第一极与所述第三控制晶体管的第二极电连接，所述节点控制晶体管的第二极与第二节点电连接。
  15. 如权利要求1至10中任一权利要求所述的移位寄存器单元，其中，第二节点控制电路包括第一控制晶体管、控制电容、第二控制晶体管和第三 控制晶体管，其中，
    所述控制电容的第一端与所述第三节点电连接；
    所述第一控制晶体管的控制极与所述第三节点电连接，所述第一控制晶体管的第一极与所述控制电容的第二端电连接，所述第一控制晶体管的第二极与第二时钟信号端电连接；所述第二控制晶体管的控制极与所述第二时钟信号端电连接，所述第二控制晶体管的第一极与所述第二隔离节点电连接；
    所述第三控制晶体管的控制极与所述第一隔离节点电连接，所述第三控制晶体管的第一极与第一电压端电连接，所述第三控制晶体管的第二极与所述第二隔离节点电连接。
  16. 如权利要求1至10中任一权利要求所述的移位寄存器单元，其中，所述第三节点控制电路包括第四控制晶体管、第五控制晶体管和第六控制晶体管，其中，
    所述第四控制晶体管的控制极与第一时钟信号端电连接，所述第四控制晶体管的第一极与第二电压端电连接，所述第四控制晶体管的第二极与第三隔离节点电连接；
    所述第五控制晶体管的控制极与第一隔离节点电连接，所述第五控制晶体管的第一极与第一电压端电连接，所述第五控制晶体管的第二极与第四节点电连接；
    所述第六控制晶体管的控制极与第二时钟信号端电连接，所述第六控制晶体管的第一极与所述第四节点电连接，所述第六控制晶体管的第二极与所述第三隔离节点电连接。
  17. 如权利要求16所述的移位寄存器单元，其中，还包括第三隔离晶体管；所述第三隔离节点为第三节点；
    所述第四控制晶体管的第二极通过所述第三隔离晶体管与所述第三节点电连接；
    所述第三隔离晶体管的控制极与控制电压端电连接，所述第三隔离晶体管的第一极与所述第四控制晶体管的第二极电连接，所述第三隔离晶体管的第二极与所述第三节点电连接。
  18. 如权利要求1至10中任一权利要求所述的移位寄存器单元，其中， 所述驱动电压信号端为发光控制信号端，所述第三电压端为第一电压端；
    所述第三节点控制电路包括第四控制晶体管、第五控制晶体管和第六控制晶体管，其中，
    所述第四控制晶体管的控制极与第二时钟信号端电连接，所述第四控制晶体管的第一极与第二电压端电连接，所述第四控制晶体管的第二极与第三隔离节点电连接；
    所述第五控制晶体管的控制极与第一隔离节点电连接，所述第五控制晶体管的第一极与第一电压端电连接，所述第五控制晶体管的第二极与第四节点电连接；
    所述第六控制晶体管的控制极与第一时钟信号端电连接，所述第六控制晶体管的第一极与所述第四节点电连接，所述第六控制晶体管的第二极与所述第三隔离节点电连接。
  19. 如权利要求18所述的移位寄存器单元，其中，还包括第三隔离晶体管；所述第三隔离节点为第三节点；
    所述第四控制晶体管的第二极通过所述第三隔离晶体管与所述第三节点电连接；
    所述第三隔离晶体管的控制极与控制电压端电连接，所述第三隔离晶体管的第一极与所述第四控制晶体管的第二极电连接，所述第三隔离晶体管的第二极与所述第三节点电连接。
  20. 如权利要求1至10中任一权利要求所述的移位寄存器单元，其中，所述第一节点控制电路包括第七控制晶体管和第八控制晶体管，其中，
    所述第七控制晶体管的控制极与第一时钟信号端电连接，所述第七控制晶体管的第一极与所述输入端电连接，所述第七控制晶体管的第二极与所述第一隔离节点电连接；
    所述第八控制晶体管的控制极与所述第四节点电连接，所述第八控制晶体管的第一极与所述第一隔离节点电连接，所述第八控制晶体管的第二极与第一电压端电连接。
  21. 如权利要求1至10中任一权利要求所述的移位寄存器单元，其中，所述输出电路包括第一输出晶体管和第二输出晶体管；
    所述第一输出晶体管的控制极与所述第一节点电连接，所述第一输出晶体管的第一极与第二电压端电连接，所述第一输出晶体管的第二极与所述驱动电压信号端电连接；
    所述第二输出晶体管的控制极与所述第二节点电连接，所述第二输出晶体管的第一极与所述驱动电压信号端电连接，所述第二输出晶体管的第二极与所述第三电压端电连接。
  22. 如权利要求1至10中任一权利要求所述的移位寄存器单元，其中，所述第一储能电路包括第一存储电容，所述第二储能电路包括第二存储电容；
    所述第一存储电容的第一端与所述第一节点电连接，所述第一存储电容的第二端与第二电压端电连接；
    所述第二存储电容的第一端与所述第二节点电连接，所述第二存储电容的第二端与第三电压端电连接；
    所述驱动电压信号端为栅极驱动信号输出端，所述第三电压端为输出时钟信号端；所述输出时钟信号端提供的输出时钟信号为与所述第二时钟信号反相的时钟信号；或者，
    所述驱动电压信号端为发光控制信号端，所述第三电压端为第一电压端。
  23. 一种驱动方法，应用于如权利要求1至22中任一权利要求所述的移位寄存器单元，所述驱动方法包括：
    所述第一节点控制电路第一时钟信号的控制下，控制将输入信号写入第一隔离节点，并在第四节点的电位的控制下，控制将第一电压信号写入至第一隔离节点；
    所述第一节点电位调节电路在第一节点的电位的控制下，根据调节时钟信号改变第一节点的电位；
    所述第一储能电路所述第一节点的电位；
    所述第三节点控制电路在第一时钟信号、第二时钟信号和第一隔离节点的电位的控制下，控制所述第三隔离节点的电位和所述第四节点的电位；
    所述第二节点控制电路在第三节点的电位和控制时钟信号的控制下，控制第二隔离节点的电位，并在第一隔离节点的电位的控制下，控制第一电压信号写入第二隔离节点；
    所述第二储能电路维持所述第二节点的电位；
    所述输出电路在第一节点的电位的控制下，将第二电压信号写入驱动电压信号输出端，所述输出电路在第二节点的电位的控制下，将第三电压信号写入所述驱动电压信号端。
  24. 一种驱动电路，包括多级如权利要求1至22中任一权利要求所述的移位寄存器单元。
  25. 如权利要求24所述的驱动电路，其中，所述驱动电路为栅极驱动电路，驱动电压信号端为栅极驱动信号输出端，第三电压端为输出时钟信号端；所述输出时钟信号端提供的输出时钟信号为与第二时钟信号反相的时钟信号。
  26. 如权利要求24所述的驱动电路，其中，所述驱动电路为发光控制信号生成电路；驱动电压信号端为发光控制信号端，第三电压端为第一电压端。
  27. 一种显示装置，包括如权利要求24至26中任一权利要求所述的驱动电路。
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