WO2018161523A1 - 移位寄存器、栅极驱动电路、显示面板及驱动方法 - Google Patents

移位寄存器、栅极驱动电路、显示面板及驱动方法 Download PDF

Info

Publication number
WO2018161523A1
WO2018161523A1 PCT/CN2017/102448 CN2017102448W WO2018161523A1 WO 2018161523 A1 WO2018161523 A1 WO 2018161523A1 CN 2017102448 W CN2017102448 W CN 2017102448W WO 2018161523 A1 WO2018161523 A1 WO 2018161523A1
Authority
WO
WIPO (PCT)
Prior art keywords
pull
transistor
control
pole
node
Prior art date
Application number
PCT/CN2017/102448
Other languages
English (en)
French (fr)
Inventor
王梓轩
王飞
陈宇霆
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 合肥鑫晟光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US15/761,749 priority Critical patent/US10593245B2/en
Publication of WO2018161523A1 publication Critical patent/WO2018161523A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • Embodiments of the present disclosure relate to a shift register, a gate driving circuit, a display panel, and a driving method.
  • the Gate-Driver on Array (GOA) technology directly integrates the gate driving circuit on the array substrate of the display device by a photolithography process, and the GOA circuit usually includes a plurality of cascaded shift registers, each of which The shift registers are each coupled to a gate line corresponding to a row or column of pixels (eg, each shift register provides a scan drive signal to a gate line) to effect scan drive of the display panel.
  • This integrated technology can save the bonding area of the integrated circuit (IC) and the space of the fan-out area, thereby achieving a narrow border of the display panel, and at the same time reducing product cost and improving Product yield.
  • the reliability of GOA directly affects the reliability of display panels. Therefore, how to improve the reliability of GOA has become one of the research priorities.
  • An embodiment of the present disclosure provides a shift register, including: an input circuit respectively connected to a pull-up node and an input signal terminal; and a reset circuit connected to the pull-up node, the reset signal end, and the first power terminal respectively to receive a first power supply voltage; an output circuit respectively connected to the pull-up node, the clock signal end and the output end; and an output pull-down circuit connected to the output end, configured to write the second power supply voltage to the output end Wherein the first supply voltage is different from the second supply voltage.
  • the output circuit includes a storage capacitor and a first transistor, and a first pole of the first transistor is connected to a clock signal end, and a control electrode of the first transistor is The pull-up node is connected, the second pole of the first transistor is connected to the output end, the first end of the storage capacitor is connected to the pull-up node, and the second end of the storage capacitor Connected to the output.
  • the input circuit includes a second transistor, a first pole of the second transistor is connected to the input signal terminal, and a control electrode of the second transistor is The input signal terminal is connected, the second pole of the second transistor is connected to the pull-up node;
  • the reset circuit includes a third transistor, and the first pole of the third transistor is connected to the pull-up node, The control electrode of the third transistor is connected to the reset signal terminal, and the second electrode of the third transistor is connected to the first power terminal.
  • the output pull-down circuit includes a first output pull-down transistor, and a first pole of the first output pull-down transistor is connected to the output terminal, and the first output pull-down A control electrode of the transistor is coupled to the reset signal terminal, and a second electrode of the first output pull-down transistor is coupled to the second power terminal to receive a second power supply voltage.
  • the shift register provided by the embodiment of the present disclosure further includes a first pull-down control circuit, wherein the output pull-down circuit includes a first output pull-down transistor, a first pole of the first output pull-down transistor and the output An end connection, a control electrode of the first output pull-down transistor is connected to the first pull-down control circuit, and a second pole of the first output pull-down transistor is configured to receive the second power supply voltage;
  • a pull down control circuit is configured to control the turning on and off of the first output pulldown transistor.
  • the first pull-down control circuit includes a first sub-control circuit and a second sub-control circuit, the first sub-control circuit and the third power terminal, the first The pull-down node and the second sub-control circuit are respectively connected, and the second sub-control circuit is respectively connected to the pull-up node, the first pull-down node and the first power terminal.
  • the first sub-control circuit includes a first control transistor and a second control transistor
  • the second sub-control circuit includes a third control transistor and a fourth control transistor.
  • a control electrode of the first output pull-down transistor is connected to the first pull-down node;
  • a first pole of the first control transistor is connected to the third power terminal, and a control pole of the first control transistor
  • the third power terminal is connected, the second pole of the first control transistor is connected to the first node;
  • the first pole of the second control transistor is connected to the third power terminal, and the second control transistor is controlled a pole connected to the first node, a second pole of the second control transistor being connected to the first pull-down node;
  • a first pole of the third control transistor being connected to the first pull-down node a control electrode of the third control transistor is connected to the pull-up node, and the third control a second pole of the transistor is connected to the first power terminal
  • a first pole of the fourth control transistor is connected to the first node
  • the shift register provided by the embodiment of the present disclosure further includes a second pull-down control circuit, wherein the output pull-down circuit further includes a second output pull-down transistor, and the first output of the second output pull-down transistor and the output An end connection, a control electrode of the second output pull-down transistor is coupled to the second pull-down control circuit, a second pole of the second output pull-down transistor is configured to receive the second supply voltage; A control circuit is configured to control the turning on and off of the second output pull-down transistor.
  • the first pull-down control circuit includes a first sub-control circuit and a second sub-control circuit
  • the second pull-down control circuit includes a third sub-control circuit and a a four sub-control circuit
  • the first sub-control circuit is respectively connected to the first power signal end, the first pull-down node and the second sub-control circuit
  • the second sub-control circuit and the pull-up node The first pull-down node and the first power terminal are respectively connected
  • the third sub-control circuit is respectively connected to the second power signal end, the second pull-down node and the fourth sub-control circuit
  • the fourth sub- The control circuit is respectively connected to the pull-up node, the second pull-down node, and the first power terminal.
  • the first sub-control circuit includes a first control transistor and a second control transistor
  • the second sub-control circuit includes a third control transistor and a fourth control transistor.
  • the third sub-control circuit includes a fifth control transistor and a sixth control transistor
  • the fourth sub-control circuit includes a seventh control transistor and an eighth control transistor, a control electrode of the first output pull-down transistor and the first a pull-down node is connected, a second pole of the first output pull-down transistor is connected to the second power signal terminal to receive a second power signal; and a first pole of the first control transistor is connected to the first power signal end
  • Receiving a first power signal a control pole of the first control transistor is coupled to the first power signal terminal to receive the first power signal, and a second pole of the first control transistor is coupled to the first node; a first pole of the second control transistor is coupled to the first power signal terminal to receive the first power signal, and a control pole of the second control transistor The first node is connected, the third sub-control circuit includes a sixth control transistor
  • the shift register provided by the embodiment of the present disclosure further includes a pull-up node pull-down circuit, and is respectively connected to the pull-up node, the first pull-down node, the second pull-down node, and the first power terminal. .
  • the pull-up node pull-down circuit includes a first pull-down transistor and a second pull-down transistor, and the first pole of the first pull-down transistor and the pull-up node Connected, a control pole of the first pull-down transistor is connected to the second pull-down node, and a second pole of the first pull-down transistor is connected to the first power supply terminal to receive the first power supply voltage; a first pole of the second pull-down transistor is connected to the pull-up node, a control pole of the second pull-down transistor is connected to the first pull-down node, and a second pole of the second pull-down transistor is opposite to the first A power terminal is connected to receive the first power voltage.
  • Embodiments of the present disclosure also provide a gate driving circuit including a shift register provided by any of the embodiments of the present disclosure.
  • the gate driving circuit provided by the embodiment of the present disclosure includes a plurality of cascaded shift registers provided by any one of the embodiments of the present disclosure, wherein the stage shift is performed except for the first stage and the last stage shift register.
  • the input signal terminal of the bit register is connected to the output terminal of the shift register of the previous stage; the reset signal terminal of the shift register of the current stage is connected to the output terminal of the shift register of the next stage.
  • An embodiment of the present disclosure further provides a display panel including the gate driving circuit provided by any one of the embodiments of the present disclosure.
  • An embodiment of the present disclosure further provides a driving method of a shift register according to any one of the embodiments of the present disclosure, including: writing the first power voltage to the pull-up node; and writing the second power voltage Into the output terminal, wherein the first power voltage is different from the second power voltage.
  • FIG. 1 is a schematic diagram of a shift register provided by an embodiment of the present disclosure
  • FIG. 2 is a second schematic diagram of a shift register according to an embodiment of the present disclosure
  • FIG. 3 is a third schematic diagram of a shift register according to an embodiment of the present disclosure.
  • FIG. 4 is a fourth schematic diagram of a shift register according to an embodiment of the present disclosure.
  • FIG. 5 is a fifth schematic diagram of a shift register according to an embodiment of the present disclosure.
  • FIG. 6 is a sixth schematic diagram of a shift register according to an embodiment of the present disclosure.
  • FIG. 7 is a seventh schematic diagram of a shift register according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of a shift register according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of a shift register provided by an embodiment of the present disclosure.
  • FIG. 10 is a timing chart of driving of a shift register according to an embodiment of the present disclosure.
  • FIG. 11 is a schematic diagram of a gate driving circuit according to an embodiment of the present disclosure.
  • FIG. 12 is a schematic diagram of a display panel according to an embodiment of the present disclosure.
  • FIG. 13 is a flowchart of a method for driving a shift register according to an embodiment of the present disclosure.
  • Embodiments of the present disclosure provide a shift register 100.
  • the shift register 100 includes an input circuit 110, a reset circuit 120, an output circuit 130, and an output pull-down circuit 140.
  • the input circuit 110 is connected to the pull-up node PU and the input signal terminal INPUT, respectively;
  • the reset circuit 120 is connected to the pull-up node PU, the reset signal terminal RESET and the first power terminal LVSS1, respectively, and the first power terminal LVSS1 is configured to provide the first power source.
  • output circuit 130 is connected to pull-up node PU, clock signal terminal CLK and output terminal OUTPUT, respectively;
  • output pull-down circuit 140 is connected to output terminal OUTPUT, and output pull-down circuit 140 is configured to write second power supply voltage VSS2 to the output terminal OUTPUT.
  • the first power supply voltage VSS1 is different from the second power supply voltage VSS2.
  • the output circuit 130 includes a storage capacitor C and a first transistor T1.
  • the first pole of the first transistor T1 is connected to the clock signal terminal CLK
  • the control electrode of the first transistor T1 is connected to the pull-up node PU
  • the second pole of the first transistor T1 is connected to the output terminal OUTPUT.
  • the first end of the storage capacitor C is connected to the pull-up node PU
  • the second end of the storage capacitor C is connected to the output terminal OUTPUT.
  • control of the transistor described in the embodiments of the present disclosure is extremely the gate of the transistor.
  • the transistors used in the embodiments of the present disclosure may each be a thin film transistor or a field effect transistor or other switching devices having the same characteristics.
  • the source and drain of the transistor used here may be structurally symmetrical, so that the source and the drain may be structurally indistinguishable.
  • one of the first poles and the other pole are directly described, so that all or part of the transistors in the embodiment of the present disclosure
  • the poles and the second pole are interchangeable as needed.
  • the first pole of the transistor of the embodiment of the present disclosure may be a source
  • the second pole may be a drain; or the first extreme drain of the transistor and the second source of the second.
  • the transistors can be divided into N-type and P-type transistors according to the characteristics of the transistors.
  • the turn-on voltage is a low level voltage (eg, 0V, -5V, or other value)
  • the turn-off voltage is a high level voltage (eg, 5V, 10V, or other value)
  • the turn-off voltage is a low level voltage (eg, 0V, -5V, or other value).
  • the first power supply voltage VSS1 is smaller than the second power supply voltage VSS2.
  • the first power supply voltage VSS1 is -11V
  • the second power supply voltage VSS2 is -8V.
  • Embodiments of the present disclosure include, but are not limited to, the first power supply voltage VSS1 and the second power supply voltage VSS2 may also be other voltage values as long as the first power supply voltage VSS1 is smaller than the second power supply voltage VSS2.
  • the first power supply voltage VSS1 is greater than the second power supply voltage VSS2.
  • the first power supply voltage VSS1 is -8V
  • the second power supply voltage VSS2 is -11V.
  • Embodiments of the present disclosure include, but are not limited to, the first power supply voltage VSS1 and the second power supply voltage VSS2 may also be other voltage values as long as the first power supply voltage VSS1 is greater than the second power supply voltage VSS2.
  • the channel of the first transistor T1 may be turned on under the action of its gate voltage and source voltage. That is to say, the drift of the threshold voltage of the first transistor T1 may cause it to be turned on when it is not turned on, thereby causing a multi-output phenomenon in the shift register circuit.
  • the shift register provided by the embodiment of the present disclosure increases the risk of the shift register failure due to the threshold voltage drift of the first transistor by applying different voltages to the gate and the second pole of the first transistor, respectively, increasing the threshold of the first transistor. Design redundancy for voltage drift.
  • each transistor is an N-type transistor. That is, the embodiment of the present disclosure is described by taking the first power supply voltage VSS1 smaller than the second power supply voltage VSS2 as an example. Based on the description and teachings of the implementation of the present disclosure, those skilled in the art can easily realize the implementation of the P-type transistor or the combination of the N-type and P-type transistors in the embodiments of the present disclosure without making creative efforts. These implementations are also within the scope of the present disclosure.
  • the first transistor T1 when the first transistor T1 is an N-type transistor: when its gate-source voltage Vgs (ie, the difference between the gate and source voltages) is less than the threshold voltage Vth, the first transistor T1 is turned off; when the first transistor T1 is gate-source voltage When Vgs is greater than the threshold voltage Vth, the first transistor T1 is turned on.
  • Vgd the gate drain voltage
  • the first pole (eg, the source) of the first transistor T1 is connected to the clock signal terminal CLK, and the control electrode (eg, the gate) of the first transistor T1 is connected to the pull-up node PU, and the first transistor T1
  • the second pole (eg, the drain) is connected to the output terminal OUTPUT. Therefore, in the voltage holding phase (for example, the fourth phase t4 shown in FIG. 10), the gate voltage of the first transistor T1 is the first power supply voltage VSS1 (for example, -11 V), and the drain voltage of the first transistor T1 is the second voltage.
  • the power supply voltage is VSS2 (for example, -8V).
  • the first transistor T1 is placed in a pinch-off state, thereby reducing the risk of failure due to drift of the threshold voltage Vth of the first transistor T1, increasing the design redundancy of the first transistor threshold voltage drift.
  • the input circuit 110 includes a second transistor T2.
  • the first transistor of the second transistor T2 is connected to the input signal terminal INPUT
  • the control electrode of the second transistor T2 is connected to the input signal terminal INPUT
  • the second electrode of the second transistor T2 is connected to the pull-up node PU.
  • the reset circuit 120 includes a third transistor T3.
  • the first pole of the third transistor T3 is connected to the pull-up node PU, the control pole of the third transistor T3 is connected to the reset signal terminal RESET, and the second pole of the third transistor T3 is connected to the first power supply terminal LVSS1 to receive the first power supply voltage. VSS1.
  • the third transistor T3 is turned on, the first power supply voltage VSS1 of the first power supply terminal LVSS1 is transmitted to the pull-up node PU.
  • the input circuit 110 and the reset circuit 120 shown in FIG. 3 are only one example of the embodiment of the present disclosure, and the embodiments of the present disclosure include but are not limited to the case shown in FIG. 3.
  • the output pull-down circuit 140 includes a first output pull-down transistor K1.
  • the first pole of the first output pull-down transistor K1 is connected to the output terminal OUTPUT, and the control pole and the reset signal terminal of the first output pull-down transistor K1
  • the second electrode of the first output pull-down transistor K1 is connected to the second power supply terminal LVSS2 to receive the second power supply voltage VSS2.
  • the signal of the reset signal terminal RESET controls the opening and closing of the first output pull-down transistor K1.
  • the shift register 100 provided by the embodiment of the present disclosure further includes a first pull-down control circuit 150.
  • the first pole of the first output pull-down transistor K1 is connected to the output terminal OUTPUT
  • the control pole of the first output pull-down transistor K1 is connected to the first pull-down control circuit 150
  • the second pole of the first output pull-down transistor K1 is configured to receive the first Two power supply voltages VSS2.
  • the first pull-down control circuit 150 is configured to control the turning on and off of the first output pull-down transistor K1.
  • the second pole of the first output pull-down transistor K1 is connected to the second power terminal LVSS2 to receive the second power voltage VSS2; the first pull-down control circuit 150 and the third power terminal VGH, the pull-up node PU, respectively
  • a power supply terminal LVSS1 is coupled to a control electrode (eg, a gate) of the first output pull-down transistor K1.
  • the third power supply terminal VGH is configured to provide a third power supply voltage VH, which is, for example, a voltage (eg, 5V, 10V, 22V, etc.) that enables the N-type transistor to be turned on.
  • the third power source voltage VH is greater than the first power source voltage VSS1, and the third power source voltage VH is greater than the second power source voltage VSS2.
  • the first pull-down control circuit 150 includes a first sub-control circuit 151 and a second sub-control circuit 152.
  • the first sub-control circuit 151 is respectively connected to the third power supply terminal VGH, the first pull-down node PD1 and the second sub-control circuit 152; the second sub-control circuit 152 and the pull-up node PU, the first pull-down node PD1 and the first The power terminals LVSS1 are connected separately.
  • the first sub-control circuit 151 includes a first control transistor M1 and a second control transistor M2; and the second sub-control circuit 152 includes a third control transistor M3 and a fourth control transistor M4.
  • the control electrode of the first output pull-down transistor K1 is connected to the first pull-down node PD1.
  • the first pole of the first control transistor M1 is connected to the third power terminal VGH, the gate of the first control transistor M1 is connected to the third power terminal VGH, and the second pole of the first control transistor M1 is connected to the first node N1.
  • the first pole of the second control transistor M2 is connected to the third power supply terminal VGH, the control pole of the second control transistor M2 is connected to the first node N1, and the second pole of the second control transistor M2 is connected to the first pull-down node PD1.
  • the first pole of the third control transistor M3 is connected to the first pull-down node PD1, the gate of the third control transistor M3 is connected to the pull-up node PU, and the second pole of the third control transistor M3 is connected to the first power supply terminal LVSS1.
  • First of the fourth control transistor M4 The pole is connected to the first node N1, the gate of the fourth control transistor M4 is connected to the pull-up node PU, and the second pole of the fourth control transistor M4 is connected to the first power terminal LVSS1.
  • the first sub-control circuit 151 and the second sub-control circuit 152 can cooperate to adjust the voltage of the first pull-down node PD1, thereby controlling the opening and closing of the first output pull-down transistor K1.
  • the shift register 100 provided by the embodiment of the present disclosure further includes a second pull-down control circuit 160.
  • the output pull-down circuit 140 further includes a second output pull-down transistor K2.
  • the first pole of the second output pull-down transistor K2 is connected to the output terminal OUTPUT
  • the control pole of the second output pull-down transistor K2 is connected to the second pull-down control circuit 160
  • the second pole of the second output pull-down transistor K2 is configured to receive the second The power supply voltage VSS2
  • the second pull-down control circuit 160 is configured to control the turning on and off of the second output pull-down transistor K2.
  • the second pole of the first output pull-down transistor K1 is connected to the second power signal terminal VDD2 to receive the second power signal V2
  • the second pole of the second output pull-down transistor K2 is connected to the first power signal terminal VDD1 to receive the second A power signal V1.
  • the first power signal V1 provided by the first power signal terminal VDD1 and the second power signal V2 provided by the second power signal terminal VDD2 are mutually inverted signals.
  • the second power signal V2 when the first power signal V1 is a high level voltage (eg, the third power voltage VH), the second power signal V2 is the second power voltage VSS2; when the first power signal V1 is the second power voltage VSS2
  • the second power supply signal V2 is a high level voltage (for example, a third power supply voltage VGH). Since the first power signal V1 provided by the first power signal terminal VDD1 and the second power signal V2 provided by the second power signal terminal VDD2 are mutually inverted signals, the first power signal V1 and the second power signal V2 are at any time. One of them is the second power supply voltage VSS2.
  • one of the first output pull-down transistor K1 and the second output pull-down transistor K2 is used to receive the second power supply voltage VSS2.
  • the second voltage terminal LVSS2 as shown in FIG. 1-6 is not separately set, and the second power voltage VSS2 may be one of the first power signal terminal VDD1 and the second power signal terminal VDD2. provide.
  • the first pull-down control circuit 150 includes a first sub-control circuit 151 and a second sub-control circuit 152; the second pull-down control circuit 160 includes The third sub-control circuit 161 and the fourth sub-control circuit 162.
  • the first sub-control circuit 151 is connected to the first power supply signal terminal VDD1, the first pull-down node PD1, and the second sub-control circuit 152, respectively.
  • the second sub-control circuit 152 is connected to the pull-up node PU, the first pull-down node PD1, and the first power supply terminal LVSS1, respectively.
  • the third sub-control circuit 161 and the second power signal end VDD2, the second pull-down node PD2, and the fourth sub-control circuit 162 are connected, respectively.
  • the fourth sub-control circuit 162 is connected to the pull-up node PU, the second pull-down node PD2, and the first power supply terminal LVSS1, respectively.
  • the third sub-control circuit 161 and the fourth sub-control circuit 162 can cooperate to adjust the voltage of the second pull-down node PD2, thereby controlling the opening and closing of the second output pull-down transistor K2.
  • the first sub-control circuit 151 includes a first control transistor M1 and a second control transistor M2; and the second sub-control circuit 152 includes a third control transistor.
  • third sub-control circuit 161 includes fifth control transistor M5 and sixth control transistor M6;
  • fourth sub-control circuit 162 includes seventh control transistor M7 and eighth control transistor M8.
  • the control electrode of the first output pull-down transistor K1 is connected to the first pull-down node PD1, and the second electrode of the first output pull-down transistor K1 is connected to the second power signal terminal VDD2 to receive the second power signal V2.
  • the first pole of the first control transistor M1 is connected to the first power signal terminal VDD1 to receive the first power signal V1
  • the gate of the first control transistor M1 is connected to the first power signal terminal VDD1 to receive the first power signal V1
  • a second pole of a control transistor M1 is coupled to the first node N1.
  • the first pole of the second control transistor M2 is connected to the first power signal terminal VDD1 to receive the first power signal V1
  • the gate of the second control transistor M2 is connected to the first node N1
  • the second pole of the second control transistor M2 is The first pulldown node PD1 is connected.
  • the first pole of the third control transistor M3 is connected to the first pull-down node PD1, the gate of the third control transistor M3 is connected to the pull-up node PU, and the second pole of the third control transistor M3 is connected to the first power terminal LVSS1.
  • the first power supply voltage VSS1 is received.
  • the first pole of the fourth control transistor M4 is connected to the first node N1, the gate of the fourth control transistor M4 is connected to the pull-up node PU, and the second pole of the fourth control transistor M4 is connected to the first power terminal LVSS1 to receive the first A power supply voltage VSS1.
  • the control electrode of the second output pull-down transistor K2 is connected to the second pull-down node PD2, and the second electrode of the second output pull-down transistor K2 is connected to the first power signal terminal VDD1 to receive the first power signal V1.
  • the first pole of the fifth control transistor M5 is connected to the second power signal terminal VDD2 to receive the second power signal V2, and the gate of the fifth control transistor M5 is connected to the second power signal terminal VDD2 to receive the second power signal V2,
  • the second pole of the five control transistor M5 is connected to the second node N2.
  • the first pole of the sixth control transistor M6 is connected to the second power signal terminal VDD2 to receive the second power signal V2, the gate of the sixth control transistor M6 is connected to the second node N2, and the second pole of the sixth control transistor M6 is The second pulldown node PD2 is connected. Seventh The first pole of the control transistor M7 is connected to the second pull-down node PD2, the control pole of the seventh control transistor M7 is connected to the pull-up node PU, and the second pole of the seventh control transistor M7 is connected to the first power supply terminal LVSS1 to receive the first Power supply voltage VSS1.
  • the first pole of the eighth control transistor M8 is connected to the second node N2, the gate of the eighth control transistor M8 is connected to the pull-up node PU, and the second pole of the eighth control transistor M8 is connected to the first power terminal LVSS1 to receive the first A power supply voltage VSS1.
  • the first power signal V1 and the second power signal V2 are mutually inverted signals.
  • the voltage supplied by the first power signal V1 is the second power voltage VSS2; and when the second power signal V2 When it is a low level signal (at this time, the first power supply signal V1 is a high level signal), the voltage supplied from the second power supply signal V2 is the second power supply voltage VSS2.
  • the shift register 100 provided by the embodiment of the present disclosure further includes a pull-up node pull-down circuit 170.
  • the pull-up node pull-down circuit 170 is connected to the pull-up node PU, the first pull-down node PD1, the second pull-down node PD2, and the first power supply terminal LVSS1, respectively.
  • the pull-up node pull-down circuit 170 includes a first pull-down transistor F1 and a second pull-down transistor F2.
  • the first pole of the first pull-down transistor F1 is connected to the pull-up node PU
  • the gate of the first pull-down transistor F1 is connected to the second pull-down node PD2
  • the second pole of the first pull-down transistor F1 is connected to the first power terminal LVSS1 Connected to receive the first power supply voltage VSS1.
  • the first pole of the second pull-down transistor F2 is connected to the pull-up node PU, the control pole of the second pull-down transistor F2 is connected to the first pull-down node PD1, and the second pole of the second pull-down transistor F2 is connected to the first power supply terminal LVSS1.
  • the first power supply voltage VSS1 is received.
  • FIG. 10 is a driving timing diagram of a shift register 100 according to an embodiment of the present disclosure. The operation of the shift register will be described below with the shift register shown in FIG. 9 and the driving timing shown in FIG.
  • the voltage of the first power signal terminal VDD1 is the third power voltage VH (the voltage supplied by the third power terminal VGH), and the voltage of the second power signal terminal VDD2 is the second power voltage. VSS2.
  • the third power supply voltage VH provided by the third power supply terminal VGH is greater than the second power supply voltage VSS2, and the second power supply voltage VSS2 is greater than the first power supply voltage VSS1.
  • the third power supply voltage VH is 22V
  • the second power supply voltage VSS2 is -8V
  • the first power supply voltage VSS1 is -11V.
  • Embodiments of the present disclosure include, but are not limited to, a third power supply voltage VH of 22V, and a second power supply voltage VSS2
  • the first power supply voltage VSS1 is -11V
  • the third power supply voltage VH, the second power supply voltage VSS2, and the first power supply voltage VSS1 may be other voltage values.
  • the third power supply voltage VH is 10V.
  • the second power supply voltage VSS2 is -5V
  • the first power supply voltage is -8V.
  • the voltage of the clock signal terminal CLK is the second power source voltage VSS2
  • the voltage of the input signal terminal INPUT is the third power source voltage VH
  • the voltage of the reset signal terminal RESET is the second power source voltage VSS2. Since the voltage of the input signal terminal INPUT is the third power supply voltage VH, the second transistor T2 is turned on, and the voltage of the pull-up node PU is the first high level voltage (the first high level voltage is equal to, for example, the third power supply voltage VH), and is stored.
  • Capacitor C is charged; the third control transistor M3 is turned on, the first power supply voltage VSS1 provided by the first power supply terminal LVSS1 is transmitted to the first pull-down node PD1, and the first output pull-down transistor K1 and the second pull-down transistor F2 are both turned off; The control transistor M7 is turned on, and the first power supply voltage VSS1 provided by the first power supply terminal LVSS1 is transmitted to the second pull-down node PD2, and the second output pull-down transistor K2 and the first pull-down transistor F1 are both turned off.
  • the voltage of the clock signal terminal CLK is the third power source voltage VH
  • the voltage of the input signal terminal INPUT is the second power source voltage VSS2
  • the voltage of the reset signal terminal RESET is the second power source voltage VSS2. Due to the bootstrap action of the storage capacitor C, when the voltage of the clock signal terminal CLK changes to the third power supply voltage VH, the storage capacitor C raises the voltage of the pull-up node PU to the second high-level voltage (the second high-level voltage)
  • the second high level voltage is higher than the first high level voltage, so that the first transistor T1 is more fully turned on, and the first transistor T1 will be at the high level of the clock signal terminal CLK.
  • the voltage is transferred to the output OUTPUT.
  • the voltage of the clock signal terminal CLK is the second power source voltage VSS2
  • the voltage of the input signal terminal INPUT is the second power source voltage VSS2
  • the voltage of the reset signal terminal RESET is the third power source voltage VH. Since the voltage of the reset signal terminal RESET is the third power source voltage VH, the third transistor T3 is turned on, and the first power source voltage VSS1 provided by the first power source terminal LVSS1 is transmitted to the pull-up node PU; the third control transistor M3 and the seventh control transistor are turned on.
  • the second control transistor M2 transmits the third power voltage VH provided by the first power signal terminal VDD1 to the first pull-down node PD1; the second pull-down transistor F2 is turned on, and transmits the first power voltage VSS1 to the pull-up node PU
  • the first output pull-down transistor K1 is turned on, and the second power supply voltage VSS2 supplied from the second power supply signal terminal VDD2 is transmitted to the output terminal OUTPUT.
  • the voltage of the input signal terminal INPUT is the second power supply voltage VSS2
  • the voltage of the reset signal terminal RESET is the second power supply voltage VSS2.
  • Pull-up node PU, first pulldown The node PD1, the second pulldown node PD2, and the output terminal OUTPUT maintain the same state as the third phase t3.
  • the gate voltage of the first transistor T1 is the first power supply voltage VSS1 (for example, -11V), and the drain voltage of the first transistor T1 is the second power supply voltage VSS2 (for example - 8V).
  • the channel is less likely to form an inductive channel, causing the first transistor T1 to be in a pinch-off state, thereby reducing the risk of failure due to drift of the threshold voltage Vth of the first transistor T1, increasing the design redundancy of the first transistor threshold voltage drift.
  • the gate drain voltage of the first transistor T1 is not limited to -3V, and the value of the gate drain voltage can be flexibly selected according to the specific design of the circuit.
  • the voltage of the first power signal terminal VDD1 and the voltage of the second power signal terminal VDD2 may be mutually converted in a stage in which one frame display screen alternates with another frame display screen.
  • the voltage of the converted first power signal terminal VDD1 is the second power voltage VSS2
  • the voltage of the second power signal terminal VDD2 is the third power voltage VH.
  • the voltage of the first power signal terminal VDD1 and the voltage of the second power signal terminal VDD2 may be mutually converted at a certain time in the fourth phase.
  • the functions of the first pull-up node PD1 and the second pull-down node PD2 are interchanged.
  • the functions of the first pull-down control circuit 150 and the second pull-down control circuit 160 are interchanged, and the functions of the first output pull-down transistor K1 and the second output pull-down transistor K2 are interchanged, and the first pull-down transistor F1 and the second pull-down transistor F2 Functional interchange.
  • the operation of the shift register is similar to the case where the voltage of the first power supply signal terminal VDD1 is the third power supply voltage VH and the voltage of the second power supply signal terminal VDD2 is the second power supply voltage VSS2, and details are not described herein again.
  • the first pull-down control circuit 150 and the second pull-down control circuit 160 may control the first pull-down node PD1 and the second pull-down node PD2 to operate, respectively, such that the first output pull-down transistor K1 and the second output pull-down transistor K2 may be divided.
  • the first pull-down transistor F1 and the second pull-down transistor F2 work in a time-sharing manner, which reduces the possibility that the transistor is turned on for a long time, thereby improving the anti-interference ability of the shift register, thereby improving the shift register. Reliability.
  • the voltage of the first power signal terminal VDD1 and the power of the second power signal terminal VDD2 The voltage is a reverse signal, and the second power voltage VSS2 provided by the first power signal terminal VDD1 and the second power signal terminal VDD2 is time-divisionally transmitted to the output terminal, so that the second power voltage VSS2 of the output terminal and the pull-up node are
  • the first supply voltage VSS1 is separated such that there is a certain voltage difference between the gate and the second electrode of the first transistor, thereby increasing the design redundancy of the first transistor threshold voltage drift.
  • Embodiments of the present disclosure also provide a gate drive circuit 10. As shown in FIG. 11, the gate drive circuit 10 includes the shift register 100 provided by any of the embodiments of the present disclosure.
  • the gate driving circuit 10 provided by the embodiment of the present disclosure includes a plurality of cascaded shift registers 100 provided by any one of the embodiments of the present disclosure, except for the first stage and the last stage shift register.
  • the input signal terminal INPUT of the shift register 100 of the present stage is connected to the output terminal OUTPUT of the shift register 100 of the previous stage; the reset signal terminal RESET of the shift register 100 of the present stage and the output of the shift register 100 of the next stage. End OUTPUT connection.
  • the input signal terminal INPUT of the first stage shift register is connected to the first trigger signal terminal STV1; the reset signal terminal RESET of the last stage shift register is connected to the second trigger signal terminal STV2.
  • the first trigger signal terminal STV1 provides an input signal for the first stage shift register
  • the second trigger signal STV2 terminal provides a reset signal for the last stage shift register.
  • the second trigger signal terminal STV2 provides an input signal for the last stage shift register
  • the first trigger signal terminal STV1 provides a reset signal for the first stage shift register.
  • the input circuit of the shift register is interchanged with the function of the reset circuit.
  • the gate driving circuit 10 includes n stages of shift registers SR1, SR2, ..., SRn, and these shift registers SR1, SR2, ..., SRn may each be a shift register provided by any of the embodiments of the present disclosure. 100.
  • the output terminals OUTPUT of the shift registers SR1, SR2, ..., SRn are connected to the gate lines G1, G2, ..., Gn, respectively.
  • the gate driving circuit 10 provided by the embodiment of the present disclosure can implement forward scanning and reverse scanning, when the scanning direction is switched, the “upper level” and “next level” in the timing are changed accordingly. Therefore, the above-mentioned “upper level” and “lower level” do not refer to the upper level and the lower level in the scanning timing, but refer to the upper level and the lower level on the physical connection.
  • An embodiment of the present disclosure also provides a display panel 1. As shown in FIG. 12, the display panel 1 includes The gate drive circuit 10 provided by any of the embodiments of the present disclosure.
  • the display panel 1 provided by the embodiment of the present disclosure further includes a gate line 11, a data line 12, and a plurality of pixel units 13 defined by the intersection of the gate line 11 and the data line 12, and the gate driving circuit 10 is It is configured to provide a gate drive signal to the gate line 11.
  • the gate line 11 may include the gate lines G1, G2, ..., Gn shown in FIG. 11, and each of the shift registers SR1, SR2, ..., SRn is used for the corresponding gate lines G1, G2, ..., Gn A row of gate drive signals is output.
  • the embodiment of the present disclosure further provides a driving method of the shift register 100 according to any embodiment of the present disclosure. As shown in FIG. 13, the driving method includes the following steps:
  • Step S10 writing the first power voltage VSS1 to the pull-up node PU;
  • Step S20 The second power supply voltage VSS2 is written to the output terminal OUTPUT, and the first power supply voltage VSS1 is different from the second power supply voltage VSS2.
  • the first power supply voltage VSS1 is smaller than the second power supply voltage VSS2.
  • the first power supply voltage VSS1 is greater than the second power supply voltage VSS2.
  • the shift register, the gate driving circuit, the display panel, and the driving method provided by the embodiments of the present disclosure can improve the stability of the circuit.

Abstract

一种移位寄存器(100)、栅极驱动电路(10)、显示面板(1)及驱动方法。该移位寄存器(100)包括：输入电路(110)，与上拉节点(PU)和输入信号端(INPUT)分别连接；复位电路(120)，与所述上拉节点(PU)、复位信号端(RESET)及第一电源端(LVSS1)分别连接以接收第一电源电压(VSS1)；输出电路(130)，与所述上拉节点(PU)、时钟信号端(CLK)及输出端(OUTPUT)分别连接；以及输出下拉电路(140)，与所述输出端(OUTPUT)连接，被配置为将第二电源电压(VSS2)写入所述输出端(OUTPUT)，其中，所述第一电源电压(VSS1)与所述第二电源电压(VSS2)不同。

Description

移位寄存器、栅极驱动电路、显示面板及驱动方法 技术领域
本公开的实施例涉及一种移位寄存器、栅极驱动电路、显示面板及驱动方法。
背景技术
随着显示技术的飞速发展，显示面板越来越向着高集成度和低成本的方向发展。栅极驱动电路基板(Gate-driver on Array，GOA)技术是通过光刻工艺将栅极驱动电路直接集成在显示装置的阵列基板上，GOA电路通常包括多个级联的移位寄存器，每个移位寄存器均与对应于一行或一列像素的栅线连接(例如，每个移位寄存器给一条栅线提供扫描驱动信号)，以实现对显示面板的扫描驱动。这种集成技术可以节省栅极集成电路(Integrated Circuit，IC)的绑定(Bonding)区域以及扇出(Fan-out)区域的空间，从而实现显示面板的窄边框，同时可以降低产品成本、提高产品的良率。
GOA的可靠性直接影响到显示面板的可靠性，因此，如何提高GOA的可靠性也成为研究的重点之一。
发明内容
本公开的实施例提供一种移位寄存器，包括：输入电路，与上拉节点和输入信号端分别连接；复位电路，与所述上拉节点、复位信号端及第一电源端分别连接以接收第一电源电压；输出电路，与所述上拉节点、时钟信号端及输出端分别连接；以及输出下拉电路，与所述输出端连接，被配置为将第二电源电压写入所述输出端，其中，所述第一电源电压与所述第二电源电压不同。
例如，在本公开实施例提供的移位寄存器中，所述输出电路包括存储电容和第一晶体管，所述第一晶体管的第一极与时钟信号端连接，所述第一晶体管的控制极与所述上拉节点连接，所述第一晶体管的第二极与所述输出端连接，所述存储电容的第一端与所述上拉节点连接，所述存储电容的第二端 与所述输出端连接。
例如，在本公开实施例提供的移位寄存器中，所述输入电路包括第二晶体管，所述第二晶体管的第一极与所述输入信号端连接，所述第二晶体管的控制极与所述输入信号端连接，所述第二晶体管的第二极与所述上拉节点连接；所述复位电路包括第三晶体管，所述第三晶体管的第一极与所述上拉节点连接，所述第三晶体管的控制极与所述复位信号端连接，所述第三晶体管的第二极与所述第一电源端连接。
例如，在本公开实施例提供的移位寄存器中，所述输出下拉电路包括第一输出下拉晶体管，所述第一输出下拉晶体管的第一极与所述输出端连接，所述第一输出下拉晶体管的控制极与所述复位信号端连接，所述第一输出下拉晶体管的第二极与第二电源端连接以接收第二电源电压。
例如，本公开实施例提供的移位寄存器，还包括第一下拉控制电路，其中，所述输出下拉电路包括第一输出下拉晶体管，所述第一输出下拉晶体管的第一极与所述输出端连接，所述第一输出下拉晶体管的控制极与所述第一下拉控制电路连接，所述第一输出下拉晶体管的第二极被配置为接收所述第二电源电压；所述第一下拉控制电路被配置为控制所述第一输出下拉晶体管的开启和关闭。
例如，在本公开实施例提供的移位寄存器中，所述第一下拉控制电路包括第一子控制电路和第二子控制电路，所述第一子控制电路与第三电源端、第一下拉节点以及所述第二子控制电路分别连接，所述第二子控制电路与所述上拉节点、所述第一下拉节点以及所述第一电源端分别连接。
例如，在本公开实施例提供的移位寄存器中，所述第一子控制电路包括第一控制晶体管和第二控制晶体管，所述第二子控制电路包括第三控制晶体管和第四控制晶体管，所述第一输出下拉晶体管的控制极与所述第一下拉节点连接；所述第一控制晶体管的第一极与所述第三电源端连接，所述第一控制晶体管的控制极与所述第三电源端连接，所述第一控制晶体管的第二极与第一节点连接；所述第二控制晶体管的第一极与所述第三电源端连接，所述第二控制晶体管的控制极与所述第一节点连接，所述第二控制晶体管的第二极与所述第一下拉节点连接；所述第三控制晶体管的第一极与所述第一下拉节点连接，所述第三控制晶体管的控制极与所述上拉节点连接，所述第三控 制晶体管的第二极与所述第一电源端连接；所述第四控制晶体管的第一极与所述第一节点连接，所述第四控制晶体管的控制极与所述上拉节点连接，所述第四控制晶体管的第二极与所述第一电源端连接。
例如，本公开实施例提供的移位寄存器，还包括第二下拉控制电路，其中，所述输出下拉电路还包括第二输出下拉晶体管，所述第二输出下拉晶体管的第一极与所述输出端连接，所述第二输出下拉晶体管的控制极与所述第二下拉控制电路连接，所述第二输出下拉晶体管的第二极被配置为接收所述第二电源电压；所述第二下拉控制电路被配置为控制所述第二输出下拉晶体管的开启和关闭。
例如，在本公开实施例提供的移位寄存器中，所述第一下拉控制电路包括第一子控制电路和第二子控制电路，所述第二下拉控制电路包括第三子控制电路和第四子控制电路，所述第一子控制电路与第一电源信号端、第一下拉节点以及所述第二子控制电路分别连接，所述第二子控制电路与所述上拉节点、所述第一下拉节点以及所述第一电源端分别连接，所述第三子控制电路与第二电源信号端、第二下拉节点以及所述第四子控制电路分别连接，所述第四子控制电路与所述上拉节点、所述第二下拉节点以及所述第一电源端分别连接。
例如，在本公开实施例提供的移位寄存器中，所述第一子控制电路包括第一控制晶体管和第二控制晶体管，所述第二子控制电路包括第三控制晶体管和第四控制晶体管，所述第三子控制电路包括第五控制晶体管和第六控制晶体管，所述第四子控制电路包括第七控制晶体管和第八控制晶体管，所述第一输出下拉晶体管的控制极与所述第一下拉节点连接，所述第一输出下拉晶体管的第二极与所述第二电源信号端连接以接收第二电源信号；所述第一控制晶体管的第一极与第一电源信号端连接以接收第一电源信号，所述第一控制晶体管的控制极与所述第一电源信号端连接以接收所述第一电源信号，所述第一控制晶体管的第二极与第一节点连接；所述第二控制晶体管的第一极与所述第一电源信号端连接以接收所述第一电源信号，所述第二控制晶体管的控制极与所述第一节点连接，所述第二控制晶体管的第二极与第一下拉节点连接；所述第三控制晶体管的第一极与所述第一下拉节点连接，所述第三控制晶体管的控制极与所述上拉节点连接，所述第三控制晶体管的第二极 与第一电源端连接以接收所述第一电源电压；所述第四控制晶体管的第一极与所述第一节点连接，所述第四控制晶体管的控制极与所述上拉节点连接，所述第四控制晶体管的第二极与所述第一电源端连接以接收所述第一电源电压；所述第二输出下拉晶体管的控制极与所述第二下拉节点连接，所述第二输出下拉晶体管的第二极与所述第一电源信号端连接以接收所述第一电源信号；所述第五控制晶体管的第一极与所述第二电源信号端连接以接收所述第二电源信号，所述第五控制晶体管的控制极与所述第二电源信号端连接以接收所述第二电源信号，所述第五控制晶体管的第二极与第二节点连接；所述第六控制晶体管的第一极与所述第二电源信号端连接以接收所述第二电源信号，所述第六控制晶体管的控制极与所述第二节点连接，所述第六控制晶体管的第二极与第二下拉节点连接；所述第七控制晶体管的第一极与所述第二下拉节点连接，所述第七控制晶体管的控制极与所述上拉节点连接，所述第七控制晶体管的第二极与第一电源端连接以接收所述第一电源电压；所述第八控制晶体管的第一极与所述第二节点连接，所述第八控制晶体管的控制极与所述上拉节点连接，所述第八控制晶体管的第二极与所述第一电源端连接以接收所述第一电源电压；所述第一电源信号与所述第二电源信号互为反向信号，所述第一电源信号和所述第二电源信号为低电平信号时的电压均为所述第二电源电压。
例如，本公开实施例提供的移位寄存器，还包括上拉节点下拉电路，与所述上拉节点、所述第一下拉节点、所述第二下拉节点及所述第一电源端分别连接。
例如，在本公开实施例提供的移位寄存器中，所述上拉节点下拉电路包括第一下拉晶体管和第二下拉晶体管，所述第一下拉晶体管的第一极与所述上拉节点连接，所述第一下拉晶体管的控制极与所述第二下拉节点连接，所述第一下拉晶体管的第二极与所述第一电源端连接以接收所述第一电源电压；所述第二下拉晶体管的第一极与所述上拉节点连接，所述第二下拉晶体管的控制极与所述第一下拉节点连接，所述第二下拉晶体管的第二极与所述第一电源端连接以接收所述第一电源电压。
本公开的实施例还提供一种栅极驱动电路，包括本公开任一实施例提供的移位寄存器。
例如，本公开实施例提供的栅极驱动电路，包括级联的多个本公开任一实施例提供的移位寄存器，其中，除第一级和最后一级移位寄存器之外，本级移位寄存器的输入信号端与上一级移位寄存器的输出端连接；本级移位寄存器的复位信号端与下一级移位寄存器的输出端连接。
本公开的实施例还提供一种显示面板，包括本公开任一实施例提供的栅极驱动电路。
本公开的实施例还提供一种本公开任一实施例提供的移位寄存器的驱动方法，包括：将所述第一电源电压写入所述上拉节点；以及将所述第二电源电压写入所述输出端，其中，所述第一电源电压与所述第二电源电压不同。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，并非对本公开的限制。
图1是本公开实施例提供的一种移位寄存器的示意图之一；
图2是本公开实施例提供的一种移位寄存器的示意图之二；
图3是本公开实施例提供的一种移位寄存器的示意图之三；
图4是本公开实施例提供的一种移位寄存器的示意图之四；
图5是本公开实施例提供的一种移位寄存器的示意图之五；
图6是本公开实施例提供的一种移位寄存器的示意图之六；
图7是本公开实施例提供的一种移位寄存器的示意图之七；
图8是本公开实施例提供的一种移位寄存器的示意图之八；
图9是本公开实施例提供的一种移位寄存器的示意图之九；
图10是本公开实施例提供的一种移位寄存器的驱动时序图；
图11是本公开实施例提供的一种栅极驱动电路的示意图；
图12是本公开实施例提供的一种显示面板的示意图；以及
图13是本公开实施例提供的一种移位寄存器的驱动方法的流程图。
具体实施方式
下面将结合附图，对本公开实施例中的技术方案进行清楚、完整地描述 参考在附图中示出并在以下描述中详述的非限制性示例实施例，更加全面地说明本公开的示例实施例和它们的多种特征及有利细节。应注意的是，图中示出的特征不是必须按照比例绘制。本公开省略了已知材料、组件和工艺技术的描述，从而不使本公开的示例实施例模糊。所给出的示例仅旨在有利于理解本公开示例实施例的实施，以及进一步使本领域技术人员能够实施示例实施例。因而，这些示例不应被理解为对本公开的实施例的范围的限制。
除非另外特别定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。此外，在本公开各个实施例中，相同或类似的参考标号表示相同或类似的构件。
本公开的实施例提供一种移位寄存器100。如图1所示，该移位寄存器100包括输入电路110、复位电路120、输出电路130和输出下拉电路140。输入电路110与上拉节点PU和输入信号端INPUT分别连接；复位电路120与上拉节点PU、复位信号端RESET及第一电源端LVSS1分别连接，第一电源端LVSS1被配置为提供第一电源电压VSS1；输出电路130与上拉节点PU、时钟信号端CLK及输出端OUTPUT分别连接；输出下拉电路140与输出端OUTPUT连接，输出下拉电路140被配置为将第二电源电压VSS2写入输出端OUTPUT。第一电源电压VSS1与第二电源电压VSS2不同。
例如，如图2所示，在本公开实施例提供的移位寄存器100中，输出电路130包括存储电容C和第一晶体管T1。第一晶体管T1的第一极与时钟信号端CLK连接，第一晶体管T1的控制极与上拉节点PU连接，第一晶体管T1的第二极与输出端OUTPUT连接。存储电容C的第一端与上拉节点PU连接，存储电容C的第二端与输出端OUTPUT连接。
例如，本公开实施例中所述的晶体管的控制极为晶体管的栅极。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极，所以本公开实施例中全部或部分晶体管的第 一极和第二极根据需要是可以互换的。例如，本公开实施例所述的晶体管的第一极可以为源极，第二极可以为漏极；或者，晶体管的第一极为漏极，第二极为源极。此外，按照晶体管的特性区分可以将晶体管分为N型和P型晶体管。当晶体管为P型晶体管时，开启电压为低电平电压(例如，0V、-5V或其他数值)，关闭电压为高电平电压(例如，5V、10V或其他数值)；当晶体管为N型晶体管时，开启电压为高电平电压(例如，5V、10V或其他数值)，关闭电压为低电平电压(例如，0V、-5V或其他数值)。
例如，当所述第一晶体管T1为N型晶体管时，第一电源电压VSS1小于第二电源电压VSS2。又例如，当所述第一晶体管T1为N型晶体管时，第一电源电压VSS1为-11V，第二电源电压VSS2为-8V。本公开的实施例包括但不局限于此，第一电源电压VSS1和第二电源电压VSS2也可以为其它电压值，只要第一电源电压VSS1小于第二电源电压VSS2即可。
例如，当所述第一晶体管T1为P型晶体管时，第一电源电压VSS1大于第二电源电压VSS2。又例如，当所述第一晶体管T1为P型晶体管时，第一电源电压VSS1为-8V，第二电源电压VSS2为-11V。本公开的实施例包括但不局限于此，第一电源电压VSS1和第二电源电压VSS2也可以为其它电压值，只要第一电源电压VSS1大于第二电源电压VSS2即可。
在一些情况下，当第一晶体管T1的阈值电压偏移至小于等于0V时，第一晶体管T1的沟道在其栅极电压和源极电压的作用下可能打开。也就是说，第一晶体管T1阈值电压的漂移可能导致其在不该导通时导通，进而导致移位寄存器电路出现多输出现象。本公开的实施例提供的移位寄存器通过在第一晶体管的栅极和第二极分别施加不同的电压，降低由于第一晶体管阈值电压漂移导致移位寄存器失效的风险，增大第一晶体管阈值电压漂移的设计冗余度。
需要说明的是，本公开的实施例以各个晶体管均为N型晶体管为例进行说明，也就是说，本公开的实施例以第一电源电压VSS1小于第二电源电压VSS2为例进行说明。基于本公开对该实现方式的描述和教导，本领域普通技术人员在没有做出创造性劳动前提下能够容易想到本公开实施例采用P型晶体管或N型和P型晶体管组合的实现方式，因此，这些实现方式也是在本公开的保护范围内的。
例如，当第一晶体管T1为N型晶体管时：当其栅源电压Vgs(即栅极和源极电压之差)小于阈值电压Vth时，第一晶体管T1关闭；当第一晶体管T1栅源电压Vgs大于阈值电压Vth时，第一晶体管T1导通。考虑到第一晶体管T1的栅漏电压Vgd(即栅极和漏极之间的电压差)在第一晶体管T1工作过程中影响漏极一侧沟道的形成，当栅漏电压Vgd小于阈值电压Vth时，在漏极一侧的沟道消失，第一晶体管进入夹止区。
例如，本公开实施例中第一晶体管T1的第一极(例如源极)与时钟信号端CLK连接，第一晶体管T1的控制极(例如栅极)与上拉节点PU连接，第一晶体管T1的第二极(例如漏极)与输出端OUTPUT连接。因此，在电压保持阶段(例如图10所示的第四阶段t4)，第一晶体管T1的栅极电压为第一电源电压VSS1(例如-11V)，第一晶体管T1的漏极电压为第二电源电压VSS2(例如-8V)。此时，第一晶体管T1的栅漏电压Vgd＝-3V，相比于栅漏电压相同(即Vgd＝0V)的情形，第一晶体管T1的漏极一侧的沟道更不易形成感应通道，使第一晶体管T1处于夹断状态，从而降低由于第一晶体管T1的阈值电压Vth漂移造成失效的风险，增大第一晶体管阈值电压漂移的设计冗余度。
例如，如图3所示，在本公开实施例提供的移位寄存器100中，输入电路110包括第二晶体管T2。第二晶体管T2的第一极与输入信号端INPUT连接，第二晶体管T2的控制极与输入信号端INPUT连接，第二晶体管T2的第二极与上拉节点PU连接。
例如，如图3所示，复位电路120包括第三晶体管T3。第三晶体管T3的第一极与上拉节点PU连接，第三晶体管T3的控制极与复位信号端RESET连接，第三晶体管T3的第二极与第一电源端LVSS1连接以接收第一电源电压VSS1。例如，当第三晶体管T3导通时，第一电源端LVSS1的第一电源电压VSS1被传输至上拉节点PU。
需要说明的是，图3所示的输入电路110和复位电路120仅为本公开实施例的一个示例，本公开的实施例包括但不局限于图3所示的情形。
例如，如图4所示，在本公开实施例提供的移位寄存器100中，输出下拉电路140包括第一输出下拉晶体管K1。第一输出下拉晶体管K1的第一极与输出端OUTPUT连接，第一输出下拉晶体管K1的控制极与复位信号端 RESET连接，第一输出下拉晶体管K1的第二极与第二电源端LVSS2连接以接收第二电源电压VSS2。在图4的实施方式中，复位信号端RESET的信号控制第一输出下拉晶体管K1的开启和关闭。
例如，如图5所示，本公开实施例提供的移位寄存器100，还包括第一下拉控制电路150。第一输出下拉晶体管K1的第一极与输出端OUTPUT连接，第一输出下拉晶体管K1的控制极与第一下拉控制电路150连接，第一输出下拉晶体管K1的第二极被配置为接收第二电源电压VSS2。第一下拉控制电路150被配置为控制第一输出下拉晶体管K1的开启和关闭。又例如，第一输出下拉晶体管K1的第二极与第二电源端LVSS2连接以接收第二电源电压VSS2；第一下拉控制电路150与分别与第三电源端VGH、上拉节点PU、第一电源端LVSS1及第一输出下拉晶体管K1的控制极(例如，栅极)连接。
例如，第三电源端VGH被配置为提供第三电源电压VH，第三电源电压VH例如为能使N型晶体管开启的电压(例如，5V，10V，22V等)。第三电源电压VH大于第一电源电压VSS1，第三电源电压VH大于第二电源电压VSS2。
例如，如图6所示，在本公开实施例提供的移位寄存器100中，第一下拉控制电路150包括第一子控制电路151和第二子控制电路152。第一子控制电路151与第三电源端VGH、第一下拉节点PD1以及第二子控制电路152分别连接；第二子控制电路152与上拉节点PU、第一下拉节点PD1以及第一电源端LVSS1分别连接。
例如，继续参见图6，第一子控制电路151包括第一控制晶体管M1和第二控制晶体管M2；第二子控制电路152包括第三控制晶体管M3和第四控制晶体管M4。第一输出下拉晶体管K1的控制极与第一下拉节点PD1连接。第一控制晶体管M1的第一极与第三电源端VGH连接，第一控制晶体管M1的控制极与第三电源端VGH连接，第一控制晶体管M1的第二极与第一节点N1连接。第二控制晶体管M2的第一极与第三电源端VGH连接，第二控制晶体管M2的控制极与第一节点N1连接，第二控制晶体管M2的第二极与第一下拉节点PD1连接。第三控制晶体管M3的第一极与第一下拉节点PD1连接，第三控制晶体管M3的控制极与上拉节点PU连接，第三控制晶体管M3的第二极与第一电源端LVSS1连接。第四控制晶体管M4的第一 极与第一节点N1连接，第四控制晶体管M4的控制极与上拉节点PU连接，第四控制晶体管M4的第二极与第一电源端LVSS1连接。
例如，第一子控制电路151和第二子控制电路152可以配合工作以调节第一下拉节点PD1的电压，进而控制第一输出下拉晶体管K1的开启和关闭。
例如，如图7所示，本公开实施例提供的移位寄存器100，还包括第二下拉控制电路160。除了第一输出下拉晶体管K1，输出下拉电路140还包括第二输出下拉晶体管K2。第二输出下拉晶体管K2的第一极与输出端OUTPUT连接，第二输出下拉晶体管K2的控制极与第二下拉控制电路160连接，第二输出下拉晶体管K2的第二极被配置为接收第二电源电压VSS2；第二下拉控制电路160被配置为控制第二输出下拉晶体管K2的开启和关闭。又例如，第一输出下拉晶体管K1的第二极与第二电源信号端VDD2连接以接收第二电源信号V2，第二输出下拉晶体管K2的第二极与第一电源信号端VDD1连接以接收第一电源信号V1。例如，第一电源信号端VDD1提供的第一电源信号V1和第二电源信号端VDD2提供的第二电源信号V2互为反向信号。也就是说，当第一电源信号V1为高电平电压(例如第三电源电压VH)时，第二电源信号V2为第二电源电压VSS2；当第一电源信号V1为第二电源电压VSS2时，第二电源信号V2为高电平电压(例如第三电源电压VGH)。由于第一电源信号端VDD1提供的第一电源信号V1和第二电源信号端VDD2提供的第二电源信号V2互为反向信号，在任意时刻，第一电源信号V1和第二电源信号V2中的一个为第二电源电压VSS2。因此，在任意时刻，第一输出下拉晶体管K1和第二输出下拉晶体管K2中的一个用于接收第二电源电压VSS2。例如，在图7-9中，不再单独设置如图1-6所示的第二电压端LVSS2，第二电源电压VSS2可以由第一电源信号端VDD1和第二电源信号端VDD2之一来提供。
例如，如图8所示，在本公开实施例提供的移位寄存器100中，第一下拉控制电路150包括第一子控制电路151和第二子控制电路152；第二下拉控制电路160包括第三子控制电路161和第四子控制电路162。第一子控制电路151与第一电源信号端VDD1、第一下拉节点PD1以及第二子控制电路152分别连接。第二子控制电路152与上拉节点PU、第一下拉节点PD1以及第一电源端LVSS1分别连接。第三子控制电路161与第二电源信号端 VDD2、第二下拉节点PD2以及第四子控制电路162分别连接。第四子控制电路162与上拉节点PU、第二下拉节点PD2以及第一电源端LVSS1分别连接。
例如，第三子控制电路161和第四子控制电路162可以配合工作以调节第二下拉节点PD2的电压，进而控制第二输出下拉晶体管K2的开启和关闭。
例如，继续参见图8，在本公开实施例提供的移位寄存器100中，第一子控制电路151包括第一控制晶体管M1和第二控制晶体管M2；第二子控制电路152包括第三控制晶体管M3和第四控制晶体管M4；第三子控制电路161包括第五控制晶体管M5和第六控制晶体管M6；第四子控制电路162包括第七控制晶体管M7和第八控制晶体管M8。第一输出下拉晶体管K1的控制极与第一下拉节点PD1连接，第一输出下拉晶体管K1的第二极与第二电源信号端VDD2连接以接收第二电源信号V2。第一控制晶体管M1的第一极与第一电源信号端VDD1连接以接收第一电源信号V1，第一控制晶体管M1的控制极与第一电源信号端VDD1连接以接收第一电源信号V1，第一控制晶体管M1的第二极与第一节点N1连接。第二控制晶体管M2的第一极与第一电源信号端VDD1连接以接收第一电源信号V1，第二控制晶体管M2的控制极与第一节点N1连接，第二控制晶体管M2的第二极与第一下拉节点PD1连接。第三控制晶体管M3的第一极与第一下拉节点PD1连接，第三控制晶体管M3的控制极与上拉节点PU连接，第三控制晶体管M3的第二极与第一电源端LVSS1连接以接收第一电源电压VSS1。第四控制晶体管M4的第一极与第一节点N1连接，第四控制晶体管M4的控制极与上拉节点PU连接，第四控制晶体管M4的第二极与第一电源端LVSS1连接以接收第一电源电压VSS1。第二输出下拉晶体管K2的控制极与第二下拉节点PD2连接，第二输出下拉晶体管K2的第二极与第一电源信号端VDD1连接以接收第一电源信号V1。第五控制晶体管M5的第一极与第二电源信号端VDD2连接以接收第二电源信号V2，第五控制晶体管M5的控制极与第二电源信号端VDD2连接以接收第二电源信号V2，第五控制晶体管M5的第二极与第二节点N2连接。第六控制晶体管M6的第一极与第二电源信号端VDD2连接以接收第二电源信号V2，第六控制晶体管M6的控制极与第二节点N2连接，第六控制晶体管M6的第二极与第二下拉节点PD2连接。第七 控制晶体管M7的第一极与第二下拉节点PD2连接，第七控制晶体管M7的控制极与上拉节点PU连接，第七控制晶体管M7的第二极与第一电源端LVSS1连接以接收第一电源电压VSS1。第八控制晶体管M8的第一极与第二节点N2连接，第八控制晶体管M8的控制极与上拉节点PU连接，第八控制晶体管M8的第二极与第一电源端LVSS1连接以接收第一电源电压VSS1。第一电源信号V1与第二电源信号V2互为反向信号。当第一电源信号V1为低电平信号时(此时，第二电源信号V2为高电平信号)，第一电源信号V1提供的电压为第二电源电压VSS2；而当第二电源信号V2为低电平信号时(此时，第一电源信号V1为高电平信号)，第二电源信号V2提供的电压为第二电源电压VSS2。
例如，如图9所示，本公开实施例提供的移位寄存器100还包括上拉节点下拉电路170。上拉节点下拉电路170与上拉节点PU、第一下拉节点PD1、第二下拉节点PD2及第一电源端LVSS1分别连接。
例如，如图9所示，在本公开实施例提供的移位寄存器100中，上拉节点下拉电路170包括第一下拉晶体管F1和第二下拉晶体管F2。第一下拉晶体管F1的第一极与上拉节点PU连接，第一下拉晶体管F1的控制极与第二下拉节点PD2连接，第一下拉晶体管F1的第二极与第一电源端LVSS1连接以接收第一电源电压VSS1。第二下拉晶体管F2的第一极与上拉节点PU连接，第二下拉晶体管F2的控制极与第一下拉节点PD1连接，第二下拉晶体管F2的第二极与第一电源端LVSS1连接以接收第一电源电压VSS1。
例如，图10是本公开实施例提供的一种移位寄存器100的驱动时序图，下面以图9所示的移位寄存器和图10所示的驱动时序介绍移位寄存器的工作过程。
例如，在图10所示的驱动时序中，第一电源信号端VDD1的电压为第三电源电压VH(第三电源端VGH提供的电压)，第二电源信号端VDD2的电压为第二电源电压VSS2。
例如，第三电源端VGH提供的第三电源电压VH大于第二电源电压VSS2，第二电源电压VSS2大于第一电源电压VSS1。又例如，第三电源电压VH为22V，第二电源电压VSS2为-8V，第一电源电压VSS1为-11V。本公开的实施例包括但不局限于第三电源电压VH为22V，第二电源电压VSS2 为-8V，第一电源电压VSS1为-11V的情形，第三电源电压VH、第二电源电压VSS2和第一电源电压VSS1也可以为其它电压值，例如，第三电源电压VH为10V，第二电源电压VSS2为-5V，第一电源电压为-8V。
例如，在第一阶段t1，时钟信号端CLK的电压为第二电源电压VSS2，输入信号端INPUT的电压为第三电源电压VH，复位信号端RESET的电压为第二电源电压VSS2。由于输入信号端INPUT的电压为第三电源电压VH，第二晶体管T2开启，上拉节点PU的电压为第一高电平电压(第一高电平电压例如等于第三电源电压VH)，存储电容C充电；第三控制晶体管M3开启，将第一电源端LVSS1提供的第一电源电压VSS1传输到第一下拉节点PD1，第一输出下拉晶体管K1和第二下拉晶体管F2均关闭；第七控制晶体管M7开启，将第一电源端LVSS1提供的第一电源电压VSS1传输到第二下拉节点PD2，第二输出下拉晶体管K2和第一下拉晶体管F1均关闭。
例如，在第二阶段t2，时钟信号端CLK的电压为第三电源电压VH，输入信号端INPUT的电压为第二电源电压VSS2，复位信号端RESET的电压为第二电源电压VSS2。由于存储电容C的自举作用，时钟信号端CLK的电压变化为第三电源电压VH时，存储电容C将上拉节点PU的电压举升至第二高电平电压(第二高电平电压例如等于两倍的第三电源电压VH)，第二高电平电压高于第一高电平电压，使得第一晶体管T1更充分地开启，第一晶体管T1将时钟信号端CLK的高电平电压传输到输出端OUTPUT。
例如，在第三阶段t3，时钟信号端CLK的电压为第二电源电压VSS2，输入信号端INPUT的电压为第二电源电压VSS2，复位信号端RESET的电压为第三电源电压VH。由于复位信号端RESET的电压为第三电源电压VH，第三晶体管T3开启，将第一电源端LVSS1提供的第一电源电压VSS1传输到上拉节点PU；第三控制晶体管M3和第七控制晶体管M7关闭，第二控制晶体管M2将第一电源信号端VDD1提供的第三电源电压VH传输到第一下拉节点PD1；第二下拉晶体管F2开启，将第一电源电压VSS1传输到上拉节点PU；第一输出下拉晶体管K1开启，将第二电源信号端VDD2提供的第二电源电压VSS2传输到输出端OUTPUT。
例如，在第四阶段t4，输入信号端INPUT的电压为第二电源电压VSS2，复位信号端RESET的电压为第二电源电压VSS2。上拉节点PU、第一下拉 节点PD1、第二下拉节点PD2和输出端OUTPUT保持和第三阶段t3相同的状态。
例如，在第三阶段t3和第四阶段t4，第一晶体管T1的栅极电压为第一电源电压VSS1(例如-11V)，第一晶体管T1的漏极电压为第二电源电压VSS2(例如-8V)。此时，第一晶体管T1的栅漏电压Vgd＝VSS1-VSS2(例如，Vgd＝-3V)，相比于栅漏电压相同(即Vgd＝0V)的情形，第一晶体管T1的漏极一侧的沟道更不易形成感应通道，使第一晶体管T1处于夹断状态，从而降低由于第一晶体管T1的阈值电压Vth漂移造成失效的风险，增大第一晶体管阈值电压漂移的设计冗余度。
需要说明的是，第一晶体管T1的栅漏电压并不局限于-3V的情形，根据电路的具体设计，可以灵活选择栅漏电压的值。
例如，第一电源信号端VDD1的电压和第二电源信号端VDD2的电压可以在一帧显示画面向另一帧显示画面交替的阶段相互转换。例如，转换后的第一电源信号端VDD1的电压为第二电源电压VSS2，第二电源信号端VDD2的电压为第三电源电压VH。又例如，如图10所示，第一电源信号端VDD1的电压和第二电源信号端VDD2的电压可以在第四阶段内的某个时刻相互转换。
例如，当第一电源信号端VDD1的电压为第二电源电压VSS2，第二电源信号端VDD2的电压为第三电源电压VH时，第一上拉节点PD1和第二下拉节点PD2的功能互换，第一下拉控制电路150和第二下拉控制电路160的功能互换，第一输出下拉晶体管K1和第二输出下拉晶体管K2的功能互换，第一下拉晶体管F1和第二下拉晶体管F2的功能互换。移位寄存器的工作原理与第一电源信号端VDD1的电压为第三电源电压VH、第二电源信号端VDD2的电压为第二电源电压VSS2时类似，在此不再赘述。
例如，第一下拉控制电路150和第二下拉控制电路160可以控制第一下拉节点PD1和第二下拉节点PD2分别工作，这样可以使得第一输出下拉晶体管K1和第二输出下拉晶体管K2分时工作、使得第一下拉晶体管F1和第二下拉晶体管F2分时工作，降低了晶体管长时间处于开启状态导致故障的可能性，提高了移位寄存器的抗干扰能力，进而提高了移位寄存器的可靠性。
例如，利用第一电源信号端VDD1的电压和第二电源信号端VDD2的电 压互为反向信号的特点，分时地将第一电源信号端VDD1和第二电源信号端VDD2提供的第二电源电压VSS2传输到输出端，使输出端的第二电源电压VSS2与上拉节点的第一电源电压VSS1区分开，从而使第一晶体管的控制极和第二极之间存在一定的电压差，从而提高了第一晶体管阈值电压漂移的设计冗余度。
本公开的实施例还提供一种栅极驱动电路10。如图11所示，栅极驱动电路10包括本公开任一实施例提供的移位寄存器100。
例如，如图11所示，本公开实施例提供的栅极驱动电路10，包括级联的多个本公开任一实施例提供的移位寄存器100，除第一级和最后一级移位寄存器100之外，本级移位寄存器100的输入信号端INPUT与上一级移位寄存器100的输出端OUTPUT连接；本级移位寄存器100的复位信号端RESET与下一级移位寄存器100的输出端OUTPUT连接。
例如，第一级移位寄存器的输入信号端INPUT与第一触发信号端STV1连接；最后一级移位寄存器的复位信号端RESET与第二触发信号端STV2连接。
例如，当栅极驱动电路10正向扫描时，第一触发信号端STV1为第一级移位寄存器提供输入信号，第二触发信号STV2端为最后一级移位寄存器提供复位信号。当栅极驱动电路10反向扫描时，第二触发信号端STV2为最后一级移位寄存器提供输入信号，第一触发信号端STV1为第一级移位寄存器提供复位信号。例如，在正向扫描和反向扫描切换时，移位寄存器的输入电路与复位电路的功能互换。
例如，如图11所示，栅极驱动电路10包括n级移位寄存器SR1、SR2……SRn，这些移位寄存器SR1、SR2……SRn均可以是本公开任一实施例提供的移位寄存器100。移位寄存器SR1、SR2……SRn的输出端OUTPUT分别与栅线G1、G2……Gn对应连接。
需要说明的是，由于本公开实施例提供的栅极驱动电路10可以实现正向扫描和逆向扫描，在扫描方向切换时，时序上的“上一级”和“下一级”会相应变换，因此，上述的“上一级”和“下一级”并不是指扫描时序上的上一级和下一级，而是指物理连接上的上一级和下一级。
本公开的实施例还提供一种显示面板1。如图12所示，显示面板1包括 本公开任一实施例提供的栅极驱动电路10。
例如，如图12所示，本公开实施例提供的显示面板1还包括栅线11、数据线12以及由栅线11和数据线12交叉限定的多个像素单元13，栅极驱动电路10被配置为向栅线11提供栅极驱动信号。
例如，栅线11可以包括图11中所示的栅线G1、G2……Gn，移位寄存器SR1、SR2……SRn中每级移位寄存器用于向对应的栅线G1、G2……Gn输出一行栅极驱动信号。
本公开的实施例还提供一种本公开任一实施例提供的移位寄存器100的驱动方法，如图13所示，该驱动方法包括如下步骤：
步骤S10：将第一电源电压VSS1写入上拉节点PU；以及
步骤S20：将第二电源电压VSS2写入输出端OUTPUT，第一电源电压VSS1与第二电源电压VSS2不同。
例如，当所述第一晶体管T1为N型晶体管时，第一电源电压VSS1小于第二电源电压VSS2。
例如，当所述第一晶体管T1为P型晶体管时，第一电源电压VSS1大于第二电源电压VSS2。
例如，本公开实施例提供的移位寄存器、栅极驱动电路、显示面板和驱动方法可以提高电路的稳定性。
虽然上文中已经用一般性说明及具体实施方式，对本公开作了详尽的描述，但在本公开实施例基础上，可以对之作一些修改或改进，这对本领域技术人员而言是显而易见的。因此，在不偏离本公开精神的基础上所做的这些修改或改进，均属于本公开要求保护的范围。
本公开要求于2017年3月8日递交的中国专利申请第201710135056.1号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (15)

  1. 一种移位寄存器，包括：
    输入电路，与上拉节点和输入信号端分别连接；
    复位电路，与所述上拉节点、复位信号端及第一电源端分别连接以接收第一电源电压；
    输出电路，与所述上拉节点、时钟信号端及输出端分别连接；以及
    输出下拉电路，与所述输出端连接，被配置为将第二电源电压写入所述输出端，
    其中，所述第一电源电压与所述第二电源电压不同。
  2. 根据权利要求1所述的移位寄存器，其中，
    所述输出电路包括存储电容和第一晶体管，所述第一晶体管的第一极与时钟信号端连接，所述第一晶体管的控制极与所述上拉节点连接，所述第一晶体管的第二极与所述输出端连接，所述存储电容的第一端与所述上拉节点连接，所述存储电容的第二端与所述输出端连接；
    所述输入电路包括第二晶体管，所述第二晶体管的第一极与所述输入信号端连接，所述第二晶体管的控制极与所述输入信号端连接，所述第二晶体管的第二极与所述上拉节点连接；以及
    所述复位电路包括第三晶体管，所述第三晶体管的第一极与所述上拉节点连接，所述第三晶体管的控制极与所述复位信号端连接，所述第三晶体管的第二极与所述第一电源端连接。
  3. 根据权利要求1或2所述的移位寄存器，其中，所述输出下拉电路包括第一输出下拉晶体管，所述第一输出下拉晶体管的第一极与所述输出端连接，所述第一输出下拉晶体管的控制极与所述复位信号端连接，所述第一输出下拉晶体管的第二极与第二电源端连接以接收第二电源电压。
  4. 根据权利要求1或2所述的移位寄存器，还包括第一下拉控制电路，其中，
    所述输出下拉电路包括第一输出下拉晶体管；
    所述第一输出下拉晶体管的第一极与所述输出端连接，所述第一输出下拉晶体管的控制极与所述第一下拉控制电路连接，所述第一输出下拉晶体管 的第二极被配置为接收所述第二电源电压；以及
    所述第一下拉控制电路被配置为控制所述第一输出下拉晶体管的开启和关闭。
  5. 根据权利要求4所述的移位寄存器，其中，
    所述第一下拉控制电路包括第一子控制电路和第二子控制电路；
    所述第一子控制电路与第三电源端、第一下拉节点以及所述第二子控制电路分别连接；以及
    所述第二子控制电路与所述上拉节点、所述第一下拉节点以及所述第一电源端分别连接。
  6. 根据权利要求5所述的移位寄存器，其中，
    所述第一子控制电路包括第一控制晶体管和第二控制晶体管，所述第二子控制电路包括第三控制晶体管和第四控制晶体管；
    所述第一输出下拉晶体管的控制极与所述第一下拉节点连接；
    所述第一控制晶体管的第一极与所述第三电源端连接，所述第一控制晶体管的控制极与所述第三电源端连接，所述第一控制晶体管的第二极与第一节点连接；
    所述第二控制晶体管的第一极与所述第三电源端连接，所述第二控制晶体管的控制极与所述第一节点连接，所述第二控制晶体管的第二极与所述第一下拉节点连接；
    所述第三控制晶体管的第一极与所述第一下拉节点连接，所述第三控制晶体管的控制极与所述上拉节点连接，所述第三控制晶体管的第二极与所述第一电源端连接；以及
    所述第四控制晶体管的第一极与所述第一节点连接，所述第四控制晶体管的控制极与所述上拉节点连接，所述第四控制晶体管的第二极与所述第一电源端连接。
  7. 根据权利要求4所述的移位寄存器，还包括第二下拉控制电路，其中，
    所述输出下拉电路还包括第二输出下拉晶体管；
    所述第二输出下拉晶体管的第一极与所述输出端连接，所述第二输出下拉晶体管的控制极与所述第二下拉控制电路连接，所述第二输出下拉晶体管的第二极被配置为接收所述第二电源电压；以及
    所述第二下拉控制电路被配置为控制所述第二输出下拉晶体管的开启和关闭。
  8. 根据权利要求7所述的移位寄存器，其中，
    所述第一下拉控制电路包括第一子控制电路和第二子控制电路，所述第二下拉控制电路包括第三子控制电路和第四子控制电路；
    所述第一子控制电路与第一电源信号端、第一下拉节点以及所述第二子控制电路分别连接；
    所述第二子控制电路与所述上拉节点、所述第一下拉节点以及所述第一电源端分别连接；
    所述第三子控制电路与第二电源信号端、第二下拉节点以及所述第四子控制电路分别连接；以及
    所述第四子控制电路与所述上拉节点、所述第二下拉节点以及所述第一电源端分别连接。
  9. 根据权利要求8所述的移位寄存器，其中，
    所述第一子控制电路包括第一控制晶体管和第二控制晶体管，所述第二子控制电路包括第三控制晶体管和第四控制晶体管，所述第三子控制电路包括第五控制晶体管和第六控制晶体管，所述第四子控制电路包括第七控制晶体管和第八控制晶体管；
    所述第一输出下拉晶体管的控制极与所述第一下拉节点连接，所述第一输出下拉晶体管的第二极与所述第二电源信号端连接以接收第二电源信号；
    所述第一控制晶体管的第一极与第一电源信号端连接以接收第一电源信号，所述第一控制晶体管的控制极与所述第一电源信号端连接以接收所述第一电源信号，所述第一控制晶体管的第二极与第一节点连接；
    所述第二控制晶体管的第一极与所述第一电源信号端连接以接收所述第一电源信号，所述第二控制晶体管的控制极与所述第一节点连接，所述第二控制晶体管的第二极与第一下拉节点连接；
    所述第三控制晶体管的第一极与所述第一下拉节点连接，所述第三控制晶体管的控制极与所述上拉节点连接，所述第三控制晶体管的第二极与第一电源端连接以接收所述第一电源电压；
    所述第四控制晶体管的第一极与所述第一节点连接，所述第四控制晶体 管的控制极与所述上拉节点连接，所述第四控制晶体管的第二极与所述第一电源端连接以接收所述第一电源电压；
    所述第二输出下拉晶体管的控制极与所述第二下拉节点连接，所述第二输出下拉晶体管的第二极与所述第一电源信号端连接以接收所述第一电源信号；
    所述第五控制晶体管的第一极与所述第二电源信号端连接以接收所述第二电源信号，所述第五控制晶体管的控制极与所述第二电源信号端连接以接收所述第二电源信号，所述第五控制晶体管的第二极与第二节点连接；
    所述第六控制晶体管的第一极与所述第二电源信号端连接以接收所述第二电源信号，所述第六控制晶体管的控制极与所述第二节点连接，所述第六控制晶体管的第二极与第二下拉节点连接；
    所述第七控制晶体管的第一极与所述第二下拉节点连接，所述第七控制晶体管的控制极与所述上拉节点连接，所述第七控制晶体管的第二极与第一电源端连接以接收所述第一电源电压；
    所述第八控制晶体管的第一极与所述第二节点连接，所述第八控制晶体管的控制极与所述上拉节点连接，所述第八控制晶体管的第二极与所述第一电源端连接以接收所述第一电源电压；以及
    所述第一电源信号与所述第二电源信号互为反向信号，所述第一电源信号和所述第二电源信号为低电平信号时的电压均为所述第二电源电压。
  10. 根据权利要求9所述的移位寄存器，还包括上拉节点下拉电路，与所述上拉节点、所述第一下拉节点、所述第二下拉节点及所述第一电源端分别连接。
  11. 根据权利要求10所述的移位寄存器，其中，
    所述上拉节点下拉电路包括第一下拉晶体管和第二下拉晶体管；
    所述第一下拉晶体管的第一极与所述上拉节点连接，所述第一下拉晶体管的控制极与所述第二下拉节点连接，所述第一下拉晶体管的第二极与所述第一电源端连接以接收所述第一电源电压；以及
    所述第二下拉晶体管的第一极与所述上拉节点连接，所述第二下拉晶体管的控制极与所述第一下拉节点连接，所述第二下拉晶体管的第二极与所述第一电源端连接以接收所述第一电源电压。
  12. 一种栅极驱动电路，包括如权利要求1-11任一项所述的移位寄存器。
  13. 根据权利要求12所述的栅极驱动电路，包括级联的多个如权利要求1-11任一项所述的移位寄存器，其中，除第一级和最后一级移位寄存器之外，本级移位寄存器的输入信号端与上一级移位寄存器的输出端连接；本级移位寄存器的复位信号端与下一级移位寄存器的输出端连接。
  14. 一种显示面板，包括如权利要求12或13所述的栅极驱动电路。
  15. 一种如权利要求1-11任一项所述的移位寄存器的驱动方法，包括：
    将所述第一电源电压写入所述上拉节点；以及
    将所述第二电源电压写入所述输出端，
    其中，所述第一电源电压与所述第二电源电压不同。
PCT/CN2017/102448 2017-03-08 2017-09-20 移位寄存器、栅极驱动电路、显示面板及驱动方法 WO2018161523A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/761,749 US10593245B2 (en) 2017-03-08 2017-09-20 Shift register, gate driving circuit, display panel and driving method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710135056.1A CN106611582A (zh) 2017-03-08 2017-03-08 移位寄存器、栅极驱动电路、显示面板及驱动方法
CN201710135056.1 2017-03-08

Publications (1)

Publication Number Publication Date
WO2018161523A1 true WO2018161523A1 (zh) 2018-09-13

Family

ID=58637007

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/102448 WO2018161523A1 (zh) 2017-03-08 2017-09-20 移位寄存器、栅极驱动电路、显示面板及驱动方法

Country Status (3)

Country Link
US (1) US10593245B2 (zh)
CN (1) CN106611582A (zh)
WO (1) WO2018161523A1 (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106611582A (zh) 2017-03-08 2017-05-03 京东方科技集团股份有限公司 移位寄存器、栅极驱动电路、显示面板及驱动方法
US11119377B2 (en) 2017-12-01 2021-09-14 Shenzhen Royole Technologies Co., Ltd. LCD panel and EOA module thereof
CN108198586B (zh) * 2018-01-18 2020-12-08 京东方科技集团股份有限公司 移位寄存器电路及其驱动方法、栅极驱动器和显示面板
CN109272963B (zh) * 2018-11-14 2020-03-03 成都中电熊猫显示科技有限公司 栅极驱动电路和栅极驱动器
CN109859670A (zh) * 2019-03-28 2019-06-07 京东方科技集团股份有限公司 一种移位寄存器单元及其驱动方法、栅极驱动电路
CN110767255B (zh) * 2019-11-04 2021-10-29 京东方科技集团股份有限公司 移位寄存器单元及驱动方法、栅极驱动电路、显示面板
US11250765B2 (en) * 2020-06-15 2022-02-15 Wuhan China Star Optoelectronics Technology Co., Ltd. Display driving circuit

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103218962A (zh) * 2012-01-20 2013-07-24 群康科技(深圳)有限公司 移位寄存器
CN103258495A (zh) * 2013-05-07 2013-08-21 京东方科技集团股份有限公司 移位寄存单元、移位寄存器和显示装置
CN103440839A (zh) * 2013-08-09 2013-12-11 京东方科技集团股份有限公司 移位寄存单元、移位寄存器和显示装置
CN105185349A (zh) * 2015-11-04 2015-12-23 京东方科技集团股份有限公司 一种移位寄存器、栅极集成驱动电路及显示装置
CN106448532A (zh) * 2016-09-28 2017-02-22 上海天马微电子有限公司 一种移位寄存器、驱动电路及显示面板
CN106611582A (zh) * 2017-03-08 2017-05-03 京东方科技集团股份有限公司 移位寄存器、栅极驱动电路、显示面板及驱动方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101478667B1 (ko) * 2008-10-16 2015-01-02 삼성디스플레이 주식회사 표시 장치 및 이의 구동 방법
CN103236273B (zh) * 2013-04-16 2016-06-22 北京京东方光电科技有限公司 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
KR102028992B1 (ko) * 2013-06-27 2019-10-07 엘지디스플레이 주식회사 쉬프트 레지스터
KR102360845B1 (ko) * 2015-06-15 2022-02-10 삼성디스플레이 주식회사 게이트 구동회로 및 이를 포함하는 표시 장치
CN105047168B (zh) * 2015-09-01 2018-01-09 京东方科技集团股份有限公司 移位寄存器、栅极驱动电路及显示装置
CN105679262B (zh) * 2016-01-12 2017-08-29 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动电路和显示装置
CN105529009B (zh) * 2016-02-04 2018-03-20 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动电路和显示装置
CN105702194B (zh) * 2016-04-26 2019-05-10 京东方科技集团股份有限公司 一种移位寄存器单元、栅极驱动电路及其驱动方法
CN106448536B (zh) * 2016-10-31 2019-05-14 合肥鑫晟光电科技有限公司 移位寄存器、栅极驱动电路、显示面板及驱动方法
CN106486082B (zh) * 2017-01-03 2020-03-31 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动装置
CN106782282A (zh) * 2017-02-23 2017-05-31 京东方科技集团股份有限公司 移位寄存器、栅极驱动电路、显示面板及驱动方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103218962A (zh) * 2012-01-20 2013-07-24 群康科技(深圳)有限公司 移位寄存器
CN103258495A (zh) * 2013-05-07 2013-08-21 京东方科技集团股份有限公司 移位寄存单元、移位寄存器和显示装置
CN103440839A (zh) * 2013-08-09 2013-12-11 京东方科技集团股份有限公司 移位寄存单元、移位寄存器和显示装置
CN105185349A (zh) * 2015-11-04 2015-12-23 京东方科技集团股份有限公司 一种移位寄存器、栅极集成驱动电路及显示装置
CN106448532A (zh) * 2016-09-28 2017-02-22 上海天马微电子有限公司 一种移位寄存器、驱动电路及显示面板
CN106611582A (zh) * 2017-03-08 2017-05-03 京东方科技集团股份有限公司 移位寄存器、栅极驱动电路、显示面板及驱动方法

Also Published As

Publication number Publication date
CN106611582A (zh) 2017-05-03
US20190066559A1 (en) 2019-02-28
US10593245B2 (en) 2020-03-17

Similar Documents

Publication Publication Date Title
WO2018161523A1 (zh) 移位寄存器、栅极驱动电路、显示面板及驱动方法
WO2018153063A1 (zh) 移位寄存器、栅极驱动电路、显示面板及驱动方法
US10593286B2 (en) Shift register, gate driving circuit, display panel and driving method
US9965985B2 (en) Shift register and method for driving the same, gate driving circuit and display apparatus
WO2018076665A1 (zh) 移位寄存器、栅极驱动电路、显示面板及驱动方法
CN107799087B (zh) 一种goa电路及显示装置
EP3832635B1 (en) Shift register, gate driving circuit, display device, and gate driving method
WO2018214613A1 (zh) 移位寄存器电路、其驱动方法、栅极驱动电路及显示面板
KR101023726B1 (ko) 쉬프트 레지스터
WO2017219824A1 (zh) 移位寄存器单元、驱动方法、栅极驱动电路和显示装置
WO2018205543A1 (zh) 移位寄存器、其驱动方法、栅极集成驱动电路及显示装置
WO2017124721A1 (zh) 移位寄存器、栅极驱动电路及显示装置
US11443682B2 (en) Display device, gate drive circuit, shift register including two shift register units and control method thereof
WO2018209937A1 (zh) 移位寄存器及其驱动方法、栅极驱动电路、显示装置
WO2019210830A1 (zh) 移位寄存器及其驱动方法、栅极驱动电路和显示装置
US11581051B2 (en) Shift register and driving method thereof, gate drive circuit, and display device
WO2019041853A1 (zh) 移位寄存器单元、驱动装置、显示装置以及驱动方法
KR102015396B1 (ko) 쉬프트 레지스터와 이의 구동방법
US10319324B2 (en) Shift registers, driving methods, gate driving circuits and display apparatuses with reduced shift register output signal voltage switching time
WO2018161527A1 (zh) 移位寄存器、栅极驱动电路、显示面板及驱动方法
US10403188B2 (en) Shift register unit, gate driving circuit and display device
WO2019015267A1 (zh) 移位寄存器单元及其驱动方法、栅极驱动电路
US11348501B2 (en) Shift register and driving method thereof, gate driving circuit and display device
KR20050113967A (ko) 쉬프트 레지스터
US20220343855A1 (en) Gate driving circuit, display substrate, display device and gate driving method

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17899255

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17899255

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 18/03/2020)

122 Ep: pct application non-entry in european phase

Ref document number: 17899255

Country of ref document: EP

Kind code of ref document: A1