WO2022262037A1 - 栅极驱动电路及显示面板 - Google Patents

栅极驱动电路及显示面板 Download PDF

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Publication number
WO2022262037A1
WO2022262037A1 PCT/CN2021/105943 CN2021105943W WO2022262037A1 WO 2022262037 A1 WO2022262037 A1 WO 2022262037A1 CN 2021105943 W CN2021105943 W CN 2021105943W WO 2022262037 A1 WO2022262037 A1 WO 2022262037A1
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WO
WIPO (PCT)
Prior art keywords
transistor
electrically connected
node
wiring
drain
Prior art date
Application number
PCT/CN2021/105943
Other languages
English (en)
French (fr)
Inventor
王选芸
戴超
吴剑龙
何瑞亭
Original Assignee
武汉华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US17/434,717 priority Critical patent/US11955084B2/en
Publication of WO2022262037A1 publication Critical patent/WO2022262037A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements

Definitions

  • the present application relates to the field of display technology, in particular to a gate drive circuit and a display panel.
  • the gate driving circuit can use the thin film transistor array (Array) substrate manufacturing process to manufacture the gate (Gate) row scanning driving technology on the Array substrate, so as to realize the driving mode of scanning the Gate.
  • Array thin film transistor array
  • Gate gate
  • the gate drive circuit is used as the drive circuit of the display panel, and whether the potential of its internal key nodes is stable directly affects the stability of the output signal, which in turn affects the working reliability of the display panel.
  • the present application provides a gate driving circuit and a display panel to alleviate the technical problem of unstable operation of the gate driving circuit.
  • the present application provides a gate drive circuit
  • the gate drive circuit includes a plurality of cascaded gate drive units, and each stage of the gate drive unit outputs a corresponding scanning signal
  • the gate drive unit includes The first wiring, the second wiring, the third wiring, the fourth wiring, the fifth wiring, the sixth wiring, the pull-down control module, the pull-down module, the pull-up control module, the first pull-up regulator module, the pull-up module, the second A pull-up voltage stabilizing module and a pull-down voltage stabilizing module; the input end of the pull-down control module is electrically connected to the first wiring, the control end of the pull-down control module is electrically connected to the second wiring and the third wiring, and the output end of the pull-down control module is electrically connected to the third wiring.
  • the first node is electrically connected; the control end of the pull-down module is electrically connected to the first node, the input end of the pull-down module is electrically connected to the fourth wiring, and the output end of the pull-down module is electrically connected to the second node to output a corresponding scan signal; the input terminal of the pull-up control module is electrically connected to the third wiring and the fourth wiring, the control terminal of the pull-up control module is electrically connected to the first node and the third wiring, and the output terminal of the pull-up control module is electrically connected to the third wiring.
  • the nodes are electrically connected; the input terminal of the first pull-up voltage stabilizing module is electrically connected with the second wiring and the third wiring, and the control terminal of the first pull-up voltage stabilizing module is electrically connected with the first node, the third node and the third wiring
  • the output end of the first pull-up regulator module is electrically connected to the fourth node; the input end of the pull-up module is electrically connected to the second wiring, and the control end of the pull-up module is electrically connected to the fourth node.
  • the output terminal of the pull-up module is electrically connected to the second node; one end of the second pull-up voltage stabilizing module is electrically connected to the second wiring, and the other end of the second pull-up voltage stabilizing module is electrically connected to the fourth node; and the pull-down The input terminal of the voltage stabilizing module is electrically connected to the fifth wiring and the sixth wiring, the control terminal of the pull-down voltage stabilizing module is electrically connected to the first node and the third node, and the output terminal of the pulling-down voltage stabilizing module is electrically connected to the first node connect.
  • the pull-down control module includes a first transistor and a second transistor, one of the source/drain of the first transistor is electrically connected to the first wiring, and the gate of the first transistor is electrically connected to the second wiring.
  • One of the source/drain of the second transistor is electrically connected with the other of the source/drain of the first transistor, the gate of the second transistor is electrically connected with the third wiring, and the second transistor The other of the source/drain is directly electrically connected to the first node.
  • the pull-down module includes a third transistor, the gate of the third transistor is electrically connected to the first node, one of the source/drain of the third transistor is electrically connected to the fourth wiring, and the third The other one of the source/drain of the transistor is electrically connected with the second node.
  • the pull-up control module includes a fourth transistor and a fifth transistor, one of the source/drain of the fourth transistor is electrically connected to the third wiring, and the gate of the fourth transistor is connected to the first node directly electrically connected, the other of the source/drain of the fourth transistor is electrically connected to the third node; one of the source/drain of the fifth transistor is electrically connected to the fourth wiring, and the fifth transistor The gate is electrically connected to the third wiring, and the other of the source/drain of the fifth transistor is electrically connected to the third node.
  • the first pull-up regulator module includes a sixth transistor, a seventh transistor, an eighth transistor, and a first capacitor; one of the source/drain of the sixth transistor is electrically connected to the third wiring , the gate of the sixth transistor is electrically connected to the third node; one of the source/drain of the seventh transistor is electrically connected to the other of the source/drain of the sixth transistor, and the gate of the seventh transistor
  • the pole is electrically connected to the third wiring, the other of the source/drain of the seventh transistor is electrically connected to the fourth node; one of the source/drain of the eighth transistor is electrically connected to the second wiring,
  • the gate of the eighth transistor is electrically connected to the first node, and the other of the source/drain of the eighth transistor is electrically connected to the fourth node; one end of the first capacitor is electrically connected to the gate of the sixth transistor , the other end of the first capacitor is electrically connected to the other of the source/drain of the sixth transistor.
  • the pull-up module includes a ninth transistor, one of the source/drain of the ninth transistor is electrically connected to the second wiring, the gate of the ninth transistor is electrically connected to the fourth node, and the ninth transistor is electrically connected to the fourth node. Another source/drain of the nine transistors is electrically connected to the second node.
  • the second pull-up voltage stabilizing module includes a second capacitor, the first end of the second capacitor is electrically connected to the second wiring, and the second end of the second capacitor is electrically connected to the fourth node.
  • the pull-down regulator module includes a tenth transistor, an eleventh transistor, and a third capacitor; one of the source/drain of the tenth transistor is electrically connected to the sixth wiring, and the gate of the tenth transistor The pole is electrically connected to the third node; one of the source/drain of the eleventh transistor is electrically connected to the other of the source/drain of the tenth transistor, and the gate of the eleventh transistor is connected to the first The nodes are electrically connected, the other of the source/drain of the eleventh transistor is electrically connected to the fifth wiring; one end of the third capacitor is electrically connected to one of the source/drain of the eleventh transistor, The other end of the third capacitor is electrically connected to the first node.
  • the Nth-level gate drive unit further includes a voltage stabilization isolation module, the input terminal of the voltage stabilization isolation module is electrically connected to the third node, and the control terminal of the voltage stabilization isolation module is electrically connected to the fourth wiring , the output end of the voltage stabilizing isolation module is electrically connected to the first pull-up voltage stabilizing module.
  • the voltage stabilizing isolation module includes a twelfth transistor, one of the source/drain of the twelfth transistor is electrically connected to the third node, and the gate of the twelfth transistor is electrically connected to the fourth wiring. The other one of the source/drain of the twelfth transistor is electrically connected to the first pull-up regulator module.
  • both the fourth transistor and the fifth transistor are P-channel thin film transistors.
  • the present application provides a display panel, which includes the gate driving circuit in any one of the above implementation manners.
  • the potential stability of the fourth node can be improved through the first pull-up voltage stabilization module and the second pull-up voltage stabilization module, and the potential stability of the first node can be improved through the pull-down voltage stabilization module.
  • Potential stability which in turn can improve the stability of the output signal of the gate drive circuit; the topological structure of the gate drive circuit is simplified, which can reduce the space occupied by the frame of the display panel, which is beneficial to realize the narrow frame of the display panel.
  • FIG. 1 is a schematic structural diagram of a gate driving circuit provided by an embodiment of the present application.
  • FIG. 2 is a timing diagram corresponding to the gate driving circuit in FIG. 1 .
  • FIG. 3 is a schematic diagram of potential changes of some transistors in the gate driving circuit shown in FIG. 1 .
  • FIG. 4 is another timing diagram corresponding to the gate driving circuit in FIG. 1 .
  • FIG. 5 is another schematic structural diagram of the gate driving circuit provided by the embodiment of the present application.
  • this embodiment provides a gate driving circuit, and the gate driving circuit includes a plurality of cascaded gate driving units, wherein the Nth-level gate driving unit Including first wiring, second wiring, third wiring, fourth wiring, fifth wiring, sixth wiring, pull-down control module 10, pull-down module 20, pull-up control module 30, first pull-up regulator module 40, upper
  • the input terminal of the pull-down control module 10 is electrically connected to the first wiring, and the control terminal of the pull-down control module 10 is electrically connected to the second wiring and the third wiring
  • the output end of the pull-down control module 10 is electrically connected to the first node Q;
  • the control end of the pull-down module 20 is electrically connected to the first node Q, and the input end of the pull-down module 20 is electrically connected to the fourth wiring.
  • the output terminal of 20 is electrically connected with the second node S to output the corresponding Nth-level scanning signal NSCAN (N); the input terminal of the pull-up control module 30 is electrically connected with the third wiring and the fourth wiring, and the pull-up control module
  • the control terminal of 30 is electrically connected to the first node Q and the third wiring, the output terminal of the pull-up control module 30 is electrically connected to the third node T; the input terminal of the first pull-up voltage stabilizing module 40 is connected to the second wiring and The third wiring is electrically connected, the control end of the first pull-up voltage stabilizing module 40 is electrically connected to the first node Q, the third node T and the third wiring, the output end of the first pull-up voltage stabilizing module 40 is connected to the fourth
  • the node P is electrically connected; the input end of the pull-up module 50 is electrically connected to the second wiring, the control end of the pull-up module 50 is electrically connected to the fourth node P, and the output end of the pull-up module 50 is electrical
  • the gate drive circuit provided in this embodiment can improve the potential stability of the fourth node P through the first pull-up voltage stabilization module 40 and the second pull-up voltage stabilization module 60, and can improve the potential stability of the fourth node P through the pull-down voltage stabilization module 70 can improve the potential stability of the first node Q, thereby improving the stability of the output signal of the gate drive circuit; the topological structure of the gate drive circuit is simplified, which can reduce the space occupied by the frame of the display panel, which is conducive to realizing the display panel Narrow bezels.
  • the first wiring may be used to transmit the N-1-th level scan signal NSCAN(N-1).
  • the second wiring can be used to transmit the clock signal XCK1.
  • the third wiring can be used to transmit the clock signal XCK2.
  • the fourth wiring can be used to transmit a low potential signal L, and the low potential signal L can be used to control the P-channel thin film transistor to turn on.
  • the fifth wiring may be used to transmit the clock signal CK2.
  • the sixth wiring can be used to transmit a high potential signal H, and the high potential signal H can be used to control the P-channel thin film transistor to turn off.
  • the clock signal XCK1 and the clock signal CK2 may be a set of reversed clock signals. That is, when the clock signal XCK1 is at a high potential, the clock signal CK2 is at a low potential; that is, when the clock signal XCK1 is at a low potential, the clock signal CK2 is at a high potential.
  • the clock signal XCK2 and the clock signal CK1 can be a set of inverted clock signals. That is, when the clock signal XCK2 is at a high potential, the clock signal CK1 is at a low potential; that is, when the clock signal XCK2 is at a low potential, the clock signal CK1 is at a high potential.
  • the clock signal CK1 please refer to the follow-up description for details.
  • the first wiring can also be used to transmit the start signal.
  • the N-level scanning signal NSCAN(N) can be connected to the gate of the N-channel thin film transistor, and the N-level scanning signal NSCAN(N) in its high potential state can be used to turn on the corresponding N-channel thin film transistor .
  • the Nth-level gate drive unit further includes a voltage stabilization isolation module 80, the input terminal of the voltage stabilization isolation module 80 is electrically connected to the third node T, and the control terminal of the voltage stabilization isolation module 80 is connected to the fourth node T.
  • the wiring is electrically connected, and the output terminal of the voltage stabilization isolation module 80 is electrically connected to the first pull-up voltage stabilization module 40 .
  • the pull-down control module 10 includes a first transistor T11 and a second transistor T1, one of the source/drain of the first transistor T11 is electrically connected to the first wiring, and the gate of the first transistor T11 It is electrically connected to the second wiring; one of the source/drain of the second transistor T1 is electrically connected to the other of the source/drain of the first transistor T11, and the gate of the second transistor T1 is connected to the third The wiring is electrically connected, and the other one of the source/drain of the second transistor T1 is directly electrically connected to the first node Q.
  • the pull-down module 20 includes a third transistor T12, the gate of the third transistor T12 is electrically connected to the first node Q, and one of the source/drain of the third transistor T12 is electrically connected to the fourth wiring. The other one of the source/drain of the third transistor T12 is electrically connected to the second node S.
  • the pull-up control module 30 includes a fourth transistor T2 and a fifth transistor T3, one of the source/drain of the fourth transistor T2 is electrically connected to the third wiring, and the gate of the fourth transistor T2 The pole is directly electrically connected to the first node Q, the other of the source/drain of the fourth transistor T2 is electrically connected to the third node T; one of the source/drain of the fifth transistor T3 is connected to the fourth The wiring is electrically connected, the gate of the fifth transistor T3 is electrically connected to the third wiring, and the other of the source/drain of the fifth transistor T3 is electrically connected to the third node T.
  • the first pull-up regulator module 40 includes a sixth transistor T7, a seventh transistor T8, an eighth transistor T10, and a first capacitor C2; one of the source/drain of the sixth transistor T7 and The third wiring is electrically connected, the gate of the sixth transistor T7 is electrically connected to the third node T; one of the source/drain of the seventh transistor T8 is connected to the other of the source/drain of the sixth transistor T7 One is electrically connected, the gate of the seventh transistor T8 is electrically connected to the third wiring, the other of the source/drain of the seventh transistor T8 is electrically connected to the fourth node P; the source of the eighth transistor T10 One of the /drains is electrically connected to the second wiring, the gate of the eighth transistor T10 is electrically connected to the first node Q, and the other of the source/drain of the eighth transistor T10 is electrically connected to the fourth node P One end of the first capacitor C2 is electrically connected to the gate of the sixth transistor T7, and the third wiring is electrically connected
  • the pull-up module 50 includes a ninth transistor T13, one of the source/drain of the ninth transistor T13 is electrically connected to the second wiring, and the gate of the ninth transistor T13 is connected to the fourth node P The other one of the source/drain of the ninth transistor T13 is electrically connected to the second node S.
  • the second pull-up regulator module 60 includes a second capacitor C3, the first end of the second capacitor C3 is electrically connected to the second wiring, and the second end of the second capacitor C3 is connected to the fourth node P electrical connection.
  • the pull-down regulator module 70 includes a tenth transistor T5, an eleventh transistor T4, and a third capacitor C1; one of the source/drain of the tenth transistor T5 is electrically connected to the sixth wiring, The gate of the tenth transistor T5 is electrically connected to the third node T; one of the source/drain of the eleventh transistor T4 is electrically connected to the other of the source/drain of the tenth transistor T5, and the first The gate of the eleventh transistor T4 is electrically connected to the first node Q, and the other of the source/drain of the eleventh transistor T4 is electrically connected to the fifth wiring; one end of the third capacitor C1 is connected to the eleventh transistor One of the source/drain of T4 is electrically connected, and the other end of the third capacitor C1 is electrically connected to the first node Q.
  • the potential of the first node Q is easier to maintain stably, thereby improving the stability of the output signal of the gate driving circuit.
  • the voltage stabilizing isolation module 80 includes a twelfth transistor T6, one of the source/drain of the twelfth transistor T6 is electrically connected to the third node T, and the gate of the twelfth transistor T6 The other one of the source/drain of the twelfth transistor T6 is electrically connected to the gate of the sixth transistor T7.
  • the potential of the third node T and the potential of the source/drain of the twelfth transistor T6 can be isolated from each other, and the potential between them can be kept. Therefore, the stability of the output signal of the gate drive circuit can be further improved.
  • At least one of T13 , the tenth transistor T5 , the eleventh transistor T4 and the twelfth transistor T6 is a P-channel thin film transistor.
  • the gate drive circuit operates in phases S10 and In S20, the corresponding N-1-level scanning signal NSCAN (N-1) and N-level scanning signal NSCAN (N) are output.
  • the N-1-level scanning signal NSCAN (N-1) the N-level scanning signal
  • the simulation waveform of NSCAN (N) the effective pulse corresponding to the output scanning signal is stable.
  • the gate-source voltage difference Vgs of the second transistor T1 is 0V in the stage S10, and is 33V in the stage S20; the gate-drain voltage difference Vgd of the second transistor T1 is in It is 5V in stage S10, and is 35V in stage S20; the drain-source voltage difference Vds of the second transistor T1 is -5V in stage S10, and is -25V in stage S20.
  • the gate-source voltage difference Vgs of the fourth transistor T2 is 0V in the stage S10, and is -34V in the stage S20; the gate-drain voltage difference Vgd of the fourth transistor T2 is 20V in the stage S10, and in the stage S20 It is -34V in S20; the drain-source voltage difference Vds of the fourth transistor T2 is -20V in stage S10, and is 0V in stage S20.
  • both the second transistor T1 and the fourth transistor T2 can be in a stable working state, which can improve the working stability of the gate driving circuit.
  • stage S10 may also include the following stages:
  • the first stage S1 the first wiring is connected to a low potential signal, the clock signal XCK1 and the clock signal XCK2 are both low potential, the potential of the first node Q and the potential of the fourth node P are both at low potential, but not enough to open the second
  • the third transistor T12 and the ninth transistor T13, at this time, the second node S is equivalent to maintaining a floating state, and the second node S still maintains the low potential of -9V output in the previous stage.
  • the second stage S2 the clock signal XCK2 is written into a high potential, turning off the fifth transistor T3 and the tenth transistor T5; the gate potential of the sixth transistor T7 is written into +6V, and due to the coupling effect of C2, the source of the seventh transistor T8 The electrode potential is pulled high, the seventh transistor T8 is turned on; at the same time, the eighth transistor T10 is turned on; the potential of the fourth node P is maintained at -4V, the third transistor T12 and the ninth transistor T13 are still in the off state, and the second node S is still In the floating state, the second node S keeps outputting a low potential of -9V.
  • the third stage S3 the clock signal CK2 changes from +6V to -9V, the potential of the first node Q is pulled from -6.5V to a lower potential due to the coupling effect of C1, and the third transistor T12 is turned on; at the same time, the eighth The transistor T10 is turned on, the fourth node P writes the high level of the clock signal XCK1, turns off the ninth transistor T13, and the second node S outputs a low potential of -9V.
  • the fourth stage S4 In the next stage, the first wiring needs to be written into a high level; the clock signal XCK2 needs to be turned off in advance; the clock signal CK2 becomes a high level; the potential of the first node Q returns to -6.5V, and the clock signal XCK1 becomes -9V; the potential of the fourth node P remains -4V, the second node S is in a floating (Floating) state, and the second node S keeps outputting a low potential of -9V.
  • the fifth stage S5 the first wiring writes a high potential, the clock signal XCK1 and the clock signal XCK2 are both low potential signals L, and the first transistor T11, the second transistor T1 and the fifth transistor T3 are all turned on; the first node Q writes input +6V, the third transistor T12 is turned off, and the eighth transistor T10 is turned off at the same time; the fourth node P remains unchanged at -4V in the previous stage due to the effect of C3; the second node S remains in a floating (Floating) state, and the second node S continues Output low potential of -9V.
  • the sixth stage S6 the high potential state of the clock signal XCK1 is in the stage before writing, the clock signal XCK2 needs to be turned off in advance to maintain the potential stability of the fourth node P, the second transistor T1 and the fifth transistor T3 are both turned off; the first node Q, the fourth node P maintains the potential of the previous stage unchanged, and the second node S continues to output a low potential of -9V.
  • the seventh stage S7 the high potential state of the clock signal XCK1 is in the writing stage; the clock signal CK2 becomes -9V, the gate potential of the sixth transistor T7 is pulled to a lower value through C2 coupling, and the sixth transistor T7 is turned on; At the same time, the seventh transistor T8 is turned on; the output potential of the fourth node P is -6.5V, the clock signal XCK1 is +6V, the ninth transistor T13 is fully turned on, and the second node S outputs a high potential of +6V.
  • the eighth stage S8 the clock signal XCK1 changes from +6V to -9V, the potential of the fourth node P reaches a lower value through C3 Holding, so that the ninth transistor T13 continues to be turned on, and the second node S can output a low-level clock
  • the signal XCK1 has thus completed a complete output of a high potential pulse of the clock signal XCK1.
  • the second wiring can be used to transmit the clock signal CK2 .
  • the third wiring may be used to transmit the clock signal CK1.
  • the fifth wiring may be used to transmit the clock signal XCK1.
  • the gate drive circuit provided in this embodiment can improve the potential stability of the fourth node P through the first pull-up voltage stabilization module 40 and the second pull-up voltage stabilization module 60, and can improve the potential stability of the fourth node P through the pull-down voltage stabilization module 70 can improve the potential stability of the first node Q, thereby improving the stability of the output signal of the gate drive circuit; the topological structure of the gate drive circuit is simplified, which can reduce the space occupied by the frame of the display panel, which is conducive to realizing the display panel Narrow bezels.
  • this embodiment provides a display panel, which includes the gate driving circuit in any one of the above embodiments.
  • the potential stability of the fourth node P can be improved through the first pull-up voltage stabilization module 40 and the second pull-up voltage stabilization module 60, and the potential stability of the fourth node P can be improved through the pull-down voltage stabilization module 70. Improving the potential stability of the first node Q can further improve the stability of the output signal of the gate drive circuit; the topological structure of the gate drive circuit is simplified, which can reduce the space occupied by the frame of the display panel, which is conducive to realizing the narrow frame of the display panel .
  • the display panel in this embodiment can be AMOLED (Active-Matrix Organic Light-Emitting Diode, active matrix organic light-emitting diode) display screen, which can be widely used in some electronic devices that require display functions, for example, it can be a mobile phone.
  • AMOLED Active-Matrix Organic Light-Emitting Diode, active matrix organic light-emitting diode
  • the display panel may further include a pixel circuit, and the pixel circuit may include a polysilicon thin film transistor and an oxide thin film transistor, and the gate drive circuit in any of the above embodiments may be electrically connected to the pixel circuit to The N-th level scan signal NSCAN(N) with a high potential is used to turn on the corresponding oxide thin film transistor.
  • the pixel circuit in this embodiment is constructed by using the technology of combining polysilicon thin film transistors and oxide thin film transistors, which not only has high dynamic performance, but also has a small leakage current. Therefore, The pixel circuit can work with less power consumption, and when it is used in a mobile phone, it can meet the characteristics of portability and long battery life required by the mobile phone.

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Abstract

本申请公开了一种栅极驱动电路及显示面板，该栅极驱动电路包括多个级联的栅极驱动单元，第N级栅极驱动单元包括下拉控制模块、下拉模块、上拉控制模块、第一上拉稳压模块、上拉模块、第二上拉稳压模块以及下拉稳压模块，通过第一上拉稳压模块、第二上拉稳压模块提高第四节点的电位稳定性，进而提高栅极驱动电路的稳定性。

Description

栅极驱动电路及显示面板 技术领域
本申请涉及显示技术领域，具体涉及一种栅极驱动电路及显示面板。
 背景技术
栅极驱动电路可以利用薄膜晶体管阵列(Array)基板制程将栅极(Gate)行扫描驱动技术制作在Array基板上，实现对Gate进行扫描的驱动方式。
栅极驱动电路作为显示面板的驱动电路，其内部关键节点的电位是否稳定直接影响输出信号的稳定性，进而影响显示面板的工作可靠性。
需要注意的是，上述关于背景技术的介绍仅仅是为了便于清楚、完整地理解本申请的技术方案。因此，不能仅仅由于其出现在本申请的背景技术中，而认为上述所涉及到的技术方案为本领域所属技术人员所公知。
 技术问题
本申请提供一种栅极驱动电路及显示面板，以缓解栅极驱动电路工作不稳定的技术问题。
 技术解决方案
第一方面，本申请提供一种栅极驱动电路，栅极驱动电路包括多个级联的栅极驱动单元，每级所述栅极驱动单元输出相应的扫描信号，其中，栅极驱动单元包括第一布线、第二布线、第三布线、第四布线、第五布线、第六布线、下拉控制模块、下拉模块、上拉控制模块、第一上拉稳压模块、上拉模块、第二上拉稳压模块以及下拉稳压模块；下拉控制模块的输入端与第一布线电性连接，下拉控制模块的控制端与第二布线和第三布线电性连接，下拉控制模块的输出端与第一节点电性连接；下拉模块的控制端与第一节点电性连接，下拉模块的输入端与第四布线电性连接，下拉模块的输出端与第二节点电性连接以输出对应的扫描信号；上拉控制模块的输入端与第三布线和第四布线电性连接，上拉控制模块的控制端与第一节点和第三布线电性连接，上拉控制模块的输出端与第三节点电性连接；第一上拉稳压模块的输入端与第二布线和第三布线电性连接，第一上拉稳压模块的控制端与第一节点、第三节点以及第三布线电性连接，第一上拉稳压模块的输出端与第四节点电性连接；上拉模块的输入端与第二布线电性连接，上拉模块的控制端与第四节点电性连接，上拉模块的输出端与第二节点电性连接；第二上拉稳压模块的一端与第二布线电性连接，第二上拉稳压模块的另一端与第四节点电性连接；以及下拉稳压模块的输入端与第五布线和第六布线电性连接，下拉稳压模块的控制端与第一节点和第三节点电性连接，下拉稳压模块的输出端与第一节点电性连接。
在其中一些实施方式中，下拉控制模块包括第一晶体管和第二晶体管，第一晶体管的源极/漏极中的一个与第一布线电性连接，第一晶体管的栅极与第二布线电性连接；第二晶体管的源极/漏极中的一个与第一晶体管的源极/漏极中的另一个电性连接，第二晶体管的栅极与第三布线电性连接，第二晶体管的源极/漏极中的另一个与第一节点直接电性连接。
在其中一些实施方式中，下拉模块包括第三晶体管，第三晶体管的栅极与第一节点电性连接，第三晶体管的源极/漏极中的一个与第四布线电性连接，第三晶体管的源极/漏极中的另一个与第二节点电性连接。
在其中一些实施方式中，上拉控制模块包括第四晶体管和第五晶体管，第四晶体管的源极/漏极中的一个与第三布线电性连接，第四晶体管的栅极与第一节点直接电性连接，第四晶体管的源极/漏极中的另一个与第三节点电性连接；第五晶体管的源极/漏极中的一个与第四布线电性连接，第五晶体管的栅极与第三布线电性连接，第五晶体管的源极/漏极中的另一个与第三节点电性连接。
在其中一些实施方式中，第一上拉稳压模块包括第六晶体管、第七晶体管、第八晶体管以及第一电容；第六晶体管的源极/漏极中的一个与第三布线电性连接，第六晶体管的栅极与第三节点电性连接；第七晶体管的源极/漏极中的一个与第六晶体管的源极/漏极中的另一个电性连接，第七晶体管的栅极与第三布线电性连接，第七晶体管的源极/漏极中的另一个与第四节点电性连接；第八晶体管的源极/漏极中的一个与第二布线电性连接，第八晶体管的栅极与第一节点电性连接，第八晶体管的源极/漏极中的另一个与第四节点电性连接；第一电容的一端与第六晶体管的栅极电性连接，第一电容的另一端与第六晶体管的源极/漏极中的另一个电性连接。
在其中一些实施方式中，上拉模块包括第九晶体管，第九晶体管的源极/漏极中的一个与第二布线电性连接，第九晶体管的栅极与第四节点电性连接，第九晶体管的源极/漏极中的另一个与第二节点电性连接。
在其中一些实施方式中，第二上拉稳压模块包括第二电容，第二电容的第一端与第二布线电性连接，第二电容的第二端与第四节点电性连接。
在其中一些实施方式中，下拉稳压模块包括第十晶体管、第十一晶体管以及第三电容；第十晶体管的源极/漏极中的一个与第六布线电性连接，第十晶体管的栅极与第三节点电性连接；第十一晶体管的源极/漏极中的一个与第十晶体管的源极/漏极中的另一个电性连接，第十一晶体管的栅极与第一节点电性连接，第十一晶体管的源极/漏极中的另一个与第五布线电性连接；第三电容的一端与第十一晶体管的源极/漏极中的一个电性连接，第三电容的另一端与第一节点电性连接。
在其中一些实施方式中，第N级栅极驱动单元还包括稳压隔离模块，稳压隔离模块的输入端与第三节点电性连接，稳压隔离模块的控制端与第四布线电性连接，稳压隔离模块的输出端与第一上拉稳压模块电性连接。
在其中一些实施方式中，稳压隔离模块包括第十二晶体管，第十二晶体管的源极/漏极中的一个与第三节点电性连接，第十二晶体管的栅极与第四布线电性连接，第十二晶体管的源极/漏极中的另一个与第一上拉稳压模块电性连接。
在其中一些实施方式中，第四晶体管、第五晶体管均为P沟道型薄膜晶体管。
第二方面，本申请提供一种显示面板，其包括上述任一实施方式中的栅极驱动电路。
 有益效果
本申请提供的栅极驱动电路及显示面板，通过第一上拉稳压模块、第二上拉稳压模块可以提高第四节点的电位稳定性，以及通过下拉稳压模块可以提高第一节点的电位稳定性，进而可以提高栅极驱动电路输出信号的稳定性；该栅极驱动电路的拓扑结构精简，可以减少显示面板的边框占用空间，有利于实现显示面板的窄边框。
 附图说明
图1为本申请实施例提供的栅极驱动电路的一种结构示意图。
图2为图1中栅极驱动电路对应的一种时序示意图。
图3为图1所示栅极驱动电路中部分晶体管的电位变化示意图。
图4为图1中栅极驱动电路对应的另一种时序示意图。
图5为本申请实施例提供的栅极驱动电路的另一种结构示意图。
 本发明的实施方式
为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
请参阅图1至图5，如图1所示，本实施例提供了一种栅极驱动电路，栅极驱动电路包括多个级联的栅极驱动单元，其中，第N级栅极驱动单元包括第一布线、第二布线、第三布线、第四布线、第五布线、第六布线、下拉控制模块10、下拉模块20、上拉控制模块30、第一上拉稳压模块40、上拉模块50、第二上拉稳压模块60以及下拉稳压模块70；下拉控制模块10的输入端与第一布线电性连接，下拉控制模块10的控制端与第二布线和第三布线电性连接，下拉控制模块10的输出端与第一节点Q电性连接；下拉模块20的控制端与第一节点Q电性连接，下拉模块20的输入端与第四布线电性连接，下拉模块20的输出端与第二节点S电性连接以输出对应的第N级扫描信号NSCAN（N）；上拉控制模块30的输入端与第三布线和第四布线电性连接，上拉控制模块30的控制端与第一节点Q和第三布线电性连接，上拉控制模块30的输出端与第三节点T电性连接；第一上拉稳压模块40的输入端与第二布线和第三布线电性连接，第一上拉稳压模块40的控制端与第一节点Q、第三节点T以及第三布线电性连接，第一上拉稳压模块40的输出端与第四节点P电性连接；上拉模块50的输入端与第二布线电性连接，上拉模块50的控制端与第四节点P电性连接，上拉模块50的输出端与第二节点S电性连接；第二上拉稳压模块60的一端与第二布线电性连接，第二上拉稳压模块60的另一端与第四节点P电性连接；以及下拉稳压模块70的输入端与第五布线和第六布线电性连接，下拉稳压模块70的控制端与第一节点Q和第三节点T电性连接，下拉稳压模块70的输出端与第一节点Q电性连接；其中，N为正整数。
可以理解的是，本实施例提供的栅极驱动电路，通过第一上拉稳压模块40、第二上拉稳压模块60可以提高第四节点P的电位稳定性，以及通过下拉稳压模块70可以提高第一节点Q的电位稳定性，进而可以提高栅极驱动电路输出信号的稳定性；该栅极驱动电路的拓扑结构精简，可以减少显示面板的边框占用空间，有利于实现显示面板的窄边框。
需要进行说明的是，在本实施例中，第一布线可以用于传输第N-1级扫描信号NSCAN（N-1）。第二布线可以用于传输时钟信号XCK1。第三布线可以用于传输时钟信号XCK2。第四布线可以用于传输低电位信号L，该低电位信号L可以用于控制P沟道型薄膜晶体管打开。第五布线可以用于传输时钟信号CK2。第六布线可以用于传输高电位信号H，该高电位信号H可以用于控制P沟道型薄膜晶体管关闭。
其中，时钟信号XCK1与时钟信号CK2可以为一组反向的时钟信号。即时钟信号XCK1为高电位时，时钟信号CK2为低电位；即时钟信号XCK1为低电位时，时钟信号CK2为高电位。时钟信号XCK2与时钟信号CK1可以为一组反向的时钟信号。即时钟信号XCK2为高电位时，时钟信号CK1为低电位；即时钟信号XCK2为低电位时，时钟信号CK1为高电位。以上各时钟信号请详细参考后续说明。
其中，当N等于1时，第一布线还可以用于传输起始信号。
其中，第N级扫描信号NSCAN（N）可以与N沟道型薄膜晶体管的栅极连接，其高电位状态的第N级扫描信号NSCAN（N）可以用于打开对应的N沟道型薄膜晶体管。
在其中一个实施例中，第N级栅极驱动单元还包括稳压隔离模块80，稳压隔离模块80的输入端与第三节点T电性连接，稳压隔离模块80的控制端与第四布线电性连接，稳压隔离模块80的输出端与第一上拉稳压模块40电性连接。
在其中一个实施例中，下拉控制模块10包括第一晶体管T11和第二晶体管T1，第一晶体管T11的源极/漏极中的一个与第一布线电性连接，第一晶体管T11的栅极与第二布线电性连接；第二晶体管T1的源极/漏极中的一个与第一晶体管T11的源极/漏极中的另一个电性连接，第二晶体管T1的栅极与第三布线电性连接，第二晶体管T1的源极/漏极中的另一个与第一节点Q直接电性连接。
在其中一个实施例中，下拉模块20包括第三晶体管T12，第三晶体管T12的栅极与第一节点Q电性连接，第三晶体管T12的源极/漏极中的一个与第四布线电性连接，第三晶体管T12的源极/漏极中的另一个与第二节点S电性连接。
在其中一个实施例中，上拉控制模块30包括第四晶体管T2和第五晶体管T3，第四晶体管T2的源极/漏极中的一个与第三布线电性连接，第四晶体管T2的栅极与第一节点Q直接电性连接，第四晶体管T2的源极/漏极中的另一个与第三节点T电性连接；第五晶体管T3的源极/漏极中的一个与第四布线电性连接，第五晶体管T3的栅极与第三布线电性连接，第五晶体管T3的源极/漏极中的另一个与第三节点T电性连接。
在其中一个实施例中，第一上拉稳压模块40包括第六晶体管T7、第七晶体管T8、第八晶体管T10以及第一电容C2；第六晶体管T7的源极/漏极中的一个与第三布线电性连接，第六晶体管T7的栅极与第三节点T电性连接；第七晶体管T8的源极/漏极中的一个与第六晶体管T7的源极/漏极中的另一个电性连接，第七晶体管T8的栅极与第三布线电性连接，第七晶体管T8的源极/漏极中的另一个与第四节点P电性连接；第八晶体管T10的源极/漏极中的一个与第二布线电性连接，第八晶体管T10的栅极与第一节点Q电性连接，第八晶体管T10的源极/漏极中的另一个与第四节点P电性连接；第一电容C2的一端与第六晶体管T7的栅极电性连接，第一电容C2的另一端与第六晶体管T7的源极/漏极中的另一个电性连接。
可以理解的是，由于第一电容C2的存在，第一节点Q的电位和第三节点T的电位更容易维持稳定，进而提高了栅极驱动电路输出信号的稳定性。
在其中一个实施例中，上拉模块50包括第九晶体管T13，第九晶体管T13的源极/漏极中的一个与第二布线电性连接，第九晶体管T13的栅极与第四节点P电性连接，第九晶体管T13的源极/漏极中的另一个与第二节点S电性连接。
在其中一个实施例中，第二上拉稳压模块60包括第二电容C3，第二电容C3的第一端与第二布线电性连接，第二电容C3的第二端与第四节点P电性连接。
可以理解的是，由于第二电容C3的存在，第四节点P的电位更容易保持稳定，进而提高了栅极驱动电路输出信号的稳定性。
在其中一个实施例中，下拉稳压模块70包括第十晶体管T5、第十一晶体管T4以及第三电容C1；第十晶体管T5的源极/漏极中的一个与第六布线电性连接，第十晶体管T5的栅极与第三节点T电性连接；第十一晶体管T4的源极/漏极中的一个与第十晶体管T5的源极/漏极中的另一个电性连接，第十一晶体管T4的栅极与第一节点Q电性连接，第十一晶体管T4的源极/漏极中的另一个与第五布线电性连接；第三电容C1的一端与第十一晶体管T4的源极/漏极中的一个电性连接，第三电容C1的另一端与第一节点Q电性连接。
可以理解的是，由于第三电容C1的存在，第一节点Q的电位更容易稳定地保持，进而提高了栅极驱动电路输出信号的稳定性。
在其中一个实施例中，稳压隔离模块80包括第十二晶体管T6，第十二晶体管T6的源极/漏极中的一个与第三节点T电性连接，第十二晶体管T6的栅极与第四布线电性连接，第十二晶体管T6的源极/漏极中的另一个与第六晶体管T7的栅极电性连接。
可以理解的是，由于第十二晶体管T6的存在，可以使得第三节点T的电位、第十二晶体管T6的源极/漏极中的另一个的电位实现相互隔离，并保持彼此之间电位的稳定性，因此，可以进一步提高栅极驱动电路输出信号的稳定性。
在其中一个实施例中，第一晶体管T11、第二晶体管T1、第三晶体管T12、第四晶体管T2、第五晶体管T3、第六晶体管T7、第七晶体管T8、第八晶体管T10、第九晶体管T13、第十晶体管T5、第十一晶体管T4以及第十二晶体管T6中的至少一个为P沟道型薄膜晶体管。
如图2所示，基于上述实施例，栅极驱动电路在时钟信号XCK1、时钟信号XCK2、时钟信号CK2、第一节点Q的信号以及第四节点P的信号的控制下，在阶段S10和阶段S20中输出了对应的第N-1级扫描信号NSCAN（N-1）、第N级扫描信号NSCAN（N），根据第N-1级扫描信号NSCAN（N-1）、第N级扫描信号NSCAN（N）的仿真波形来看，输出的对应扫描信号的有效脉冲是稳定的。
对应地，如图3所示，第二晶体管T1的栅极-源极电压差Vgs在阶段S10中为0V，在阶段S20中为33V；第二晶体管T1的栅极-漏极电压差Vgd在阶段S10中为5V，在阶段S20中为35V；第二晶体管T1的漏极-源极电压差Vds在阶段S10中为-5V，在阶段S20中为-25V。
第四晶体管T2的栅极-源极电压差Vgs在阶段S10中为0V，在阶段S20中为-34V；第四晶体管T2的栅极-漏极电压差Vgd在阶段S10中为20V，在阶段S20中为-34V；第四晶体管T2的漏极-源极电压差Vds在阶段S10中为-20V，在阶段S20中为0V。
基于此，可以确定第二晶体管T1、第四晶体管T2均可以处于稳定的工作状态，能够提高栅极驱动电路的工作稳定性。
其中，如图4所示，阶段S10还可以包括以下几个阶段：
第一阶段S1：第一布线接入低电位的信号，时钟信号XCK1、时钟信号XCK2均为低电位，第一节点Q的电位、第四节点P的电位均处于低电位, 但不足以打开第三晶体管T12和第九晶体管T13，此时，第二节点S相当于保持悬浮（Floating）状态，第二节点S仍然保持上一阶段输出-9V的低电位。
第二阶段S2：时钟信号XCK2写入高电位，将第五晶体管T3、第十晶体管T5关闭；第六晶体管T7的栅极电位写入+6V，由于C2的耦合作用，第七晶体管T8的源极电位被拉高，第七晶体管T8被打开；同时第八晶体管T10打开; 第四节点P的电位维持-4V，第三晶体管T12、第九晶体管T13仍处于关闭状态，第二节点S仍然为悬浮（Floating）状态，第二节点S保持输出-9V的低电位。
第三阶段S3：时钟信号CK2由+6V变为-9V，第一节点Q的电位由于C1的耦合作用由-6.5V被拉到更低的一个电位，将第三晶体管T12打开；同时第八晶体管T10被打开，第四节点P写入时钟信号XCK1的高电平，将第九晶体管T13关闭，第二节点S输出-9V的低电位。
第四阶段S4：下一个阶段，第一布线需要写入高电平；时钟信号XCK2需提前关闭；时钟信号CK2变为高电平；第一节点Q的电位恢复到-6.5V，时钟信号XCK1变为-9V；第四节点P的电位保持-4V，第二节点S为悬浮（Floating）状态，第二节点S保持输出-9V的低电位。
第五阶段S5：第一布线写入高电位，时钟信号XCK1、时钟信号XCK2均为低电位信号L，将第一晶体管T11、第二晶体管T1以及第五晶体管T3均打开；第一节点Q写入+6V，第三晶体管T12关闭，同时第八晶体管T10关闭；第四节点P由于C3的作用保持上一阶段-4V不变；第二节点S保持悬浮（Floating）状态，第二节点S继续输出-9V的低电位。
第六阶段S6：时钟信号XCK1的高电位状态处于写入前阶段，时钟信号XCK2需提前关闭来保持第四节点P的电位稳定性，第二晶体管T1、第五晶体管T3均关闭；第一节点Q、第四节点P维持上一阶段的电位保持不变，第二节点S继续输出-9V的低电位。
第七阶段S7：时钟信号XCK1的高电位状态处于写入阶段; 时钟信号CK2变为-9V，第六晶体管T7的栅极电位通过C2耦合被拉到更低值，第六晶体管T7被打开；同时第七晶体管T8被打开；第四节点P输出的电位为-6.5V，时钟信号XCK1为+6V，第九晶体管T13完全打开，第二节点S输出+6V的高电位。
第八阶段S8：时钟信号XCK1由+6V变为-9V，第四节点P的电位通过C3 Holding到更低值，使得第九晶体管T13继续保持打开，第二节点S可以输出低电平的时钟信号XCK1，至此，完成了时钟信号XCK1的一个高电位脉冲的完整输出。
在其中一个实施例中，如图5所示，与第N级栅极驱动单元相比，第N+1级栅极驱动单元中，第二布线可以用于传输时钟信号CK2。第三布线可以用于传输时钟信号CK1。第五布线可以用于传输时钟信号XCK1。
可以理解的是，本实施例提供的栅极驱动电路，通过第一上拉稳压模块40、第二上拉稳压模块60可以提高第四节点P的电位稳定性，以及通过下拉稳压模块70可以提高第一节点Q的电位稳定性，进而可以提高栅极驱动电路输出信号的稳定性；该栅极驱动电路的拓扑结构精简，可以减少显示面板的边框占用空间，有利于实现显示面板的窄边框。
在其中一个实施例中，本实施例提供一种显示面板，其包括上述任一实施例中的栅极驱动电路。
可以理解的是，本实施例提供的显示面板，通过第一上拉稳压模块40、第二上拉稳压模块60可以提高第四节点P的电位稳定性，以及通过下拉稳压模块70可以提高第一节点Q的电位稳定性，进而可以提高栅极驱动电路输出信号的稳定性；该栅极驱动电路的拓扑结构精简，可以减少显示面板的边框占用空间，有利于实现显示面板的窄边框。
需要进行说明的是，本实施例中的显示面板可以为AMOLED（Active-Matrix Organic Light-Emitting Diode，有源矩阵有机发光二极体）显示屏，其可以广泛应用于一些需要显示功能的电子设备，例如，可以为手机。
在其中一个实施例中，该显示面板还可以包括像素电路，像素电路可以包括多晶硅薄膜晶体管和氧化物薄膜晶体管，上述任一实施例中的栅极驱动电路可以与该像素电路电性连接，以用于采用高电位的第N级扫描信号NSCAN（N）打开对应的氧化物薄膜晶体管。
需要进行说明的是，本实施例中的像素电路由于采用多晶硅薄膜晶体管与氧化物薄膜晶体管相互搭配的技术构造而成，既具有较高的动态性能，又可以具有较小的漏电流，因此，该像素电路可以以较小的功耗进行工作，当其用于手机时，可以满足手机所需的便携、长续航的使用特点。
可以理解的是，对本领域普通技术人员来说，可以根据本申请的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本申请所附的权利要求的保护范围。

Claims (20)

  1. 一种栅极驱动电路，所述栅极驱动电路包括多个级联的栅极驱动单元，每级所述栅极驱动单元输出相应的扫描信号，其中，所述栅极驱动单元包括：
    第一布线；
    第二布线；
    第三布线；
    第四布线；
    第五布线；
    第六布线；
    下拉控制模块，所述下拉控制模块的输入端与所述第一布线电性连接，所述下拉控制模块的控制端与所述第二布线和所述第三布线电性连接，所述下拉控制模块的输出端与第一节点电性连接；
    下拉模块，所述下拉模块的控制端与所述第一节点电性连接，所述下拉模块的输入端与所述第四布线电性连接，所述下拉模块的输出端与第二节点电性连接以输出对应的扫描信号；
    上拉控制模块，所述上拉控制模块的输入端与所述第三布线和所述第四布线电性连接，所述上拉控制模块的控制端与所述第一节点和所述第三布线电性连接，所述上拉控制模块的输出端与第三节点电性连接；
    第一上拉稳压模块，所述第一上拉稳压模块的输入端与所述第二布线和所述第三布线电性连接，所述第一上拉稳压模块的控制端与所述第一节点、所述第三节点以及所述第三布线电性连接，所述第一上拉稳压模块的输出端与第四节点电性连接；
    上拉模块，所述上拉模块的输入端与所述第二布线电性连接，所述上拉模块的控制端与所述第四节点电性连接，所述上拉模块的输出端与所述第二节点电性连接；
    第二上拉稳压模块，所述第二上拉稳压模块的一端与所述第二布线电性连接，所述第二上拉稳压模块的另一端与所述第四节点电性连接；以及
    下拉稳压模块，所述下拉稳压模块的输入端与所述第五布线和所述第六布线电性连接，所述下拉稳压模块的控制端与所述第一节点和所述第三节点电性连接，所述下拉稳压模块的输出端与所述第一节点电性连接。
  2. 根据权利要求1所述的栅极驱动电路，其中，所述下拉控制模块包括：
    第一晶体管，所述第一晶体管的源极/漏极中的一个与所述第一布线电性连接，所述第一晶体管的栅极与所述第二布线电性连接；和
    第二晶体管，所述第二晶体管的源极/漏极中的一个与所述第一晶体管的源极/漏极中的另一个电性连接，所述第二晶体管的栅极与所述第三布线电性连接，所述第二晶体管的源极/漏极中的另一个与所述第一节点直接电性连接。
  3. 根据权利要求1所述的栅极驱动电路，其中，所述上拉控制模块包括：
    第四晶体管，所述第四晶体管的源极/漏极中的一个与所述第三布线电性连接，所述第四晶体管的栅极与所述第一节点直接电性连接，所述第四晶体管的源极/漏极中的另一个与所述第三节点电性连接；和
    第五晶体管，所述第五晶体管的源极/漏极中的一个与所述第四布线电性连接，所述第五晶体管的栅极与所述第三布线电性连接，所述第五晶体管的源极/漏极中的另一个与所述第三节点电性连接。
  4. 根据权利要求3所述的栅极驱动电路，其中，所述第四晶体管、所述第五晶体管均为P沟道型薄膜晶体管。
  5. 根据权利要求1所述的栅极驱动电路，其中，所述下拉模块包括：
    第三晶体管，所述第三晶体管的栅极与所述第一节点电性连接，所述第三晶体管的源极/漏极中的一个与所述第四布线电性连接，所述第三晶体管的源极/漏极中的另一个与所述第二节点电性连接。
  6. 根据权利要求1所述的栅极驱动电路，其中，所述第一上拉稳压模块包括：
    第六晶体管，所述第六晶体管的源极/漏极中的一个与所述第三布线电性连接，所述第六晶体管的栅极与所述第三节点电性连接；
    第七晶体管，所述第七晶体管的源极/漏极中的一个与所述第六晶体管的源极/漏极中的另一个电性连接，所述第七晶体管的栅极与所述第三布线电性连接，所述第七晶体管的源极/漏极中的另一个与所述第四节点电性连接；
    第八晶体管，所述第八晶体管的源极/漏极中的一个与所述第二布线电性连接，所述第八晶体管的栅极与所述第一节点电性连接，所述第八晶体管的源极/漏极中的另一个与所述第四节点电性连接；以及
    第一电容，所述第一电容的一端与所述第六晶体管的栅极电性连接，所述第一电容的另一端与所述第六晶体管的源极/漏极中的另一个电性连接。
  7. 根据权利要求1所述的栅极驱动电路，其中，所述下拉稳压模块包括：
    第十晶体管，所述第十晶体管的源极/漏极中的一个与所述第六布线电性连接，所述第十晶体管的栅极与所述第三节点电性连接；
    第十一晶体管，所述第十一晶体管的源极/漏极中的一个与所述第十晶体管的源极/漏极中的另一个电性连接，所述第十一晶体管的栅极与所述第一节点电性连接，所述第十一晶体管的源极/漏极中的另一个与所述第五布线电性连接；
    第三电容，所述第三电容的一端与所述第十一晶体管的源极/漏极中的一个电性连接，所述第三电容的另一端与所述第一节点电性连接。
  8. 根据权利要求1所述的栅极驱动电路，其中，所述上拉模块包括：
    第九晶体管，所述第九晶体管的源极/漏极中的一个与所述第二布线电性连接，所述第九晶体管的栅极与所述第四节点电性连接，所述第九晶体管的源极/漏极中的另一个与所述第二节点电性连接。
  9. 根据权利要求1所述的栅极驱动电路，其中，所述第二上拉稳压模块包括：
    第二电容，所述第二电容的第一端与所述第二布线电性连接，所述第二电容的第二端与所述第四节点电性连接。
  10. 一种显示面板，包括如权利要求1所述的栅极驱动电路，其中，所述栅极驱动单元还包括：
    稳压隔离模块，所述稳压隔离模块的输入端与所述第三节点电性连接，所述稳压隔离模块的控制端与所述第四布线电性连接，所述稳压隔离模块的输出端与所述第一上拉稳压模块电性连接。
  11. 根据权利要求10所述的显示面板，其中，所述稳压隔离模块包括：
    第十二晶体管，所述第十二晶体管的源极/漏极中的一个与所述第三节点电性连接，所述第十二晶体管的栅极与所述第四布线电性连接，所述第十二晶体管的源极/漏极中的另一个与所述第一上拉稳压模块电性连接。
  12. 根据权利要求10所述的显示面板，其中，所述下拉控制模块包括：
    第一晶体管，所述第一晶体管的源极/漏极中的一个与所述第一布线电性连接，所述第一晶体管的栅极与所述第二布线电性连接；和
    第二晶体管，所述第二晶体管的源极/漏极中的一个与所述第一晶体管的源极/漏极中的另一个电性连接，所述第二晶体管的栅极与所述第三布线电性连接，所述第二晶体管的源极/漏极中的另一个与所述第一节点直接电性连接。
  13. 根据权利要求10所述的显示面板，其中，所述上拉控制模块包括：
    第四晶体管，所述第四晶体管的源极/漏极中的一个与所述第三布线电性连接，所述第四晶体管的栅极与所述第一节点直接电性连接，所述第四晶体管的源极/漏极中的另一个与所述第三节点电性连接；和
    第五晶体管，所述第五晶体管的源极/漏极中的一个与所述第四布线电性连接，所述第五晶体管的栅极与所述第三布线电性连接，所述第五晶体管的源极/漏极中的另一个与所述第三节点电性连接。
  14. 根据权利要求12所述的显示面板，其中，所述第四晶体管、所述第五晶体管均为P沟道型薄膜晶体管。
  15. 根据权利要求10所述的显示面板，其中，所述下拉模块包括：
    第三晶体管，所述第三晶体管的栅极与所述第一节点电性连接，所述第三晶体管的源极/漏极中的一个与所述第四布线电性连接，所述第三晶体管的源极/漏极中的另一个与所述第二节点电性连接。
  16. 根据权利要求10所述的显示面板，其中，所述第一上拉稳压模块包括：
    第六晶体管，所述第六晶体管的源极/漏极中的一个与所述第三布线电性连接，所述第六晶体管的栅极与所述第三节点电性连接；
    第七晶体管，所述第七晶体管的源极/漏极中的一个与所述第六晶体管的源极/漏极中的另一个电性连接，所述第七晶体管的栅极与所述第三布线电性连接，所述第七晶体管的源极/漏极中的另一个与所述第四节点电性连接；
    第八晶体管，所述第八晶体管的源极/漏极中的一个与所述第二布线电性连接，所述第八晶体管的栅极与所述第一节点电性连接，所述第八晶体管的源极/漏极中的另一个与所述第四节点电性连接；以及
    第一电容，所述第一电容的一端与所述第六晶体管的栅极电性连接，所述第一电容的另一端与所述第六晶体管的源极/漏极中的另一个电性连接。
  17. 根据权利要求10所述的显示面板，其中，所述下拉稳压模块包括：
    第十晶体管，所述第十晶体管的源极/漏极中的一个与所述第六布线电性连接，所述第十晶体管的栅极与所述第三节点电性连接；
    第十一晶体管，所述第十一晶体管的源极/漏极中的一个与所述第十晶体管的源极/漏极中的另一个电性连接，所述第十一晶体管的栅极与所述第一节点电性连接，所述第十一晶体管的源极/漏极中的另一个与所述第五布线电性连接；
    第三电容，所述第三电容的一端与所述第十一晶体管的源极/漏极中的一个电性连接，所述第三电容的另一端与所述第一节点电性连接。
  18. 根据权利要求10所述的显示面板，其中，所述上拉模块包括：
    第九晶体管，所述第九晶体管的源极/漏极中的一个与所述第二布线电性连接，所述第九晶体管的栅极与所述第四节点电性连接，所述第九晶体管的源极/漏极中的另一个与所述第二节点电性连接。
  19. 根据权利要求18所述的显示面板，其中，所述第九晶体管为P沟道型薄膜晶体管。
  20. 根据权利要求10所述的显示面板，其中，所述第二上拉稳压模块包括：
    第二电容，所述第二电容的第一端与所述第二布线电性连接，所述第二电容的第二端与所述第四节点电性连接。
PCT/CN2021/105943 2021-06-18 2021-07-13 栅极驱动电路及显示面板 WO2022262037A1 (zh)

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