WO2022266875A1 - 像素电路、驱动方法和显示装置 - Google Patents

像素电路、驱动方法和显示装置 Download PDF

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Publication number
WO2022266875A1
WO2022266875A1 PCT/CN2021/101757 CN2021101757W WO2022266875A1 WO 2022266875 A1 WO2022266875 A1 WO 2022266875A1 CN 2021101757 W CN2021101757 W CN 2021101757W WO 2022266875 A1 WO2022266875 A1 WO 2022266875A1
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Prior art keywords
circuit
transistor
control
electrically connected
light emission
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Application number
PCT/CN2021/101757
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English (en)
French (fr)
Inventor
黄耀
承天一
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2021/101757 priority Critical patent/WO2022266875A1/zh
Priority to US17/783,238 priority patent/US20240169909A1/en
Priority to CN202180001592.7A priority patent/CN115956265A/zh
Publication of WO2022266875A1 publication Critical patent/WO2022266875A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0248—Precharge or discharge of column electrodes before or after applying exact column voltages
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a pixel circuit, a driving method and a display device.
  • LTPS low temperature polysilicon
  • an embodiment of the present disclosure provides a pixel circuit, including a first reset circuit and a drive circuit;
  • the first reset circuit is respectively electrically connected to the first light emission control line, the reset control line, the first reset voltage line and the first end of the drive circuit, for the first Under the control of the light emission control signal and the reset control signal provided by the reset control line, control writing the first reset voltage provided by the first reset voltage line into the first end of the drive circuit;
  • the driving circuit is used to conduct the connection between the first terminal of the driving circuit and the second terminal of the driving circuit under the control of the potential of the control terminal.
  • the first reset circuit includes a first transistor and a second transistor
  • the control electrode of the first transistor is electrically connected to the first light-emitting control line, and the first electrode of the first transistor is electrically connected to the first end of the driving circuit;
  • the control pole of the second transistor is electrically connected to the reset control line
  • the first pole of the second transistor is electrically connected to the second pole of the first transistor
  • the second pole of the second transistor is electrically connected to the reset control line.
  • the first reset voltage line is electrically connected.
  • the reset control line is a second light emission control line
  • the first transistor is a p-type transistor
  • the second transistor is an n-type transistor
  • the pixel circuit includes a first light emission control circuit and a second light emission control circuit
  • the first light emission control circuit is electrically connected to the first light emission control line, the first terminal of the driving circuit and the first pole of the light emitting element, and is used to control the driving circuit under the control of the first light emission control signal.
  • the first end of the light-emitting element communicates with the first pole;
  • the second light emission control circuit is electrically connected to the second light emission control line, the first voltage terminal and the second end of the driving circuit respectively, and is used for controlling the second light emission control signal provided on the second light emission control line Next, the connection between the first voltage terminal and the second terminal of the driving circuit is controlled.
  • the first reset circuit includes a first transistor and a second transistor
  • the control electrode of the first transistor is electrically connected to the reset control line, and the first electrode of the first transistor is electrically connected to the first terminal of the driving circuit;
  • the control electrode of the second transistor is electrically connected to the first light-emitting control line
  • the first electrode of the second transistor is electrically connected to the second electrode of the first transistor
  • the second electrode of the second transistor is electrically connected to the The first reset voltage line is electrically connected.
  • the reset control line is a second light emission control line
  • the first transistor is an n-type transistor
  • the second transistor is a p-type transistor
  • the pixel circuit includes a first light emission control circuit and a second light emission control circuit
  • the first light emission control circuit is electrically connected to the first light emission control line, the first terminal of the driving circuit and the first pole of the light emitting element, and is used to control the driving circuit under the control of the first light emission control signal.
  • the first end of the light-emitting element communicates with the first pole;
  • the second light emission control circuit is electrically connected to the second light emission control line, the first voltage terminal and the second end of the driving circuit respectively, and is used for controlling the second light emission control signal provided on the second light emission control line Next, the connection between the first voltage terminal and the second terminal of the driving circuit is controlled.
  • the reset control line is a first scan line, and both the first transistor and the second transistor are p-type transistors;
  • the pixel circuit includes a first light emission control circuit and a second light emission control circuit
  • the first light emission control circuit is electrically connected to the second light emission control line, the first terminal of the driving circuit and the first pole of the light emitting element respectively, and is used for the second light emission control signal provided on the second light emission control line Under the control of the control, the communication between the first end of the driving circuit and the first pole of the light-emitting element is controlled;
  • the second light emission control circuit is electrically connected to the first light emission control line, the first voltage terminal and the second end of the drive circuit, and is used to control the first light emission control signal under the control of the first light emission control signal.
  • the voltage end communicates with the second end of the drive circuit.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a second reset circuit
  • the second reset circuit is electrically connected to the second light emission control line, the second reset voltage line and the first pole of the light emitting element, and is used to switch the second reset voltage line to the second pole under the control of the second light emission control signal.
  • the provided second reset voltage is written into the first pole of the light emitting element.
  • the second reset circuit includes a third transistor
  • the control electrode of the third transistor is electrically connected to the second light emission control line
  • the first electrode of the third transistor is electrically connected to the second reset voltage line
  • the second electrode of the third transistor is electrically connected to the second reset voltage line.
  • the first poles of the light emitting elements are electrically connected.
  • the third transistor is an n-type transistor.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a compensation control circuit, a data writing circuit, and an energy storage circuit;
  • the compensation control circuit is electrically connected to the second scanning line, the control terminal of the driving circuit and the first terminal of the driving circuit, and is used to control the second scanning signal provided by the second scanning line.
  • the control end of the driving circuit is connected with the first end of the driving circuit;
  • the data writing circuit is electrically connected to the third scanning line, the data line and the second end of the driving circuit, and is used to write the data on the data line under the control of the third scanning signal provided by the third scanning line. writing voltage into the second terminal of the driving circuit;
  • the energy storage circuit is electrically connected to the control terminal of the drive circuit for storing electric energy.
  • the compensation control circuit includes a fourth transistor, the data writing circuit includes a fifth transistor, the driving circuit includes a driving transistor, and the energy storage circuit includes a storage capacitor;
  • the control pole of the driving transistor is electrically connected to the control terminal of the driving circuit, the first pole of the driving transistor is electrically connected to the first terminal of the driving circuit, and the second pole of the driving transistor is electrically connected to the driving circuit. the second end of the circuit is electrically connected;
  • the control electrode of the fourth transistor is electrically connected to the second scanning line, the first electrode of the fourth transistor is electrically connected to the control electrode of the driving transistor, and the second electrode of the fourth transistor is electrically connected to the the first pole of the driving circuit is electrically connected;
  • the control electrode of the fifth transistor is electrically connected to the third scan line, the first electrode of the fifth transistor is electrically connected to the data line, and the second electrode of the fifth transistor is electrically connected to the driving transistor.
  • the second pole is electrically connected;
  • the first end of the storage capacitor is electrically connected to the control electrode of the driving transistor, and the second end of the storage capacitor is electrically connected to the first voltage end.
  • the first light emission control circuit includes a sixth transistor, and the second light emission control circuit includes a seventh transistor;
  • the control electrode of the sixth transistor is electrically connected to the first light-emitting control line, the first electrode of the sixth transistor is electrically connected to the first terminal of the driving circuit, and the second electrode of the sixth transistor is electrically connected to the first terminal of the driving circuit.
  • the first pole of the light emitting element is electrically connected;
  • the control electrode of the seventh transistor is electrically connected to the second light emission control line, the first electrode of the seventh transistor is electrically connected to the first voltage terminal, and the second electrode of the seventh transistor is electrically connected to the the second end of the driving circuit is electrically connected;
  • the second pole of the light emitting element is electrically connected to the second voltage terminal.
  • the first light emission control circuit includes a sixth transistor, and the second light emission control circuit includes a seventh transistor;
  • the control electrode of the sixth transistor is electrically connected to the second light emission control line, the first electrode of the sixth transistor is electrically connected to the first end of the driving circuit, and the second electrode of the sixth transistor is electrically connected to the first terminal of the driving circuit.
  • the first pole of the light emitting element is electrically connected;
  • the control electrode of the seventh transistor is electrically connected to the first light-emitting control line, the first electrode of the seventh transistor is electrically connected to the first voltage terminal, and the second electrode of the seventh transistor is electrically connected to the the second end of the driving circuit is electrically connected;
  • the second pole of the light emitting element is electrically connected to the second voltage terminal.
  • the embodiment of the present disclosure further provides a driving method, which is applied to the above-mentioned pixel circuit, and the driving method includes: in the refresh reset phase and the hold reset phase, the first reset circuit Under the control of the first light emission control signal provided by the light emission control line and the reset control signal provided by the reset control line, the first reset voltage provided by the first reset voltage line is controlled to be written into the first terminal of the drive circuit .
  • the pixel circuit further includes a compensation control circuit
  • the driving method further includes: in the refresh reset phase, the compensation control circuit controls the communication between the first terminal of the driving circuit and the control terminal of the driving circuit under the control of the second scanning signal provided by the second scanning line, to write the first reset voltage into the control terminal of the drive circuit.
  • the pixel circuit also includes a light-emitting element, a compensation control circuit, a data writing circuit, an energy storage circuit, a first light-emitting control circuit, and a second light-emitting control circuit;
  • the refresh charging phase and the refresh light emitting phase after the phase; the driving method also includes:
  • the data writing circuit writes the data voltage on the data line into the second end of the driving circuit under the control of the third scanning signal provided by the third scanning line
  • the compensation control circuit writes the data voltage on the data line into the second terminal of the driving circuit under the control of the second scanning signal Under the control of the first terminal of the control drive circuit and the control terminal of the drive circuit are connected to charge the energy storage circuit through the data voltage
  • the first light emission control circuit controls the communication between the first end of the driving circuit and the first pole of the light emitting element
  • the second light emission control circuit controls the communication between the first voltage end and the second end of the driving circuit
  • drives The circuit drives the light emitting element to emit light
  • the pixel circuit further includes a first light-emitting control circuit and a light-emitting element; the reset control line is a second light-emitting control line; the first light-emitting control circuit is electrically connected to the first light-emitting control line; the The drive method also includes:
  • the first light emission control circuit controls the communication between the first end of the driving circuit and the first pole of the light emitting element, so as to control the A reset voltage is written into the first pole of the light emitting element.
  • the pixel circuit further includes a first light emission control circuit, a second reset circuit and a light emitting element; the first light emission control circuit is electrically connected to the second light emission control line; the driving method further includes:
  • the first light emission control circuit controls the disconnection between the first end of the driving circuit and the first pole of the light emitting element
  • the second reset circuit Under the control of the second light-emitting control signal, the second reset voltage is written into the first electrode of the light-emitting element.
  • the maintaining display period further includes a maintaining light-emitting period arranged after the maintaining reset period; the driving method further includes:
  • the first light emission control circuit controls the communication between the first terminal of the driving circuit and the first pole of the light emitting element
  • the second light emission control circuit controls the communication between the first voltage terminal and the second terminal of the driving circuit.
  • the driving circuit drives the light-emitting element to emit light.
  • the driving method described in at least one embodiment of the present disclosure further includes:
  • the frequency of the signal is such that the frequency of the first light emission control signal and the frequency of the second light emission control signal are greater than a predetermined frequency.
  • the driving method described in at least one embodiment of the present disclosure further includes:
  • an embodiment of the present disclosure provides a display device, including the above-mentioned pixel circuit.
  • FIG. 1 is a structural diagram of a pixel circuit described in an embodiment of the present disclosure
  • Fig. 2 is a structural diagram of a pixel circuit described in at least one embodiment of the present disclosure
  • Fig. 3 is a structural diagram of a pixel circuit described in at least one embodiment of the present disclosure.
  • Fig. 4 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Fig. 5 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Fig. 6 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG. 7 is a structural diagram of a pixel circuit described in at least one embodiment of the present disclosure.
  • Fig. 8 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG. 9 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Fig. 10 is a working timing diagram of the pixel circuit described in at least one embodiment of the present disclosure.
  • Fig. 11 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG. 12 is a working timing diagram of at least one embodiment of the pixel circuit shown in FIG. 11;
  • FIG. 13 is another working timing diagram of at least one embodiment of the pixel circuit shown in FIG. 11 .
  • the transistors used in all the embodiments of the present disclosure may be triodes, thin film transistors or field effect transistors or other devices with the same characteristics.
  • one pole is called the first pole, and the other pole is called the second pole.
  • the control electrode when the transistor is a triode, can be a base, the first electrode can be a collector, and the second electrode can be an emitter; or, the control electrode can be a base pole, the first pole may be an emitter, and the second pole may be a collector.
  • the control electrode when the transistor is a thin film transistor or a field effect transistor, the control electrode may be a gate, the first electrode may be a drain, and the second electrode may be a source; or, the The control electrode may be a gate, the first electrode may be a source, and the second electrode may be a drain.
  • the pixel circuit described in the embodiment of the present disclosure includes a first reset circuit 11 and a drive circuit 12;
  • the first reset circuit 11 is respectively electrically connected to the first light emission control line E1, the reset control line R1, the first reset voltage line I1 and the first end of the drive circuit 12, for controlling the first light emission. Under the control of the first lighting control signal provided by the line E1 and the reset control signal provided by the reset control line R1, the first reset voltage Vi1 provided by the first reset voltage line I1 is controlled to be written into the drive circuit the first end of 12;
  • the driving circuit 12 is used for conducting the connection between the first terminal of the driving circuit 12 and the second terminal of the driving circuit 12 under the control of the potential of the control terminal.
  • the pixel circuit described in the embodiment of the present disclosure writes the first reset voltage Vi1 into the first end of the drive circuit 12 through the first reset circuit 11 under the control of the first light emission control signal and the reset control signal, and through the compensation With the cooperation of the control circuit, the first reset voltage Vi1 can be written into the control terminal of the drive circuit 12 in the refresh reset phase and the hold reset phase, so as to provide a new structure of the pixel circuit, and also realize the key Node reset.
  • the refresh display cycle may include a refresh reset phase
  • the hold display cycle may include a hold reset phase.
  • the first The reset circuit 11 writes Vi1 into the first terminal of the drive circuit 12 under the control of the first light-emitting control signal and the reset control signal.
  • the first reset circuit may include a first transistor and a second transistor
  • the control electrode of the first transistor is electrically connected to the first light-emitting control line, and the first electrode of the first transistor is electrically connected to the first end of the driving circuit;
  • the control pole of the second transistor is electrically connected to the reset control line
  • the first pole of the second transistor is electrically connected to the second pole of the first transistor
  • the second pole of the second transistor is electrically connected to the reset control line.
  • the first reset voltage line is electrically connected.
  • the reset control line is a second light emission control line
  • the first transistor is a p-type transistor
  • the second transistor is an n-type transistor
  • the pixel circuit includes a first light emission control circuit and a second light emission control circuit
  • the first light emission control circuit is electrically connected to the first light emission control line, the first terminal of the driving circuit and the first pole of the light emitting element, and is used to control the driving circuit under the control of the first light emission control signal.
  • the first end of the light-emitting element communicates with the first pole;
  • the second light emission control circuit is electrically connected to the second light emission control line, the first voltage terminal and the second end of the driving circuit respectively, and is used for controlling the second light emission control signal provided on the second light emission control line Next, the connection between the first voltage terminal and the second terminal of the driving circuit is controlled.
  • the reset control line is the second light emission control line E2;
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a Light emission control circuit 21 and second light emission control circuit 22;
  • the first reset circuit 11 includes a first transistor T1 and a second transistor T2;
  • the gate of the first transistor T1 is electrically connected to the first light emission control line E1, and the source of the first transistor T1 is electrically connected to the first terminal of the driving circuit 12;
  • the gate of the second transistor T2 is electrically connected to the second light emission control line E2, the source of the second transistor T2 is electrically connected to the drain of the first transistor T1, and the drain of the second transistor T2 The drain is electrically connected to the first reset voltage line I1;
  • the first light emission control circuit 21 is electrically connected to the first light emission control line E1, the first end of the driving circuit 12 and the first pole of the light emitting element 10, and is used to control the light emission under the control of the first light emission control signal.
  • the first end of the driving circuit 12 is connected to the first pole of the light emitting element 10;
  • the second light emission control circuit 21 is electrically connected to the second light emission control line E2, the first voltage terminal V1 and the second end of the driving circuit 12 respectively, and is used for the second light emission provided by the second light emission control line E2. Under the control of the light emission control signal, control the communication between the first voltage terminal V1 and the second terminal of the driving circuit 12;
  • T1 is a p-type transistor
  • T2 is an n-type transistor
  • At least one embodiment of the pixel circuit shown in FIG. 2 of the present disclosure is working.
  • the potential of the first light emission control signal is a low voltage
  • the potential of the second light emission control signal is high.
  • voltage, E1 provides a low-voltage signal
  • E2 provides a high-voltage signal
  • T1 and T2 are turned on
  • the first light-emitting control circuit 21 controls the first end of the driving circuit 12 and the first end of the light-emitting element 10 under the control of the first light-emitting control signal.
  • the poles are connected to provide the first reset voltage Vi1 provided by the first reset voltage line I1 to the first pole of the light-emitting element 10 to clear the residual charge of the first pole of the light-emitting element 10 .
  • T1 may be a low-temperature polysilicon thin film transistor
  • T2 may be an IGZO (indium gallium zinc oxide) thin film transistor.
  • the first reset circuit may include a first transistor and a second transistor
  • the control electrode of the first transistor is electrically connected to the reset control line, and the first electrode of the first transistor is electrically connected to the first terminal of the driving circuit;
  • the control electrode of the second transistor is electrically connected to the first light-emitting control line
  • the first electrode of the second transistor is electrically connected to the second electrode of the first transistor
  • the second electrode of the second transistor is electrically connected to the The first reset voltage line is electrically connected.
  • the reset control line is a second light emission control line
  • the first transistor is an n-type transistor
  • the second transistor is a p-type transistor
  • the pixel circuit includes a first light emission control circuit and a second light emission control circuit
  • the first light emission control circuit is electrically connected to the first light emission control line, the first terminal of the driving circuit and the first pole of the light emitting element, and is used to control the driving circuit under the control of the first light emission control signal.
  • the first end of the light-emitting element communicates with the first pole;
  • the second light emission control circuit is electrically connected to the second light emission control line, the first voltage terminal and the second end of the driving circuit respectively, and is used for controlling the second light emission control signal provided on the second light emission control line Next, the communication between the first voltage terminal and the second terminal of the driving circuit is controlled.
  • the reset control line is the second light emission control line E2;
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a Light emission control circuit 21 and second light emission control circuit 22;
  • the first reset circuit 11 includes a first transistor T1 and a second transistor T2;
  • the gate of the first transistor T1 is electrically connected to the second light emission control line E2, and the source of the first transistor T1 is electrically connected to the first end of the driving circuit 12;
  • the gate of the second transistor T2 is electrically connected to the first light emission control line E1, the source of the second transistor T2 is electrically connected to the drain of the first transistor T1, and the drain of the second transistor T2 The drain is electrically connected to the first reset voltage line I1;
  • the first light emission control circuit 21 is electrically connected to the first light emission control line E1, the first end of the driving circuit 12 and the first pole of the light emitting element 10, and is used to control the light emission under the control of the first light emission control signal.
  • the first end of the driving circuit 12 is connected to the first pole of the light emitting element 10;
  • the second light emission control circuit 21 is electrically connected to the second light emission control line E2, the first voltage terminal V1 and the second end of the driving circuit 12 respectively, and is used for the second light emission provided by the second light emission control line E2. Under the control of the light emission control signal, control the communication between the first voltage terminal V1 and the second terminal of the driving circuit 12;
  • T1 is an n-type transistor
  • T2 is a p-type transistor
  • the potential of the first light-emitting control signal is low and the potential of the second light-emitting control signal is high during the refresh reset phase and the hold reset phase.
  • voltage, E1 provides a low-voltage signal
  • E2 provides a high-voltage signal
  • T1 and T2 are turned on
  • the first light-emitting control circuit 21 controls the first end of the driving circuit 12 and the first end of the light-emitting element 10 under the control of the first light-emitting control signal.
  • the poles are connected to provide the first reset voltage Vi1 provided by the first reset voltage line I1 to the first pole of the light-emitting element 10 to clear the residual charge of the first pole of the light-emitting element 10 .
  • T2 may be a low-temperature polysilicon thin film transistor
  • T1 may be an IGZO (indium gallium zinc oxide) thin film transistor.
  • the first light emission control circuit includes a sixth transistor, and the second light emission control circuit includes a seventh transistor;
  • the control electrode of the sixth transistor is electrically connected to the first light-emitting control line, the first electrode of the sixth transistor is electrically connected to the first terminal of the driving circuit, and the second electrode of the sixth transistor is electrically connected to the first terminal of the driving circuit.
  • the first pole of the light emitting element is electrically connected;
  • the control electrode of the seventh transistor is electrically connected to the second light emission control line, the first electrode of the seventh transistor is electrically connected to the first voltage terminal, and the second electrode of the seventh transistor is electrically connected to the the second end of the drive circuit is electrically connected;
  • the second pole of the light emitting element is electrically connected to the second voltage terminal.
  • the reset control line is a first scan line, and both the first transistor and the second transistor are p-type transistors;
  • the pixel circuit includes a first light emission control circuit and a second light emission control circuit
  • the first light emission control circuit is electrically connected to the second light emission control line, the first terminal of the driving circuit and the first pole of the light emitting element respectively, and is used for the second light emission control signal provided on the second light emission control line Under the control of the control, the communication between the first end of the driving circuit and the first pole of the light-emitting element is controlled;
  • the second light emission control circuit is electrically connected to the first light emission control line, the first voltage terminal and the second end of the drive circuit, and is used to control the first light emission control signal under the control of the first light emission control signal.
  • the voltage end communicates with the second end of the drive circuit.
  • the reset control line is the first scanning line S1; the pixel circuit described in at least one embodiment of the present disclosure also includes a first light emitting A control circuit 21 and a second lighting control circuit 22;
  • the first reset circuit 11 includes a first transistor T1 and a second transistor T2;
  • the gate of the first transistor T1 is electrically connected to the first light emission control line E1, and the source of the first transistor T1 is electrically connected to the first terminal of the driving circuit 12;
  • the gate of the second transistor T2 is electrically connected to the first scanning line S1
  • the source of the second transistor T2 is electrically connected to the drain of the first transistor T1
  • the drain of the second transistor T2 is electrically connected to the first scanning line S1.
  • the first reset voltage line I1 is electrically connected;
  • the first light emission control circuit 21 is electrically connected to the second light emission control line E2, the first end of the driving circuit 12 and the first pole of the light emitting element 10 respectively, and is used for the second light emission provided on the second light emission control line E2. Under the control of the light-emitting control signal, control the communication between the first end of the driving circuit 12 and the first pole of the light-emitting element 10;
  • the second light emission control circuit 22 is electrically connected to the first light emission control line E1, the first voltage terminal V1 and the second end of the driving circuit 12 respectively, and is used for the second light emission provided by the first light emission control line E1. Under the control of the light emission control signal, control the communication between the first voltage terminal V1 and the second terminal of the driving circuit 12;
  • T1 is a p-type transistor
  • T2 is a p-type transistor
  • T1 and T2 may be low temperature polysilicon thin film transistors.
  • At least one embodiment of the pixel circuit shown in FIG. 4 of the present disclosure is working.
  • the potential of the first light-emitting control signal provided by E1 is a low voltage
  • the first scan signal provided by S1 The potential of the signal is a low voltage
  • T1 and T2 are turned on, so as to write the first reset voltage Vi1 provided by the first reset voltage line into the first terminal of the driving circuit 12 .
  • the reset control line is the first scanning line S1; the pixel circuit described in at least one embodiment of the present disclosure also includes a first light emitting A control circuit 21 and a second lighting control circuit 22;
  • the first reset circuit 11 includes a first transistor T1 and a second transistor T2;
  • the gate of the first transistor T1 is electrically connected to the first scanning line S1, and the source of the first transistor T1 is electrically connected to the first terminal of the driving circuit 12;
  • the gate of the second transistor T2 is electrically connected to the first light emission control line E1, the source of the second transistor T2 is electrically connected to the drain of the first transistor T1, and the drain of the second transistor T2 electrically connected to the first reset voltage line I1;
  • the first light emission control circuit 21 is electrically connected to the second light emission control line E2, the first end of the driving circuit 12 and the first pole of the light emitting element 10 respectively, and is used for the second light emission provided on the second light emission control line E2. Under the control of the light emission control signal, control the communication between the first end of the driving circuit 12 and the first pole of the light emitting element 10;
  • the second light emission control circuit 22 is electrically connected to the first light emission control line E1, the first voltage terminal V1 and the second end of the driving circuit 12 respectively, and is used for the second light emission provided by the first light emission control line E1. Under the control of the light emission control signal, control the communication between the first voltage terminal V1 and the second terminal of the driving circuit 12;
  • T1 is a p-type transistor
  • T2 is a p-type transistor
  • T1 and T2 may be low temperature polysilicon thin film transistors.
  • At least one embodiment of the pixel circuit shown in FIG. 5 of the present disclosure is working.
  • the potential of the first light-emitting control signal provided by E1 is a low voltage
  • the first scanning signal provided by S1 The potential of the signal is a low voltage
  • T1 and T2 are turned on, so as to write the first reset voltage Vi1 provided by the first reset voltage line into the first terminal of the driving circuit 12 .
  • the first light emission control circuit includes a sixth transistor, and the second light emission control circuit includes a seventh transistor;
  • the control electrode of the sixth transistor is electrically connected to the second light emission control line, the first electrode of the sixth transistor is electrically connected to the first end of the driving circuit, and the second electrode of the sixth transistor is electrically connected to the first terminal of the driving circuit.
  • the first pole of the light emitting element is electrically connected;
  • the control electrode of the seventh transistor is electrically connected to the first light-emitting control line, the first electrode of the seventh transistor is electrically connected to the first voltage terminal, and the second electrode of the seventh transistor is electrically connected to the the second end of the driving circuit is electrically connected;
  • the second pole of the light emitting element is electrically connected to the second voltage terminal.
  • the pixel circuit described in at least one embodiment of the present disclosure may further include a second reset circuit 40 ;
  • the second reset circuit 40 is electrically connected to the second light emission control line E2, the second reset voltage line I2 and the first pole of the light emitting element 10 respectively, and is used for the second light emission control provided on the second light emission control line E2. Under the control of the signal, the second reset voltage Vi2 provided by the second reset voltage line I2 is written into the first electrode of the light emitting element 10 .
  • At least one embodiment of the pixel circuit shown in FIG. 6 of the present disclosure is in operation, in the refresh reset phase, refresh charge phase and hold reset phase, the second reset circuit 40 is controlled by the second light emission control signal, Write Vi2 into the first pole of the light-emitting element 10 to clear the residual charge of the first pole of the light-emitting element 10 .
  • the second reset circuit includes a third transistor
  • the control electrode of the third transistor is electrically connected to the second light emission control line
  • the first electrode of the third transistor is electrically connected to the second reset voltage line
  • the second electrode of the third transistor is electrically connected to the second reset voltage line.
  • the first poles of the light emitting elements are electrically connected.
  • the third transistor is an n-type transistor, and the third transistor may be an IGZO thin film transistor.
  • the pixel circuit described in at least one embodiment of the present disclosure may further include a compensation control circuit, a data writing circuit, and an energy storage circuit;
  • the compensation control circuit is electrically connected to the second scanning line, the control terminal of the driving circuit and the first terminal of the driving circuit, and is used to control the second scanning signal provided by the second scanning line.
  • the control end of the driving circuit is connected with the first end of the driving circuit;
  • the data writing circuit is electrically connected to the third scanning line, the data line and the second end of the driving circuit, and is used to write the data on the data line under the control of the third scanning signal provided by the third scanning line. writing voltage into the second terminal of the driving circuit;
  • the energy storage circuit is electrically connected to the control terminal of the drive circuit for storing electric energy.
  • the compensation control circuit 51 is electrically connected to the second scanning line S2, the control terminal of the driving circuit 12, and the first terminal of the driving circuit 12, and is used for controlling the second scanning signal provided on the second scanning line S2. Under control, controlling the communication between the control terminal of the driving circuit 12 and the first terminal of the driving circuit 12;
  • the data writing circuit 52 is electrically connected to the third scanning line S3, the data line D0 and the second end of the driving circuit 12, and is used to write writing the data voltage on the data line D0 into the second terminal of the driving circuit 12;
  • the energy storage circuit 53 is electrically connected to the control terminal of the drive circuit for storing electric energy.
  • the compensation control circuit 51 controls the control terminal of the driving circuit 12 and the control terminal of the driving circuit 12 under the control of the second scanning signal.
  • the first ends are connected to each other, so as to write the first reset voltage Vi into the control end of the drive circuit 12, so that when the refresh charging phase starts, the drive circuit 12 can turn on its control end under the control of the potential of its control end. communication between the first end and the second end;
  • the data writing circuit 52 writes the data voltage into the second terminal of the driving circuit 12 under the control of the third scanning signal, so as to charge the energy storage circuit 53 with the data voltage, and improve the control of the driving circuit 12. terminal until the driving circuit 12 disconnects the connection between the first terminal and the second terminal under the control of the potential of the control terminal.
  • the compensation control circuit 51 is electrically connected to the second scanning line S2, the control terminal of the driving circuit 12, and the first terminal of the driving circuit 12, and is used for controlling the second scanning signal provided on the second scanning line S2. Under control, controlling the communication between the control terminal of the driving circuit 12 and the first terminal of the driving circuit 12;
  • the data writing circuit 52 is electrically connected to the third scanning line S3, the data line D0 and the second end of the driving circuit 12, and is used to write writing the data voltage on the data line D0 into the second terminal of the driving circuit 12;
  • the energy storage circuit 53 is electrically connected to the control terminal of the drive circuit for storing electric energy.
  • the compensation control circuit 51 controls the control terminal of the driving circuit 12 and the control terminal of the driving circuit 12 under the control of the second scanning signal.
  • the first ends are connected to each other, so as to write the first reset voltage Vi into the control end of the drive circuit 12, so that when the refresh charging phase starts, the drive circuit 12 can turn on its control end under the control of the potential of its control end. communication between the first end and the second end;
  • the data writing circuit 52 writes the data voltage into the second terminal of the driving circuit 12 under the control of the third scanning signal, so as to charge the energy storage circuit 53 with the data voltage, and improve the control of the driving circuit 12. terminal until the driving circuit 12 disconnects the connection between the first terminal and the second terminal under the control of the potential of the control terminal.
  • the compensation control circuit includes a fourth transistor, the data writing circuit includes a fifth transistor, the driving circuit includes a driving transistor, and the energy storage circuit includes a storage capacitor;
  • the control pole of the driving transistor is electrically connected to the control terminal of the driving circuit, the first pole of the driving transistor is electrically connected to the first terminal of the driving circuit, and the second pole of the driving transistor is electrically connected to the driving circuit. the second end of the circuit is electrically connected;
  • the control electrode of the fourth transistor is electrically connected to the second scanning line, the first electrode of the fourth transistor is electrically connected to the control electrode of the driving transistor, and the second electrode of the fourth transistor is electrically connected to the the first pole of the driving circuit is electrically connected;
  • the control electrode of the fifth transistor is electrically connected to the third scan line, the first electrode of the fifth transistor is electrically connected to the data line, and the second electrode of the fifth transistor is electrically connected to the driving transistor.
  • the second pole is electrically connected;
  • the first end of the storage capacitor is electrically connected to the control electrode of the driving transistor, and the second end of the storage capacitor is electrically connected to the first voltage end.
  • the fourth transistor may be an n-type transistor, the fifth transistor and the driving transistor are p-type transistors; the fourth transistor is an IGZO thin film transistor, and the fifth transistor and the driving transistor are low temperature polysilicon thin film transistors.
  • the light-emitting element is an organic light-emitting diode O1;
  • the compensation control circuit 51 includes a fourth transistor T4, and the data writing
  • the circuit 52 includes a fifth transistor T5, the driving circuit 12 includes a driving transistor T0, and the energy storage circuit 53 includes a storage capacitor C1;
  • the gate of the drive transistor T0 is electrically connected to the control terminal of the drive circuit 12
  • the drain of the drive transistor T0 is electrically connected to the first end of the drive circuit 12
  • the source of the drive transistor T0 is electrically connected to the control terminal of the drive circuit 12.
  • the second end of the driving circuit 12 is electrically connected;
  • the gate of the fourth transistor T4 is electrically connected to the second scanning line S2, the source of the fourth transistor T4 is electrically connected to the gate of the driving transistor T0, and the drain of the fourth transistor T4 electrically connected to the drain of the driving transistor;
  • the gate of the fifth transistor T5 is electrically connected to the third scan line S3, the source of the fifth transistor T5 is electrically connected to the data line D0, and the drain of the fifth transistor T5 is electrically connected to the The source of the drive transistor T0 is electrically connected;
  • the first end of the storage capacitor C1 is electrically connected to the gate of the driving transistor T0, and the second end of the storage capacitor C1 is electrically connected to a high voltage end; the high voltage end is used to provide a high voltage signal VDD;
  • the first light emission control circuit includes a sixth transistor T6, and the second light emission control circuit 22 includes a seventh transistor T7;
  • the gate of the sixth transistor T6 is electrically connected to the first light emission control line E1, the source of the sixth transistor T6 is electrically connected to the drain of the driving transistor T0, and the drain of the sixth transistor T6 The pole is electrically connected to the anode of O1;
  • the gate of the seventh transistor T7 is electrically connected to the second light emission control line E2, the source of the seventh transistor T7 is electrically connected to the high voltage terminal, and the drain of the seventh transistor T7 is electrically connected to the The source electrode of the driving transistor T0 is electrically connected;
  • the cathode of O1 is electrically connected to the low voltage terminal; the low voltage terminal is used to provide a low voltage signal VSS.
  • the first voltage terminal is a high voltage terminal
  • the second voltage terminal is a low voltage terminal
  • T1, T0, T5, T6 and T7 are p-type transistors
  • T2 and T4 are n-type transistors
  • T1, T0, T5, T6 and T7 are low-temperature polysilicon thin film transistors
  • T2 and T4 are IGZO (indium gallium zinc oxide) thin film transistors.
  • the refresh display cycle includes a refresh reset phase t1, a refresh charge phase t2, and a refresh light emission phase t3;
  • the potential of the first light emission control signal provided by E1 is a low voltage
  • the potential of the second light emission control signal provided by E2 is a high voltage
  • the potential of the second scanning signal provided by S2 is a high voltage
  • the potential of the second light emission control signal provided by S2 is a high voltage.
  • the potential of the third scanning signal is a high voltage, T1 is turned on, T2 is turned on, and T4 is turned on, so as to write the first reset voltage Vi1 provided by I1 into the gate of T0, so that when the refresh charging phase t2 starts, T0 can be turned on ; T6 is turned on to write Vi1 into the anode of O1, and remove the residual charge of the anode of O1; T7 is turned off, and T5 is turned off;
  • the potential of the first light emission control signal provided by E1 is a high voltage
  • the potential of the second light emission control signal provided by E2 is a high voltage
  • the potential of the second scan signal provided by S2 is a high voltage
  • the potential of the second light emission control signal provided by S3 is a high voltage.
  • the potential of the third scanning signal is a low voltage, T1 is turned off, T2 is turned on, T4 is turned on, T5 is turned on; T6 is turned off, and T7 is turned off;
  • T0 is turned on, and the data voltage Vd on the data line D0 charges C1 through T5, T0 and T4 to increase the potential of the gate of T0 until the potential of T0 rises to Vd+Vth, and Vth is The threshold voltage of T0, T0 is turned off, and charging stops;
  • the potential of the first lighting control signal provided by E1 is a low voltage
  • the potential of the second lighting control signal provided by E2 is a low voltage
  • the potential of the second scanning signal provided by S2 is a low voltage
  • the potential of the second scanning signal provided by S3 is a low voltage.
  • the potential of the third scanning signal is a high voltage
  • T4 is turned off
  • T5 is turned off
  • T1 is turned on
  • T2 is turned off
  • T6 and T7 are turned on
  • T0 drives O1 to emit light
  • the light emitting current I of O1 is equal to K (Vdd-Vd) 2
  • K is the current coefficient of T0
  • Vdd is the voltage value of VDD.
  • the frequency of the first light emission control signal may be the same as that of the second light emission control signal
  • the duty ratio of the first light emission control signal may be the same as that of the second light emission control signal
  • the first light emission control signal may be the same as the duty cycle of the second light emission control signal.
  • the signal is delayed for a period of time from the second light emission control signal, and the first light emission control signal and the second light emission control signal may be adjacent two-stage light emission control signals output by a light emission control signal generation circuit;
  • the first scan signal provided by S1 and the third scan signal provided by S3 may be active low scan signals, and the second scan signal provided by S2 may be active high scan signals.
  • the maintaining display period includes maintaining a reset phase and maintaining a light emitting phase
  • the potential of the first light-emitting control signal provided by E1 is a low voltage
  • the potential of the second light-emitting control signal provided by E2 is a high voltage
  • the potential of the second scanning signal provided by S2 is a high voltage
  • the potential of the second scan signal provided by S3 is a high voltage.
  • the potential of the third scanning signal is a high voltage
  • T1 is turned on
  • T2 is turned on
  • T6 is turned on, so as to write Vi1 into the anode of O1, and remove the residual charge of the anode of O1
  • T7 is turned off
  • T5 is turned off;
  • the potential of the first light emission control signal provided by E1 is a low voltage
  • the potential of the second light emission control signal provided by E2 is a low voltage
  • the potential of the second scan signal provided by S2 is a low voltage
  • the potential of the second light emission control signal provided by S3 is a low voltage.
  • the potential of the three-scanning signal is a high voltage, T4 is turned off, T5 is turned off, T1 is turned on, T2 is turned off, T6 and T7 are turned on, T0 drives O1 to emit light, and the luminous current I of O1 is equal to K(Vdd-Vd)2; K is The current coefficient of T0, Vdd is the voltage value of VDD; wherein, Vd is the data voltage provided by the data line D0 in the adjacent previous refreshing charging phase.
  • the driving current of the light emitting element 11 is still related to the data voltage in the refresh charging phase in the immediately preceding refresh display cycle.
  • the display panel to which the pixel circuit is applied displays at low brightness, that is, when the display brightness range of the display panel corresponds to the maximum
  • the frequency of the first light-emitting control signal and the frequency of the second light-emitting control signal can be increased so that the frequency of the first light-emitting control signal and the frequency of the second light-emitting control signal are greater than the predetermined Frequency, set the frequency by increasing the potential of the anode to O1, to improve the flicker (flicker) phenomenon under low brightness.
  • the potential of the anode of O1 is set by the transistor controlled by E1 and the transistor controlled by E2, instead of the transistor controlled by the scan signal is O1
  • the potential of the anode of the pixel circuit is set so that when the display panel to which the pixel circuit is applied works at a low frequency, the potential of the scanning signal does not need to be an effective voltage while maintaining the display period, which reduces the IC (integrated circuit) at low frequency ) power consumption.
  • the predetermined frequency may be, for example, 50 Hz, but it is not limited thereto.
  • the displaying of the display panel at low brightness may refer to: a maximum brightness corresponding to a display brightness range of the display panel is less than or equal to a predetermined brightness.
  • the predetermined brightness may be greater than or equal to 100 nits and less than or equal to 140 nits, for example, the predetermined brightness may be 120 nits.
  • the display brightness range can be adjusted by pulling a brightness adjustment bar of the mobile phone.
  • the display brightness range of the display panel may refer to: the display brightness of the display panel is greater than or equal to the first brightness and less than or equal to the second brightness, and the second brightness is the maximum brightness corresponding to the display brightness range ;
  • the second brightness may refer to: the maximum brightness that the display panel can display;
  • the first brightness may refer to: the minimum brightness that the display panel can display.
  • the display brightness range of the display panel is within a predetermined brightness range, which does not mean that when the display panel displays a predetermined picture, the display brightness range of the display panel is within a predetermined brightness range, but It means that when the display panel displays any picture, the display brightness range of the display panel is within a predetermined brightness range.
  • the light emitting element is an organic light emitting diode O1;
  • the second reset circuit 40 includes a third transistor T3;
  • the compensation control circuit 51 includes a fourth transistor T4, the data writing circuit 52 includes a fifth transistor T5, the driving circuit 12 includes a driving transistor T0, and the energy storage circuit includes a storage capacitor C1;
  • the gate of the third transistor T3 is electrically connected to the second light emission control line E2, the source of the third transistor T3 is electrically connected to the second reset voltage line I2, and the third transistor T3 The drain is electrically connected to the anode of O1;
  • the gate of the drive transistor T0 is electrically connected to the control terminal of the drive circuit 12
  • the drain of the drive transistor T0 is electrically connected to the first end of the drive circuit 12
  • the source of the drive transistor T0 is electrically connected to the control terminal of the drive circuit 12.
  • the second end of the driving circuit 12 is electrically connected;
  • the gate of the fourth transistor T4 is electrically connected to the second scanning line S2, the source of the fourth transistor T4 is electrically connected to the gate of the driving transistor T0, and the drain of the fourth transistor T4 electrically connected to the drain of the driving transistor;
  • the gate of the fifth transistor T5 is electrically connected to the third scan line S3, the source of the fifth transistor T5 is electrically connected to the data line D0, and the drain of the fifth transistor T5 is electrically connected to the The source of the drive transistor T0 is electrically connected;
  • the first end of the storage capacitor C1 is electrically connected to the gate of the driving transistor T0, and the second end of the storage capacitor C1 is electrically connected to a high voltage end; the high voltage end is used to provide a high voltage signal VDD;
  • the first light emission control circuit includes a sixth transistor T6, and the second light emission control circuit 22 includes a seventh transistor T7;
  • the gate of the sixth transistor T6 is electrically connected to the second light emission control line E2, the source of the sixth transistor T6 is electrically connected to the drain of the driving transistor T0, and the drain of the sixth transistor T6
  • the pole is electrically connected to the anode of O1;
  • the gate of the seventh transistor T7 is electrically connected to the first light emission control line E1, the source of the seventh transistor T7 is electrically connected to the high voltage terminal, and the drain of the seventh transistor T7 is electrically connected to the The source electrode of the driving transistor T0 is electrically connected;
  • the cathode of O1 is electrically connected to the low voltage terminal; the low voltage terminal is used to provide a low voltage signal VSS.
  • T1, T2, T6, T7, T0 and T5 are p-type transistors
  • T3 and T4 are n-type transistors
  • T1, T2, T6, T7, T0 and Both T5 are low-temperature polysilicon thin film transistors
  • T3 and T4 are IGZO thin film transistors.
  • the refresh display cycle may include a refresh reset phase t1, a refresh charge phase t2, and a refresh light emission phase t3;
  • the potential of the first light-emitting control signal provided by E1 is a low voltage
  • the potential of the second light-emitting control signal provided by E2 is a high voltage
  • the potential of the first scanning signal provided by S1 is a low voltage
  • the potential of the second light-emitting control signal provided by S1 is a low voltage.
  • the potential of the second scanning signal is a high voltage
  • the potential of the third scanning signal provided by S3 is a high voltage
  • T1 and T2 are turned on
  • T3 is turned on
  • T4 is turned on
  • T6 is turned off
  • the first reset voltage Vi1 provided by I1 is written into The gate of T0, so that T0 can be turned on at the beginning of the refresh charging phase
  • the second reset voltage Vi2 provided by I2 is written into the anode of O1 to clear the charge of the anode of O1;
  • the potential of the first light-emitting control signal provided by E1 is a high voltage
  • the potential of the second light-emitting control signal provided by E2 is a high voltage
  • the potential of the first scanning signal provided by S1 is a low voltage
  • the potential of the second light-emitting control signal provided by S2 is a low voltage.
  • the potential of the second scanning signal is a high voltage
  • the potential of the third scanning signal provided by S3 is a low voltage
  • T1 is turned off
  • T2 is turned on
  • T3 is turned on to write Vi2 into the anode of O1, T4 and T5 are turned on; T6 and T7 turn off;
  • T0 is turned on, and the data voltage Vd on the data line charges C1 through T5, T4 and T0 to increase the potential of the gate of T0 until the potential of the gate of T0 becomes Vd+Vth, Vth is the threshold voltage of T0, T0 is turned off and stops charging;
  • the potential of the first light-emitting control signal provided by E1 is a low voltage
  • the potential of the second light-emitting control signal provided by E2 is a low voltage
  • the potential of the first scanning signal provided by S1 is a high voltage
  • the potential of the second light-emitting control signal provided by S2 is a high voltage.
  • the potential of the second scanning signal is low voltage
  • the potential of the third scanning signal provided by S3 is high voltage
  • T1, T2, T3, T4 and T5 are all turned off
  • T6 and T7 are turned on
  • E2 provides a high voltage signal and T3 is turned on to set the anode of O1.
  • the voltage value of Vi2 may be smaller than the voltage value of Vi1.
  • the frequency of the second light-emitting control signal can be increased so that the frequency of the second light-emitting control signal is greater than the predetermined frequency, and the frequency of setting the potential of the anode of O1 can be increased to improve the Flicker under low brightness. (blinking) phenomenon.
  • the predetermined frequency may be 50 Hz
  • the predetermined brightness may be greater than or equal to 100 nits and less than or equal to 140 nits, but not limited thereto.
  • the potential of the anode of O1 is set by the transistor controlled by E2, instead of the potential of the anode of O1 by the transistor controlled by the scan signal. Set, so that when the display panel to which the pixel circuit is applied works at a low frequency, the potential of the scanning signal does not need to be an effective voltage during the display period, which reduces the power consumption of the IC (integrated circuit) at low frequencies.
  • At least one embodiment of the pixel circuit shown in FIG. 11 of the present disclosure is working, and at low brightness, the frequency of the first light-emitting control signal provided by E2 can be increased to improve O1’s performance at low frequencies. Flicker phenomenon in brightness.
  • E2 provides a high voltage signal
  • S2 provides a high voltage signal
  • S3 provides a low voltage signal
  • the data voltage provided by the data line D0 charges C1;
  • S2 can continuously provide a low voltage signal
  • S3 can continuously provide a high voltage signal, so as to save power consumption.
  • FIG. 13 when maintaining the frame time, S3 provides a clock signal, but the frequency of the clock signal is lower, which can also save power consumption.
  • the driving method described in the embodiments of the present disclosure is applied to the above-mentioned pixel circuit, and the pixel circuit is applied to a display panel.
  • the driving method includes: in the refresh reset phase and the hold reset phase, the first reset circuit Under the control of the first light emission control signal provided by the light emission control line and the reset control signal provided by the reset control line, the first reset voltage provided by the first reset voltage line is controlled to be written into the first reset voltage of the driving circuit. end.
  • the first reset voltage is written into the first end of the driving circuit by the first reset circuit under the control of the first light emission control signal and the reset control signal , through the cooperation of the compensation control circuit, the first reset voltage can be written into the control terminal of the drive circuit in the refresh reset phase and the hold reset phase, so that a new pixel circuit structure can also be implemented. Reset of key nodes.
  • the pixel circuit further includes a compensation control circuit; the driving method may further include: in the refresh reset phase, the compensation control circuit controls the driving The first terminal of the circuit communicates with the control terminal of the drive circuit, so as to write the first reset voltage into the control terminal of the drive circuit, so that when the refresh charging phase begins, the drive circuit can be at the potential of the control terminal Under the control of , the connection between the first terminal and the second terminal is turned on.
  • the pixel circuit may further include a light-emitting element, a compensation control circuit, a data writing circuit, an energy storage circuit, a first light-emitting control circuit, and a second light-emitting control circuit;
  • the refresh display cycle further includes setting A refresh charging phase and a refresh light emitting phase after the refresh reset phase;
  • the driving method may also include:
  • the data writing circuit writes the data voltage on the data line into the second end of the driving circuit under the control of the third scanning signal provided by the third scanning line
  • the compensation control circuit writes the data voltage on the data line into the second terminal of the driving circuit under the control of the second scanning signal
  • the first end of the driving circuit is controlled to communicate with the control end of the driving circuit, so as to charge the energy storage circuit through the data voltage, and increase the potential of the control end of the driving circuit until the driving circuit is at the control end of the driving circuit. Under the control of the potential, the communication between the first end and the second end is disconnected;
  • the first light emission control circuit controls the communication between the first end of the driving circuit and the first pole of the light emitting element
  • the second light emission control circuit controls the communication between the first voltage end and the second end of the driving circuit
  • drives The circuit drives the light emitting element to emit light
  • the pixel circuit further includes a first light-emitting control circuit and a light-emitting element; the reset control line is a second light-emitting control line; the first light-emitting control circuit is electrically connected to the first light-emitting control line; the The drive method also includes:
  • the first light emission control circuit controls the communication between the first end of the driving circuit and the first pole of the light emitting element, so as to control the A reset voltage is written into the first pole of the light-emitting element, so as to set the potential of the first pole of the light-emitting element, so as to clear the residual charge of the first pole of the light-emitting element.
  • the frequency of the signal is such that the frequency of the first light emission control signal and the frequency of the second light emission control signal are greater than a predetermined frequency.
  • the frequency of the first light-emitting control signal and the frequency of the second light-emitting control signal can be increased so that the frequency of the first light-emitting control signal and the frequency of the second light-emitting control signal
  • the frequency of the second light-emitting control signal is higher than the predetermined frequency, and the frequency of setting is set by increasing the potential of the anode of O1, so as to improve the flicker (flicker) phenomenon under low brightness.
  • the predetermined frequency may be 50 Hz
  • the predetermined brightness may be greater than or equal to 100 nit and less than or equal to 140 nit.
  • the pixel circuit further includes a first light emission control circuit, a second reset circuit and a light emitting element; the first light emission control circuit is electrically connected to the second light emission control line; the driving method further includes:
  • the first light emission control circuit controls the disconnection between the first end of the driving circuit and the first pole of the light emitting element
  • the second reset circuit Under the control of the second light-emitting control signal, the second reset voltage is written into the first electrode of the light-emitting element.
  • the second reset voltage can be written into The first pole of the light emitting element sets the potential of the first pole of the light emitting element.
  • the frequency of the second light emission control signal can be increased so that all The frequency of the second light-emitting control signal is higher than the predetermined frequency, so as to increase the frequency of setting the potential of the first electrode of the light-emitting element, so as to improve the flicker (flicker) phenomenon under low brightness.
  • keeping the display period further includes a keeping lighting period set after the keeping reset period; the driving method further includes:
  • the first light emission control circuit controls the communication between the first terminal of the driving circuit and the first pole of the light emitting element
  • the second light emission control circuit controls the communication between the first voltage terminal and the second terminal of the driving circuit.
  • the driving circuit drives the light-emitting element to emit light.
  • the display device described in the embodiment of the present disclosure includes the above-mentioned pixel circuit.
  • the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.

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Abstract

一种像素电路、驱动方法和显示装置。像素电路包括第一重置电路（11）和驱动电路（12）；第一重置电路（11）分别与第一发光控制线（E1）、重置控制线(R1)、第一重置电压线(I1)和驱动电路(12)的第一端电连接，用于在第一发光控制线(E1)提供的第一发光控制信号和重置控制线(R1)提供的重置控制信号的控制下，控制将第一重置电压线(I1)提供的第一重置电压写入驱动电路（12）的第一端；驱动电路（12）用于在其控制端的电位的控制下，导通驱动电路（12）的第一端和驱动电路（12）的第二端之间的连接。提供了一种新的低温多晶氧化物像素电路的结构。

Description

像素电路、驱动方法和显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种像素电路、驱动方法和显示装置。
背景技术
现有的LTPS(低温多晶硅)显示面板，利用LTPS高迁移率特性应用于要求高切换速度的显示领域；然而由于LTPS TFT(薄膜晶体管)由于其晶体管特性，会存在漏电问题，在低频显示领域显示效果不理想。
发明内容
在一个方面中，本公开实施例提供了一种像素电路，包括第一重置电路和驱动电路；
所述第一重置电路分别与第一发光控制线、重置控制线、第一重置电压线和所述驱动电路的第一端电连接，用于在第一发光控制线提供的第一发光控制信号和重置控制线提供的重置控制信号的控制下，控制将所述第一重置电压线提供的第一重置电压写入所述驱动电路的第一端；
所述驱动电路用于在其控制端的电位的控制下，导通所述驱动电路的第一端和所述驱动电路的第二端之间的连接。
可选的，所述第一重置电路包括第一晶体管和第二晶体管；
所述第一晶体管的控制极与第一发光控制线电连接，所述第一晶体管的第一极与所述驱动电路的第一端电连接；
所述第二晶体管的控制极与所述重置控制线电连接，所述第二晶体管的第一极与所述第一晶体管的第二极电连接，所述第二晶体管的第二极与所述第一重置电压线电连接。
可选的，所述重置控制线为第二发光控制线，所述第一晶体管为p型晶体管，所述第二晶体管为n型晶体管；
所述像素电路包括第一发光控制电路和第二发光控制电路；
所述第一发光控制电路分别与第一发光控制线、所述驱动电路的第一端和发光元件的第一极电连接，用于在第一发光控制信号的控制下，控制所述驱动电路的第一端与发光元件的第一极之间连通；
所述第二发光控制电路分别与第二发光控制线、第一电压端和所述驱动电路的第二端电连接，用于在所述第二发光控制线提供的第二发光控制信号的控制下，控制所述第一电压端与所述驱动电路的第二端之间连通。
可选的，所述第一重置电路包括第一晶体管和第二晶体管；
所述第一晶体管的控制极与所述重置控制线电连接，所述第一晶体管的第一极与所述驱动电路的第一端电连接；
所述第二晶体管的控制极与第一发光控制线电连接，所述第二晶体管的第一极与所述第一晶体管的第二极电连接，所述第二晶体管的第二极与所述第一重置电压线电连接。
可选的，所述重置控制线为第二发光控制线，所述第一晶体管为n型晶体管，所述第二晶体管为p型晶体管；
所述像素电路包括第一发光控制电路和第二发光控制电路；
所述第一发光控制电路分别与第一发光控制线、所述驱动电路的第一端和发光元件的第一极电连接，用于在第一发光控制信号的控制下，控制所述驱动电路的第一端与发光元件的第一极之间连通；
所述第二发光控制电路分别与第二发光控制线、第一电压端和所述驱动电路的第二端电连接，用于在所述第二发光控制线提供的第二发光控制信号的控制下，控制所述第一电压端与所述驱动电路的第二端之间连通。
可选的，所述重置控制线为第一扫描线，所述第一晶体管和所述第二晶体管都为p型晶体管；
所述像素电路包括第一发光控制电路和第二发光控制电路；
所述第一发光控制电路分别与第二发光控制线、所述驱动电路的第一端和发光元件的第一极电连接，用于在所述第二发光控制线提供的第二发光控制信号的控制下，控制所述驱动电路的第一端与发光元件的第一极之间连通；
所述第二发光控制电路分别与第一发光控制线、第一电压端和所述驱动电路的第二端电连接，用于在所述第一发光控制信号的控制下，控制所述第 一电压端与所述驱动电路的第二端之间连通。
可选的，本公开至少一实施例所述的像素电路还包括第二重置电路；
所述第二重置电路分别与第二发光控制线、第二重置电压线和发光元件的第一极电连接，用于在第二发光控制信号的控制下，将第二重置电压线提供的第二重置电压写入所述发光元件的第一极。
可选的，所述第二重置电路包括第三晶体管；
所述第三晶体管的控制极与所述第二发光控制线电连接，所述第三晶体管的第一极与所述第二重置电压线电连接，所述第三晶体管的第二极与所述发光元件的第一极电连接。
可选的，所述第三晶体管为n型晶体管。
可选的，本公开至少一实施例所述的像素电路还包括补偿控制电路、数据写入电路和储能电路；
所述补偿控制电路分别与第二扫描线、所述驱动电路的控制端和所述驱动电路的第一端电连接，用于在第二扫描线提供的第二扫描信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第一端之间连通；
所述数据写入电路分别与第三扫描线、数据线和所述驱动电路的第二端电连接，用于在第三扫描线提供的第三扫描信号的控制下，将数据线上的数据电压写入所述驱动电路的第二端；
所述储能电路与所述驱动电路的控制端电连接，用于储存电能。
可选的，所述补偿控制电路包括第四晶体管，所述数据写入电路包括第五晶体管，所述驱动电路包括驱动晶体管，所述储能电路包括存储电容；
所述驱动晶体管的控制极与所述驱动电路的控制端电连接，所述驱动晶体管的第一极与所述驱动电路的第一端电连接，所述驱动晶体管的第二极与所述驱动电路的第二端电连接；
所述第四晶体管的控制极与所述第二扫描线电连接，所述第四晶体管的第一极与所述驱动晶体管的控制极电连接，所述第四晶体管的第二极与所述驱动电路的第一极电连接；
所述第五晶体管的控制极与所述第三扫描线电连接，所述第五晶体管的第一极与所述数据线电连接，所述第五晶体管的第二极与所述驱动晶体管的 第二极电连接；
所述存储电容的第一端与所述驱动晶体管的控制极电连接，所述存储电容的第二端与所述第一电压端电连接。
可选的，所述第一发光控制电路包括第六晶体管，所述第二发光控制电路包括第七晶体管；
所述第六晶体管的控制极与所述第一发光控制线电连接，所述第六晶体管的第一极与所述驱动电路的第一端电连接，所述第六晶体管的第二极与所述发光元件的第一极电连接；
所述第七晶体管的控制极与所述第二发光控制线电连接，所述第七晶体管的第一极与所述第一电压端电连接，所述第七晶体管的第二极与所述驱动电路的第二端电连接；
所述发光元件的第二极与第二电压端电连接。
可选的，所述第一发光控制电路包括第六晶体管，所述第二发光控制电路包括第七晶体管；
所述第六晶体管的控制极与所述第二发光控制线电连接，所述第六晶体管的第一极与所述驱动电路的第一端电连接，所述第六晶体管的第二极与所述发光元件的第一极电连接；
所述第七晶体管的控制极与所述第一发光控制线电连接，所述第七晶体管的第一极与所述第一电压端电连接，所述第七晶体管的第二极与所述驱动电路的第二端电连接；
所述发光元件的第二极与第二电压端电连接。
在第二个方面中，本公开实施例还提供一种驱动方法，应用于上述的像素电路，所述驱动方法包括：在刷新重置阶段和保持重置阶段，第一重置电路在第一发光控制线提供的第一发光控制信号和重置控制线提供的重置控制信号的控制下，控制将所述第一重置电压线提供的第一重置电压写入驱动电路的第一端。
可选的，所述像素电路还包括补偿控制电路；
所述驱动方法还包括：在所述刷新重置阶段，补偿控制电路在第二扫描线提供的第二扫描信号的控制下，控制驱动电路的第一端与驱动电路的控制 端之间连通，以将第一重置电压写入所述驱动电路的控制端。
可选的，所述像素电路还包括发光元件、补偿控制电路、数据写入电路、储能电路、第一发光控制电路和第二发光控制电路；刷新显示周期还包括设置于所述刷新重置阶段之后的刷新充电阶段和刷新发光阶段；所述驱动方法还包括：
在所述刷新充电阶段，数据写入电路在第三扫描线提供的第三扫描信号的控制下，将数据线上的数据电压写入驱动电路的第二端，补偿控制电路在第二扫描信号的控制下，控制驱动电路的第一端与驱动电路的控制端之间连通，以通过所述数据电压为储能电路充电；
在刷新发光阶段，第一发光控制电路控制驱动电路的第一端与发光元件的第一极之间连通，第二发光控制电路控制第一电压端与驱动电路的第二端之间连通，驱动电路驱动发光元件发光。
可选的，所述像素电路还包括第一发光控制电路和发光元件；所述重置控制线为第二发光控制线；所述第一发光控制电路与第一发光控制线电连接；所述驱动方法还包括：
在刷新重置阶段和保持重置阶段，第一发光控制电路在第一发光控制信号的控制下，控制驱动电路的第一端与发光元件的第一极之间连通，以控制将所述第一重置电压写入所述发光元件的第一极。
可选的，所述像素电路还包括第一发光控制电路、第二重置电路和发光元件；所述第一发光控制电路与第二发光控制线电连接；所述驱动方法还包括：
在刷新重置阶段和保持重置阶段，第一发光控制电路在第二发光控制信号的控制下，控制驱动电路的第一端与发光元件的第一极之间断开，第二重置电路在第二发光控制信号的控制下，将第二重置电压写入发光元件的第一极。
可选的，保持显示周期还包括设置于所述保持重置阶段之后的保持发光阶段；所述驱动方法还包括：
在所述保持发光阶段，第一发光控制电路控制驱动电路的第一端与发光元件的第一极之间连通，第二发光控制电路控制第一电压端与驱动电路的第 二端之间连通，驱动电路驱动发光元件发光。
可选的，本公开至少一实施例所述的驱动方法还包括：
检测所述显示面板的显示亮度范围，当所述显示亮度范围对应的最大亮度小于或等于预定亮度时，控制提升所述第一发光控制信号的频率和第二发光控制线提供的第二发光控制信号的频率，以使得所述第一发光控制信号的频率和所述第二发光控制信号的频率大于预定频率。
可选的，本公开至少一实施例所述的驱动方法还包括：
检测所述显示面板的显示亮度范围，当所述显示亮度范围对应的最大亮度小于或等于预定亮度时，控制提升第二发光控制线提供的第二发光控制信号的频率，以使得所述第二发光控制信号的频率大于预定频率。
在第三个方面中，本公开实施例提供一种显示装置，包括上述的像素电路。
附图说明
图1是本公开实施例所述的像素电路的结构图；
图2是本公开至少一实施例所述的像素电路的结构图；
图3是本公开至少一实施例所述的像素电路的结构图；
图4是本公开至少一实施例所述的像素电路的结构图；
图5是本公开至少一实施例所述的像素电路的结构图；
图6是本公开至少一实施例所述的像素电路的结构图；
图7本公开至少一实施例所述的像素电路的结构图；
图8是本公开至少一实施例所述的像素电路的结构图；
图9是本公开至少一实施例所述的像素电路的电路图；
图10是本公开至少一实施例所述的像素电路的工作时序图；
图11是本公开至少一实施例所述的像素电路的电路图；
图12是图11所示的像素电路的至少一实施例的一工作时序图；
图13是图11所示的像素电路的至少一实施例的另一工作时序图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为三极管、薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除控制极之外的两极，将其中一极称为第一极，另一极称为第二极。
在实际操作时，当所述晶体管为三极管时，所述控制极可以为基极，所述第一极可以为集电极，所述第二极可以发射极；或者，所述控制极可以为基极，所述第一极可以为发射极，所述第二极可以集电极。
在实际操作时，当所述晶体管为薄膜晶体管或场效应管时，所述控制极可以为栅极，所述第一极可以为漏极，所述第二极可以为源极；或者，所述控制极可以为栅极，所述第一极可以为源极，所述第二极可以为漏极。
如图1所示，本公开实施例所述的像素电路包括第一重置电路11和驱动电路12；
所述第一重置电路11分别与第一发光控制线E1、重置控制线R1、第一重置电压线I1和所述驱动电路12的第一端电连接，用于在第一发光控制线E1提供的第一发光控制信号和重置控制线R1提供的重置控制信号的控制下，控制将所述第一重置电压线I1提供的第一重置电压Vi1写入所述驱动电路12的第一端；
所述驱动电路12用于在其控制端的电位的控制下，导通所述驱动电路12的第一端和所述驱动电路12的第二端之间的连接。
本公开实施例所述的像素电路通过第一重置电路11在第一发光控制信号和重置控制信号的控制下，将第一重置电压Vi1写入驱动电路12的第一端，通过补偿控制电路的配合，可以在刷新重置阶段和保持重置阶段，将第一重置电压Vi1写入驱动电路12的控制端，以能够提供一种新的像素电路的结构，也能实现对关键节点的重置。
本公开如图1所示的像素电路的实施例在工作时，刷新显示周期可以包括刷新重置阶段，保持显示周期可以包括保持重置阶段，在刷新重置阶段和 保持重置阶段，第一重置电路11在第一发光控制信号和重置控制信号的控制下，将Vi1写入驱动电路12的第一端。
在本公开至少一实施例中，所述第一重置电路可以包括第一晶体管和第二晶体管；
所述第一晶体管的控制极与第一发光控制线电连接，所述第一晶体管的第一极与所述驱动电路的第一端电连接；
所述第二晶体管的控制极与所述重置控制线电连接，所述第二晶体管的第一极与所述第一晶体管的第二极电连接，所述第二晶体管的第二极与所述第一重置电压线电连接。
可选的，所述重置控制线为第二发光控制线，所述第一晶体管为p型晶体管，所述第二晶体管为n型晶体管；
所述像素电路包括第一发光控制电路和第二发光控制电路；
所述第一发光控制电路分别与第一发光控制线、所述驱动电路的第一端和发光元件的第一极电连接，用于在第一发光控制信号的控制下，控制所述驱动电路的第一端与发光元件的第一极之间连通；
所述第二发光控制电路分别与第二发光控制线、第一电压端和所述驱动电路的第二端电连接，用于在所述第二发光控制线提供的第二发光控制信号的控制下，控制所述第一电压端与所述驱动电路的第二端之间连通。
如图2所示，在图1所述的像素电路的实施例的基础上，所述重置控制线为第二发光控制线E2；本公开至少一实施例所述的像素电路还包括第一发光控制电路21和第二发光控制电路22；
所述第一重置电路11包括第一晶体管T1和第二晶体管T2；
所述第一晶体管T1的栅极与第一发光控制线E1电连接，所述第一晶体管T1的源极与所述驱动电路12的第一端电连接；
所述第二晶体管T2的栅极与所述第二发光控制线E2电连接，所述第二晶体管T2的源极与所述第一晶体管T1的漏极电连接，所述第二晶体管T2的漏极与所述第一重置电压线I1电连接；
所述第一发光控制电路21分别与第一发光控制线E1、所述驱动电路12的第一端和发光元件10的第一极电连接，用于在第一发光控制信号的控制下， 控制所述驱动电路12的第一端与发光元件10的第一极之间连通；
所述第二发光控制电路21分别与第二发光控制线E2、第一电压端V1和所述驱动电路12的第二端电连接，用于在所述第二发光控制线E2提供的第二发光控制信号的控制下，控制所述第一电压端V1与所述驱动电路12的第二端之间连通；
T1为p型晶体管，T2为n型晶体管。
本公开如图2所示的像素电路的至少一实施例在工作时，在刷新重置阶段和保持重置阶段，第一发光控制信号的电位为低电压，第二发光控制信号的电位为高电压，E1提供低电压信号，E2提供高电压信号，T1和T2打开，第一发光控制电路21在第一发光控制信号的控制下，控制驱动电路12的第一端与发光元件10的第一极之间连通，以将第一重置电压线I1提供的第一重置电压Vi1提供至所述发光元件10的第一极，清除发光元件10的第一极残留的电荷。
在本公开如图2所示的像素电路的至少一实施例中，T1可以为低温多晶硅薄膜晶体管，T2可以为IGZO(铟镓锌氧化物)薄膜晶体管。
在本公开至少一实施例中，所述第一重置电路可以包括第一晶体管和第二晶体管；
所述第一晶体管的控制极与所述重置控制线电连接，所述第一晶体管的第一极与所述驱动电路的第一端电连接；
所述第二晶体管的控制极与第一发光控制线电连接，所述第二晶体管的第一极与所述第一晶体管的第二极电连接，所述第二晶体管的第二极与所述第一重置电压线电连接。
可选的，所述重置控制线为第二发光控制线，所述第一晶体管为n型晶体管，所述第二晶体管为p型晶体管；
所述像素电路包括第一发光控制电路和第二发光控制电路；
所述第一发光控制电路分别与第一发光控制线、所述驱动电路的第一端和发光元件的第一极电连接，用于在第一发光控制信号的控制下，控制所述驱动电路的第一端与发光元件的第一极之间连通；
所述第二发光控制电路分别与第二发光控制线、第一电压端和所述驱动 电路的第二端电连接，用于在所述第二发光控制线提供的第二发光控制信号的控制下，控制所述第一电压端与所述驱动电路的第二端之间连通。
如图3所示，在图1所述的像素电路的实施例的基础上，所述重置控制线为第二发光控制线E2；本公开至少一实施例所述的像素电路还包括第一发光控制电路21和第二发光控制电路22；
所述第一重置电路11包括第一晶体管T1和第二晶体管T2；
所述第一晶体管T1的栅极与第二发光控制线E2电连接，所述第一晶体管T1的源极与所述驱动电路12的第一端电连接；
所述第二晶体管T2的栅极与所述第一发光控制线E1电连接，所述第二晶体管T2的源极与所述第一晶体管T1的漏极电连接，所述第二晶体管T2的漏极与所述第一重置电压线I1电连接；
所述第一发光控制电路21分别与第一发光控制线E1、所述驱动电路12的第一端和发光元件10的第一极电连接，用于在第一发光控制信号的控制下，控制所述驱动电路12的第一端与发光元件10的第一极之间连通；
所述第二发光控制电路21分别与第二发光控制线E2、第一电压端V1和所述驱动电路12的第二端电连接，用于在所述第二发光控制线E2提供的第二发光控制信号的控制下，控制所述第一电压端V1与所述驱动电路12的第二端之间连通；
T1为n型晶体管，T2为p型晶体管。
本公开如图3所示的像素电路的至少一实施例在工作时，在刷新重置阶段和保持重置阶段，第一发光控制信号的电位为低电压，第二发光控制信号的电位为高电压，E1提供低电压信号，E2提供高电压信号，T1和T2打开，第一发光控制电路21在第一发光控制信号的控制下，控制驱动电路12的第一端与发光元件10的第一极之间连通，以将第一重置电压线I1提供的第一重置电压Vi1提供至所述发光元件10的第一极，清除发光元件10的第一极残留的电荷。
在本公开如图3所示的像素电路的至少一实施例中，T2可以为低温多晶硅薄膜晶体管，T1可以为IGZO(铟镓锌氧化物)薄膜晶体管。
可选的，所述第一发光控制电路包括第六晶体管，所述第二发光控制电 路包括第七晶体管；
所述第六晶体管的控制极与所述第一发光控制线电连接，所述第六晶体管的第一极与所述驱动电路的第一端电连接，所述第六晶体管的第二极与所述发光元件的第一极电连接；
所述第七晶体管的控制极与所述第二发光控制线电连接，所述第七晶体管的第一极与所述第一电压端电连接，所述第七晶体管的第二极与所述驱动电路的第二端电连接；
所述发光元件的第二极与第二电压端电连接。
可选的，所述重置控制线为第一扫描线，所述第一晶体管和所述第二晶体管都为p型晶体管；
所述像素电路包括第一发光控制电路和第二发光控制电路；
所述第一发光控制电路分别与第二发光控制线、所述驱动电路的第一端和发光元件的第一极电连接，用于在所述第二发光控制线提供的第二发光控制信号的控制下，控制所述驱动电路的第一端与发光元件的第一极之间连通；
所述第二发光控制电路分别与第一发光控制线、第一电压端和所述驱动电路的第二端电连接，用于在所述第一发光控制信号的控制下，控制所述第一电压端与所述驱动电路的第二端之间连通。
如图4所示，在图1所述的像素电路的实施例的基础上，所述重置控制线为第一扫描线S1；本公开至少一实施例所述的像素电路还包括第一发光控制电路21和第二发光控制电路22；
所述第一重置电路11包括第一晶体管T1和第二晶体管T2；
所述第一晶体管T1的栅极与第一发光控制线E1电连接，所述第一晶体管T1的源极与所述驱动电路12的第一端电连接；
所述第二晶体管T2的栅极与第一扫描线S1电连接，所述第二晶体管T2的源极与所述第一晶体管T1的漏极电连接，所述第二晶体管T2的漏极与所述第一重置电压线I1电连接；
所述第一发光控制电路21分别与第二发光控制线E2、所述驱动电路12的第一端和发光元件10的第一极电连接，用于在第二发光控制线E2提供的第二发光控制信号的控制下，控制所述驱动电路12的第一端与发光元件10 的第一极之间连通；
所述第二发光控制电路22分别与第一发光控制线E1、第一电压端V1和所述驱动电路12的第二端电连接，用于在所述第一发光控制线E1提供的第二发光控制信号的控制下，控制所述第一电压端V1与所述驱动电路12的第二端之间连通；
T1为p型晶体管，T2为p型晶体管。
在本公开如图4所示的像素电路的至少一实施例中，T1和T2可以为低温多晶硅薄膜晶体管。
本公开如图4所示的像素电路的至少一实施例在工作时，在刷新重置阶段和保持重置阶段，E1提供的第一发光控制信号的电位为低电压，S1提供的第一扫描信号的电位为低电压，T1和T2打开，以将第一重置电压线提供的第一重置电压Vi1写入驱动电路12的第一端。
如图5所示，在图1所述的像素电路的实施例的基础上，所述重置控制线为第一扫描线S1；本公开至少一实施例所述的像素电路还包括第一发光控制电路21和第二发光控制电路22；
所述第一重置电路11包括第一晶体管T1和第二晶体管T2；
所述第一晶体管T1的栅极与第一扫描线S1电连接，所述第一晶体管T1的源极与所述驱动电路12的第一端电连接；
所述第二晶体管T2的栅极与第一发光控制线E1电连接，所述第二晶体管T2的源极与所述第一晶体管T1的漏极电连接，所述第二晶体管T2的漏极与所述第一重置电压线I1电连接；
所述第一发光控制电路21分别与第二发光控制线E2、所述驱动电路12的第一端和发光元件10的第一极电连接，用于在第二发光控制线E2提供的第二发光控制信号的控制下，控制所述驱动电路12的第一端与发光元件10的第一极之间连通；
所述第二发光控制电路22分别与第一发光控制线E1、第一电压端V1和所述驱动电路12的第二端电连接，用于在所述第一发光控制线E1提供的第二发光控制信号的控制下，控制所述第一电压端V1与所述驱动电路12的第二端之间连通；
T1为p型晶体管，T2为p型晶体管。
在本公开如图5所示的像素电路的至少一实施例中，T1和T2可以为低温多晶硅薄膜晶体管。
本公开如图5所示的像素电路的至少一实施例在工作时，在刷新重置阶段和保持重置阶段，E1提供的第一发光控制信号的电位为低电压，S1提供的第一扫描信号的电位为低电压，T1和T2打开，以将第一重置电压线提供的第一重置电压Vi1写入驱动电路12的第一端。
可选的，所述第一发光控制电路包括第六晶体管，所述第二发光控制电路包括第七晶体管；
所述第六晶体管的控制极与所述第二发光控制线电连接，所述第六晶体管的第一极与所述驱动电路的第一端电连接，所述第六晶体管的第二极与所述发光元件的第一极电连接；
所述第七晶体管的控制极与所述第一发光控制线电连接，所述第七晶体管的第一极与所述第一电压端电连接，所述第七晶体管的第二极与所述驱动电路的第二端电连接；
所述发光元件的第二极与第二电压端电连接。
如图6所示，在图4所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还可以包括第二重置电路40；
所述第二重置电路40分别与第二发光控制线E2、第二重置电压线I2和发光元件10的第一极电连接，用于在第二发光控制线E2提供的第二发光控制信号的控制下，将第二重置电压线I2提供的第二重置电压Vi2写入所述发光元件10的第一极。
本公开如图6所示的像素电路的至少一实施例在工作时，在刷新重置阶段、刷新充电阶段和保持重置阶段，第二重置电路40在第二发光控制信号的控制下，将Vi2写入发光元件10的第一极，以清除发光元件10的第一极残留的电荷。
可选的，所述第二重置电路包括第三晶体管；
所述第三晶体管的控制极与所述第二发光控制线电连接，所述第三晶体管的第一极与所述第二重置电压线电连接，所述第三晶体管的第二极与所述 发光元件的第一极电连接。
在本公开至少一实施例中，所述第三晶体管为n型晶体管，所述第三晶体管可以为IGZO薄膜晶体管。
本公开至少一实施例所述的像素电路还可以包括补偿控制电路、数据写入电路和储能电路；
所述补偿控制电路分别与第二扫描线、所述驱动电路的控制端和所述驱动电路的第一端电连接，用于在第二扫描线提供的第二扫描信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第一端之间连通；
所述数据写入电路分别与第三扫描线、数据线和所述驱动电路的第二端电连接，用于在第三扫描线提供的第三扫描信号的控制下，将数据线上的数据电压写入所述驱动电路的第二端；
所述储能电路与所述驱动电路的控制端电连接，用于储存电能。
如图7所示，在图2所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还可以包括补偿控制电路51、数据写入电路52和储能电路53；
所述补偿控制电路51分别与第二扫描线S2、所述驱动电路12的控制端和所述驱动电路12的第一端电连接，用于在第二扫描线S2提供的第二扫描信号的控制下，控制所述驱动电路12的控制端与所述驱动电路12的第一端之间连通；
所述数据写入电路52分别与第三扫描线S3、数据线D0和所述驱动电路12的第二端电连接，用于在第三扫描线S3提供的第三扫描信号的控制下，将数据线D0上的数据电压写入所述驱动电路12的第二端；
所述储能电路53与所述驱动电路的控制端电连接，用于储存电能。
本公开如图7所示的像素电路的至少一实施例在工作时，在刷新重置阶段，补偿控制电路51在第二扫描信号的控制下，控制驱动电路12的控制端与驱动电路12的第一端之间连通，以将第一重置电压Vi写入驱动电路12的控制端，使得在刷新充电阶段开始时，所述驱动电路12能够在其控制端的电位的控制下，导通其第一端与第二端之间的连通；
在刷新充电阶段，数据写入电路52在第三扫描信号的控制下，将数据电 压写入驱动电路12的第二端，以通过数据电压为储能电路53进行充电，提升驱动电路12的控制端的电位，直至所述驱动电路12在其控制端的电位的控制下，断开其第一端与第二端之间的连接。
如图8所示，在图6所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还可以包括补偿控制电路51、数据写入电路52和储能电路53；
所述补偿控制电路51分别与第二扫描线S2、所述驱动电路12的控制端和所述驱动电路12的第一端电连接，用于在第二扫描线S2提供的第二扫描信号的控制下，控制所述驱动电路12的控制端与所述驱动电路12的第一端之间连通；
所述数据写入电路52分别与第三扫描线S3、数据线D0和所述驱动电路12的第二端电连接，用于在第三扫描线S3提供的第三扫描信号的控制下，将数据线D0上的数据电压写入所述驱动电路12的第二端；
所述储能电路53与所述驱动电路的控制端电连接，用于储存电能。
本公开如图8所示的像素电路的至少一实施例在工作时，在刷新重置阶段，补偿控制电路51在第二扫描信号的控制下，控制驱动电路12的控制端与驱动电路12的第一端之间连通，以将第一重置电压Vi写入驱动电路12的控制端，使得在刷新充电阶段开始时，所述驱动电路12能够在其控制端的电位的控制下，导通其第一端与第二端之间的连通；
在刷新充电阶段，数据写入电路52在第三扫描信号的控制下，将数据电压写入驱动电路12的第二端，以通过数据电压为储能电路53进行充电，提升驱动电路12的控制端的电位，直至所述驱动电路12在其控制端的电位的控制下，断开其第一端与第二端之间的连接。
可选的，所述补偿控制电路包括第四晶体管，所述数据写入电路包括第五晶体管，所述驱动电路包括驱动晶体管，所述储能电路包括存储电容；
所述驱动晶体管的控制极与所述驱动电路的控制端电连接，所述驱动晶体管的第一极与所述驱动电路的第一端电连接，所述驱动晶体管的第二极与所述驱动电路的第二端电连接；
所述第四晶体管的控制极与所述第二扫描线电连接，所述第四晶体管的 第一极与所述驱动晶体管的控制极电连接，所述第四晶体管的第二极与所述驱动电路的第一极电连接；
所述第五晶体管的控制极与所述第三扫描线电连接，所述第五晶体管的第一极与所述数据线电连接，所述第五晶体管的第二极与所述驱动晶体管的第二极电连接；
所述存储电容的第一端与所述驱动晶体管的控制极电连接，所述存储电容的第二端与所述第一电压端电连接。
可选的，所述第四晶体管可以为n型晶体管，第五晶体管和驱动晶体管为p型晶体管；所述第四晶体管为IGZO薄膜晶体管，第五晶体管和驱动晶体管为低温多晶硅薄膜晶体管。
如图9所示，在图7所示的像素电路的至少一实施例的基础上，所述发光元件为有机发光二极管O1；所述补偿控制电路51包括第四晶体管T4，所述数据写入电路52包括第五晶体管T5，所述驱动电路12包括驱动晶体管T0，所述储能电路53包括存储电容C1；
所述驱动晶体管T0的栅极与所述驱动电路12的控制端电连接，所述驱动晶体管T0的漏极与所述驱动电路12的第一端电连接，所述驱动晶体管T0的源极与所述驱动电路12的第二端电连接；
所述第四晶体管T4的栅极与所述第二扫描线S2电连接，所述第四晶体管T4的源极与所述驱动晶体管T0的栅极电连接，所述第四晶体管T4的漏极与所述驱动晶体管的漏极电连接；
所述第五晶体管T5的栅极与所述第三扫描线S3电连接，所述第五晶体管T5的源极与所述数据线D0电连接，所述第五晶体管T5的漏极与所述驱动晶体管T0的源极电连接；
所述存储电容C1的第一端与所述驱动晶体管T0的栅极电连接，所述存储电容C1的第二端与高电压端电连接；所述高电压端用于提供高电压信号VDD；
所述第一发光控制电路包括第六晶体管T6，所述第二发光控制电路22包括第七晶体管T7；
所述第六晶体管T6的栅极与所述第一发光控制线E1电连接，所述第六 晶体管T6的源极与所述驱动晶体管T0的漏极电连接，所述第六晶体管T6的漏极与O1的阳极电连接；
所述第七晶体管T7的栅极与所述第二发光控制线E2电连接，所述第七晶体管T7的源极与所述高电压端电连接，所述第七晶体管T7的漏极与所述驱动晶体管T0的源极电连接；
O1的阴极与低电压端电连接；所述低电压端用于提供低电压信号VSS。
在图9所示的像素电路的至少一实施例中，第一电压端为高电压端，第二电压端为低电压端；T1、T0、T5、T6和T7为p型晶体管，T2和T4为n型晶体管；T1、T0、T5、T6和T7为低温多晶硅薄膜晶体管，T2和T4为IGZO(铟镓锌氧化物)薄膜晶体管。
如图10所示，本公开如图9所示的像素电路的至少一实施例在工作时，刷新显示周期包括刷新重置阶段t1、刷新充电阶段t2和刷新发光阶段t3；
在刷新重置阶段t1，E1提供的第一发光控制信号的电位为低电压，E2提供的第二发光控制信号的电位为高电压，S2提供的第二扫描信号的电位为高电压，S3提供的第三扫描信号的电位为高电压，T1打开，T2打开，T4打开，以将I1提供的第一重置电压Vi1写入T0的栅极，使得在刷新充电阶段t2开始时，T0能够打开；T6打开，以将Vi1写入O1的阳极，清除O1的阳极残留的电荷；T7关断，T5关断；
在刷新充电阶段t2，E1提供的第一发光控制信号的电位为高电压，E2提供的第二发光控制信号的电位为高电压，S2提供的第二扫描信号的电位为高电压，S3提供的第三扫描信号的电位为低电压，T1关断，T2打开，T4打开，T5打开；T6关断，T7关断；
在刷新充电阶段t2开始时，T0打开，数据线D0上的数据电压Vd通过T5、T0和T4为C1充电，以提升T0的栅极的电位，直至T0的电位升至Vd+Vth，Vth为T0的阈值电压，T0关断，停止充电；
在刷新发光阶段t3，E1提供的第一发光控制信号的电位为低电压，E2提供的第二发光控制信号的电位为低电压，S2提供的第二扫描信号的电位为低电压，S3提供的第三扫描信号的电位为高电压，T4关断，T5关断，T1打开，T2关断，T6和T7打开，T0驱动O1发光，O1的发光电流I等于K(Vdd-Vd) 2；K为T0的电流系数，Vdd为VDD的电压值。
如图10所示，第一发光控制信号的频率可以与第二发光控制信号的频率相同，第一发光控制信号的占空比与第二发光控制信号的占空比可以相同，第一发光控制信号比第二发光控制信号延迟一段时间，第一发光控制信号和第二发光控制信号可以为一发光控制信号生成电路输出的相邻两级发光控制信号；
S1提供的第一扫描信号和S3提供的第三扫描信号可以为低电平有效的扫描信号，S2提供的第二扫描信号可以为高电平有效的扫描信号。
本公开如图9所示的像素电路的至少一实施例在工作时，保持显示周期包括保持重置阶段和保持发光阶段；
在保持重置阶段，E1提供的第一发光控制信号的电位为低电压，E2提供的第二发光控制信号的电位为高电压，S2提供的第二扫描信号的电位为高电压，S3提供的第三扫描信号的电位为高电压，T1打开，T2打开，T6打开，以将Vi1写入O1的阳极，清除O1的阳极残留的电荷；T7关断，T5关断；
在保持发光阶段，E1提供的第一发光控制信号的电位为低电压，E2提供的第二发光控制信号的电位为低电压，S2提供的第二扫描信号的电位为低电压，S3提供的第三扫描信号的电位为高电压，T4关断，T5关断，T1打开，T2关断，T6和T7打开，T0驱动O1发光，O1的发光电流I等于K(Vdd-Vd)2；K为T0的电流系数，Vdd为VDD的电压值；其中，Vd为相邻上一刷新充电阶段，数据线D0提供的数据电压。
本公开如图9所示的像素电路的至少一实施例在工作时，在保持显示周期，不存在为所述储能电路23充电的过程，在保持发光阶段，所述驱动电路11驱动所述发光元件11的驱动电流仍与紧邻上一次刷新显示周期中的刷新充电阶段中的数据电压相关。
本公开如图9所示的像素电路的至少一实施例在工作时，当所述像素电路应用于的显示面板在低亮度下显示时，也即当所述显示面板的显示亮度范围对应的最大亮度小于或等于预定亮度时，可以通过提升第一发光控制信号的频率和第二发光控制信号的频率，以使得所述第一发光控制信号的频率和所述第二发光控制信号的频率大于预定频率，以提升为O1的阳极的电位进 行置位的频率，改善低亮度下Flicker(闪烁)现象。
并且，在本公开如图9所示的像素电路的至少一实施例中，通过E1控制的晶体管和E2控制的晶体管为O1的阳极的电位进行置位，而不是通过扫描信号控制的晶体管为O1的阳极的电位进行置位，以在所述像素电路应用于的显示面板在低频下工作时，在保持显示周期，该扫描信号的电位不需为有效电压，降低了低频下的IC(集成电路)功耗。
在本公开至少一实施例中，所述预定频率例如可以为50Hz，但不以此为限。
在本公开至少一实施例中，所述显示面板在低亮度下显示指的可以是：所述显示面板的显示亮度范围对应的最大亮度小于或等于预定亮度。所述预定亮度可以大于或等于100尼特而小于或等于140尼特，例如，所述预定亮度可以为120尼特。
在本公开至少一实施例中，当显示面板为手机包括的显示屏时，可以通过拉动手机的亮度调节条来调节所述显示亮度范围。
所述显示面板的显示亮度范围指的可以是：所述显示面板的显示亮度大于或等于第一亮度而小于或等于第二亮度，所述第二亮度即为所述显示亮度范围对应的最大亮度；
所述第二亮度指的可以是：所述显示面板能够显示的最大亮度；
所述第一亮度指的可以是：所述显示面板能够显示的最小亮度。
在本公开至少一实施例中，所述显示面板的显示亮度范围在预定亮度范围内，指的并非是当所述显示面板显示预定画面时，显示面板的显示亮度范围在预定亮度范围内，而指的是：当显示面板显示任意画面时，所述显示面板的显示亮度范围在预定亮度范围内。
如图11所示，在图8所示的像素电路的至少一实施例的基础上，所述发光元件为有机发光二极管O1；所述第二重置电路40包括第三晶体管T3；
所述补偿控制电路51包括第四晶体管T4，所述数据写入电路52包括第五晶体管T5，所述驱动电路12包括驱动晶体管T0，所述储能电路包括存储电容C1；
所述第三晶体管T3的栅极与所述第二发光控制线E2电连接，所述第三 晶体管T3的源极与所述第二重置电压线I2电连接，所述第三晶体管T3的漏极与O1的阳极电连接；
所述驱动晶体管T0的栅极与所述驱动电路12的控制端电连接，所述驱动晶体管T0的漏极与所述驱动电路12的第一端电连接，所述驱动晶体管T0的源极与所述驱动电路12的第二端电连接；
所述第四晶体管T4的栅极与所述第二扫描线S2电连接，所述第四晶体管T4的源极与所述驱动晶体管T0的栅极电连接，所述第四晶体管T4的漏极与所述驱动晶体管的漏极电连接；
所述第五晶体管T5的栅极与所述第三扫描线S3电连接，所述第五晶体管T5的源极与所述数据线D0电连接，所述第五晶体管T5的漏极与所述驱动晶体管T0的源极电连接；
所述存储电容C1的第一端与所述驱动晶体管T0的栅极电连接，所述存储电容C1的第二端与高电压端电连接；所述高电压端用于提供高电压信号VDD；
所述第一发光控制电路包括第六晶体管T6，所述第二发光控制电路22包括第七晶体管T7；
所述第六晶体管T6的栅极与所述第二发光控制线E2电连接，所述第六晶体管T6的源极与所述驱动晶体管T0的漏极电连接，所述第六晶体管T6的漏极与O1的阳极电连接；
所述第七晶体管T7的栅极与所述第一发光控制线E1电连接，所述第七晶体管T7的源极与所述高电压端电连接，所述第七晶体管T7的漏极与所述驱动晶体管T0的源极电连接；
O1的阴极与低电压端电连接；所述低电压端用于提供低电压信号VSS。
在图11所示的像素电路的至少一实施例中，T1、T2、T6、T7、T0和T5都为p型晶体管，T3和T4为n型晶体管；T1、T2、T6、T7、T0和T5都为低温多晶硅薄膜晶体管，T3和T4为IGZO薄膜晶体管。
如图10所示，本公开如图11所示的像素电路的至少一实施例在工作时，刷新显示周期可以包括刷新重置阶段t1、刷新充电阶段t2和刷新发光阶段t3；
在刷新重置阶段t1，E1提供的第一发光控制信号的电位为低电压，E2 提供的第二发光控制信号的电位为高电压，S1提供的第一扫描信号的电位为低电压，S2提供的第二扫描信号的电位为高电压，S3提供的第三扫描信号的电位为高电压，T1和T2打开，T3打开，T4打开，T6关断，I1提供的第一重置电压Vi1写入T0的栅极，以使得T0在刷新充电阶段开始时能够打开；I2提供的第二重置电压Vi2写入O1的阳极，以清除O1的阳极的电荷；
在刷新充电阶段t2，E1提供的第一发光控制信号的电位为高电压，E2提供的第二发光控制信号的电位为高电压，S1提供的第一扫描信号的电位为低电压，S2提供的第二扫描信号的电位为高电压，S3提供的第三扫描信号的电位为低电压，T1关断，T2打开，T3打开，以将Vi2写入O1的阳极，T4和T5打开；T6和T7关断；
在刷新充电阶段t2开始时，T0打开，数据线上的数据电压Vd通过T5、T4和T0为C1充电，以提升T0的栅极的电位，直至T0的栅极的电位变为Vd+Vth，Vth为T0的阈值电压，T0关断，停止充电；
在刷新发光阶段t3，E1提供的第一发光控制信号的电位为低电压，E2提供的第二发光控制信号的电位为低电压，S1提供的第一扫描信号的电位为高电压，S2提供的第二扫描信号的电位为低电压，S3提供的第三扫描信号的电位为高电压，T1、T2、T3、T4和T5都关断，T6和T7打开，T0驱动O1发光；
在刷新充电阶段t2与刷新发光阶段t3之间的时间段，E2提供高电压信号，T3打开，以为O1的阳极进行置位。
在本公开至少一实施例中，Vi2的电压值可以小于Vi1的电压值。
本公开如图11所示的像素电路的至少一实施例在工作时，当所述像素电路应用于的显示面板在低亮度下显示时，也即当所述显示亮度范围对应的最大亮度小于或等于预定亮度时，可以通过提升第二发光控制信号的频率，以使得所述第二发光控制信号的频率大于预定频率，以提升为O1的阳极的电位进行置位的频率，改善低亮度下Flicker(闪烁)现象。
在本公开至少一实施例中，所述预定频率可以为50Hz，所述预定亮度可以大于或等于100尼特而小于或等于140尼特，但不以此为限。
并且，在本公开如图11所示的像素电路的至少一实施例中，通过E2控 制的晶体管为O1的阳极的电位进行置位，而不是通过扫描信号控制的晶体管为O1的阳极的电位进行置位，以在所述像素电路应用于的显示面板在低频下工作时，在保持显示周期，该扫描信号的电位不需为有效电压，降低了低频下的IC(集成电路)功耗。
如图12所示，本公开如图11所示的像素电路的至少一实施例在工作时，在低亮度下，可以通过提升E2提供的第一发光控制信号的频率，以改善O1在低频低亮度下的闪烁现象。
在图12中，标号为F11的为第一刷新帧时间，标号为F12的为第一保持帧时间；标号为F21的为第二刷新帧时间，标号为F22的为第二保持帧时间，标号为F31的为第三刷新帧时间，标号为F32的为第三保持帧时间；
在刷新帧时间中，存在刷新充电阶段，在刷新充电阶段，E2提供高电压信号，S2提供高电压信号，S3提供低电压信号，通过数据线D0提供的数据电压为C1充电；
在保持帧时间中，不存在充电阶段，S2可以持续提供低电压信号，S3可以持续提供高电压信号，以能够节省功耗。
图13与图12的区别在于：在保持帧时间，S3提供时钟信号，但是该时钟信号的频率较低，同样能够节省功耗。
本公开实施例所述的驱动方法，应用于上述的像素电路，所述像素电路应用于显示面板，所述驱动方法包括：在刷新重置阶段和保持重置阶段，第一重置电路在第一发光控制线提供的第一发光控制信号和重置控制线提供的重置控制信号的控制下，控制将所述第一重置电压线提供的第一重置电压写入驱动电路的第一端。
在本公开实施例所述的像素电路的驱动方法中，通过第一重置电路在第一发光控制信号和重置控制信号的控制下，将第一重置电压写入驱动电路的第一端，通过补偿控制电路的配合，可以在刷新重置阶段和保持重置阶段，将第一重置电压写入驱动电路的控制端，以能够通过一种新的像素电路的结构，也能实现对关键节点的重置。
可选的，所述像素电路还包括补偿控制电路；所述驱动方法还可以包括：在所述刷新重置阶段，补偿控制电路在第二扫描线提供的第二扫描信号的控 制下，控制驱动电路的第一端与驱动电路的控制端之间连通，以将第一重置电压写入所述驱动电路的控制端，以在刷新充电阶段开始时，所述驱动电路能够在其控制端的电位的控制下，导通其第一端与第二端之间的连接。
在本公开至少一实施例中，所述像素电路还可以包括发光元件、补偿控制电路、数据写入电路、储能电路、第一发光控制电路和第二发光控制电路；刷新显示周期还包括设置于所述刷新重置阶段之后的刷新充电阶段和刷新发光阶段；所述驱动方法还可以包括：
在所述刷新充电阶段，数据写入电路在第三扫描线提供的第三扫描信号的控制下，将数据线上的数据电压写入驱动电路的第二端，补偿控制电路在第二扫描信号的控制下，控制驱动电路的第一端与驱动电路的控制端之间连通，以通过所述数据电压为储能电路充电，提升驱动电路的控制端的电位，直至所述驱动电路在其控制端的电位的控制下，断开其第一端与第二端之间的连通；
在刷新发光阶段，第一发光控制电路控制驱动电路的第一端与发光元件的第一极之间连通，第二发光控制电路控制第一电压端与驱动电路的第二端之间连通，驱动电路驱动发光元件发光。
可选的，所述像素电路还包括第一发光控制电路和发光元件；所述重置控制线为第二发光控制线；所述第一发光控制电路与第一发光控制线电连接；所述驱动方法还包括：
在刷新重置阶段和保持重置阶段，第一发光控制电路在第一发光控制信号的控制下，控制驱动电路的第一端与发光元件的第一极之间连通，以控制将所述第一重置电压写入所述发光元件的第一极，以对发光元件的第一极的电位进行置位，以清除所述发光元件的第一极残留的电荷。
本公开至少一实施例所述的驱动方法还可以包括：
检测所述显示面板的显示亮度范围，当所述显示亮度范围对应的最大亮度小于或等于预定亮度时，控制提升所述第一发光控制信号的频率和第二发光控制线提供的第二发光控制信号的频率，以使得所述第一发光控制信号的频率和所述第二发光控制信号的频率大于预定频率。
当检测到所述显示亮度范围对应的最大亮度小于或等于预定亮度时，可 以通过提升第一发光控制信号的频率和第二发光控制信号的频率，以使得所述第一发光控制信号的频率和所述第二发光控制信号的频率大于预定频率，以提升为O1的阳极的电位进行置位的频率，改善低亮度下Flicker(闪烁)现象。
可选的，所述预定频率可以为50Hz，所述预定亮度可以大于或等于100nit而小于或等于140尼特。
可选的，所述像素电路还包括第一发光控制电路、第二重置电路和发光元件；所述第一发光控制电路与第二发光控制线电连接；所述驱动方法还包括：
在刷新重置阶段和保持重置阶段，第一发光控制电路在第二发光控制信号的控制下，控制驱动电路的第一端与发光元件的第一极之间断开，第二重置电路在第二发光控制信号的控制下，将第二重置电压写入发光元件的第一极。
当所述像素电路还包括第二重置电路时，可以在刷新重置阶段和保持重置阶段，通过第二重置电路在第二发光控制信号的控制下，将第二重置电压写入发光元件的第一极，对发光元件的第一极的电位进行置位。
本公开至少一实施例所述的驱动方法还可以包括：
检测所述显示面板的显示亮度范围，当所述显示亮度范围对应的最大亮度小于或等于预定亮度时，控制提升第二发光控制线提供的第二发光控制信号的频率，以使得所述第二发光控制信号的频率大于预定频率。
当所述显示面板在低亮度下显示时，也即当检测到所述显示面板的显示亮度范围对应的最大亮度小于或等于预定亮度时，可以通过提升第二发光控制信号的频率，以使得所述第二发光控制信号的频率大于预定频率，以提升为发光元件的第一极的电位进行置位的频率，改善低亮度下Flicker(闪烁)现象。
在本公开至少一实施例中，保持显示周期还包括设置于所述保持重置阶段之后的保持发光阶段；所述驱动方法还包括：
在所述保持发光阶段，第一发光控制电路控制驱动电路的第一端与发光元件的第一极之间连通，第二发光控制电路控制第一电压端与驱动电路的第 二端之间连通，驱动电路驱动发光元件发光。
本公开实施例所述的显示装置包括上述的像素电路。
本公开实施例所提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (22)

  1. 一种像素电路，包括第一重置电路和驱动电路；
    所述第一重置电路分别与第一发光控制线、重置控制线、第一重置电压线和所述驱动电路的第一端电连接，用于在第一发光控制线提供的第一发光控制信号和重置控制线提供的重置控制信号的控制下，控制将所述第一重置电压线提供的第一重置电压写入所述驱动电路的第一端；
    所述驱动电路用于在其控制端的电位的控制下，导通所述驱动电路的第一端和所述驱动电路的第二端之间的连接。
  2. 如权利要求1所述的像素电路，其中，所述第一重置电路包括第一晶体管和第二晶体管；
    所述第一晶体管的控制极与第一发光控制线电连接，所述第一晶体管的第一极与所述驱动电路的第一端电连接；
    所述第二晶体管的控制极与所述重置控制线电连接，所述第二晶体管的第一极与所述第一晶体管的第二极电连接，所述第二晶体管的第二极与所述第一重置电压线电连接。
  3. 如权利要求2所述的像素电路，其中，所述重置控制线为第二发光控制线，所述第一晶体管为p型晶体管，所述第二晶体管为n型晶体管；
    所述像素电路包括第一发光控制电路和第二发光控制电路；
    所述第一发光控制电路分别与第一发光控制线、所述驱动电路的第一端和发光元件的第一极电连接，用于在第一发光控制信号的控制下，控制所述驱动电路的第一端与发光元件的第一极之间连通；
    所述第二发光控制电路分别与第二发光控制线、第一电压端和所述驱动电路的第二端电连接，用于在所述第二发光控制线提供的第二发光控制信号的控制下，控制所述第一电压端与所述驱动电路的第二端之间连通。
  4. 如权利要求1所述的像素电路，其中，所述第一重置电路包括第一晶体管和第二晶体管；
    所述第一晶体管的控制极与所述重置控制线电连接，所述第一晶体管的第一极与所述驱动电路的第一端电连接；
    所述第二晶体管的控制极与第一发光控制线电连接，所述第二晶体管的第一极与所述第一晶体管的第二极电连接，所述第二晶体管的第二极与所述第一重置电压线电连接。
  5. 如权利要求4所述的像素电路，其中，所述重置控制线为第二发光控制线，所述第一晶体管为n型晶体管，所述第二晶体管为p型晶体管；
    所述像素电路包括第一发光控制电路和第二发光控制电路；
    所述第一发光控制电路分别与第一发光控制线、所述驱动电路的第一端和发光元件的第一极电连接，用于在第一发光控制信号的控制下，控制所述驱动电路的第一端与发光元件的第一极之间连通；
    所述第二发光控制电路分别与第二发光控制线、第一电压端和所述驱动电路的第二端电连接，用于在所述第二发光控制线提供的第二发光控制信号的控制下，控制所述第一电压端与所述驱动电路的第二端之间连通。
  6. 如权利要求2或4所述的像素电路，其中，所述重置控制线为第一扫描线，所述第一晶体管和所述第二晶体管都为p型晶体管；
    所述像素电路包括第一发光控制电路和第二发光控制电路；
    所述第一发光控制电路分别与第二发光控制线、所述驱动电路的第一端和发光元件的第一极电连接，用于在所述第二发光控制线提供的第二发光控制信号的控制下，控制所述驱动电路的第一端与发光元件的第一极之间连通；
    所述第二发光控制电路分别与第一发光控制线、第一电压端和所述驱动电路的第二端电连接，用于在所述第一发光控制信号的控制下，控制所述第一电压端与所述驱动电路的第二端之间连通。
  7. 如权利要求6所述的像素电路，其中，还包括第二重置电路；
    所述第二重置电路分别与第二发光控制线、第二重置电压线和发光元件的第一极电连接，用于在第二发光控制信号的控制下，将第二重置电压线提供的第二重置电压写入所述发光元件的第一极。
  8. 如权利要求7所述的像素电路，其中，所述第二重置电路包括第三晶体管；
    所述第三晶体管的控制极与所述第二发光控制线电连接，所述第三晶体管的第一极与所述第二重置电压线电连接，所述第三晶体管的第二极与所述 发光元件的第一极电连接。
  9. 如权利要求8所述的像素电路，其中，所述第三晶体管为n型晶体管。
  10. 如权利要求1至9中任一权利要求所述的像素电路，其中，还包括补偿控制电路、数据写入电路和储能电路；
    所述补偿控制电路分别与第二扫描线、所述驱动电路的控制端和所述驱动电路的第一端电连接，用于在第二扫描线提供的第二扫描信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第一端之间连通；
    所述数据写入电路分别与第三扫描线、数据线和所述驱动电路的第二端电连接，用于在第三扫描线提供的第三扫描信号的控制下，将数据线上的数据电压写入所述驱动电路的第二端；
    所述储能电路与所述驱动电路的控制端电连接，用于储存电能。
  11. 如权利要求10所述的像素电路，其中，所述补偿控制电路包括第四晶体管，所述数据写入电路包括第五晶体管，所述驱动电路包括驱动晶体管，所述储能电路包括存储电容；
    所述驱动晶体管的控制极与所述驱动电路的控制端电连接，所述驱动晶体管的第一极与所述驱动电路的第一端电连接，所述驱动晶体管的第二极与所述驱动电路的第二端电连接；
    所述第四晶体管的控制极与所述第二扫描线电连接，所述第四晶体管的第一极与所述驱动晶体管的控制极电连接，所述第四晶体管的第二极与所述驱动电路的第一极电连接；
    所述第五晶体管的控制极与所述第三扫描线电连接，所述第五晶体管的第一极与所述数据线电连接，所述第五晶体管的第二极与所述驱动晶体管的第二极电连接；
    所述存储电容的第一端与所述驱动晶体管的控制极电连接，所述存储电容的第二端与所述第一电压端电连接。
  12. 如权利要求3或5所述的像素电路，其中，所述第一发光控制电路包括第六晶体管，所述第二发光控制电路包括第七晶体管；
    所述第六晶体管的控制极与所述第一发光控制线电连接，所述第六晶体管的第一极与所述驱动电路的第一端电连接，所述第六晶体管的第二极与所 述发光元件的第一极电连接；
    所述第七晶体管的控制极与所述第二发光控制线电连接，所述第七晶体管的第一极与所述第一电压端电连接，所述第七晶体管的第二极与所述驱动电路的第二端电连接；
    所述发光元件的第二极与第二电压端电连接。
  13. 如权利要求6所述的像素电路，其中，所述第一发光控制电路包括第六晶体管，所述第二发光控制电路包括第七晶体管；
    所述第六晶体管的控制极与所述第二发光控制线电连接，所述第六晶体管的第一极与所述驱动电路的第一端电连接，所述第六晶体管的第二极与所述发光元件的第一极电连接；
    所述第七晶体管的控制极与所述第一发光控制线电连接，所述第七晶体管的第一极与所述第一电压端电连接，所述第七晶体管的第二极与所述驱动电路的第二端电连接；
    所述发光元件的第二极与第二电压端电连接。
  14. 一种驱动方法，应用于如权利要求1至13中任一权利要求所述的像素电路，所述像素电路应用于显示面板，所述驱动方法包括：在刷新重置阶段和保持重置阶段，第一重置电路在第一发光控制线提供的第一发光控制信号和重置控制线提供的重置控制信号的控制下，控制将所述第一重置电压线提供的第一重置电压写入驱动电路的第一端。
  15. 如权利要求14所述的驱动方法，其中，所述像素电路还包括补偿控制电路；
    所述驱动方法还包括：在所述刷新重置阶段，补偿控制电路在第二扫描线提供的第二扫描信号的控制下，控制驱动电路的第一端与驱动电路的控制端之间连通，以将第一重置电压写入所述驱动电路的控制端。
  16. 如权利要求14所述的驱动方法，其中，所述像素电路还包括发光元件、补偿控制电路、数据写入电路、储能电路、第一发光控制电路和第二发光控制电路；刷新显示周期还包括设置于所述刷新重置阶段之后的刷新充电阶段和刷新发光阶段；所述驱动方法还包括：
    在所述刷新充电阶段，数据写入电路在第三扫描线提供的第三扫描信号 的控制下，将数据线上的数据电压写入驱动电路的第二端，补偿控制电路在第二扫描信号的控制下，控制驱动电路的第一端与驱动电路的控制端之间连通，以通过所述数据电压为储能电路充电；
    在刷新发光阶段，第一发光控制电路控制驱动电路的第一端与发光元件的第一极之间连通，第二发光控制电路控制第一电压端与驱动电路的第二端之间连通，驱动电路驱动发光元件发光。
  17. 如权利要求16所述的驱动方法，其中，所述像素电路还包括第一发光控制电路和发光元件；所述重置控制线为第二发光控制线；所述第一发光控制电路与第一发光控制线电连接；所述驱动方法还包括：
    在刷新重置阶段和保持重置阶段，第一发光控制电路在第一发光控制信号的控制下，控制驱动电路的第一端与发光元件的第一极之间连通，以控制将所述第一重置电压写入所述发光元件的第一极。
  18. 如权利要求16所述的驱动方法，其中，所述像素电路还包括第一发光控制电路、第二重置电路和发光元件；所述第一发光控制电路与第二发光控制线电连接；所述驱动方法还包括：
    在刷新重置阶段和保持重置阶段，第一发光控制电路在第二发光控制信号的控制下，控制驱动电路的第一端与发光元件的第一极之间断开，第二重置电路在第二发光控制信号的控制下，将第二重置电压写入发光元件的第一极。
  19. 如权利要求16至18中任一权利要求所述的驱动方法，其中，保持显示周期还包括设置于所述保持重置阶段之后的保持发光阶段；所述驱动方法还包括：
    在所述保持发光阶段，第一发光控制电路控制驱动电路的第一端与发光元件的第一极之间连通，第二发光控制电路控制第一电压端与驱动电路的第二端之间连通，驱动电路驱动发光元件发光。
  20. 如权利要求17所述的驱动方法，其中，还包括：
    检测所述显示面板的显示亮度范围，当所述显示亮度范围对应的最大亮度小于或等于预定亮度时，控制提升所述第一发光控制信号的频率和第二发光控制线提供的第二发光控制信号的频率，以使得所述第一发光控制信号的 频率和所述第二发光控制信号的频率大于预定频率。
  21. 如权利要求18所述的驱动方法，其中，还包括：
    检测所述显示面板的显示亮度范围，当所述显示亮度范围对应的最大亮度小于或等于预定亮度时，控制提升第二发光控制线提供的第二发光控制信号的频率，以使得所述第二发光控制信号的频率大于预定频率。
  22. 一种显示装置，包括如权利要求1至13中任一权利要求所述的像素电路。
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