WO2023178663A1 - 像素电路、像素驱动方法和显示装置 - Google Patents

像素电路、像素驱动方法和显示装置 Download PDF

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Publication number
WO2023178663A1
WO2023178663A1 PCT/CN2022/083081 CN2022083081W WO2023178663A1 WO 2023178663 A1 WO2023178663 A1 WO 2023178663A1 CN 2022083081 W CN2022083081 W CN 2022083081W WO 2023178663 A1 WO2023178663 A1 WO 2023178663A1
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WIPO (PCT)
Prior art keywords
control
circuit
node
electrically connected
light
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PCT/CN2022/083081
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English (en)
French (fr)
Inventor
李春阳
黄星维
王仓鸿
袁满
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/083081 priority Critical patent/WO2023178663A1/zh
Priority to CN202280000554.4A priority patent/CN117441205A/zh
Publication of WO2023178663A1 publication Critical patent/WO2023178663A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a pixel circuit, a pixel driving method and a display device.
  • the parasitic capacitance of the first node (the first node may be a node electrically connected to the first terminal of the driving circuit) will retain the charge of the previous light-emitting stage, and at the same time, the first voltage
  • the leakage factor of the transistor included in the first light-emitting control circuit will cause the first node to accumulate a certain amount of charge when entering the light-emitting stage again, causing the brightness to increase in the same display period, forming a flicker.
  • an embodiment of the present disclosure provides a pixel circuit including a first light-emitting control circuit, a driving circuit, a second light-emitting control circuit, a reset control circuit and a light-emitting element;
  • the first lighting control circuit is electrically connected to the lighting control line, the first voltage terminal and the first node respectively, and is used to control the first voltage terminal and the lighting control signal under the control of the lighting control signal provided by the lighting control line.
  • the first nodes are connected or disconnected;
  • the control end of the drive circuit is electrically connected to the second node, the first end of the drive circuit is electrically connected to the first node, the second end of the drive circuit is electrically connected to the third node;
  • the drive circuit For controlling the generation of a driving current for driving the light-emitting element under the control of the potential of its control terminal;
  • the second lighting control circuit is electrically connected to the lighting control line, the third node and the fourth node respectively, and is used to control the third node and the fourth node under the control of the lighting control signal. Nodes are connected or disconnected;
  • the first pole of the light-emitting element is electrically connected to the fourth node, and the second pole of the light-emitting element is electrically connected to the second voltage terminal;
  • the reset control circuit is electrically connected to the reset control line, the connection node and the first initial voltage terminal for providing the first initial voltage, and is used to control the reset control signal provided by the reset control line.
  • a first initial voltage is provided to the connection node;
  • connection node is the first node, the third node or the fourth node.
  • the reset control circuit is also electrically connected to the fifth node, and is used to control the connection or disconnection between the first initial voltage terminal and the fifth node under the control of the reset control signal, And control the disconnection or connection between the fifth node and the connection node, and maintain the potential of the fifth node.
  • the reset control circuit includes a first control circuit, a second control circuit and a first energy storage circuit
  • the first control circuit is electrically connected to the reset control line, the connection node and the fifth node respectively, and is used to control the connection node and the fifth node under the control of the reset control signal. connected or disconnected;
  • the second control circuit is electrically connected to the reset control line, the fifth node and the first initial voltage terminal respectively, and is used to control the voltage provided by the first initial voltage terminal under the control of the reset control signal. A first initial voltage is written into the fifth node;
  • the first energy storage circuit is electrically connected to the fifth node and is used to store electrical energy.
  • the reset control line is the lighting control line; or, the reset control signal provided by the reset control line is the same as the lighting control signal provided by the lighting control line.
  • the first control circuit includes a first transistor, and the second control circuit includes a second transistor;
  • the control electrode of the first transistor is electrically connected to the reset control line, the first electrode of the first transistor is electrically connected to the fifth node, and the second electrode of the first transistor is electrically connected to the third node. ;
  • the control electrode of the second transistor is electrically connected to the reset control line
  • the first electrode of the second transistor is electrically connected to the first initial voltage terminal
  • the second electrode of the second transistor is electrically connected to the first initial voltage terminal. Five nodes are electrically connected.
  • the first transistor is an oxide thin film transistor
  • the second transistor is a low-temperature polysilicon thin film transistor.
  • the first energy storage circuit includes a first capacitor
  • the first terminal of the first capacitor is electrically connected to the fifth node, and the second terminal of the first capacitor is electrically connected to the first voltage terminal.
  • the pixel circuit also includes a data writing circuit, a compensation control circuit, a first initialization circuit, a second energy storage circuit and a second initialization circuit;
  • the data writing circuit is electrically connected to the writing control line, the data line and the first node respectively, and is used to convert the data voltage provided by the data line under the control of the writing control signal provided by the writing control line. Write to the first node;
  • the compensation control circuit is electrically connected to the compensation control line, the control end of the drive circuit and the second end of the drive circuit respectively, and is used to control the compensation control signal under the control of the compensation control signal provided by the compensation control line.
  • the control end of the drive circuit is connected or disconnected from the second end of the drive circuit;
  • the first initialization circuit is electrically connected to the initialization control line, the second initial voltage terminal and the control terminal of the drive circuit respectively, and is used to control the second initialization circuit under the control of the initialization control signal provided by the initialization control line.
  • the second initial voltage provided by the initial voltage terminal is written into the control terminal of the driving circuit;
  • the second energy storage circuit is electrically connected to the control terminal of the drive circuit and is used to store electrical energy
  • the second initialization circuit is electrically connected to the write control line, the third initial voltage terminal and the fourth node respectively, and is used to set the third initial voltage terminal under the control of the write control signal.
  • a third initial voltage is provided to write to the fourth node.
  • the first lighting control circuit includes a third transistor
  • the second lighting control circuit includes a fourth transistor
  • the driving circuit includes a driving transistor
  • the control electrode of the third transistor is electrically connected to the light-emitting control line, the first electrode of the third transistor is electrically connected to the first voltage terminal, and the second electrode of the third transistor is electrically connected to the first voltage terminal. Node electrical connection;
  • the control electrode of the fourth transistor is electrically connected to the light-emitting control line, the first electrode of the fourth transistor is electrically connected to the third node, and the second electrode of the fourth transistor is electrically connected to the fourth node. electrical connection;
  • the control electrode of the driving transistor is electrically connected to the second node, the first electrode of the driving transistor is electrically connected to the first node, and the second electrode of the driving transistor is electrically connected to the third node.
  • the data writing circuit includes a fifth transistor
  • the compensation control circuit includes a sixth transistor
  • the first initialization circuit includes a seventh transistor
  • the second initialization circuit includes an eighth transistor
  • the The second energy storage circuit includes a second capacitor
  • the control electrode of the fifth transistor is electrically connected to the write control line, the first electrode of the fifth transistor is electrically connected to the data line, and the second electrode of the fifth transistor is electrically connected to the drive circuit.
  • the first end is electrically connected;
  • the control electrode of the sixth transistor is electrically connected to the compensation control line, the first electrode of the sixth transistor is electrically connected to the control end of the drive circuit, and the second electrode of the sixth transistor is electrically connected to the drive circuit.
  • the second end of the circuit is electrically connected;
  • the control electrode of the seventh transistor is electrically connected to the initialization control line, the first electrode of the seventh transistor is electrically connected to the second initial voltage terminal, and the second electrode of the seventh transistor is electrically connected to the driving The control terminal of the circuit is electrically connected;
  • the control electrode of the eighth transistor is electrically connected to the write control line, the first electrode of the eighth transistor is electrically connected to the third initial voltage terminal, and the second electrode of the eighth transistor is electrically connected to the above The fourth node is electrically connected;
  • the first terminal of the second capacitor is electrically connected to the second node, and the second terminal of the second capacitor is electrically connected to the first voltage terminal.
  • an embodiment of the present disclosure provides a pixel driving method, which is applied to the above-mentioned pixel circuit.
  • the display cycle includes a non-light-emitting phase and a light-emitting phase; the pixel driving method includes:
  • the reset control circuit provides the first initial voltage to the connection node under the control of the reset control signal.
  • the reset control circuit includes a first control circuit, a second control circuit and a first energy storage circuit;
  • the pixel driving method includes:
  • the second control circuit writes the first initial voltage into the fifth node under the control of the reset control signal, and the first energy storage circuit stores the first initial voltage into the fifth node;
  • the first control circuit controls the connection between the fifth node and the connection node under the control of the reset control signal to write the first initial voltage into the connection node.
  • the pixel circuit also includes a data writing circuit, a compensation control circuit, a first initialization circuit, a second energy storage circuit and a second initialization circuit;
  • the first display stage included in the display cycle includes successively set initializations.
  • the pixel driving method includes:
  • the first initialization circuit writes the second initial voltage to the control terminal of the driving circuit under the control of the reset control signal, so that at the beginning of the compensation phase, the driving circuit can adjust the potential of its control terminal to Under control, control the connection between the first node and the third node;
  • the data line provides data voltage Vdata
  • the data writing circuit writes the data voltage Vdata into the first node under the control of the writing control signal
  • the compensation control circuit controls the connection between the second node and the third node under the control of the compensation control signal
  • the first light-emitting control circuit controls the connection between the first voltage terminal and the first node under the control of the light-emitting control signal
  • the second light-emitting control circuit controls the connection between the first voltage terminal and the first node under the control of the light-emitting control signal.
  • the third node and the fourth node are connected, and the driving circuit generates a driving current for driving the light-emitting element.
  • the pixel circuit also includes a data writing circuit; the non-light-emitting phase includes a data writing phase; the display frame includes a refresh sub-display frame and at least one holding sub-display frame; the refresh sub-display frame includes the A display period, the maintained sub-display frame includes the display period; the pixel driving method further includes:
  • the data line provides a first voltage signal
  • the data writing circuit writes the first voltage signal into the first node under the control of a writing control signal.
  • the pixel circuit further includes a compensation control circuit; the display cycle further includes a compensation phase; and the pixel driving method further includes:
  • the data line provides data voltage
  • the data writing circuit writes the data voltage to the first node under the control of the writing control signal
  • the compensation control circuit controls the connection between the control end of the drive circuit and the second end of the drive circuit under the control of the compensation control signal
  • the first light-emitting control circuit controls the connection between the first voltage terminal and the first node under the control of the light-emitting control signal.
  • the second light-emitting control circuit controls the connection between the third node and the fourth node under the control of the light-emitting control signal, and the driving circuit generates a driving current for driving the light-emitting element;
  • the compensation control circuit controls the connection between the control terminal of the driving circuit and the second terminal of the driving circuit to be disconnected under the control of the compensation control signal.
  • the frequency of the writing control signal is smaller than the frequency of the lighting control signal.
  • an embodiment of the present disclosure provides a display device including the above-mentioned pixel circuit.
  • Figure 1 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure
  • Figure 2 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure
  • Figure 3 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 4 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 5 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 6 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 7 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 8 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 9 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 10 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 11 is an operating timing diagram of at least one embodiment of the pixel circuit shown in Figure 10 of the present disclosure.
  • Figure 12 is an operating timing diagram of at least one embodiment of the pixel circuit shown in Figure 10 of the present disclosure.
  • Figure 13 is an operating timing diagram of at least one embodiment of the pixel circuit shown in Figure 10 of the present disclosure.
  • Figure 14 is a schematic diagram of the brightness difference when switching frequencies according to at least one embodiment of the pixel circuit shown in Figure 10 of the present disclosure
  • Figure 15 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 16 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG. 17 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • the transistors used in all embodiments of the present disclosure may be transistors, thin film transistors, field effect transistors, or other devices with the same characteristics.
  • one pole is called the first pole and the other pole is called the second pole.
  • the first electrode when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, The second electrode may be a drain electrode.
  • the pixel circuit described in the embodiment of the present disclosure includes a first light-emitting control circuit, a driving circuit, a second light-emitting control circuit, a reset control circuit and a light-emitting element;
  • the first lighting control circuit is electrically connected to the lighting control line, the first voltage terminal and the first node respectively, and is used to control the first voltage terminal and the lighting control signal under the control of the lighting control signal provided by the lighting control line.
  • the first nodes are connected or disconnected;
  • the control end of the drive circuit is electrically connected to the second node, the first end of the drive circuit is electrically connected to the first node, the second end of the drive circuit is electrically connected to the third node;
  • the drive circuit For controlling the generation of a driving current for driving the light-emitting element under the control of the potential of its control terminal;
  • the second light-emitting control circuit is electrically connected to the light-emitting control line, the third node and the fourth node respectively, and is used to control one of the third node and the fourth node under the control of the light-emitting control signal. connected or disconnected;
  • the first pole of the light-emitting element is electrically connected to the fourth node, and the second pole of the light-emitting element is electrically connected to the second voltage terminal;
  • the reset control circuit is electrically connected to the reset control line, the connection node and the first initial voltage terminal for providing the first initial voltage, and is used to control the reset control signal provided by the reset control line.
  • a first initial voltage is provided to the connection node;
  • connection node is the first node, the third node or the fourth node.
  • the display cycle may include a non-light-emitting phase and a light-emitting phase
  • the reset control circuit provides the first initial voltage to the connection node under the control of the reset control signal, so that when entering the light-emitting phase, the additional accumulated excess charge of the first node is provided to
  • the first initial voltage of the connection node is offset, so that the phenomenon of increasing brightness within the same display period (the display period can be one frame display time, but is not limited to this) is suppressed, and flicker is improved. Phenomenon.
  • the first voltage terminal may be a high voltage terminal
  • the second voltage terminal may be a low voltage terminal, but is not limited thereto.
  • the light-emitting element may be an organic light-emitting diode, but is not limited thereto.
  • the non-light-emitting phase may include a time period included in the display period other than the light-emitting phase, but is not limited to this.
  • the reset control line is the light-emitting control line; or, the reset control signal provided by the reset control line is the same as the light-emitting control signal provided by the light-emitting control line; but this is not the case. is limited.
  • the reset control circuit is also electrically connected to a fifth node for controlling the connection between the first initial voltage terminal and the fifth node under the control of the reset control signal. connected or disconnected, and controls the disconnection or connection between the fifth node and the connecting node, and is used to maintain the potential of the fifth node.
  • the voltage value of the first initial voltage may be greater than or equal to -3V and less than or equal to -2.3V.
  • the voltage value of the first initial voltage may be -3V, -2.3V, -2.4V, - 2.5V or -2.8V, but not limited to this.
  • the pixel circuit includes a first light emitting control circuit 11, a driving circuit 12, a second light emitting control circuit 13, a reset control circuit 20 and a light emitting element 10;
  • the first light-emitting control circuit 11 is electrically connected to the light-emitting control line E1, the first voltage terminal V1 and the first node N1 respectively, and is used to control the first light-emitting control circuit 11 under the control of the light-emitting control signal provided by the light-emitting control line E1.
  • a voltage terminal V1 is connected to the first node N1; the first voltage terminal V1 is used to provide a first voltage signal;
  • the control terminal of the driving circuit 12 is electrically connected to the second node N2, the first terminal of the driving circuit 12 is electrically connected to the first node N1, and the second terminal of the driving circuit 12 is electrically connected to the third node N3. Connection; the driving circuit is used to control the generation of the driving current that drives the light-emitting element 10 under the control of the potential of its control terminal;
  • the second lighting control circuit 13 is electrically connected to the lighting control line E1, the third node N3 and the fourth node N4 respectively, and is used to control the third node N3 and the third node N3 under the control of the lighting control signal.
  • the fourth node N4 is connected;
  • the first pole of the light-emitting element 10 is electrically connected to the fourth node N4, and the second pole of the light-emitting element 10 is electrically connected to the second voltage terminal V2;
  • the reset control circuit 20 is electrically connected to the reset control line R0, the third node N3 and the first initial voltage terminal I1 for providing the first initial voltage Vi1, respectively, for the reset control signal provided on the reset control line R0. Under the control of , the first initial voltage Vi1 is provided to the third node N3.
  • connection node is the third node N3.
  • the reset control line may be the light emission control line, or the reset control signal provided by the reset control line and the light emission control provided by the light emission control line
  • the signals can be the same control signal, but are not limited to this.
  • the display cycle includes a light-emitting phase and a non-light-emitting phase
  • the reset control circuit 20 provides the first initial voltage Vi1 to the third node N3 under the control of the reset control signal to reset the potential of the third node N3, thereby
  • the excess charge accumulated in the first node N1 is offset by the reset low potential when flowing through the third node N3, so that the brightness appears within the same display period (the display period can be one frame display time). The increasing phenomenon is suppressed and the flicker problem is improved.
  • the pixel circuit includes a first light-emitting control circuit 11, a driving circuit 12, a second light-emitting control circuit 13, a reset control circuit 20 and a light-emitting element 10;
  • the first lighting control circuit 11 is electrically connected to the lighting control line E1, the first voltage terminal V1 and the first node N1 respectively, and is used to control the first lighting control signal under the control of the lighting control signal provided by the lighting control line E1.
  • a voltage terminal V1 is connected to the first node N1; the first voltage terminal V1 is used to provide a first voltage signal;
  • the control terminal of the driving circuit 12 is electrically connected to the second node N2; the driving circuit is used to control the generation of a driving current for driving the light-emitting element 10 under the control of the potential of its control terminal;
  • the second lighting control circuit 13 is electrically connected to the lighting control line E1, the third node N3 and the fourth node N4 respectively, and is used to control the third node N3 and the third node N3 under the control of the lighting control signal.
  • the fourth node N4 is connected;
  • the first pole of the light-emitting element 10 is electrically connected to the fourth node N4, and the second pole of the light-emitting element 10 is electrically connected to the second voltage terminal V2;
  • the reset control circuit 20 is electrically connected to the reset control line R0, the first node N1 and the first initial voltage terminal I1 for providing the first initial voltage Vi1, respectively, for the reset control signal provided on the reset control line R0. Under the control of , the first initial voltage Vi1 is provided to the first node N1.
  • connection node is the first node N1.
  • the reset control line may be the light-emitting control line, or the reset control signal provided by the reset control line and the light-emitting control provided by the light-emitting control line
  • the signals can be the same control signal, but are not limited to this.
  • the display cycle includes a light-emitting phase and a non-light-emitting phase
  • the reset control circuit 20 provides the first initial voltage Vi1 to the first node N1 under the control of the reset control signal, so that when entering the light-emitting phase again, the first node N1 additionally
  • the accumulated excess charge is offset by the reset low potential, so that the phenomenon of increasing brightness within the same display period (the display period may be one frame display time) is suppressed, thereby improving the flicker problem.
  • the pixel circuit includes a first light-emitting control circuit 11, a driving circuit 12, a second light-emitting control circuit 13, a reset control circuit 20 and a light-emitting element 10;
  • the first light-emitting control circuit 11 is electrically connected to the light-emitting control line E1, the first voltage terminal V1 and the first node N1 respectively, and is used to control the first light-emitting control circuit 11 under the control of the light-emitting control signal provided by the light-emitting control line E1.
  • a voltage terminal V1 is connected to the first node N1; the first voltage terminal V1 is used to provide a first voltage signal;
  • the control terminal of the driving circuit 12 is electrically connected to the second node N2; the driving circuit is used to control the generation of a driving current for driving the light-emitting element 10 under the control of the potential of its control terminal;
  • the second lighting control circuit 13 is electrically connected to the lighting control line E1, the third node N3 and the fourth node N4 respectively, and is used to control the third node N3 and the third node N3 under the control of the lighting control signal.
  • the fourth node N4 is connected;
  • the first pole of the light-emitting element 10 is electrically connected to the fourth node N4, and the second pole of the light-emitting element 10 is electrically connected to the second voltage terminal V2;
  • the reset control circuit 20 is electrically connected to the reset control line R0, the fourth node N4 and the first initial voltage terminal I1 for providing the first initial voltage Vi1, respectively, for the reset control signal provided on the reset control line R0. Under the control of , the first initial voltage Vi1 is provided to the fourth node N4.
  • connection node is the fourth node N4.
  • the reset control line may be the lighting control line, or the reset control signal provided by the reset control line and the lighting control provided by the lighting control line
  • the signals can be the same control signal, but are not limited to this.
  • the display cycle includes a light-emitting phase and a non-light-emitting phase
  • the reset control circuit 20 provides the first initial voltage Vi1 to the fourth node N4 under the control of the reset control signal, so that when entering the light-emitting stage again, the first node N1 additionally
  • the accumulated excess charge is offset by the reset low potential when flowing through the fourth node N4, so that the phenomenon of increasing brightness within the same display period (the display period can be one frame display time) is suppressed, and flicker is improved. question.
  • the reset control circuit may include a first control circuit, a second control circuit and a first energy storage circuit
  • the first control circuit is electrically connected to the reset control line, the connection node and the fifth node respectively, and is used to control the connection node and the fifth node under the control of the reset control signal. connected or disconnected;
  • the second control circuit is electrically connected to the reset control line, the fifth node and the first initial voltage terminal respectively, and is used to control the voltage provided by the first initial voltage terminal under the control of the reset control signal. A first initial voltage is written into the fifth node;
  • the first energy storage circuit is electrically connected to the fifth node and is used to store electrical energy.
  • the reset control circuit may include a first control circuit, a second control circuit and a first energy storage circuit
  • the second control circuit writes the first initial voltage into the fifth node under the control of the reset control signal, and the first energy storage circuit stores the first initial voltage into the fifth node N5;
  • the first control circuit controls the connection between the fifth node and the third node under the control of the reset control signal to write the first initial voltage into the connection node.
  • the pixel circuit includes a first light emitting control circuit 11, a driving circuit 12, a second light emitting control circuit 13, a reset control circuit and a light emitting element 10;
  • the reset circuit includes a first control circuit circuit 14, second control circuit 15 and first energy storage circuit 16;
  • the first light-emitting control circuit 11 is electrically connected to the light-emitting control line E1, the first voltage terminal V1 and the first node N1 respectively, and is used to control the first light-emitting control circuit 11 under the control of the light-emitting control signal provided by the light-emitting control line E1.
  • a voltage terminal V1 is connected to the first node N1; the first voltage terminal V1 is used to provide a first voltage signal;
  • the control terminal of the driving circuit 12 is electrically connected to the second node N2; the driving circuit is used to control the generation of a driving current for driving the light-emitting element 10 under the control of the potential of its control terminal;
  • the second lighting control circuit 13 is electrically connected to the lighting control line E1, the third node N3 and the fourth node N4 respectively, and is used to control the third node N3 and the third node N3 under the control of the lighting control signal.
  • the fourth node N4 is connected;
  • the first pole of the light-emitting element 10 is electrically connected to the fourth node N4, and the second pole of the light-emitting element 10 is electrically connected to the second voltage terminal V2;
  • the first control circuit 14 is electrically connected to the lighting control line E1, the third node N3 and the fifth node N5 respectively, and is used to control the third node N3 and the fifth node N5 under the control of the lighting control signal.
  • the fifth node N5 is connected;
  • the second control circuit 15 is electrically connected to the light-emitting control line E1, the fifth node N5 and the first initial voltage terminal I1 respectively, and is used to control the first light-emitting voltage terminal under the control of the light-emitting control signal.
  • the first initial voltage Vi1 provided by the initial voltage terminal I1 is written into the fifth node N5;
  • the first energy storage circuit 16 is electrically connected to the fifth node N5 and is used to store electrical energy.
  • connection node is the third node N3
  • the reset control line is the light-emitting control line E1 .
  • the second control circuit 15 writes the first initial voltage Vi1 into the fifth node N5 under the control of the light-emitting control signal, and the first energy storage circuit 16 stores the first initial voltage Vi1 at the fifth node N5. ;
  • Vi1 stored in the fifth node N5 resets the potential of the third node N3 through the first control circuit 14, so that when entering the light-emitting stage again, the excess charge accumulated in the first node N1 flows
  • the low potential that is reset when passing through the third node N3 is offset, so that the phenomenon of increasing brightness within the same display period (the display period may be one frame display time) is suppressed, and the flicker problem is improved.
  • the pixel circuit includes a first light-emitting control circuit 11, a driving circuit 12, a second light-emitting control circuit 13, a reset control circuit and a light-emitting element 10;
  • the reset control circuit includes a first Control circuit 14, second control circuit 15 and first energy storage circuit 16;
  • the first light-emitting control circuit 11 is electrically connected to the light-emitting control line E1, the first voltage terminal V1 and the first node N1 respectively, and is used to control the first light-emitting control circuit 11 under the control of the light-emitting control signal provided by the light-emitting control line E1.
  • a voltage terminal V1 is connected to the first node N1; the first voltage terminal V1 is used to provide a first voltage signal;
  • the control terminal of the driving circuit 12 is electrically connected to the second node N2; the driving circuit is used to control the generation of a driving current for driving the light-emitting element 10 under the control of the potential of its control terminal;
  • the second lighting control circuit 13 is electrically connected to the lighting control line E1, the third node N3 and the fourth node N4 respectively, and is used to control the third node N3 and the third node N3 under the control of the lighting control signal.
  • the fourth node N4 is connected;
  • the first pole of the light-emitting element 10 is electrically connected to the fourth node N4, and the second pole of the light-emitting element 10 is electrically connected to the second voltage terminal V2;
  • the first control circuit 14 is electrically connected to the lighting control line E1, the first node N1 and the fifth node N5 respectively, and is used to control the first node N1 and the fifth node N5 under the control of the lighting control signal.
  • the fifth node N5 is connected;
  • the second control circuit 15 is electrically connected to the light-emitting control line E1, the fifth node N5 and the first initial voltage terminal I1 respectively, and is used to control the first light-emitting voltage terminal under the control of the light-emitting control signal.
  • the first initial voltage Vi1 provided by the initial voltage terminal I1 is written into the fifth node N5;
  • the first energy storage circuit 16 is electrically connected to the fifth node N5 and is used to store electrical energy.
  • connection node is the first node N1
  • the reset control line is the light-emitting control line E1 .
  • the display cycle includes a non-light-emitting phase and a light-emitting phase
  • the second control circuit 15 writes the first initial voltage Vi1 into the fifth node N5 under the control of the light-emitting control signal, and the first energy storage circuit 16 stores the first initial voltage Vi1 at the fifth node N5. ;
  • Vi1 stored in the fifth node N5 resets the potential of the first node N1 through the first control circuit 14, so that when entering the light-emitting stage again, so that when entering the light-emitting stage again, the third
  • the excess charge accumulated at one node N1 is offset by the reset low potential, so that the phenomenon of increasing brightness within the same display period (the display period may be one frame display time) is suppressed, thereby improving the flicker problem.
  • the pixel circuit includes a first light-emitting control circuit 11, a driving circuit 12, a second light-emitting control circuit 13, a reset control circuit and a light-emitting element 10;
  • the reset control circuit includes a first Control circuit 14, second control circuit 15 and first energy storage circuit 16;
  • the first light-emitting control circuit 11 is electrically connected to the light-emitting control line E1, the first voltage terminal V1 and the first node N1 respectively, and is used to control the first light-emitting control circuit 11 under the control of the light-emitting control signal provided by the light-emitting control line E1.
  • a voltage terminal V1 is connected to the first node N1; the first voltage terminal V1 is used to provide a first voltage signal;
  • the control terminal of the driving circuit 12 is electrically connected to the second node N2; the driving circuit is used to control the generation of a driving current for driving the light-emitting element 10 under the control of the potential of its control terminal;
  • the second lighting control circuit 13 is electrically connected to the lighting control line E1, the third node N3 and the fourth node N4 respectively, and is used to control the third node N3 and the third node N3 under the control of the lighting control signal.
  • the fourth node N4 is connected;
  • the first pole of the light-emitting element 10 is electrically connected to the fourth node N4, and the second pole of the light-emitting element 10 is electrically connected to the second voltage terminal V2;
  • the first control circuit 14 is electrically connected to the lighting control line E1, the fourth node N4 and the fifth node N5 respectively, and is used to control the fourth node N4 and the fifth node N5 under the control of the lighting control signal.
  • the fifth node N5 is connected;
  • the second control circuit 15 is electrically connected to the light-emitting control line E1, the fifth node N5 and the first initial voltage terminal I1 respectively, and is used to control the first light-emitting voltage terminal under the control of the light-emitting control signal.
  • the first initial voltage Vi1 provided by the initial voltage terminal I1 is written into the fifth node N5;
  • the first energy storage circuit 16 is electrically connected to the fifth node N5 and is used to store electrical energy.
  • connection node is the fourth node N4
  • the reset control line is the light-emitting control line E1 .
  • the display cycle includes a non-light-emitting phase and a light-emitting phase
  • the second control circuit 15 writes the first initial voltage Vi1 into the fifth node N5 under the control of the light-emitting control signal, and the first energy storage circuit 16 stores the first initial voltage Vi1 at the fifth node N5. ;
  • Vi1 stored in the fifth node N5 resets the potential of the fourth node N4 through the first control circuit 14, so that when entering the light-emitting stage again, the excess charge accumulated in the first node N1 is When flowing through the fourth node N4, it is offset by the reset low potential, so that the phenomenon of increasing brightness within the same display period (the display period may be one frame display time) is suppressed, thereby improving the flicker problem.
  • the first control circuit includes a first transistor, and the second control circuit includes a second transistor;
  • the control electrode of the first transistor is electrically connected to the reset control line, the first electrode of the first transistor is electrically connected to the fifth node, and the second electrode of the first transistor is electrically connected to the third node. ;
  • the control electrode of the second transistor is electrically connected to the reset control line
  • the first electrode of the second transistor is electrically connected to the first initial voltage terminal
  • the second electrode of the second transistor is electrically connected to the first initial voltage terminal. Five nodes are electrically connected.
  • the first transistor is an oxide thin film transistor
  • the second transistor is a low-temperature polysilicon thin film transistor.
  • the first energy storage circuit includes a first capacitor
  • the first terminal of the first capacitor is electrically connected to the fifth node, and the second terminal of the first capacitor is electrically connected to the first voltage terminal.
  • the pixel circuit may also include a data writing circuit, a compensation control circuit, a first initialization circuit, a second energy storage circuit and a second initialization circuit;
  • the data writing circuit is electrically connected to the writing control line, the data line and the first node respectively, and is used to convert the data voltage provided by the data line under the control of the writing control signal provided by the writing control line. Write to the first node;
  • the compensation control circuit is electrically connected to the compensation control line, the control end of the drive circuit and the second end of the drive circuit respectively, and is used to control the compensation control signal under the control of the compensation control signal provided by the compensation control line.
  • the control end of the drive circuit is connected to the second end of the drive circuit;
  • the first initialization circuit is electrically connected to the initialization control line, the second initial voltage terminal and the control terminal of the drive circuit respectively, and is used to control the second initialization circuit under the control of the initialization control signal provided by the initialization control line.
  • the second initial voltage provided by the initial voltage terminal is written into the control terminal of the driving circuit, so that at the beginning of the compensation phase, the driving circuit can control the first terminal of the driving circuit under the control of the potential of its control terminal. Communicated with the second end of the driving circuit;
  • the second energy storage circuit is electrically connected to the control terminal of the drive circuit and is used to store electrical energy
  • the second initialization circuit is electrically connected to the write control line, the third initial voltage terminal and the fourth node respectively, and is used to set the third initial voltage terminal under the control of the write control signal.
  • the provided third initial voltage is written into the fourth node to control the light-emitting element not to emit light.
  • the pixel circuit further includes a data writing circuit 41, a compensation control circuit, a first initialization circuit, a second energy storage circuit and a second initialization circuit, and the data writing circuit is used to Control data voltage writing, the compensation control circuit is used to control threshold voltage compensation; the first initialization circuit is used to reset the potential of the control end of the drive circuit to control the drive circuit when the compensation phase begins.
  • the second energy storage circuit is used to maintain the potential of the control end of the drive circuit
  • the second initialization circuit is used to reset the potential of the first pole of the light-emitting element to control the light-emitting element not to emit light.
  • the display frame may include a refresh sub-display frame and at least one holding sub-display frame;
  • the data line may provide a first voltage signal
  • the data writing circuit writes the first voltage signal into the first node under the control of a writing control signal.
  • the potential of the first node will be maintained at the first voltage value (the first voltage value is the voltage value of the first voltage signal) , so that when different frequencies are displayed, the potential of the first node is maintained at the same level, reducing the brightness difference.
  • the first voltage signal may be a high voltage signal, and the first voltage value may be greater than or equal to 2.5V and less than or equal to 7V; for example, the first voltage value may be 2.5V, 3V, 4V, 4.6V, 5V, 5.8V, 6.4V or 7V, but not limited to this.
  • the display frame may include a refresh sub-display frame and at least one holding sub-display frame.
  • the data voltage is written into the pixel circuit and emits light accordingly, and the holding sub-display frame
  • the display frame at least extends the lighting time and achieves the purpose of low frequency; in the holding sub-display frame, the data line provides a DC voltage signal, for example, the voltage value of the DC voltage signal can be 6.4V; in the holding sub-display frame frame, the DC voltage signal will leak to the first node through the transistor included in the data writing circuit, causing the potential of the first node to rise.
  • At least one embodiment of the present disclosure controls the data line to provide a first voltage signal while maintaining the sub-display frame, so as to improve the problem of large brightness differences when displaying at different frequencies.
  • the data line when the pixel circuit performs low-frequency display, can be controlled to provide the first voltage signal in a time period other than the data writing phase in the refresh sub-display frame;
  • the data line may be controlled to provide the first voltage signal.
  • the pixel circuit according to at least one embodiment of the present disclosure also includes a data writing circuit 41 , a compensation control circuit 42 , and a first initialization circuit. Circuit 43, second energy storage circuit 44 and second initialization circuit 45;
  • the data writing circuit 41 is electrically connected to the writing control line GP, the data line D1 and the first node N1 respectively, and is used to write the data under the control of the writing control signal provided by the writing control line GP.
  • the data voltage provided by line D1 is written into the first node N1;
  • the compensation control circuit 42 is electrically connected to the compensation control line GN, the control end of the drive circuit 12 and the second end of the drive circuit 12 respectively, and is used to control the compensation control signal provided on the compensation control line GN. Next, control the connection between the control terminal of the driving circuit 12 and the second terminal of the driving circuit 12;
  • the first initialization circuit 43 is electrically connected to the initialization control line R1, the second initial voltage terminal I2 and the control terminal of the drive circuit 12 respectively, and is used for controlling the initialization control signal provided by the initialization control line R1, Write the second initial voltage Vi2 provided by the second initial voltage terminal I2 into the control terminal of the driving circuit 12;
  • the second energy storage circuit 44 is electrically connected to the control terminal of the drive circuit 12 for storing electrical energy
  • the second initialization circuit 45 is electrically connected to the write control line GP, the third initial voltage terminal I3 and the fourth node N4 respectively, and is used to set the third initialization circuit 45 to the write control line GP under the control of the write control signal.
  • the third initial voltage provided by the three initial voltage terminals I3 is written into the fourth node N4.
  • the second initial voltage Vi2 may be greater than or equal to -5V and less than or equal to -3V, but is not limited to this.
  • the third initial voltage terminal I3 may be the same initial voltage terminal as the first initial voltage terminal I1, but is not limited to this. In actual operation, the third initial voltage terminal I3 may be a different initial voltage terminal from the first initial voltage terminal I1.
  • the pixel circuit As shown in FIG. 8 , based on at least one embodiment of the pixel circuit shown in FIG. 5 , the pixel circuit according to at least one embodiment of the present disclosure also includes a data writing circuit 41 , a compensation control circuit 42 , a first initialization Circuit 43, second energy storage circuit 44 and second initialization circuit 45;
  • the data writing circuit 41 is electrically connected to the writing control line GP, the data line D1 and the first node N1 respectively, and is used to write the data under the control of the writing control signal provided by the writing control line GP.
  • the data voltage provided by line D1 is written into the first node N1;
  • the compensation control circuit 42 is electrically connected to the compensation control line GN, the control end of the drive circuit 12 and the second end of the drive circuit 12 respectively, and is used to control the compensation control signal provided on the compensation control line GN. Next, control the connection between the control terminal of the driving circuit 12 and the second terminal of the driving circuit 12;
  • the first initialization circuit 43 is electrically connected to the initialization control line R1, the second initial voltage terminal I2 and the control terminal of the drive circuit 12 respectively, and is used for controlling the initialization control signal provided by the initialization control line R1, Write the second initial voltage Vi2 provided by the second initial voltage terminal I2 into the control terminal of the driving circuit 12;
  • the second energy storage circuit 44 is electrically connected to the control terminal of the drive circuit 12 for storing electrical energy
  • the second initialization circuit 45 is electrically connected to the write control line GP, the third initial voltage terminal I3 and the fourth node N4 respectively, and is used to set the third initialization circuit 45 to the write control line GP under the control of the write control signal.
  • the third initial voltage provided by the three initial voltage terminals I3 is written into the fourth node N4.
  • the pixel circuit As shown in FIG. 9 , based on at least one embodiment of the pixel circuit shown in FIG. 6 , the pixel circuit according to at least one embodiment of the present disclosure also includes a data writing circuit 41 , a compensation control circuit 42 , a first initialization Circuit 43, second energy storage circuit 44 and second initialization circuit 45;
  • the data writing circuit 41 is electrically connected to the writing control line GP, the data line D1 and the first node N1 respectively, and is used to write the data under the control of the writing control signal provided by the writing control line GP.
  • the data voltage provided by line D1 is written into the first node N1;
  • the compensation control circuit 42 is electrically connected to the compensation control line GN, the control end of the drive circuit 12 and the second end of the drive circuit 12 respectively, and is used to control the compensation control signal provided on the compensation control line GN. Next, control the connection between the control terminal of the driving circuit 12 and the second terminal of the driving circuit 12;
  • the first initialization circuit 43 is electrically connected to the initialization control line R1, the second initial voltage terminal I2 and the control terminal of the drive circuit 12 respectively, and is used for controlling the initialization control signal provided by the initialization control line R1, Write the second initial voltage Vi2 provided by the second initial voltage terminal I2 into the control terminal of the driving circuit 12;
  • the second energy storage circuit 44 is electrically connected to the control terminal of the drive circuit 12 for storing electrical energy
  • the second initialization circuit 45 is electrically connected to the write control line GP, the third initial voltage terminal I3 and the fourth node N4 respectively, and is used to set the third initialization circuit 45 to the write control line GP under the control of the write control signal.
  • the third initial voltage provided by the three initial voltage terminals I3 is written into the fourth node N4.
  • the first lighting control circuit includes a third transistor
  • the second lighting control circuit includes a fourth transistor
  • the driving circuit includes a driving transistor
  • the control electrode of the third transistor is electrically connected to the light-emitting control line, the first electrode of the third transistor is electrically connected to the first voltage terminal, and the second electrode of the third transistor is electrically connected to the first voltage terminal. Node electrical connection;
  • the control electrode of the fourth transistor is electrically connected to the light-emitting control line, the first electrode of the fourth transistor is electrically connected to the third node, and the second electrode of the fourth transistor is electrically connected to the fourth node. electrical connection;
  • the control electrode of the driving transistor is electrically connected to the second node, the first electrode of the driving transistor is electrically connected to the first node, and the second electrode of the driving transistor is electrically connected to the third node.
  • the data writing circuit includes a fifth transistor
  • the compensation control circuit includes a sixth transistor
  • the first initialization circuit includes a seventh transistor
  • the second initialization circuit includes an eighth transistor
  • the The second energy storage circuit includes a second capacitor
  • the control electrode of the fifth transistor is electrically connected to the write control line, the first electrode of the fifth transistor is electrically connected to the data line, and the second electrode of the fifth transistor is electrically connected to the drive circuit.
  • the first end is electrically connected;
  • the control electrode of the sixth transistor is electrically connected to the compensation control line, the first electrode of the sixth transistor is electrically connected to the control end of the drive circuit, and the second electrode of the sixth transistor is electrically connected to the drive circuit.
  • the second end of the circuit is electrically connected;
  • the control electrode of the seventh transistor is electrically connected to the initialization control line, the first electrode of the seventh transistor is electrically connected to the second initial voltage terminal, and the second electrode of the seventh transistor is electrically connected to the driving The control terminal of the circuit is electrically connected;
  • the control electrode of the eighth transistor is electrically connected to the write control line, the first electrode of the eighth transistor is electrically connected to the third initial voltage terminal, and the second electrode of the eighth transistor is electrically connected to the above The fourth node is electrically connected;
  • the first terminal of the second capacitor is electrically connected to the second node, and the second terminal of the second capacitor is electrically connected to the first voltage terminal.
  • the light-emitting element is an organic light-emitting diode O1;
  • the first control circuit 14 includes a first transistor T1, and the second The control circuit 15 includes a second transistor T2;
  • the gate of the first transistor T1 is electrically connected to the light emitting control line E1, the source of the first transistor T1 is electrically connected to the fifth node N5, and the drain of the first transistor T1 is electrically connected to the third node N3. electrical connection;
  • the gate of the second transistor T2 is electrically connected to the light-emitting control line E1
  • the source of the second transistor T2 is electrically connected to the first initial voltage terminal I1
  • the drain of the second transistor T2 is electrically connected to the first initial voltage terminal I1.
  • the fifth node N5 is electrically connected; the first initial voltage terminal I1 is used to provide the first initial voltage Vi1;
  • the first energy storage circuit 16 includes a first capacitor C1;
  • the first end of the first capacitor C1 is electrically connected to the fifth node N5, and the second end of the first capacitor C1 is electrically connected to the high voltage terminal VDD;
  • the first lighting control circuit 11 includes a third transistor T3, the second lighting control circuit 13 includes a fourth transistor T4, and the driving circuit 12 includes a driving transistor T0;
  • the gate of the third transistor T3 is electrically connected to the light-emitting control line E1, the source of the third transistor T3 is electrically connected to the high voltage terminal VDD, and the drain of the third transistor T3 is electrically connected to the first Node N1 is electrically connected;
  • the gate of the fourth transistor T4 is electrically connected to the light-emitting control line E1, the source of the fourth transistor T4 is electrically connected to the third node N3, and the drain of the fourth transistor T4 is electrically connected to the light-emitting control line E1.
  • the fourth node N4 is electrically connected; the anode of the organic light-emitting diode O1 is electrically connected with the fourth node N4, and the cathode of the organic light-emitting diode O1 is electrically connected with the low voltage terminal VSS;
  • the gate of the driving transistor T0 is electrically connected to the second node N2, the source of the driving transistor T0 is electrically connected to the first node N1, and the drain of the driving transistor T2 is electrically connected to the third node. N3 electrical connection;
  • the data writing circuit 41 includes a fifth transistor T5, the compensation control circuit 42 includes a sixth transistor T6, the first initialization circuit 43 includes a seventh transistor T7, and the second initialization circuit 45 includes an eighth transistor T8. , the second energy storage circuit 44 includes a second capacitor C2;
  • the gate of the fifth transistor T5 is electrically connected to the write control line GP, the source of the fifth transistor T5 is electrically connected to the data line D1, and the drain of the fifth transistor T5 is electrically connected to the data line D1.
  • the source of the driving transistor T0 is electrically connected;
  • the gate of the sixth transistor T6 is electrically connected to the compensation control line GN, the source of the sixth transistor T6 is electrically connected to the gate of the driving transistor T0, and the drain of the sixth transistor T6 is electrically connected to the compensation control line GN.
  • the drain of the driving transistor T0 is electrically connected;
  • the gate of the seventh transistor T7 is electrically connected to the initialization control line R1, the source of the seventh transistor T7 is electrically connected to the second initial voltage terminal I2, and the drain of the seventh transistor T7 is electrically connected to the initialization control line R1.
  • the gate of the driving transistor T0 is electrically connected; the second initial voltage terminal I2 is used to provide a second initial voltage Vi2;
  • the gate of the eighth transistor T8 is electrically connected to the write control line GP, the source of the eighth transistor T8 is electrically connected to the first initial voltage terminal I1, and the drain of the eighth transistor T8 Electrically connected to the fourth node N4 mentioned above;
  • the first end of the second capacitor C2 is electrically connected to the second node N2, and the second end of the second capacitor C2 is electrically connected to the high voltage terminal VDD.
  • C0 is the parasitic capacitance between the first node N1 and the high voltage terminal VDD.
  • the first initial voltage terminal and the third initial voltage terminal are the same voltage terminal, the first voltage terminal is a high voltage terminal VDD, and the third initial voltage terminal is a high voltage terminal VDD.
  • the second voltage terminal is the low voltage terminal VSS, but it is not limited to this.
  • the reset control line is the light emission control line E1.
  • T1, T6, and T7 are oxide thin film transistors
  • T0, T2, T3, T4, T5, and T8 are low-temperature polysilicon thin film transistors, but are not limited thereto.
  • the display cycle may include an initialization phase S1, a compensation phase S2, a data writing phase and a light emitting phase S3;
  • the data writing stage is included in the compensation stage S2; the initialization stage S1, the compensation stage S2 and the light-emitting stage S3 are set successively;
  • R1 provides a high voltage signal
  • T7 is turned on to provide the second initial voltage Vi2 provided by the second initial voltage terminal I2 to the second node N2, so that at the beginning of the compensation phase, the driving transistor T0 can conduct;
  • GN provides a low voltage signal
  • GP provides a high voltage signal
  • E1 provides a high voltage signal
  • T1 is turned on
  • T2, T3, T4, T5, T6 and T0 are all turned off
  • the data line D1 provides the data voltage Vdata
  • GP provides the low voltage signal
  • T5 is turned on to write the data voltage Vdata to the first node N1
  • T8 is turned on to write the first initial voltage Vi1 to the anode of O1, so that O1 does not glow; glow;
  • GN provides a high voltage signal
  • E1 provides a high voltage signal
  • R1 provides a low voltage signal
  • T7 is turned off
  • T1 is turned on
  • T6 is turned on to connect the second node N2 and the third node N3;
  • T0 is turned on, and Vdata charges C2 through T5, T0 and T6 to increase the potential of the second node N2 until T0 is turned off, at which time the potential of the second node N2 is Vdata+Vth, Vth is the threshold voltage of T0, and Vth is a negative value;
  • E1 provides a low-voltage signal
  • R1 provides a low-voltage signal
  • GN provides a low-voltage signal
  • GP provides a high-voltage signal.
  • T3 and T4 are both turned on, and T0 drives O1 to emit light; T2 is turned on to connect the first initial voltage terminal.
  • the first initial voltage Vi1 provided by I1 is written into the fifth node N5.
  • L0 is the luminous brightness of O1.
  • the data writing stage is included in the compensation stage S2, but is not limited to this; in actual operation, the data writing stage can also be included in the compensation stage S2. for the same time period.
  • the label GP_2 is the next row write control line adjacent to GP
  • the waveform corresponding to GP_2 is the waveform of the next row write control signal provided by the next row write control line.
  • GP in the first half of the compensation phase S2, GP provides a low voltage signal, and in the second half of the compensation phase S2, GP_2 provides a low voltage signal to control the time sharing of adjacent row pixel circuits. Connect the corresponding data voltage.
  • T2 is turned on to write the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the fifth node N5.
  • a capacitor C1 stores the first initial voltage Vi1 at the fifth node N5;
  • the non-light-emitting phase may be the time period included in the display period except the light-emitting phase
  • T1 is turned on to control the connection between the fifth node N5 and the third node N3 to connect
  • the first initial voltage Vi1 is written into the third node N3, so that when entering the light-emitting stage again, the excess charge accumulated by the first node N1 is offset by the reset low potential when flowing through the third node N3, thus the same
  • the phenomenon of increasing brightness within a display period (the display period may be one frame of display time) is suppressed, thereby improving the flicker problem.
  • the display cycle in the refresh sub-display frame may include an initialization phase S1, a compensation phase S2, and a data writing phase that are set successively.
  • the initialization stage S1, the compensation stage S2, the first light-emitting stage S31, the second light-emitting stage S32, the third light-emitting stage S33 and the fourth light-emitting stage S34 are set successively;
  • a first interval stage S01 is provided between the first light-emitting stage S31 and the second light-emitting stage S32.
  • a second interval stage S02 is provided between the second light-emitting stage S32 and the third light-emitting stage S33.
  • a first interval stage S01 is provided in the third light-emitting stage S33.
  • a third interval stage S03 is provided between the stage S33 and the fourth lighting stage S34;
  • R1 provides a high voltage signal
  • T7 is turned on to provide the second initial voltage Vi2 provided by the second initial voltage terminal I2 to the second node N2, so that at the beginning of the compensation phase, the driving transistor T0 can conduct;
  • GN provides a low voltage signal
  • GP provides a high voltage signal
  • E1 provides a high voltage signal
  • T1 is turned on
  • T2, T3, T4, T5, T6 and T0 are all turned off;
  • data line D1 provides data voltage Vdata
  • GP provides a low voltage signal
  • T5 is turned on to write data voltage Vdata to the first node N1
  • T8 is turned on to write the first initial voltage Vi1 to O1 anode so that O1 does not emit light
  • GN provides a high voltage signal
  • E1 provides a high voltage signal
  • R1 provides a low voltage signal
  • T7 is turned off
  • T1 is turned on
  • T6 is turned on to connect the second node N2 and the third node N3;
  • T0 is turned on, and Vdata charges C2 through T5, T0 and T6 to increase the potential of the second node N2 until T0 is turned off, at which time the potential of the second node N2 is Vdata+Vth, Vth is the threshold voltage of T0, and Vth is a negative value;
  • E1 provides a low voltage signal
  • R1 provides a low voltage signal
  • GN Provide a low voltage signal
  • GP provides a high voltage signal
  • both T3 and T4 are turned on, T0 drives O1 to emit light;
  • T2 is turned on to write the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the fifth node N5;
  • E1 provides a high voltage signal
  • R1 provides a low voltage signal
  • GN provides a low voltage signal
  • GP provides a high voltage signal
  • T1 is turned on to store the The first initial voltage Vi1 of the fifth node N5 is written into the third node N3.
  • the frequency of the write control signal provided by the write control line GP is smaller than that provided by the light-emitting control line E1
  • the frequency of the light-emitting control signal, the light-emitting control signal is a high-frequency signal
  • the write control signal, the initialization control signal provided by the initialization control line R1, and the compensation control signal provided by the compensation control line GN are all for low-frequency signals to reduce power consumption.
  • the display frame may include a refresh sub-display frame F1 and at least one holding sub-display frame;
  • the data line D1 provides a high voltage signal; the voltage value of the high voltage signal provided by the data line D1 is equal to the voltage value of the high voltage signal provided by the high voltage terminal VDD.
  • the high voltage signal The voltage value can be 4.6V;
  • GP provides low voltage and T5 is turned on to write the high voltage signal to the first node N1;
  • T1 and T2 are turned on, and T0 drives O1 to emit light.
  • the potential of the high-voltage signal provided by the data line D1 is equal to the voltage value of the high-voltage signal provided by the high-voltage terminal VDD during the maintenance of the sub-display frame, even if T5 leaks electricity, the potential of N1 will be maintained at 4.6V. Therefore, when different frequencies are displayed, the potential of the first node N1 remains at the same level, thereby improving the brightness difference caused by this.
  • the one labeled F21 is the first holding sub-display frame
  • the one labeled F2N is the N-th holding sub-display frame
  • N is an integer greater than 1;
  • S41 is the data writing stage included in the first holding sub-display frame F21
  • S4N is the data writing stage included in the Nth holding sub-display frame F2N.
  • the label GP_2 is the next row of write control lines adjacent to GP
  • the waveform corresponding to GP_2 is the waveform of the next row of write control signals provided by the next row of write control lines.
  • the difference between at least one embodiment of the pixel circuit shown in FIG. 15 of the present disclosure and at least one embodiment of the pixel circuit shown in FIG. 10 of the present disclosure is that the drain of T1 is electrically connected to the first node N1.
  • E1 provides a low voltage signal
  • T1 is turned off
  • T2 is turned on
  • the first initial voltage Vi1 is written into the fifth node N5
  • C1 stores the first initial voltage Vi1 at the fifth node N5;
  • E1 provides a high-voltage signal
  • T1 is turned on
  • Vi1 stored in the fifth node N5 resets the potential of the first node N1 through T1, so that when entering the light-emitting phase again, the additional accumulated energy of the first node N1
  • the excess charge is offset by the reset low potential, so that the phenomenon of increasing brightness within the same display period (the display period may be one frame of display time) is suppressed, thereby improving the flicker problem.
  • the frequency of the writing control signal provided by GP is smaller than the frequency of the light-emitting control signal provided by E1, so as to reduce power consumption.
  • the difference between at least one embodiment of the pixel circuit shown in FIG. 16 of the present disclosure and at least one embodiment of the pixel circuit shown in FIG. 10 of the present disclosure is that the drain of T1 is electrically connected to the fourth node N4.
  • the drain of T1 is electrically connected to the fourth node N4.
  • E1 provides a low voltage signal
  • T1 is turned off
  • T2 is turned on
  • the first initial voltage Vi1 is written into the fifth node N5
  • C1 ⁇ stores the first initial voltage Vi1 at the fifth node N5;
  • E1 provides a high-voltage signal
  • T2 is turned off
  • T1 is turned on.
  • Vi1 stored in the fifth node N5 resets the potential of the fourth node N4 through T1, so that when entering the light-emitting phase again, the first node
  • the excess charge accumulated in N1 is offset by the reset low potential when flowing through the fourth node N4, so that the phenomenon of increasing brightness within the same display period (the display period can be one frame of display time) is suppressed, improving Flicker ( flashing) problem.
  • the frequency of the writing control signal provided by GP is smaller than the frequency of the light-emitting control signal provided by E1, so as to reduce power consumption.
  • the difference between at least one embodiment of the pixel circuit shown in FIG. 17 of the present disclosure and at least one embodiment of the pixel circuit shown in FIG. 16 of the present disclosure is that: at least one embodiment of the pixel circuit shown in FIG. 17 of the present disclosure does not include the third Eight transistors T8.
  • E1 provides a low voltage signal
  • T1 is turned off
  • T2 is turned on
  • the first initial voltage Vi1 is written into the fifth node N5
  • C1 ⁇ stores the first initial voltage Vi1 at the fifth node N5;
  • E1 provides a high-voltage signal
  • T2 is turned off
  • T1 is turned on.
  • Vi1 stored in the fifth node N5 resets the potential of the fourth node N4 through T1, so that when entering the light-emitting phase again, the first node
  • the excess charge accumulated in N1 is offset by the reset low potential when flowing through the fourth node N4, so that the phenomenon of increasing brightness within the same display period (the display period can be one frame of display time) is suppressed, improving Flicker ( flashing) problem.
  • the frequency of the writing control signal provided by GP is smaller than the frequency of the light-emitting control signal provided by E1, so as to reduce power consumption.
  • the pixel driving method described in the embodiment of the present disclosure is applied to the above-mentioned pixel circuit, and the display cycle includes a non-light-emitting phase and a light-emitting phase; the pixel driving method includes:
  • the reset control circuit provides the first initial voltage to the connection node under the control of the reset control signal, so that when entering the light-emitting phase, the additional accumulated excess charge of the first node is provided to the third connection node.
  • An initial voltage is offset, so that the phenomenon of increasing brightness within the same display period (the display period may be one frame display time) is suppressed, thereby improving the flicker problem.
  • the reset control circuit includes a first control circuit, a second control circuit and a first energy storage circuit;
  • the pixel driving method according to at least one embodiment of the present disclosure includes:
  • the second control circuit writes the first initial voltage into the fifth node under the control of the reset control signal, and the first energy storage circuit stores the first initial voltage into the fifth node;
  • the first control circuit controls the connection between the fifth node and the connection node under the control of the reset control signal to write the first initial voltage into the connection node.
  • the reset control circuit may include a first control circuit, a second control circuit and a first energy storage circuit; during the light-emitting phase, the second control circuit and the first energy storage circuit control writing the first initial voltage and stored in the fifth stage. In the non-light-emitting stage, the first control circuit writes the first initial voltage into the connection node.
  • the pixel circuit further includes a data writing circuit, a compensation control circuit, a first initialization circuit, a second energy storage circuit and a second initialization circuit;
  • the display cycle includes a first display stage It includes an initialization stage, a compensation stage and a light-emitting stage that are set successively.
  • the compensation stage includes a data writing stage;
  • the pixel driving method includes:
  • the first initialization circuit writes the second initial voltage to the control terminal of the driving circuit under the control of the reset control signal, so that at the beginning of the compensation phase, the driving circuit can adjust the potential of its control terminal to Under control, control the connection between the first node and the third node;
  • the data line provides data voltage Vdata
  • the data writing circuit writes the data voltage Vdata into the first node under the control of the writing control signal
  • the compensation control circuit controls the connection between the second node and the third node under the control of the compensation control signal
  • the first light-emitting control circuit controls the connection between the first voltage terminal and the first node under the control of the light-emitting control signal
  • the second light-emitting control circuit controls the connection between the first voltage terminal and the first node under the control of the light-emitting control signal.
  • the third node and the fourth node are connected, and the driving circuit generates a driving current for driving the light-emitting element.
  • the pixel circuit further includes a data writing circuit; the non-light emitting phase includes a data writing phase; the display frame includes a refresh sub-display frame and at least one holding sub-display frame; the refresh sub-frame The display frame includes the display period, the holding sub-display frame includes the display period; the pixel driving method further includes:
  • the data line provides a first voltage signal
  • the data writing circuit writes the first voltage signal into the first node under the control of a writing control signal.
  • the potential of the first node will be maintained at the first voltage value (the first voltage value is the voltage value of the first voltage signal) , so that when different frequencies are displayed, the potential of the first node is maintained at the same level, reducing the brightness difference.
  • the pixel circuit further includes a compensation control circuit; the display cycle further includes a compensation phase; the pixel driving method according to at least one embodiment of the present disclosure further includes:
  • the data line provides data voltage
  • the data writing circuit writes the data voltage to the first node under the control of the writing control signal
  • the compensation control circuit controls the connection between the control end of the drive circuit and the second end of the drive circuit under the control of the compensation control signal
  • the first light-emitting control circuit controls the connection between the first voltage terminal and the first node under the control of the light-emitting control signal.
  • the second light-emitting control circuit controls the connection between the third node and the fourth node under the control of the light-emitting control signal, and the driving circuit generates a driving current for driving the light-emitting element;
  • the compensation control circuit controls the connection between the control terminal of the driving circuit and the second terminal of the driving circuit to be disconnected under the control of the compensation control signal.
  • the driving circuit drives the light-emitting element to emit light
  • the compensation control circuit The control terminal of the driving circuit is disconnected from the second terminal of the driving circuit, so even if the transistor included in the data writing circuit is turned on during a specific period of time in the holding sub-display frame, the potential of the control terminal of the driving circuit is It will not turn on and will not affect the display brightness.
  • the frequency of the writing control signal is smaller than the frequency of the lighting control signal.
  • the display frame when the pixel circuit operates in a low-frequency display mode, the display frame includes a refresh sub-display frame and at least one holding sub-display frame, and in the display frame, the write control signal The frequency is smaller than the frequency of the lighting control signal, so as to reduce power consumption.
  • the display device includes the above-mentioned pixel circuit.
  • the display device provided in the embodiment of the present disclosure can be any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.

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Abstract

一种像素电路、像素驱动方法和显示装置。像素电路，包括第一发光控制电路(11)、驱动电路(12)、第二发光控制电路(13)、复位控制电路(20)和发光元件(10)；复位控制电路(20)分别与复位控制线(R0)、连接节点和用于提供第一初始电压(Vi1)的第一初始电压端(I1)电连接，用于在复位控制线(R0)提供的复位控制信号的控制下，将第一初始电压(Vi1)提供至连接节点；连接节点为第一节点(N1)、第三节点(N3)或第四节点(N4)。

Description

像素电路、像素驱动方法和显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种像素电路、像素驱动方法和显示装置。
背景技术
相关的像素电路在工作时，在非发光阶段，第一节点(第一节点可以为与驱动电路的第一端电连接的节点)的寄生电容会残留上一发光阶段的电荷，同时第一电压端通过第一发光控制电路包括的晶体管漏电的因素，会使得再次进入发光阶段时，第一节点会有一定的电荷积累，造成同一显示周期内亮度呈现递增的现象，形成Flicker(闪烁)。
发明内容
在一个方面中，本公开实施例提供了一种像素电路，包括第一发光控制电路、驱动电路、第二发光控制电路、复位控制电路和发光元件；
所述第一发光控制电路分别与发光控制线、第一电压端和第一节点电连接，用于在所述发光控制线提供的发光控制信号的控制下，控制所述第一电压端和所述第一节点之间连通或断开；
所述驱动电路的控制端与第二节点电连接，所述驱动电路的第一端与所述第一节点电连接，所述驱动电路的第二端与第三节点电连接；所述驱动电路用于在其控制端的电位的控制下，控制产生驱动所述发光元件的驱动电流；
所述第二发光控制电路分别与所述发光控制线、所述第三节点和第四节点电连接，用于在所述发光控制信号的控制下，控制所述第三节点和所述第四节点之间连通或断开；
所述发光元件的第一极与所述第四节点电连接，所述发光元件的第二极与第二电压端电连接；
所述复位控制电路分别与复位控制线、连接节点和用于提供第一初始电 压的第一初始电压端电连接，用于在所述复位控制线提供的复位控制信号的控制下，将所述第一初始电压提供至所述连接节点；
所述连接节点为所述第一节点、所述第三节点或所述第四节点。
可选的，所述复位控制电路还与第五节点电连接，用于在所述复位控制信号的控制下，控制所述第一初始电压端与所述第五节点之间连通或断开，并控制所述第五节点与所述连接节点之间断开或连通，并用于维持所述第五节点的电位。
可选的，所述复位控制电路包括第一控制电路、第二控制电路和第一储能电路；
所述第一控制电路分别与所述复位控制线、所述连接节点和所述第五节点电连接，用于在所述复位控制信号的控制下，控制所述连接节点和所述第五节点之间连通或断开；
所述第二控制电路分别与所述复位控制线、所述第五节点和第一初始电压端电连接，用于在所述复位控制信号的控制下控制将所述第一初始电压端提供的第一初始电压写入所述第五节点；
所述第一储能电路与所述第五节点电连接，用于储存电能。
可选的，所述复位控制线为所述发光控制线；或者，所述复位控制线提供的复位控制信号与所述发光控制线提供的发光控制信号相同。
可选的，所述第一控制电路包括第一晶体管，所述第二控制电路包括第二晶体管；
所述第一晶体管的控制极与所述复位控制线电连接，所述第一晶体管的第一极与所述第五节点电连接，所述第一晶体管的第二极与第三节点电连接；
所述第二晶体管的控制极与所述复位控制线电连接，所述第二晶体管的第一极与所述第一初始电压端电连接，所述第二晶体管的第二极与所述第五节点电连接。
可选的，所述第一晶体管为氧化物薄膜晶体管，所述第二晶体管为低温多晶硅薄膜晶体管。
可选的，所述第一储能电路包括第一电容；
所述第一电容的第一端与所述第五节点电连接，所述第一电容的第二端 与第一电压端电连接。
可选的，本公开至少一实施例所述的像素电路还包括数据写入电路、补偿控制电路、第一初始化电路、第二储能电路和第二初始化电路；
所述数据写入电路分别与写入控制线、数据线和第一节点电连接，用于在所述写入控制线提供的写入控制信号的控制下，将所述数据线提供的数据电压写入所述第一节点；
所述补偿控制电路分别与补偿控制线、所述驱动电路的控制端和所述驱动电路的第二端电连接，用于在所述补偿控制线提供的补偿控制信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间连通或断开；
所述第一初始化电路分别与初始化控制线、第二初始电压端和所述驱动电路的控制端电连接，用于在所述初始化控制线提供的初始化控制信号的控制下，将所述第二初始电压端提供的第二初始电压写入所述驱动电路的控制端；
所述第二储能电路与所述驱动电路的控制端电连接，用于储存电能；
所述第二初始化电路分别与所述写入控制线、第三初始电压端和所述第四节点电连接，用于在所述写入控制信号的控制下，将所述第三初始电压端提供的第三初始电压写入所述第四节点。
可选的，所述第一发光控制电路包括第三晶体管，所述第二发光控制电路包括第四晶体管，所述驱动电路包括驱动晶体管；
所述第三晶体管的控制极与所述发光控制线电连接，所述第三晶体管的第一极与所述第一电压端电连接，所述第三晶体管的第二极与所述第一节点电连接；
所述第四晶体管的控制极与所述发光控制线电连接，所述第四晶体管的第一极与所述第三节点电连接，所述第四晶体管的第二极与所述第四节点电连接；
所述驱动晶体管的控制极与所述第二节点电连接，所述驱动晶体管的第一极与所述第一节点电连接，所述驱动晶体管的第二极与所述第三节点电连接。
可选的，所述数据写入电路包括第五晶体管，所述补偿控制电路包括第 六晶体管，所述第一初始化电路包括第七晶体管，所述第二初始化电路包括第八晶体管，所述第二储能电路包括第二电容；
所述第五晶体管的控制极与所述写入控制线电连接，所述第五晶体管的第一极与所述数据线电连接，所述第五晶体管的第二极与所述驱动电路的第一端电连接；
所述第六晶体管的控制极与所述补偿控制线电连接，所述第六晶体管的第一极与所述驱动电路的控制端电连接，所述第六晶体管的第二极与所述驱动电路的第二端电连接；
所述第七晶体管的控制极与所述初始化控制线电连接，所述第七晶体管的第一极与所述第二初始电压端电连接，所述第七晶体管的第二极与所述驱动电路的控制端电连接；
所述第八晶体管的控制极与所述写入控制线电连接，所述第八晶体管的第一极与所述第三初始电压端电连接，所述第八晶体管的第二极与上所述第四节点电连接；
所述第二电容的第一端与所述第二节点电连接，所述第二电容的第二端与第一电压端电连接。
在第二个方面中，本公开实施例提供一种像素驱动方法，应用于上述的像素电路，显示周期包括非发光阶段和发光阶段；所述像素驱动方法包括：
在非发光阶段，复位控制电路在复位控制信号的控制下，将第一初始电压提供至连接节点。
可选的，所述复位控制电路包括第一控制电路、第二控制电路和第一储能电路；所述像素驱动方法包括：
在发光阶段，第二控制电路在所述复位控制信号的控制下，将第一初始电压写入第五节点，第一储能电路将第一初始电压存储于所述第五节点；
在非发光阶段，第一控制电路在所述复位控制信号的控制下，控制所述第五节点与连接节点之间连通，以将所述第一初始电压写入所述连接节点。
可选的，所述像素电路还包括数据写入电路、补偿控制电路、第一初始化电路、第二储能电路和第二初始化电路；所述显示周期包括的第一显示阶段包括先后设置的初始化阶段、补偿阶段和发光阶段，所述补偿阶段包括数 据写入阶段；所述像素驱动方法包括：
在所述初始化阶段，第一初始化电路在复位控制信号的控制下，将第二初始电压写入驱动电路的控制端，以使得在补偿阶段开始时，所述驱动电路能够在其控制端的电位的控制下，控制第一节点与第三节点之间连通；
在所述数据写入阶段，数据线提供数据电压Vdata，所述数据写入电路在写入控制信号的控制下，将所述数据电压Vdata写入所述第一节点；
在所述补偿阶段，所述补偿控制电路在补偿控制信号的控制下，控制第二节点与所述第三节点之间连通；
在所述发光阶段，第一发光控制电路在发光控制信号的控制下，控制第一电压端与所述第一节点之间连通，第二发光控制电路在所述发光控制信号的控制下，控制所述第三节点与所述第四节点之间连通，所述驱动电路产生驱动发光元件的驱动电流。
可选的，所述像素电路还包括数据写入电路；所述非发光阶段包括数据写入阶段；显示帧包括刷新子显示帧和至少一个保持子显示帧；所述刷新子显示帧包括所述显示周期，所述保持子显示帧包括所述显示周期；所述像素驱动方法还包括：
在所述保持子显示帧，数据线提供第一电压信号；
在所述保持子显示帧中的数据写入阶段，所述数据写入电路在写入控制信号的控制下，将所述第一电压信号写入第一节点。
可选的，所述像素电路还包括补偿控制电路；所述显示周期还包括补偿阶段；所述像素驱动方法还包括：
在所述刷新子显示帧中的数据写入阶段，数据线提供数据电压，所述数据写入电路在写入控制信号的控制下，将所述数据电压写入第一节点；
在所述刷新子显示帧中的补偿阶段，所述补偿控制电路在补偿控制信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间连通；
在所述刷新子显示帧中的发光阶段和保持子显示帧中的发光阶段，第一发光控制电路在发光控制信号的控制下，控制第一电压端与所述第一节点之间连通，第二发光控制电路在所述发光控制信号的控制下，控制所述第三节点与所述第四节点之间连通，驱动电路产生驱动发光元件的驱动电流；
在所述保持子显示帧，所述补偿控制电路在补偿控制信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间断开。
可选的，在所述显示帧，所述写入控制信号的频率小于所述发光控制信号的频率。
在第三个方面中，本公开实施例提供一种显示装置，包括上述的像素电路。
附图说明
图1是本公开至少一实施例所述的像素电路的结构图；
图2是本公开至少一实施例所述的像素电路的结构图；
图3是本公开至少一实施例所述的像素电路的结构图；
图4是本公开至少一实施例所述的像素电路的结构图；
图5是本公开至少一实施例所述的像素电路的结构图；
图6是本公开至少一实施例所述的像素电路的结构图；
图7是本公开至少一实施例所述的像素电路的结构图；
图8是本公开至少一实施例所述的像素电路的结构图；
图9是本公开至少一实施例所述的像素电路的结构图；
图10是本公开至少一实施例所述的像素电路的电路图；
图11是本公开如图10所示的像素电路的至少一实施例的工作时序图；
图12是本公开如图10所示的像素电路的至少一实施例的工作时序图；
图13是本公开如图10所示的像素电路的至少一实施例的工作时序图；
图14是本公开如图10所示的像素电路的至少一实施例切换频率时亮度差异示意图；
图15是本公开至少一实施例所述的像素电路的电路图；
图16是本公开至少一实施例所述的像素电路的电路图；
图17是本公开至少一实施例所述的像素电路的电路图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行 清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为三极管、薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除控制极之外的两极，将其中一极称为第一极，另一极称为第二极。
在实际操作时，当所述晶体管为薄膜晶体管或场效应管时，所述第一极可以为漏极，所述第二极可以为源极；或者，所述第一极可以为源极，所述第二极可以为漏极。
本公开实施例所述的像素电路包括第一发光控制电路、驱动电路、第二发光控制电路、复位控制电路和发光元件；
所述第一发光控制电路分别与发光控制线、第一电压端和第一节点电连接，用于在所述发光控制线提供的发光控制信号的控制下，控制所述第一电压端和所述第一节点之间连通或断开；
所述驱动电路的控制端与第二节点电连接，所述驱动电路的第一端与所述第一节点电连接，所述驱动电路的第二端与第三节点电连接；所述驱动电路用于在其控制端的电位的控制下，控制产生驱动所述发光元件的驱动电流；
所述第二发光控制电路分别与所述发光控制线、第三节点和第四节点电连接，用于在所述发光控制信号的控制下，控制所述第三节点和所述第四节点之间连通或断开；
所述发光元件的第一极与所述第四节点电连接，所述发光元件的第二极与第二电压端电连接；
所述复位控制电路分别与复位控制线、连接节点和用于提供第一初始电压的第一初始电压端电连接，用于在所述复位控制线提供的复位控制信号的控制下，将所述第一初始电压提供至所述连接节点；
所述连接节点为所述第一节点、所述第三节点或所述第四节点。
本公开实施例所述的像素电路在工作时，显示周期可以包括非发光阶段和发光阶段；
在非发光阶段，所述复位控制电路在复位控制信号的控制下，将所述第 一初始电压提供至所述连接节点，从而使得进入发光阶段时，第一节点额外累积的多余电荷被提供至所述连接节点的第一初始电压抵消，从而从而同一显示周期(所述显示周期可以为一帧显示时间，但不以此为限)内亮度呈现递增的现象被抑制，改善了Flicker(闪烁)现象。
在本公开至少一实施例中，所述第一电压端可以为高电压端，所述第二电压端可以为低电压端，但不以此为限。
可选的，所述发光元件可以为有机发光二极管，但不以此为限。
在本公开至少一实施例中，所述非发光阶段可以包括所述显示周期包括的除了所述发光阶段之外的时间段，但不以此为限。
在本公开至少一实施例中，所述复位控制线为所述发光控制线；或者，所述复位控制线提供的复位控制信号与所述发光控制线提供的发光控制信号相同；但不以此为限。
在本公开至少一实施例中，所述复位控制电路还与第五节点电连接，用于在所述复位控制信号的控制下，控制所述第一初始电压端与所述第五节点之间连通或断开，并控制所述第五节点与所述连接节点之间断开或连通，并用于维持所述第五节点的电位。
可选的，所述第一初始电压的电压值可以大于等于-3V而小于等于-2.3V，例如，所述第一初始电压的电压值可以为-3V、-2.3V、-2.4V、-2.5V或-2.8V，但不以此为限。
如图1所示，本公开至少一实施例所述的像素电路包括第一发光控制电路11、驱动电路12、第二发光控制电路13、复位控制电路20和发光元件10；
所述第一发光控制电路11分别与发光控制线E1、第一电压端V1和第一节点N1电连接，用于在所述发光控制线E1提供的发光控制信号的控制下，控制所述第一电压端V1和所述第一节点N1之间连通；所述第一电压端V1用于提供第一电压信号；
所述驱动电路12的控制端与第二节点N2电连接，所述驱动电路12的第一端与所述第一节点N1电连接，所述驱动电路12的第二端与第三节点N3电连接；所述驱动电路用于在其控制端的电位的控制下，控制产生驱动所述发光元件10的驱动电流；
所述第二发光控制电路13分别与所述发光控制线E1、第三节点N3和第四节点N4电连接，用于在所述发光控制信号的控制下，控制所述第三节点N3和所述第四节点N4之间连通；
所述发光元件10的第一极与所述第四节点N4电连接，所述发光元件10的第二极与第二电压端V2电连接；
所述复位控制电路20分别与复位控制线R0、第三节点N3和用于提供第一初始电压Vi1的第一初始电压端I1电连接，用于在所述复位控制线R0提供的复位控制信号的控制下，将所述第一初始电压Vi1提供至所述第三节点N3。
在图1所示的像素电路的至少一实施例中，所述连接节点为第三节点N3。
在图1所示的像素电路的至少一实施例中，所述复位控制线可以为所述发光控制线，或者，所述复位控制线提供的复位控制信号与所述发光控制线提供的发光控制信号可以为同一控制信号，但不以此为限。
本公开如图1所示的像素电路的至少一实施例在工作时，显示周期包括发光阶段和非发光阶段；
在非发光阶段，所述复位控制电路20在复位控制信号的控制下，将所述第一初始电压Vi1提供至所述第三节点N3，以对所述第三节点N3的电位进行复位，从而使得再一次进入发光阶段时，第一节点N1额外积累的多余电荷流经第三节点N3时被复位的低电位抵消，从而同一显示周期(所述显示周期可以为一帧显示时间)内亮度呈现递增的现象被抑制，改善了Flicker(闪烁)问题。
如图2所示，本公开至少一实施例所述的像素电路包括第一发光控制电路11、驱动电路12、第二发光控制电路13、复位控制电路20和发光元件10；
所述第一发光控制电路11分别与发光控制线E1、第一电压端V1和第一节点N1电连接，用于在所述发光控制线E1提供的发光控制信号的控制下，控制所述第一电压端V1和所述第一节点N1之间连通；所述第一电压端V1用于提供第一电压信号；
所述驱动电路12的控制端与第二节点N2电连接；所述驱动电路用于在其控制端的电位的控制下，控制产生驱动所述发光元件10的驱动电流；
所述第二发光控制电路13分别与所述发光控制线E1、第三节点N3和第四节点N4电连接，用于在所述发光控制信号的控制下，控制所述第三节点N3和所述第四节点N4之间连通；
所述发光元件10的第一极与所述第四节点N4电连接，所述发光元件10的第二极与第二电压端V2电连接；
所述复位控制电路20分别与复位控制线R0、第一节点N1和用于提供第一初始电压Vi1的第一初始电压端I1电连接，用于在所述复位控制线R0提供的复位控制信号的控制下，将所述第一初始电压Vi1提供至所述第一节点N1。
在图2所示的像素电路的至少一实施例中，所述连接节点为第一节点N1。
在图2所示的像素电路的至少一实施例中，所述复位控制线可以为所述发光控制线，或者，所述复位控制线提供的复位控制信号与所述发光控制线提供的发光控制信号可以为同一控制信号，但不以此为限。
本公开如图2所示的像素电路的至少一实施例在工作时，显示周期包括发光阶段和非发光阶段；
在非发光阶段，所述复位控制电路20在复位控制信号的控制下，将所述第一初始电压Vi1提供至所述第一节点N1，从而使得再一次进入发光阶段时，第一节点N1额外积累的多余电荷被复位的低电位抵消，从而同一显示周期(所述显示周期可以为一帧显示时间)内亮度呈现递增的现象被抑制，改善了Flicker(闪烁)问题。
如图3所示，本公开至少一实施例所述的像素电路包括第一发光控制电路11、驱动电路12、第二发光控制电路13、复位控制电路20和发光元件10；
所述第一发光控制电路11分别与发光控制线E1、第一电压端V1和第一节点N1电连接，用于在所述发光控制线E1提供的发光控制信号的控制下，控制所述第一电压端V1和所述第一节点N1之间连通；所述第一电压端V1用于提供第一电压信号；
所述驱动电路12的控制端与第二节点N2电连接；所述驱动电路用于在其控制端的电位的控制下，控制产生驱动所述发光元件10的驱动电流；
所述第二发光控制电路13分别与所述发光控制线E1、第三节点N3和第 四节点N4电连接，用于在所述发光控制信号的控制下，控制所述第三节点N3和所述第四节点N4之间连通；
所述发光元件10的第一极与所述第四节点N4电连接，所述发光元件10的第二极与第二电压端V2电连接；
所述复位控制电路20分别与复位控制线R0、第四节点N4和用于提供第一初始电压Vi1的第一初始电压端I1电连接，用于在所述复位控制线R0提供的复位控制信号的控制下，将所述第一初始电压Vi1提供至所述第四节点N4。
在图3所示的像素电路的至少一实施例中，所述连接节点为第四节点N4。
在图3所示的像素电路的至少一实施例中，所述复位控制线可以为所述发光控制线，或者，所述复位控制线提供的复位控制信号与所述发光控制线提供的发光控制信号可以为同一控制信号，但不以此为限。
本公开如图3所示的像素电路的至少一实施例在工作时，显示周期包括发光阶段和非发光阶段；
在非发光阶段，所述复位控制电路20在复位控制信号的控制下，将所述第一初始电压Vi1提供至所述第四节点N4，从而使得再一次进入发光阶段时，第一节点N1额外积累的多余电荷在流经第四节点N4时被复位的低电位抵消，从而同一显示周期(所述显示周期可以为一帧显示时间)内亮度呈现递增的现象被抑制，改善了Flicker(闪烁)问题。
可选的，所述复位控制电路可以包括第一控制电路、第二控制电路和第一储能电路；
所述第一控制电路分别与所述复位控制线、所述连接节点和所述第五节点电连接，用于在所述复位控制信号的控制下，控制所述连接节点和所述第五节点之间连通或断开；
所述第二控制电路分别与所述复位控制线、所述第五节点和第一初始电压端电连接，用于在所述复位控制信号的控制下控制将所述第一初始电压端提供的第一初始电压写入所述第五节点；
所述第一储能电路与所述第五节点电连接，用于储存电能。
在本公开至少一实施例中，所述复位控制电路可以包括第一控制电路、 第二控制电路和第一储能电路；
在发光阶段，第二控制电路在所述复位控制信号的控制下，将第一初始电压写入第五节点，第一储能电路将第一初始电压存储于所述第五节点N5；
在非发光阶段，第一控制电路在所述复位控制信号的控制下，控制所述第五节点与第三节点之间连通，以将所述第一初始电压写入所述连接节点。
如图4所示，本公开实施例所述的像素电路包括第一发光控制电路11、驱动电路12、第二发光控制电路13、复位控制电路和发光元件10；所述复位电路包括第一控制电路14、第二控制电路15和第一储能电路16；
所述第一发光控制电路11分别与发光控制线E1、第一电压端V1和第一节点N1电连接，用于在所述发光控制线E1提供的发光控制信号的控制下，控制所述第一电压端V1和所述第一节点N1之间连通；所述第一电压端V1用于提供第一电压信号；
所述驱动电路12的控制端与第二节点N2电连接；所述驱动电路用于在其控制端的电位的控制下，控制产生驱动所述发光元件10的驱动电流；
所述第二发光控制电路13分别与所述发光控制线E1、第三节点N3和第四节点N4电连接，用于在所述发光控制信号的控制下，控制所述第三节点N3和所述第四节点N4之间连通；
所述发光元件10的第一极与所述第四节点N4电连接，所述发光元件10的第二极与第二电压端V2电连接；
所述第一控制电路14分别与所述发光控制线E1、第三节点N3和第五节点N5电连接，用于在所述发光控制信号的控制下，控制所述第三节点N3和所述第五节点N5之间连通；
所述第二控制电路15分别与所述发光控制线E1、所述第五节点N5和第一初始电压端I1电连接，用于在所述发光控制信号的控制下，控制将所述第一初始电压端I1提供的第一初始电压Vi1写入所述第五节点N5；
所述第一储能电路16与所述第五节点N5电连接，用于储存电能。
在图4所示的至少一实施例中，所述连接节点为第三节点N3，所述复位控制线为发光控制线E1。
本公开如图4所示的像素电路的至少一实施例在工作时，
在发光阶段，第二控制电路15在发光控制信号的控制下，将第一初始电压Vi1写入第五节点N5，第一储能电路16将第一初始电压Vi1存储于所述第五节点N5；
在非发光阶段，存储于第五节点N5的Vi1通过所述第一控制电路14将第三节点N3的电位进行复位，从而使得再一次进入发光阶段时，第一节点N1额外积累的多余电荷流经第三节点N3时被复位的低电位抵消，从而同一显示周期(所述显示周期可以为一帧显示时间)内亮度呈现递增的现象被抑制，改善了Flicker(闪烁)问题。
如图5所示，本公开实施例所述的像素电路包括第一发光控制电路11、驱动电路12、第二发光控制电路13、复位控制电路和发光元件10；所述复位控制电路包括第一控制电路14、第二控制电路15和第一储能电路16；
所述第一发光控制电路11分别与发光控制线E1、第一电压端V1和第一节点N1电连接，用于在所述发光控制线E1提供的发光控制信号的控制下，控制所述第一电压端V1和所述第一节点N1之间连通；所述第一电压端V1用于提供第一电压信号；
所述驱动电路12的控制端与第二节点N2电连接；所述驱动电路用于在其控制端的电位的控制下，控制产生驱动所述发光元件10的驱动电流；
所述第二发光控制电路13分别与所述发光控制线E1、第三节点N3和第四节点N4电连接，用于在所述发光控制信号的控制下，控制所述第三节点N3和所述第四节点N4之间连通；
所述发光元件10的第一极与所述第四节点N4电连接，所述发光元件10的第二极与第二电压端V2电连接；
所述第一控制电路14分别与所述发光控制线E1、第一节点N1和第五节点N5电连接，用于在所述发光控制信号的控制下，控制所述第一节点N1和所述第五节点N5之间连通；
所述第二控制电路15分别与所述发光控制线E1、所述第五节点N5和第一初始电压端I1电连接，用于在所述发光控制信号的控制下，控制将所述第一初始电压端I1提供的第一初始电压Vi1写入所述第五节点N5；
所述第一储能电路16与所述第五节点N5电连接，用于储存电能。
在图5所示的至少一实施例中，所述连接节点为第一节点N1，所述复位控制线为发光控制线E1。
本公开如图5所示的像素电路的至少一实施例在工作时，显示周期包括非发光阶段和发光阶段；
在发光阶段，第二控制电路15在发光控制信号的控制下，将第一初始电压Vi1写入第五节点N5，第一储能电路16将第一初始电压Vi1存储于所述第五节点N5；
在非发光阶段，存储于第五节点N5的Vi1通过所述第一控制电路14将第一节点N1的电位进行复位，从而使得再一次进入发光阶段时，从而使得再一次进入发光阶段时，第一节点N1额外积累的多余电荷被复位的低电位抵消，从而同一显示周期(所述显示周期可以为一帧显示时间)内亮度呈现递增的现象被抑制，改善了Flicker(闪烁)问题。
如图6所示，本公开实施例所述的像素电路包括第一发光控制电路11、驱动电路12、第二发光控制电路13、复位控制电路和发光元件10；所述复位控制电路包括第一控制电路14、第二控制电路15和第一储能电路16；
所述第一发光控制电路11分别与发光控制线E1、第一电压端V1和第一节点N1电连接，用于在所述发光控制线E1提供的发光控制信号的控制下，控制所述第一电压端V1和所述第一节点N1之间连通；所述第一电压端V1用于提供第一电压信号；
所述驱动电路12的控制端与第二节点N2电连接；所述驱动电路用于在其控制端的电位的控制下，控制产生驱动所述发光元件10的驱动电流；
所述第二发光控制电路13分别与所述发光控制线E1、第三节点N3和第四节点N4电连接，用于在所述发光控制信号的控制下，控制所述第三节点N3和所述第四节点N4之间连通；
所述发光元件10的第一极与所述第四节点N4电连接，所述发光元件10的第二极与第二电压端V2电连接；
所述第一控制电路14分别与所述发光控制线E1、第四节点N4和第五节点N5电连接，用于在所述发光控制信号的控制下，控制所述第四节点N4和所述第五节点N5之间连通；
所述第二控制电路15分别与所述发光控制线E1、所述第五节点N5和第一初始电压端I1电连接，用于在所述发光控制信号的控制下，控制将所述第一初始电压端I1提供的第一初始电压Vi1写入所述第五节点N5；
所述第一储能电路16与所述第五节点N5电连接，用于储存电能。
在图6所示的至少一实施例中，所述连接节点为第四节点N4，所述复位控制线为发光控制线E1。
本公开如图6所示的像素电路的至少一实施例在工作时，显示周期包括非发光阶段和发光阶段；
在发光阶段，第二控制电路15在发光控制信号的控制下，将第一初始电压Vi1写入第五节点N5，第一储能电路16将第一初始电压Vi1存储于所述第五节点N5；
在非发光阶段，存储于第五节点N5的Vi1通过所述第一控制电路14将第四节点N4的电位进行复位，从而使得再一次进入发光阶段时，第一节点N1额外积累的多余电荷在流经第四节点N4时被复位的低电位抵消，从而同一显示周期(所述显示周期可以为一帧显示时间)内亮度呈现递增的现象被抑制，改善了Flicker(闪烁)问题。
可选的，所述第一控制电路包括第一晶体管，所述第二控制电路包括第二晶体管；
所述第一晶体管的控制极与所述复位控制线电连接，所述第一晶体管的第一极与所述第五节点电连接，所述第一晶体管的第二极与第三节点电连接；
所述第二晶体管的控制极与所述复位控制线电连接，所述第二晶体管的第一极与所述第一初始电压端电连接，所述第二晶体管的第二极与所述第五节点电连接。
可选的，所述第一晶体管为氧化物薄膜晶体管，所述第二晶体管为低温多晶硅薄膜晶体管。
在本公开至少一实施例中，所述第一储能电路包括第一电容；
所述第一电容的第一端与所述第五节点电连接，所述第一电容的第二端与第一电压端电连接。
本公开至少一实施例所述的像素电路还可以包括数据写入电路、补偿控 制电路、第一初始化电路、第二储能电路和第二初始化电路；
所述数据写入电路分别与写入控制线、数据线和第一节点电连接，用于在所述写入控制线提供的写入控制信号的控制下，将所述数据线提供的数据电压写入所述第一节点；
所述补偿控制电路分别与补偿控制线、所述驱动电路的控制端和所述驱动电路的第二端电连接，用于在所述补偿控制线提供的补偿控制信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间连通；
所述第一初始化电路分别与初始化控制线、第二初始电压端和所述驱动电路的控制端电连接，用于在所述初始化控制线提供的初始化控制信号的控制下，将所述第二初始电压端提供的第二初始电压写入所述驱动电路的控制端，以使得在补偿阶段开始时，所述驱动电路能够在其控制端的电位的控制下，控制所述驱动电路的第一端与所述驱动电路的第二端之间连通；
所述第二储能电路与所述驱动电路的控制端电连接，用于储存电能；
所述第二初始化电路分别与所述写入控制线、第三初始电压端和所述第四节点电连接，用于在所述写入控制信号的控制下，将所述第三初始电压端提供的第三初始电压写入所述第四节点，以控制所述发光元件不发光。
在本公开至少一实施例中，所述的像素电路还包括数据写入电路41、补偿控制电路、第一初始化电路、第二储能电路和第二初始化电路，所述数据写入电路用于控制数据电压写入，所述补偿控制电路用于控制阈值电压补偿；所述第一初始化电路用于对所述驱动电路的控制端的电位进行复位，以控制在补偿阶段开始时，所述驱动电路能够在其控制端的电位的控制下，控制所述驱动电路的第一端与所述驱动电路的第二端之间连通；所述第二储能电路用于维持所述驱动电路的控制端的电位，所述第二初始化电路用于对所述发光元件的第一极的电位进行复位，以控制所述发光元件不发光。
本公开至少一实施例所述的像素电路在工作时，在进行低频显示时，显示帧包括可以包括刷新子显示帧和至少一个保持子显示帧；
在所述保持子显示帧，数据线可以提供第一电压信号；
在所述保持子显示帧中的数据写入阶段，所述数据写入电路在写入控制信号的控制下，将所述第一电压信号写入第一节点。
在所述保持子显示帧，即使所述数据写入电路包括的晶体管漏电，也会使得第一节点的电位保持为第一电压值(所述第一电压值为第一电压信号的电压值)，从而使得在不同频率显示时，第一节点的电位保持为相同的准位，降低亮度差异。
在本公开至少一实施例中，所述第一电压信号可以为高电压信号，所述第一电压值可以大于等于2.5V而小于等于7V；例如，所述第一电压值可以为2.5V、3V、4V、4.6V、5V、5.8V、6.4V或7V，但不以此为限。
在相关技术中，在像素电路进行低频显示时，显示帧可以包括刷新子显示帧和至少一个保持子显示帧，在所述刷新子显示帧，将数据电压写入像素电路并相应发光，保持子显示帧至少起到拉长发光时间，达到低频的目的；在保持子显示帧内，所述数据线提供一直流电压信号，例如，该直流电压信号的电压值可以为6.4V；在保持子显示帧，该直流电压信号会通过数据写入电路包括的晶体管漏到第一节点，使得第一节点的电位上升，在再次进入发光阶段时，会使得驱动电路包括的晶体管的驱动电流增加，从而导致发光亮度增加。基于此，本公开至少一实施例在保持子显示帧，控制数据线提供第一电压信号，以改善不同频率显示时亮度差异大的问题。
在本公开至少一实施例中，当所述像素电路进行低频显示时，可以在除了刷新子显示帧中的数据写入阶段之外的时间段内，控制所述数据线提供第一电压信号；
在像素电路进行正常显示(也即所述像素电路的显示频率较高时)时，可以在所述显示帧包括的除了数据写入阶段之外的时间段内，控制所述数据线提供第一电压信号。
如图7所示，在图4所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还包括数据写入电路41、补偿控制电路42、第一初始化电路43、第二储能电路44和第二初始化电路45；
所述数据写入电路41分别与写入控制线GP、数据线D1和第一节点N1电连接，用于在所述写入控制线GP提供的写入控制信号的控制下，将所述数据线D1提供的数据电压写入所述第一节点N1；
所述补偿控制电路42分别与补偿控制线GN、所述驱动电路12的控制端 和所述驱动电路12的第二端电连接，用于在所述补偿控制线GN提供的补偿控制信号的控制下，控制所述驱动电路12的控制端与所述驱动电路12的第二端之间连通；
所述第一初始化电路43分别与初始化控制线R1、第二初始电压端I2和所述驱动电路12的控制端电连接，用于在所述初始化控制线R1提供的初始化控制信号的控制下，将所述第二初始电压端I2提供的第二初始电压Vi2写入所述驱动电路12的控制端；
所述第二储能电路44与所述驱动电路12的控制端电连接，用于储存电能；
所述第二初始化电路45分别与所述写入控制线GP、第三初始电压端I3和所述第四节点N4电连接，用于在所述写入控制信号的控制下，将所述第三初始电压端I3提供的第三初始电压写入所述第四节点N4。
可选的，所述第二初始电压Vi2可以大于等于-5V而小于等于-3V，但不以此为限。
在本公开至少一实施例中，所述第三初始电压端I3可以与所述第一初始电压端I1为同一初始电压端，但不以此为限。在实际操作时，所述第三初始电压端I3可以与所述第一初始电压端I1为不同的初始电压端。
如图8所示，在图5所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还包括数据写入电路41、补偿控制电路42、第一初始化电路43、第二储能电路44和第二初始化电路45；
所述数据写入电路41分别与写入控制线GP、数据线D1和第一节点N1电连接，用于在所述写入控制线GP提供的写入控制信号的控制下，将所述数据线D1提供的数据电压写入所述第一节点N1；
所述补偿控制电路42分别与补偿控制线GN、所述驱动电路12的控制端和所述驱动电路12的第二端电连接，用于在所述补偿控制线GN提供的补偿控制信号的控制下，控制所述驱动电路12的控制端与所述驱动电路12的第二端之间连通；
所述第一初始化电路43分别与初始化控制线R1、第二初始电压端I2和所述驱动电路12的控制端电连接，用于在所述初始化控制线R1提供的初始 化控制信号的控制下，将所述第二初始电压端I2提供的第二初始电压Vi2写入所述驱动电路12的控制端；
所述第二储能电路44与所述驱动电路12的控制端电连接，用于储存电能；
所述第二初始化电路45分别与所述写入控制线GP、第三初始电压端I3和所述第四节点N4电连接，用于在所述写入控制信号的控制下，将所述第三初始电压端I3提供的第三初始电压写入所述第四节点N4。
如图9所示，在图6所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还包括数据写入电路41、补偿控制电路42、第一初始化电路43、第二储能电路44和第二初始化电路45；
所述数据写入电路41分别与写入控制线GP、数据线D1和第一节点N1电连接，用于在所述写入控制线GP提供的写入控制信号的控制下，将所述数据线D1提供的数据电压写入所述第一节点N1；
所述补偿控制电路42分别与补偿控制线GN、所述驱动电路12的控制端和所述驱动电路12的第二端电连接，用于在所述补偿控制线GN提供的补偿控制信号的控制下，控制所述驱动电路12的控制端与所述驱动电路12的第二端之间连通；
所述第一初始化电路43分别与初始化控制线R1、第二初始电压端I2和所述驱动电路12的控制端电连接，用于在所述初始化控制线R1提供的初始化控制信号的控制下，将所述第二初始电压端I2提供的第二初始电压Vi2写入所述驱动电路12的控制端；
所述第二储能电路44与所述驱动电路12的控制端电连接，用于储存电能；
所述第二初始化电路45分别与所述写入控制线GP、第三初始电压端I3和所述第四节点N4电连接，用于在所述写入控制信号的控制下，将所述第三初始电压端I3提供的第三初始电压写入所述第四节点N4。
可选的，所述第一发光控制电路包括第三晶体管，所述第二发光控制电路包括第四晶体管，所述驱动电路包括驱动晶体管；
所述第三晶体管的控制极与所述发光控制线电连接，所述第三晶体管的 第一极与所述第一电压端电连接，所述第三晶体管的第二极与所述第一节点电连接；
所述第四晶体管的控制极与所述发光控制线电连接，所述第四晶体管的第一极与所述第三节点电连接，所述第四晶体管的第二极与所述第四节点电连接；
所述驱动晶体管的控制极与所述第二节点电连接，所述驱动晶体管的第一极与所述第一节点电连接，所述驱动晶体管的第二极与所述第三节点电连接。
可选的，所述数据写入电路包括第五晶体管，所述补偿控制电路包括第六晶体管，所述第一初始化电路包括第七晶体管，所述第二初始化电路包括第八晶体管，所述第二储能电路包括第二电容；
所述第五晶体管的控制极与所述写入控制线电连接，所述第五晶体管的第一极与所述数据线电连接，所述第五晶体管的第二极与所述驱动电路的第一端电连接；
所述第六晶体管的控制极与所述补偿控制线电连接，所述第六晶体管的第一极与所述驱动电路的控制端电连接，所述第六晶体管的第二极与所述驱动电路的第二端电连接；
所述第七晶体管的控制极与所述初始化控制线电连接，所述第七晶体管的第一极与所述第二初始电压端电连接，所述第七晶体管的第二极与所述驱动电路的控制端电连接；
所述第八晶体管的控制极与所述写入控制线电连接，所述第八晶体管的第一极与所述第三初始电压端电连接，所述第八晶体管的第二极与上所述第四节点电连接；
所述第二电容的第一端与所述第二节点电连接，所述第二电容的第二端与第一电压端电连接。
如图10所示，在图7所示的像素电路的至少一实施例的基础上，所述发光元件为有机发光二极管O1；所述第一控制电路14包括第一晶体管T1，所述第二控制电路15包括第二晶体管T2；
所述第一晶体管T1的栅极与发光控制线E1电连接，所述第一晶体管T1 的源极与所述第五节点N5电连接，所述第一晶体管T1的漏极与第三节点N3电连接；
所述第二晶体管T2的栅极与所述发光控制线E1电连接，所述第二晶体管T2的源极与所述第一初始电压端I1电连接，所述第二晶体管T2的漏极与所述第五节点N5电连接；所述第一初始电压端I1用于提供第一初始电压Vi1；
所述第一储能电路16包括第一电容C1；
所述第一电容C1的第一端与所述第五节点N5电连接，所述第一电容C1的第二端与高电压端VDD电连接；
所述第一发光控制电路11包括第三晶体管T3，所述第二发光控制电路13包括第四晶体管T4，所述驱动电路12包括驱动晶体管T0；
所述第三晶体管T3的栅极与所述发光控制线E1电连接，所述第三晶体管T3的源极与高电压端VDD电连接，所述第三晶体管T3的漏极与所述第一节点N1电连接；
所述第四晶体管T4的栅极与所述发光控制线E1电连接，所述第四晶体管T4的源极与所述第三节点N3电连接，所述第四晶体管T4的漏极与所述第四节点N4电连接；所述有机发光二极管O1的阳极与所述第四节点N4电连接，所述有机发光二极管O1的阴极与低电压端VSS电连接；
所述驱动晶体管T0的栅极与所述第二节点N2电连接，所述驱动晶体管T0的源极与所述第一节点N1电连接，所述驱动晶体管T2的漏极与所述第三节点N3电连接；
所述数据写入电路41包括第五晶体管T5，所述补偿控制电路42包括第六晶体管T6，所述第一初始化电路43包括第七晶体管T7，所述第二初始化电路45包括第八晶体管T8，所述第二储能电路44包括第二电容C2；
所述第五晶体管T5的栅极与所述写入控制线GP电连接，所述第五晶体管T5的源极与所述数据线D1电连接，所述第五晶体管T5的漏极与所述驱动晶体管T0的源极电连接；
所述第六晶体管T6的栅极与所述补偿控制线GN电连接，所述第六晶体管T6的源极与所述驱动晶体管T0的栅极电连接，所述第六晶体管T6的漏极与所述驱动晶体管T0的漏极电连接；
所述第七晶体管T7的栅极与所述初始化控制线R1电连接，所述第七晶体管T7的源极与所述第二初始电压端I2电连接，所述第七晶体管T7的漏极与所述驱动晶体管T0的栅极电连接；所述第二初始电压端I2用于提供第二初始电压Vi2；
所述第八晶体管T8的栅极与所述写入控制线GP电连接，所述第八晶体管T8的源极与所述第一初始电压端I1电连接，所述第八晶体管T8的漏极与上所述第四节点N4电连接；
所述第二电容C2的第一端与所述第二节点N2电连接，所述第二电容C2的第二端与高电压端VDD电连接。
在图10中，标号为C0的为所述第一节点N1与所述高电压端VDD之间的寄生电容。
在图10所示的像素电路的至少一实施例中，所述第一初始电压端与所述第三初始电压端为同一电压端，所述第一电压端为高电压端VDD，所述第二电压端为低电压端VSS，但不以此为限。
在图10所示的像素电路的至少一实施例中，所述复位控制线为所述发光控制线E1。
在图10所示的像素电路的至少一实施例中，T1、T6和T7为氧化物薄膜晶体管，T0、T2、T3、T4、T5和T8为低温多晶硅薄膜晶体管，但不以此为限。
如图11所示，本公开如图10所示的像素电路的至少一实施例在工作时，所述显示周期可以包括初始化阶段S1、补偿阶段S2、数据写入阶段和发光阶段S3；所述数据写入阶段包含于所述补偿阶段S2；所述初始化阶段S1、所述补偿阶段S2和所述发光阶段S3先后设置；
在所述初始化阶段S1，R1提供高电压信号，T7打开，以将第二初始电压端I2提供的第二初始电压Vi2提供至第二节点N2，以使得在补偿阶段开始时，所述驱动晶体管T0能够导通；
在所述初始化阶段S1，GN提供低电压信号，GP提供高电压信号，E1提供高电压信号，T1打开，T2、T3、T4、T5、T6和T0都关断；在所述数据写入阶段，数据线D1提供数据电压Vdata，GP提供低电压信号，T5打开， 以将数据电压Vdata写入第一节点N1；T8打开，以将第一初始电压Vi1写入O1的阳极，以使得O1不发光；
在所述补偿阶段S2，GN提供高电压信号，E1提供高电压信号，R1提供低电压信号，T7关断，T1打开；T6打开，以将第二节点N2与第三节点N3之间连通；
在所述补偿阶段S2开始时，T0打开，Vdata通过T5、T0和T6向C2充电，以提升第二节点N2的电位，直至T0关断，此时第二节点N2的电位为Vdata+Vth，Vth为T0的阈值电压，Vth为负值；
在发光阶段S3，E1提供低电压信号，R1提供低电压信号，GN提供低电压信号，GP提供高电压信号，T3和T4都打开，T0驱动O1发光；T2打开，以将第一初始电压端I1提供的第一初始电压Vi1写入第五节点N5。
在图11和图12中，标号为L0的为O1的发光亮度。
在图11所示的工作时序中，所述数据写入阶段包含于所述补偿阶段S2，但不以此为限；在实际操作时，所述数据写入阶段也可以与所述补偿阶段S2为同一时间段。
在图11中，标号为GP_2为与GP相邻的下一行写入控制线，与GP_2对应的波形是所述下一行写入控制线提供的下一行写入控制信号的波形。
如图11所示，在所述补偿阶段S2的前半部分时间，GP提供低电压信号，在所述补偿阶段S2的后半部分时间，GP_2提供低电压信号，以控制相邻行像素电路分时接入相应的数据电压。
本公开如图10所示的像素电路的至少一实施例在工作时，在发光阶段S3，T2打开，以将第一初始电压端I1提供的第一初始电压Vi1写入第五节点N5，第一电容C1将第一初始电压Vi1存储于所述第五节点N5；
在非发光阶段(所述非发光阶段可以为所述显示周期包括的除了发光阶段之外的时间段)，T1打开，以控制所述第五节点N5与第三节点N3之间连通，以将所述第一初始电压Vi1写入所述第三节点N3，从而使得再一次进入发光阶段时，第一节点N1额外积累的多余电荷流经第三节点N3时被复位的低电位抵消，从而同一显示周期(所述显示周期可以为一帧显示时间)内亮度呈现递增的现象被抑制，改善了Flicker(闪烁)问题。
如图12所示，本公开如图10所示的像素电路的至少一实施例在工作时，刷新子显示帧中的显示周期可以包括先后设置的初始化阶段S1、补偿阶段S2、数据写入阶段、第一发光阶段S31、第二发光阶段S32、第三发光阶段S33和第四发光阶段S34；所述数据写入阶段包含于所述补偿阶段S2；
所述初始化阶段S1、所述补偿阶段S2、所述第一发光阶段S31、所述第二发光阶段S32、所述第三发光阶段S33和所述第四发光阶段S34先后设置；
在第一发光阶段S31与第二发光阶段S32之间设置有第一间隔阶段S01，在第二发光阶段S32与所述第三发光阶段S33之间设置有第二间隔阶段S02，在第三发光阶段S33与第四发光阶段S34之间设置有第三间隔阶段S03；
在所述初始化阶段S1，R1提供高电压信号，T7打开，以将第二初始电压端I2提供的第二初始电压Vi2提供至第二节点N2，以使得在补偿阶段开始时，所述驱动晶体管T0能够导通；
在所述初始化阶段S1，GN提供低电压信号，GP提供高电压信号，E1提供高电压信号，T1打开，T2、T3、T4、T5、T6和T0都关断；
在所述数据写入阶段，数据线D1提供数据电压Vdata，GP提供低电压信号，T5打开，以将数据电压Vdata写入第一节点N1；T8打开，以将第一初始电压Vi1写入O1的阳极，以使得O1不发光；
在所述补偿阶段S2，GN提供高电压信号，E1提供高电压信号，R1提供低电压信号，T7关断，T1打开；T6打开，以将第二节点N2与第三节点N3之间连通；
在所述补偿阶段S2开始时，T0打开，Vdata通过T5、T0和T6向C2充电，以提升第二节点N2的电位，直至T0关断，此时第二节点N2的电位为Vdata+Vth，Vth为T0的阈值电压，Vth为负值；在第一发光阶段S31、第二发光阶段S32、第三发光阶段S33和第四发光阶段S34，E1提供低电压信号，R1提供低电压信号，GN提供低电压信号，GP提供高电压信号，T3和T4都打开，T0驱动O1发光；T2打开，以将第一初始电压端I1提供的第一初始电压Vi1写入第五节点N5；
在第一间隔阶段S01、第二间隔阶段S02和第三间隔阶段S03，E1提供高电压信号，R1提供低电压信号，GN提供低电压信号，GP提供高电压信号， T1打开，以将存储于第五节点N5的第一初始电压Vi1写入第三节点N3。
如图12所示，本公开所述的像素电路的至少一实施例在工作于低频显示模式下时，所述写入控制线GP提供的写入控制信号的频率小于所述发光控制线E1提供的发光控制信号的频率，所述发光控制信号为高频信号，所述写入控制信号、所述初始化控制线R1提供的初始化控制信号，以及，所述补偿控制线GN提供的补偿控制信号都为低频信号，以降低功耗。
如图13所示，本公开如图10所示的像素电路的至少一实施例在工作时，在低频显示时，显示帧可以包括刷新子显示帧F1和至少一个保持子显示帧；
在所述保持子显示帧，数据线D1提供高电压信号；所述数据线D1提供的高电压信号的电压值等于高电压端VDD提供的高电压信号的电压值，例如，该高电压信号的电压值可以为4.6V；
在所述保持子显示帧中的数据写入阶段，GP提供低电压，T5打开，以将所述高电压信号写入第一节点N1；
在所述保持子显示帧，当E1提供低电压信号时，T1和T2打开，T0驱动O1发光。
由于在保持子显示帧，所述数据线D1提供的高电压信号的电压值等于高电压端VDD提供的高电压信号的电压值，因此即使T5漏电，也会使得N1的电位保持在4.6V，从而使得在不同频率显示时，第一节点N1的电位保持相同的准位，改善了由此带来的亮度差异。
在图12和图13中，标号为F21的为第一保持子显示帧，标号为F2N的为第N保持子显示帧，N为大于1的整数；
标号为S41的为第一保持子显示帧F21包括的数据写入阶段，标号为S4N的为第N保持子显示帧F2N包括的数据写入阶段。
在图13中，标号为GP_2为与GP相邻的下一行写入控制线，与GP_2对应的波形是所述下一行写入控制线提供的下一行写入控制信号的波形。
由图14可知，当在所述保持子显示帧，数据线D1提供高电压信号，并该高电压信号的电压值等于高电压端VDD提供的高电压信号的电压值时，在刷新频率由120Hz变为1Hz时，亮度变化为2.8％，切换频率时亮度差异改善明显。
本公开图15所示的像素电路的至少一实施例与本公开图10所示的像素电路的至少一实施例的区别在于：T1的漏极与第一节点N1电连接。
本公开如图15所示的像素电路的至少一实施例在工作时，
在发光阶段，E1提供低电压信号，T1关断，T2打开，将第一初始电压Vi1写入第五节点N5，C1将第一初始电压Vi1存储于所述第五节点N5；
在非发光阶段，E1提供高电压信号，T1打开，存储于第五节点N5的Vi1通过T1将第一节点N1的电位进行复位，从而使得再一次进入发光阶段时，第一节点N1额外积累的多余电荷被复位的低电位抵消，从而同一显示周期(所述显示周期可以为一帧显示时间)内亮度呈现递增的现象被抑制，改善了Flicker(闪烁)问题。
本公开如图15所示的像素电路的至少一实施例在处于低频显示模式下时，GP提供的写入控制信号的频率小于E1提供的发光控制信号的频率，以能够降低功耗。
本公开图16所示的像素电路的至少一实施例与本公开图10所示的像素电路的至少一实施例的区别在于：T1的漏极与第四节点N4电连接。本公开如图16所示的像素电路的至少一实施例在工作时，
在发光阶段，E1提供低电压信号，T1关断，T2打开，将第一初始电压Vi1写入第五节点N5，C1`将第一初始电压Vi1存储于所述第五节点N5；
在非发光阶段，E1提供高电压信号，T2关断，T1打开，存储于第五节点N5的Vi1通过T1将第四节点N4的电位进行复位，从而使得再一次进入发光阶段时，第一节点N1额外积累的多余电荷在流经第四节点N4时被复位的低电位抵消，从而同一显示周期(所述显示周期可以为一帧显示时间)内亮度呈现递增的现象被抑制，改善了Flicker(闪烁)问题。
本公开如图16所示的像素电路的至少一实施例在处于低频显示模式下时，GP提供的写入控制信号的频率小于E1提供的发光控制信号的频率，以能够降低功耗。
本公开图17所示的像素电路的至少一实施例与本公开图16所示的像素电路的至少一实施例的区别在于：本公开图17所示的像素电路的至少一实施例不包括第八晶体管T8。
本公开如图17所示的像素电路的至少一实施例在工作时，
在发光阶段，E1提供低电压信号，T1关断，T2打开，将第一初始电压Vi1写入第五节点N5，C1`将第一初始电压Vi1存储于所述第五节点N5；
在非发光阶段，E1提供高电压信号，T2关断，T1打开，存储于第五节点N5的Vi1通过T1将第四节点N4的电位进行复位，从而使得再一次进入发光阶段时，第一节点N1额外积累的多余电荷在流经第四节点N4时被复位的低电位抵消，从而同一显示周期(所述显示周期可以为一帧显示时间)内亮度呈现递增的现象被抑制，改善了Flicker(闪烁)问题。
本公开如图17所示的像素电路的至少一实施例在处于低频显示模式下时，GP提供的写入控制信号的频率小于E1提供的发光控制信号的频率，以能够降低功耗。
本公开实施例所述的像素驱动方法，应用于上述的像素电路，显示周期包括非发光阶段和发光阶段；所述像素驱动方法包括：
在非发光阶段，复位控制电路在复位控制信号的控制下，将第一初始电压提供至连接节点，从而使得进入发光阶段时，第一节点额外累积的多余电荷被提供至所述连接节点的第一初始电压抵消，从而从而同一显示周期(所述显示周期可以为一帧显示时间)内亮度呈现递增的现象被抑制，改善了Flicker(闪烁)问题。
可选的，所述复位控制电路包括第一控制电路、第二控制电路和第一储能电路；本公开至少一实施例所述的像素驱动方法包括：
在发光阶段，第二控制电路在所述复位控制信号的控制下，将第一初始电压写入第五节点，第一储能电路将第一初始电压存储于所述第五节点；
在非发光阶段，第一控制电路在所述复位控制信号的控制下，控制所述第五节点与连接节点之间连通，以将所述第一初始电压写入所述连接节点。
在具体实施时，所述复位控制电路可以包括第一控制电路、第二控制电路和第一储能电路；在发光阶段，第二控制电路和第一储能电路控制将第一初始电压写入并存储于第五阶段，在非发光阶段，第一控制电路将所述第一初始电压写入所述连接节点。
在本公开至少一实施例中，所述像素电路还包括数据写入电路、补偿控 制电路、第一初始化电路、第二储能电路和第二初始化电路；所述显示周期包括的第一显示阶段包括先后设置的初始化阶段、补偿阶段和发光阶段，所述补偿阶段包括数据写入阶段；所述像素驱动方法包括：
在所述初始化阶段，第一初始化电路在复位控制信号的控制下，将第二初始电压写入驱动电路的控制端，以使得在补偿阶段开始时，所述驱动电路能够在其控制端的电位的控制下，控制第一节点与第三节点之间连通；
在所述数据写入阶段，数据线提供数据电压Vdata，所述数据写入电路在写入控制信号的控制下，将所述数据电压Vdata写入所述第一节点；
在所述补偿阶段，所述补偿控制电路在补偿控制信号的控制下，控制第二节点与所述第三节点之间连通；
在所述发光阶段，第一发光控制电路在发光控制信号的控制下，控制第一电压端与所述第一节点之间连通，第二发光控制电路在所述发光控制信号的控制下，控制所述第三节点与所述第四节点之间连通，所述驱动电路产生驱动发光元件的驱动电流。
在本公开至少一实施例中，所述像素电路还包括数据写入电路；所述非发光阶段包括数据写入阶段；显示帧包括刷新子显示帧和至少一个保持子显示帧；所述刷新子显示帧包括所述显示周期，所述保持子显示帧包括所述显示周期；所述像素驱动方法还包括：
在所述保持子显示帧，数据线提供第一电压信号；
在所述保持子显示帧中的数据写入阶段，所述数据写入电路在写入控制信号的控制下，将所述第一电压信号写入第一节点。
在所述保持子显示帧，即使所述数据写入电路包括的晶体管漏电，也会使得第一节点的电位保持为第一电压值(所述第一电压值为第一电压信号的电压值)，从而使得在不同频率显示时，第一节点的电位保持为相同的准位，降低亮度差异。
可选的，所述像素电路还包括补偿控制电路；所述显示周期还包括补偿阶段；本公开至少一实施例所述的像素驱动方法还包括：
在所述刷新子显示帧中的数据写入阶段，数据线提供数据电压，所述数据写入电路在写入控制信号的控制下，将所述数据电压写入第一节点；
在所述刷新子显示帧中的补偿阶段，所述补偿控制电路在补偿控制信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间连通；
在所述刷新子显示帧中的发光阶段和保持子显示帧中的发光阶段，第一发光控制电路在发光控制信号的控制下，控制第一电压端与所述第一节点之间连通，第二发光控制电路在所述发光控制信号的控制下，控制所述第三节点与所述第四节点之间连通，驱动电路产生驱动发光元件的驱动电流；
在所述保持子显示帧，所述补偿控制电路在补偿控制信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间断开。
在本公开至少一实施例所述的像素驱动方法中，在刷新子显示帧中的发光阶段和保持子显示帧中的发光阶段，驱动电路驱动发光元件发光，在保持子显示帧，补偿控制电路控制所述驱动电路的控制端与所述驱动电路的第二端之间断开，因此即使在保持子显示帧中的特定时间段，数据写入电路包括的晶体管打开，驱动电路的控制端的电位也不会打开，不会影响显示亮度。
可选的，在所述显示帧，所述写入控制信号的频率小于所述发光控制信号的频率。
在本公开至少一实施例中，当像素电路工作于低频显示模式下时，所述显示帧包括刷新子显示帧和至少一个保持子显示帧，在所述显示帧，所述述写入控制信号的频率小于所述发光控制信号的频率，以能够降低功耗。
本公开实施例所述的显示装置包括上述的像素电路。
本公开实施例所提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (17)

  1. 一种像素电路，包括第一发光控制电路、驱动电路、第二发光控制电路、复位控制电路和发光元件；
    所述第一发光控制电路分别与发光控制线、第一电压端和第一节点电连接，用于在所述发光控制线提供的发光控制信号的控制下，控制所述第一电压端和所述第一节点之间连通或断开；
    所述驱动电路的控制端与第二节点电连接，所述驱动电路的第一端与所述第一节点电连接，所述驱动电路的第二端与第三节点电连接；所述驱动电路用于在其控制端的电位的控制下，控制产生驱动所述发光元件的驱动电流；
    所述第二发光控制电路分别与所述发光控制线、所述第三节点和第四节点电连接，用于在所述发光控制信号的控制下，控制所述第三节点和所述第四节点之间连通或断开；
    所述发光元件的第一极与所述第四节点电连接，所述发光元件的第二极与第二电压端电连接；
    所述复位控制电路分别与复位控制线、连接节点和用于提供第一初始电压的第一初始电压端电连接，用于在所述复位控制线提供的复位控制信号的控制下，将所述第一初始电压提供至所述连接节点；
    所述连接节点为所述第一节点、所述第三节点或所述第四节点。
  2. 如权利要求1所述的像素电路，其中，所述复位控制电路还与第五节点电连接，用于在所述复位控制信号的控制下，控制所述第一初始电压端与所述第五节点之间连通或断开，并控制所述第五节点与所述连接节点之间断开或连通，并用于维持所述第五节点的电位。
  3. 如权利要求2所述的像素电路，其中，所述复位控制电路包括第一控制电路、第二控制电路和第一储能电路；
    所述第一控制电路分别与所述复位控制线、所述连接节点和所述第五节点电连接，用于在所述复位控制信号的控制下，控制所述连接节点和所述第五节点之间连通或断开；
    所述第二控制电路分别与所述复位控制线、所述第五节点和第一初始电 压端电连接，用于在所述复位控制信号的控制下控制将所述第一初始电压端提供的第一初始电压写入所述第五节点；
    所述第一储能电路与所述第五节点电连接，用于储存电能。
  4. 如权利要求1至3中任一权利要求所述的像素电路，其中，所述复位控制线为所述发光控制线；或者，所述复位控制线提供的复位控制信号与所述发光控制线提供的发光控制信号相同。
  5. 如权利要求3所述的像素电路，其中，所述第一控制电路包括第一晶体管，所述第二控制电路包括第二晶体管；
    所述第一晶体管的控制极与所述复位控制线电连接，所述第一晶体管的第一极与所述第五节点电连接，所述第一晶体管的第二极与第三节点电连接；
    所述第二晶体管的控制极与所述复位控制线电连接，所述第二晶体管的第一极与所述第一初始电压端电连接，所述第二晶体管的第二极与所述第五节点电连接。
  6. 如权利要求5所述的像素电路，其中，所述第一晶体管为氧化物薄膜晶体管，所述第二晶体管为低温多晶硅薄膜晶体管。
  7. 如权利要求3所述的像素电路，其中，所述第一储能电路包括第一电容；
    所述第一电容的第一端与所述第五节点电连接，所述第一电容的第二端与第一电压端电连接。
  8. 如权利要求1至3中任一权利要求所述的像素电路，其中，还包括数据写入电路、补偿控制电路、第一初始化电路、第二储能电路和第二初始化电路；
    所述数据写入电路分别与写入控制线、数据线和第一节点电连接，用于在所述写入控制线提供的写入控制信号的控制下，将所述数据线提供的数据电压写入所述第一节点；
    所述补偿控制电路分别与补偿控制线、所述驱动电路的控制端和所述驱动电路的第二端电连接，用于在所述补偿控制线提供的补偿控制信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间连通或断开；
    所述第一初始化电路分别与初始化控制线、第二初始电压端和所述驱动 电路的控制端电连接，用于在所述初始化控制线提供的初始化控制信号的控制下，将所述第二初始电压端提供的第二初始电压写入所述驱动电路的控制端；
    所述第二储能电路与所述驱动电路的控制端电连接，用于储存电能；
    所述第二初始化电路分别与所述写入控制线、第三初始电压端和所述第四节点电连接，用于在所述写入控制信号的控制下，将所述第三初始电压端提供的第三初始电压写入所述第四节点。
  9. 如权利要求1至3中任一权利要求所述的像素电路，其中，所述第一发光控制电路包括第三晶体管，所述第二发光控制电路包括第四晶体管，所述驱动电路包括驱动晶体管；
    所述第三晶体管的控制极与所述发光控制线电连接，所述第三晶体管的第一极与所述第一电压端电连接，所述第三晶体管的第二极与所述第一节点电连接；
    所述第四晶体管的控制极与所述发光控制线电连接，所述第四晶体管的第一极与所述第三节点电连接，所述第四晶体管的第二极与所述第四节点电连接；
    所述驱动晶体管的控制极与所述第二节点电连接，所述驱动晶体管的第一极与所述第一节点电连接，所述驱动晶体管的第二极与所述第三节点电连接。
  10. 如权利要求8所述的像素电路，其中，所述数据写入电路包括第五晶体管，所述补偿控制电路包括第六晶体管，所述第一初始化电路包括第七晶体管，所述第二初始化电路包括第八晶体管，所述第二储能电路包括第二电容；
    所述第五晶体管的控制极与所述写入控制线电连接，所述第五晶体管的第一极与所述数据线电连接，所述第五晶体管的第二极与所述驱动电路的第一端电连接；
    所述第六晶体管的控制极与所述补偿控制线电连接，所述第六晶体管的第一极与所述驱动电路的控制端电连接，所述第六晶体管的第二极与所述驱动电路的第二端电连接；
    所述第七晶体管的控制极与所述初始化控制线电连接，所述第七晶体管的第一极与所述第二初始电压端电连接，所述第七晶体管的第二极与所述驱动电路的控制端电连接；
    所述第八晶体管的控制极与所述写入控制线电连接，所述第八晶体管的第一极与所述第三初始电压端电连接，所述第八晶体管的第二极与上所述第四节点电连接；
    所述第二电容的第一端与所述第二节点电连接，所述第二电容的第二端与第一电压端电连接。
  11. 一种像素驱动方法，应用于如权利要求1至10中任一权利要求所述的像素电路，显示周期包括非发光阶段和发光阶段；所述像素驱动方法包括：
    在非发光阶段，复位控制电路在复位控制信号的控制下，将第一初始电压提供至连接节点。
  12. 如权利要求11所述的像素驱动方法，其中，所述复位控制电路包括第一控制电路、第二控制电路和第一储能电路；所述像素驱动方法包括：
    在发光阶段，第二控制电路在所述复位控制信号的控制下，将第一初始电压写入第五节点，第一储能电路将第一初始电压存储于所述第五节点；
    在非发光阶段，第一控制电路在所述复位控制信号的控制下，控制所述第五节点与连接节点之间连通，以将所述第一初始电压写入所述连接节点。
  13. 如权利要求11或12所述的像素驱动方法，其中，所述像素电路还包括数据写入电路、补偿控制电路、第一初始化电路、第二储能电路和第二初始化电路；所述显示周期包括的第一显示阶段包括先后设置的初始化阶段、补偿阶段和发光阶段，所述补偿阶段包括数据写入阶段；所述像素驱动方法包括：
    在所述初始化阶段，第一初始化电路在复位控制信号的控制下，将第二初始电压写入驱动电路的控制端，以使得在补偿阶段开始时，所述驱动电路能够在其控制端的电位的控制下，控制第一节点与第三节点之间连通；
    在所述数据写入阶段，数据线提供数据电压Vdata，所述数据写入电路在写入控制信号的控制下，将所述数据电压Vdata写入所述第一节点；
    在所述补偿阶段，所述补偿控制电路在补偿控制信号的控制下，控制第 二节点与所述第三节点之间连通；
    在所述发光阶段，第一发光控制电路在发光控制信号的控制下，控制第一电压端与所述第一节点之间连通，第二发光控制电路在所述发光控制信号的控制下，控制所述第三节点与所述第四节点之间连通，所述驱动电路产生驱动发光元件的驱动电流。
  14. 如权利要求11或12所述的像素驱动方法，其中，所述像素电路还包括数据写入电路；所述非发光阶段包括数据写入阶段；显示帧包括刷新子显示帧和至少一个保持子显示帧；所述刷新子显示帧包括所述显示周期，所述保持子显示帧包括所述显示周期；所述像素驱动方法还包括：
    在所述保持子显示帧，数据线提供第一电压信号；
    在所述保持子显示帧中的数据写入阶段，所述数据写入电路在写入控制信号的控制下，将所述第一电压信号写入第一节点。
  15. 如权利要求14所述的像素驱动方法，其中，所述像素电路还包括补偿控制电路；所述显示周期还包括补偿阶段；所述像素驱动方法还包括：
    在所述刷新子显示帧中的数据写入阶段，数据线提供数据电压，所述数据写入电路在写入控制信号的控制下，将所述数据电压写入第一节点；
    在所述刷新子显示帧中的补偿阶段，所述补偿控制电路在补偿控制信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间连通；
    在所述刷新子显示帧中的发光阶段和保持子显示帧中的发光阶段，第一发光控制电路在发光控制信号的控制下，控制第一电压端与所述第一节点之间连通，第二发光控制电路在所述发光控制信号的控制下，控制所述第三节点与所述第四节点之间连通，驱动电路产生驱动发光元件的驱动电流；
    在所述保持子显示帧，所述补偿控制电路在补偿控制信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间断开。
  16. 如权利要求15所述的像素驱动方法，其中，在所述显示帧，所述写入控制信号的频率小于所述发光控制信号的频率。
  17. 一种显示装置，包括如权利要求1至10中任一权利要求所述的像素电路。
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