WO2018192353A1 - 像素驱动电路及其操作方法以及显示面板 - Google Patents

像素驱动电路及其操作方法以及显示面板 Download PDF

Info

Publication number
WO2018192353A1
WO2018192353A1 PCT/CN2018/081332 CN2018081332W WO2018192353A1 WO 2018192353 A1 WO2018192353 A1 WO 2018192353A1 CN 2018081332 W CN2018081332 W CN 2018081332W WO 2018192353 A1 WO2018192353 A1 WO 2018192353A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
circuit
signal
control
sub
Prior art date
Application number
PCT/CN2018/081332
Other languages
English (en)
French (fr)
Inventor
王鑫
刘颖
Original Assignee
京东方科技集团股份有限公司
北京京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 北京京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/089,875 priority Critical patent/US20200234633A1/en
Publication of WO2018192353A1 publication Critical patent/WO2018192353A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G09G3/3241—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror
    • G09G3/325—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror the data current flowing through the driving transistor during a setting phase, e.g. by using a switch for connecting the driving transistor to the data driver
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0814—Several active elements per pixel in active matrix panels used for selection purposes, e.g. logical AND for partial update
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a pixel driving circuit, an operating method, and a display panel.
  • OLED Organic Light Emitting Diode
  • LCDs liquid crystal displays
  • OLED displays have the advantages of low energy consumption, low production cost, self-illumination, wide viewing angle and fast response.
  • LCDs liquid crystal displays
  • OLED displays have begun to replace traditional LCD displays.
  • LCDs that use a stable voltage to control brightness
  • OLEDs are current driven and require a constant current to control their illumination. Due to process process and device aging, etc., a pixel compensation circuit having a function of compensating for the threshold voltage Vth of the driving transistor is generally used as a driving circuit to drive the OLED to emit light.
  • an initialization transistor is generally provided in the pixel compensation circuit, which receives an initialization signal, and supplies an initialization signal to the gate of the driving transistor at a stage after the driving transistor drives the OLED to complete illumination, and initializes the gate voltage of the driving transistor. .
  • the initialization transistors are all off. In particular, the initialization transistor is guaranteed to be in an off state during the illumination phase in which the drive transistor drives the OLED illumination.
  • the initialization transistor generally uses a switching transistor for the switching function.
  • the switching transistor may not guarantee lossless conduction or complete turn-off, so a leakage current path may be formed in the switching transistor, causing part of the current for OLED illumination to flow into the initialization signal path through the initialization transistor, thereby affecting the luminance of the OLED. , which causes flicker.
  • Some embodiments of the present disclosure provide a pixel driving circuit, a method of operating the same, and a display panel. According to the embodiment of the present disclosure, it is possible to avoid formation of a leakage current path by the initialization transistor, improve the luminance of the OLED, and improve or eliminate the flicker phenomenon during display.
  • a pixel driving circuit including: a pixel compensation circuit including a driving transistor and an initialization transistor for driving a light emitting device in a pixel, the initialization transistor The first pole is connected to the initialization signal terminal to receive an initialization signal, the second pole of the initialization transistor is connected to the control electrode of the driving transistor, and the signal input sub-circuit, wherein the signal input sub-circuit is connected to the reset signal Between the terminal and the control electrode of the initialization transistor, the signal input sub-circuit is configured to selectively provide a reset signal to a control electrode of the initialization transistor under control of a reset signal received from the reset signal terminal; a leakage suppression sub-circuit connected to the leakage control signal terminal and the control electrode of the initialization transistor, respectively, the leakage suppression sub-circuit being configured to: receive a leakage control signal from the leakage control signal terminal Charging or discharging the leakage suppressor circuit and passing the Charging or discharging so that the initialization transistor is turned off.
  • the leakage suppression sub-circuit is further configured to: cause a voltage difference between a control electrode of the initialization transistor and a second electrode of the initialization transistor under the control of the leakage control signal Changed to cause the initialization transistor to be further turned off.
  • the initialization transistor is an N-type transistor, and wherein the changing comprises reducing a voltage difference between a control electrode of the initialization transistor and a second electrode of the initialization transistor.
  • the initialization transistor is a P-type transistor, and wherein the changing comprises increasing a voltage difference between a control electrode of the initialization transistor and a second electrode of the initialization transistor.
  • the leakage control signal includes a pulse signal including a high level period and a low level period in each pulse period of the pulse signal; and wherein the leakage suppression sub-circuit is configured for : charging the leakage suppression sub-circuit by a high-level period of the pulse signal, and discharging the leakage suppression sub-circuit by a low-level period of the pulse signal, wherein in the pulse period, for discharging The duration of the low level period is less than the high level period for charging.
  • the leakage control signal includes a pulse signal including a high level period and a low level period in each pulse period of the pulse signal;
  • leakage suppression sub-circuit is configured to:
  • the duration of the low level period for discharging is greater than the high level period for charging.
  • the signal input sub-circuit includes: a first switching transistor, wherein
  • the control electrode of the first switching transistor and its first pole are both connected to the reset signal terminal, and the second pole of the first switching transistor is connected to the control electrode of the initialization transistor.
  • the active layer of the first switching transistor comprises polysilicon.
  • the leakage suppression sub-circuit includes: a first capacitor; wherein
  • the first end of the first capacitor is connected to the leakage control signal end, and the second end is connected to the control electrode of the initialization transistor.
  • the pixel compensation circuit further includes a data writing sub-circuit, a reset sub-circuit, a compensation control sub-circuit, a storage sub-circuit, and an illumination control sub-circuit;
  • first pole of the driving transistor is connected to the first power terminal
  • the data writing sub-circuit is respectively connected to the data signal end, the scanning signal end and the first node, and is used for data provided at the data signal end under the control of the scanning signal provided at the scanning signal end. a signal is provided to the first node;
  • the reset sub-circuit is respectively connected to the reset signal end, the reference signal end, and the first node, and is configured to provide a reference signal provided at the reference signal end to the control under the control of the reset signal Said first node;
  • the compensation control sub-circuit is respectively connected to the scan signal terminal, the control electrode of the driving transistor, and the second electrode of the driving transistor, for driving the driving transistor under the control of the scanning signal.
  • the control electrode is electrically connected to the second pole of the driving transistor;
  • the storage sub-circuit is respectively connected to the first node and the control electrode of the driving transistor for charging or discharging under the control of the signal of the first node and the signal of the control electrode of the driving transistor. And maintaining a voltage difference between the first node and a control electrode of the driving transistor stable when the control electrode of the driving transistor is in a floating state;
  • the illumination control sub-circuit is respectively connected to the illumination control signal end, the reference signal end, the first node, the second pole of the driving transistor, and the first end of the light emitting device, and the illumination control a sub-circuit for electrically connecting the reference signal terminal to the first node under control of an illumination control signal provided at the end of the illumination control signal, and electrically connecting the second pole of the drive transistor and the illumination device
  • the first end is such that the drive transistor is capable of driving the light emitting device to emit light.
  • the data writing sub-circuit includes: a second switching transistor; wherein a control electrode of the second switching transistor is connected to the scan signal end, and a first pole of the second switching transistor The data signal ends are connected, and the second pole of the second switching transistor is connected to the first node;
  • the reset sub-circuit includes: a third switching transistor; wherein a control electrode of the third switching transistor is connected to the reset signal terminal, and a first pole of the third switching transistor is connected to the reference signal terminal The second pole of the third switching transistor is connected to the first node;
  • the compensation control sub-circuit includes: a fourth switching transistor; wherein a control electrode of the fourth switching transistor is connected to the scan signal end, and a first pole of the fourth switching transistor and the driving transistor a control electrode is connected, and a second pole of the fourth switching transistor is connected to a second pole of the driving transistor;
  • the storage sub-circuit includes: a second capacitor, wherein a first end of the second capacitor is connected to the first node, and a second end is connected to a control pole of the driving transistor;
  • the illuminating control sub-circuit includes: a fifth switching transistor and a sixth switching transistor; wherein a control electrode of the fifth switching transistor is connected to the illuminating control signal end, and a first pole of the fifth switching transistor Connected to the reference signal end, the second pole of the fifth switching transistor is connected to the first node; the control pole of the sixth switching transistor is connected to the light emission control signal end, the sixth switching transistor The first pole is connected to the second pole of the driving transistor, and the second pole of the sixth switching transistor is connected to the first end of the light emitting device.
  • the driving transistor is a P-type transistor
  • the driving transistor is a P-type transistor
  • the reset sub-circuit, the compensation control sub-circuit, the storage sub-circuit, and the illumination control sub-circuit All of the switching transistors in the process are formed by P-type transistors.
  • the driving transistor is an N-type transistor
  • the data writing sub-circuit, the reset sub-circuit, the compensation control sub-circuit, the storage sub-circuit, and the illumination control sub-circuit All of the switching transistors in the process are formed by N-type transistors.
  • a display device comprising: a light emitting device, and a pixel driving circuit according to any of the embodiments of the present disclosure for driving the light emitting device.
  • the voltage difference between the control electrode of the initialization transistor and the second electrode of the initialization transistor is changed by the leakage suppression sub-circuit under the control of the leakage control signal; and in the light-emitting phase,
  • the light emitting device is driven to emit light by the driving transistor.
  • the initialization transistor is an N-type transistor
  • the changing comprises: reducing a voltage difference between a control electrode of the initialization transistor and a second electrode of the initialization transistor.
  • the initialization transistor is a P-type transistor
  • the changing comprises increasing a voltage difference between a control electrode of the initialization transistor and a second electrode of the initialization transistor.
  • the leakage control signal includes a pulse signal including a high level period and a low level period in each pulse period of the pulse signal;
  • reducing the voltage difference comprises:
  • the duration of the low level period for discharging is less than the high level period for charging.
  • the leakage control signal includes a pulse signal including a high level period and a low level period in each pulse period of the pulse signal;
  • increasing the voltage difference comprises:
  • the duration of the low level period for discharging is greater than the high level period for charging.
  • the pixel compensation circuit further includes a data writing sub-circuit, a reset sub-circuit, a compensation control sub-circuit, a storage sub-circuit, and an illumination control sub-circuit;
  • the first pole of the driving transistor is connected to the first power terminal;
  • the data writing sub-circuit is respectively connected to the data signal end, the scanning signal end and the first node;
  • the reset sub-circuit and the reset signal respectively a terminal, a reference signal terminal, and the first node;
  • the compensation control sub-circuit is respectively connected to the scan signal terminal, the control electrode of the driving transistor, and the second electrode of the driving transistor;
  • the storage sub-circuit Connected to the first node and the control electrode of the driving transistor respectively;
  • the light emitting control sub-circuit is respectively connected to the light-emitting control signal end, the reference signal end, the first node, and the second pole of the driving transistor And the first end of the light emitting device is connected,
  • the method further includes:
  • the storage sub-circuit is discharged under control of a signal at the first node and a signal of a control electrode of the drive transistor.
  • the method further includes:
  • the storage subcircuit is charged under control of a signal at the first node and a signal at a control pole of the drive transistor.
  • FIG. 1 is a block diagram showing the structure of a pixel driving circuit according to some embodiments of the present disclosure
  • FIG. 2 is a schematic structural diagram of a pixel driving circuit according to some embodiments of the present disclosure
  • FIG. 3a illustrates a detailed structural diagram of a pixel driving circuit according to some embodiments of the present disclosure
  • FIG. 3b illustrates a detailed structural diagram of a pixel driving circuit according to some embodiments of the present disclosure
  • FIG. 4a shows a detailed structural diagram of a pixel driving circuit in accordance with some embodiments of the present disclosure
  • FIG. 4b illustrates a detailed structural diagram of a pixel driving circuit in accordance with some embodiments of the present disclosure
  • Figure 5a is a timing diagram schematically showing the operation of the pixel driving circuit shown in Figure 3a;
  • Figure 5b is a timing diagram schematically showing the operation of the pixel driving circuit shown in Figure 4a;
  • FIG. 6 is a flow chart of a method of operation of a pixel driving circuit in accordance with some embodiments of the present disclosure
  • FIG. 7 is a flow chart of a method of operation of a pixel driving circuit, in accordance with some embodiments of the present disclosure.
  • FIGS. 8a and 8b are flow diagrams showing some additional steps of a method of operation of a pixel driving circuit, in accordance with some embodiments of the present disclosure.
  • FIGS. 1 and 2 Some embodiments of the present disclosure provide a pixel circuit, as shown in FIGS. 1 and 2, which may include a light emitting device L (such as, but not limited to, an OLED) and a pixel driving circuit for driving the light emitting device L.
  • a light emitting device L such as, but not limited to, an OLED
  • FIGS. 1 and 2 Also shown in FIGS. 1 and 2 is a block diagram showing the structure of a pixel driving circuit in accordance with some embodiments of the present disclosure. The main difference between FIG. 1 and FIG. 2 is the difference in the type of transistors used, and therefore, the following description will be collectively described in conjunction with the two figures.
  • the pixel driving circuit may include a pixel compensation circuit 10.
  • the pixel compensation circuit 10 may include a driving transistor DTFT and an initialization transistor M0.
  • the control electrode (eg, the gate) of the initialization transistor M0 is connected to the reset signal terminal Reset.
  • the first pole (for example, the source or the drain) of the initialization transistor M0 is connected to the initialization signal terminal (first signal terminal) Vinit.
  • the second pole (eg, drain or source) of the initialization transistor M0 is coupled to the gate (eg, gate) m0 of the drive transistor DTFT.
  • the initialization transistor M0 and the drive transistor DTFT can be implemented using a P-type transistor (for example, a P-type MOS transistor).
  • the initialization transistor M0 and the driving transistor DTFT can be implemented using an N-type transistor (for example, an N-type MOS transistor).
  • the remaining modules, components or elements, etc. can be adaptively adjusted or changed to practice the principles of the present disclosure and Example.
  • the remaining modules, components or components can be implemented using appropriate types of transistors accordingly.
  • the electrode of the transistor that is not the control electrode such as the drain or source, also referred to as the non-control electrode
  • the first pole or “second pole”
  • sexual just to distinguish it from the control pole.
  • MOS transistors generally, the source and drain are interchangeable.
  • the pixel driving circuit may further include: a signal input module 20 and a leakage suppression module 30.
  • the reset signal terminal (second signal terminal) Reset can be connected to the control electrode of the initialization transistor M0 through the signal input module 20.
  • the signal input module 20 can be configured to selectively provide a reset signal provided at the reset signal terminal Reset to the control electrode of the initialization transistor M0 under the control of the reset signal (second signal) provided by the reset signal terminal Reset.
  • the leakage suppression module 30 can be connected to the leakage control signal terminal (third signal terminal) CK and the control electrode of the initialization transistor M0, respectively.
  • One end of the leakage suppression module 30 may be connected to the leakage control signal terminal (third signal terminal) CK to receive the leakage control signal (the third signal, also indicated by CK), and the other end may be connected to the control electrode of the initialization transistor M0.
  • the leakage suppression module 30 can be configured to: charge or discharge the leakage suppression module by the leakage control signal, and cause the initialization transistor to be turned off by the charging or discharging, as further described below.
  • the pixel compensation circuit 10 may further include: a data writing module 11 , a reset module 12 , a compensation control module 13 , a storage module 14 , and a lighting control module 15 .
  • the data writing module 11 can be connected to the data signal terminal Data, the scanning signal terminal Scan and the first node A, respectively.
  • the data writing module 11 may be configured to provide the data signal supplied from the data signal terminal Data to the first node A under the control of the scanning signal (also indicated by Scan) provided by the scanning signal terminal Scan.
  • the reset module 12 can be connected to the reset signal end Reset, the reference signal terminal VREF, and the first node A, respectively.
  • the reset module 12 can be configured to provide a reference signal (also indicated by VREF) provided by the reference signal terminal VREF to the first node A under the control of a reset signal (also denoted by Reset).
  • the compensation control module 13 can be connected to the scan signal terminal Scan, the control electrode m0 of the drive transistor DTFT, and the second electrode m2 of the drive transistor DTFT, respectively.
  • the compensation control module 13 may be configured to electrically communicate the control electrode m0 of the driving transistor DTFT and the second electrode m2 of the driving transistor DTFT under the control of the scanning signal Scan.
  • the first electrode m1 of the driving transistor DTFT may be connected to the first power supply terminal VDD.
  • the memory module 14 can be connected to the first node A and the control electrode m0 of the driving transistor DTFT, respectively.
  • the memory module 14 can be configured to charge or discharge under the control of the signal of the first node A and the signal of the control electrode m0 of the driving transistor DTFT.
  • the memory module 14 may be configured to maintain a voltage difference between the first node A and the control electrode m0 of the driving transistor DTFT stable when the gate electrode m0 of the driving transistor DTFT is in a floating state.
  • the illumination control module 15 can be respectively connected to the illumination control signal terminal EM, the reference signal terminal VREF, the first node A, the second pole m2 of the driving transistor DTFT, and the first end of the light emitting device L.
  • the second end of the light emitting device L may be connected to the second power supply terminal VSS.
  • the illumination control module 15 can be configured to electrically connect the reference signal terminal VREF with the first node A and to electrically connect the driving transistor DTFT under the control of the illumination control signal (also indicated by EM) provided at the illumination control signal terminal EM.
  • the second pole m2 is opposite to the first end of the light emitting device L. Thereby, the driving transistor DTFT can drive the light emitting device L to emit light.
  • the pixel driving circuit of the embodiment of the present disclosure compensation of the threshold voltage of the driving transistor can be achieved, and the leakage current path can be formed by avoiding the initialization transistor. Thereby, the brightness of the light emitting device can be improved, and the flicker phenomenon at the time of display can be improved.
  • the driving transistor DTFT may be formed of a P-type transistor.
  • the gate of the P-type transistor is the gate m0 of the driving transistor DTFT.
  • the source of the P-type transistor drives the first pole m1 of the transistor DTFT, and the drain of the P-type transistor is the second pole m2 of the driving transistor DTFT.
  • the operating current for driving the light-emitting device L to emit light flows from the source of the P-type transistor to the drain thereof.
  • the driving transistor DTFT may be formed of an N-type transistor.
  • the gate of the N-type transistor is the gate m0 of the driving transistor DTFT.
  • the drain of the N-type transistor is the first pole m1 of the driving transistor DTFT, and the source of the N-type transistor drives the second pole m2 of the transistor DTFT.
  • the operating current for driving the light-emitting device L to emit light flows from the drain of the N-type transistor to its source.
  • the initialization transistor M0 may be formed of a P-type transistor.
  • the initialization transistor M0 may also be formed of an N-type transistor.
  • the leakage suppression module is further configured to: under the control of the leakage control signal (third signal), make a control electrode of the initialization transistor and a second of the initialization transistor The voltage difference between the poles changes such that the initialization transistor is further turned off.
  • the leakage suppression module can be configured to: under the control of the leakage control signal terminal, the control electrode of the initialization transistor and the second pole of the initialization transistor The voltage difference between them increases.
  • the voltage difference can generally have a value greater than the threshold Vth of the P-type initialization transistor (Vth can typically be 0V or less than 0V) to turn off the P-type initialization transistor. Therefore, in the case where the threshold value of the P-type initialization transistor is about 0 V, the "increased voltage difference" may also refer to the absolute value of the voltage difference between the gate electrode of the initialization transistor and the second electrode of the initialization transistor. increase. As the voltage difference increases, the degree of turn-off of the P-type initialization transistor also increases.
  • the light emitting device may generally be an organic electroluminescent diode.
  • a current may be supplied to drive the light emitting device to achieve illumination while the drive transistor is in a saturated operating state.
  • the voltage of the first power terminal may be set to be higher than the voltage of the second power terminal.
  • the voltage V dd of the first power supply terminal can generally be a positive value
  • the voltage V ss of the second power supply terminal can generally be grounded or negative.
  • the voltage V dd of the first power supply terminal and the voltage V ss of the second power supply terminal need to be determined according to the actual application environment, which is not limited herein.
  • the leakage suppression module can be configured to: under the control of the leakage control signal terminal, the control electrode of the initialization transistor and the second electrode of the initialization transistor The voltage difference between them decreases.
  • the voltage difference can generally have a value that is less than a threshold Vth of the N-type initialization transistor (Vth can generally be a value greater than 0V) to turn off the N-type initialization transistor. As the voltage difference decreases, the degree to which the N-type initialization transistor is turned off increases.
  • the initialization transistor can be further turned off, thereby preventing the initialization transistor from forming a leakage current path, thereby improving the luminance of the light emitting device and improving the flicker phenomenon during display.
  • FIG. 3a and 3b show a detailed structural diagram of a pixel driving circuit in accordance with some embodiments of the present disclosure.
  • 4a and 4b show a detailed structural diagram of a pixel driving circuit in accordance with some embodiments of the present disclosure.
  • Fig. 5a is a timing chart schematically showing the operation of the pixel driving circuit shown in Fig. 3a.
  • Fig. 5b is a timing chart schematically showing the operation of the pixel driving circuit shown in Fig. 4a. Description will be made below in conjunction with these drawings.
  • the signal input module 20 may include a first switching transistor M1.
  • the control electrode of the first switching transistor M1 and its first pole are both connected to the reset signal terminal Reset.
  • the second pole of the first switching transistor M1 is connected to the gate of the initialization transistor M0.
  • the first switching transistor M1 may be a P-type transistor; or, as shown in FIG. 3b and FIG. 4a, the first switching transistor M1 may also be an N-type transistor. .
  • a reset signal provided by the reset signal terminal is supplied to the gate of the initialization transistor.
  • the reset signal Reset is logic low
  • the P-type transistor M1 is turned on
  • the reset signal Reset is supplied to the control electrode of the initialization transistor M0
  • the reset signal Reset is logic high
  • P The transistor M1 is turned off.
  • the first switching transistor can be formed on the base substrate by a multi-pass lithography process.
  • the active layer of the first switching transistor can be formed of polysilicon (eg, high resistance polysilicon).
  • the leakage suppression module 30 may specifically include: a first capacitor C1. As shown in the figure, the first end of the first capacitor C1 may be connected to the leakage control signal terminal CK to receive a leakage control signal (also indicated by CK), and the second terminal may be connected to the control electrode of the initialization transistor M0.
  • the leakage control signal CK may include a pulse signal.
  • the pulse signal may include a high level period and a low level period in one pulse period.
  • the leakage suppression module is configured to: charge the leakage suppression module by a high level period of the pulse signal, and discharge the leakage suppression module by a low level period of the pulse signal.
  • the reset signal at the reset signal terminal is active low (e.g., logic low).
  • the low potential reset signal causes transistor M1 to be turned on, thereby causing a low potential reset signal to be supplied to the gate of initialization transistor M0.
  • the initialization transistor M0 is in an on state under the control of the reset signal (low potential).
  • the leakage control signal can be set to have two or more pulses. For example, if the voltage at the leakage control signal terminal is at a high potential (for example, logic high) and the voltage at the reset signal terminal is at a high potential, the leakage control signal can be set to have a pulse greater than or equal to 2, as shown in FIG. Shown in 5a.
  • the leakage control signal can also be set to have one or more pulses. For example, if the voltage at which the leakage control signal of the leakage control signal terminal is at a high potential is greater than the voltage at which the reset signal terminal is at a high potential, the leakage control signal can be set to have a pulse greater than or equal to one.
  • the direction and magnitude of the voltage when the signal of the leakage control signal is high can be designed according to the requirements of practical applications. Incidentally, although an embodiment in which a high potential is used as a logic high and a low potential is used as a logic low is described as an example, the reverse may be used. It is also possible to use a high potential as a logic low and a low potential as a logic high. The opposite logic is to design.
  • the reset signal at the reset signal terminal is active high.
  • the high potential reset signal causes transistor M1 to be turned on, thereby causing a high potential reset signal to be supplied to the gate of initialization transistor M0.
  • the initialization transistor is in an on state under the control of the high potential signal at the reset signal terminal.
  • the leakage control signal can be set to have two or more pulses. For example, when the voltage at the time when the signal of the leakage control signal is low is equal to the voltage when the signal at the reset signal is low, the number of pulses of the signal at the leakage control signal end can be set to be greater than or equal to 2, as shown in FIG. 5b. .
  • the number of pulses of the signal at the leakage control signal terminal can be set to be greater than or equal to one.
  • the signal at the leakage control signal terminal can be designed according to the actual application.
  • the first capacitor is charged or discharged under the control of a signal at the leakage control signal terminal (ie, a leakage control signal).
  • a leakage control signal ie, a leakage control signal
  • two pulse signals are provided in the leakage control signal.
  • discharge is performed (in the low-level period of the pulse signal P1), And the first capacitor is charged the next time the discharge is not completed. Since the discharge of the first capacitor is not complete after the first charge, the first capacitor has a certain voltage (or voltage difference) ⁇ V at the end of the low-level period of the first pulse P1 of the CK signal.
  • the first capacitor may employ a CST structure.
  • the CST structure includes three conductive layers and a dielectric layer between each adjacent two conductive layers, that is, a structure obtained by connecting two capacitors in series. In this way, the capacitance of the first capacitor is larger and the occupied area is smaller.
  • the CST structure may employ a CST structure known in the art or developed in the future. It will not be described in detail here.
  • the data writing module 11 may specifically include: a second switching transistor M2.
  • the control electrode of the second switching transistor M2 is connected to the scanning signal terminal Scan, the first pole of the second switching transistor M2 is connected to the data signal terminal Data, and the second pole of the second switching transistor M2 is connected to the first node A.
  • the second switching transistor M2 may be a P-type transistor; or, as shown in FIG. 3b and FIG. 4a, the second switching transistor M2 may also be an N-type transistor. .
  • the second switching transistor may be in an on state under the control of the scan signal of the scan signal terminal, and provide a data signal (also indicated by Data) of the data signal terminal to the first node A.
  • the reset module 12 may specifically include: a third switching transistor M3.
  • the control electrode of the third switching transistor M3 is connected to the reset signal terminal Reset, the first pole of the third switching transistor M2 is connected to the reference signal terminal VREF, and the second pole of the third switching transistor M3 is connected to the first node A.
  • the third switching transistor M3 may be a P-type transistor; or, as shown in FIG. 3b and FIG. 4a, the third switching transistor M3 may also be an N-type transistor. .
  • the third switching transistor may be in an on state under the control of the reset signal of the reset signal terminal, and provide a signal of the reference signal terminal to the first node.
  • the compensation control module 13 may specifically include: a fourth switching transistor M4.
  • the control electrode of the fourth switching transistor M4 is connected to the scanning signal terminal Scan, the first electrode of the fourth switching transistor M4 is connected to the control electrode m0 of the driving transistor DTFT, the second electrode of the fourth switching transistor M4 is connected to the second electrode of the driving transistor DTFT.
  • the poles are connected by m2.
  • the fourth switching transistor M4 may be a P-type transistor; or, as shown in FIG. 3b and FIG. 4a, the fourth switching transistor M4 may also be an N-type transistor. .
  • the fourth switching transistor may be in an on state under the control of the scan signal of the scan signal terminal to electrically connect the control electrode of the driving transistor with the second electrode of the driving transistor.
  • the driving transistor is in a diode-connected state, so that the signal of the first power supply terminal (for example, the power supply voltage) charges the control electrode of the driving transistor (or the node to which the control electrode is connected).
  • the illumination control module 15 may specifically include: a fifth switching transistor M5 and a sixth switching transistor M6.
  • the control electrode of the fifth switching transistor M5 is connected to the light emission control signal terminal EM
  • the first electrode of the fifth switching transistor M5 is connected to the reference signal terminal VREF
  • the second electrode of the fifth switching transistor M5 is connected to the first node A.
  • the control electrode of the sixth switching transistor M6 is connected to the light emission control signal terminal EM
  • the first electrode of the sixth switching transistor M6 is connected to the second electrode m2 of the driving transistor DTFT
  • the second electrode of the sixth switching transistor M6 is connected to the light emitting device L. The first end is connected.
  • the fifth switching transistor M5 and the sixth switching transistor M6 may be P-type transistors; or, as shown in FIG. 3b and FIG. 4a, the fifth switching transistor M5
  • the sixth switching transistor M6 may also be an N-type transistor.
  • the fifth switching transistor may be in an on state under the control of the illumination control signal of the illumination control signal end to electrically connect the reference signal end with the first node, thereby using the reference signal (VREF) of the reference signal end.
  • VREF reference signal
  • the sixth switching transistor When the sixth switching transistor is in an on state under the control of the illumination control signal, the second end of the driving transistor and the first end of the light emitting device may be electrically connected to provide a current of the second pole of the driving transistor to the light emitting device, To drive the light emitting device to emit light.
  • the storage module 14 may specifically include: a second capacitor C2.
  • the first end of the second capacitor C2 is connected to the first node A, and the second end is connected to the control electrode m0 of the driving transistor M0.
  • the second capacitor is charged or discharged under the control of a signal (or potential) at the first node and a signal (or potential) of the gate of the drive transistor.
  • the second capacitor can keep the voltage difference between the first node and the control electrode of the driving transistor stable when the control electrode of the driving transistor is in the floating state.
  • the second capacitor may employ a CST structure. This allows the second capacitor to occupy a smaller area.
  • the CST structure can adopt the CST structure in the prior art, and details are not described herein.
  • each module in the pixel driving circuit provided by some embodiments of the present disclosure.
  • the specific structure of each module is not limited to the above structure provided in the disclosure, and other types known to those skilled in the art may also be used. structure.
  • all of the switching transistors in one or more of the above modules or components may be P-type transistors.
  • all of the switching transistors in one or more of the above modules or components may be N-type transistors. It should be understood that the configurations shown in the figures are merely exemplary and that the type of transistor can be set or selected as desired.
  • the driving transistor DTFT when the driving transistor DTFT is a P-type transistor, all of the switching transistors in one or more of the above modules or components may be provided as P-type transistors.
  • the driving transistor DTFT when the driving transistor DTFT is an N-type transistor, all of the switching transistors in one or more of the above modules or components may be provided as N-type transistors.
  • the processes of the respective switching transistors in the pixel driving circuit can be unified, simplifying the fabrication process.
  • the P-type transistor is configured to be turned off under a high potential and turned on at a low potential; the N-type transistor is configured to be turned on under a high potential and turned off at a low potential. It should be understood that the present disclosure is not limited thereto.
  • the driving transistor, the initialization transistor, and each of the switching transistors may be thin film transistors (TFTs).
  • the driving transistor, the initialization transistor, and each of the switching transistors may be a metal oxide semiconductor field effect transistor (MOS, Metal Oxide Scmiconductor).
  • MOS Metal Oxide Scmiconductor
  • MOS transistor its control is extremely gated, its first pole can be its source or drain, and its second pole can be a drain or source.
  • MOS transistors MOS transistors
  • a high level is indicated by a logic 1 and a low level is indicated by a logic 0.
  • 1 and 0 are logic levels, which are only for better explaining the working process of some embodiments of the present disclosure, and do not represent the specific potential applied to the gates of the respective switching transistors.
  • FIG. 3a illustrates a detailed structural diagram of a pixel driving circuit in accordance with some embodiments of the present disclosure.
  • Fig. 5a is a timing chart schematically showing the operation of the pixel driving circuit shown in Fig. 3a.
  • one operation cycle of the pixel driving circuit may include, for example, but not limited to, three stages of an initialization phase T1, a data writing phase T2, and an emission phase T3.
  • Vg(M0) represents the gate voltage of the initialization transistor M0.
  • the driving transistor and each switching transistor are implemented with PMOS transistors.
  • the high-voltage voltage V ck of the leakage control signal terminal CK is equal to the high-potential voltage of the reset signal terminal Reset.
  • the reset signal Reset 0
  • the scan signal Scan 1
  • the light emission control signal EM 1
  • the leakage control signal CK 0.
  • the turned-on first switching transistor M1 supplies a low potential signal (reset signal) of the reset signal terminal Reset to the gate of the initialization transistor M0 to turn on the initialization transistor M0.
  • the signal of the initialization signal terminal Vinit (initialization signal Vinit) is supplied to the gate of the driving transistor DTFT to initialize the gate voltage of the driving transistor DTFT, and thus the gate voltage of the driving transistor DTFT is V init .
  • the driving transistor DTFT can be in an on state. However, since the sixth switching transistor M6 is turned off, the light-emitting device L does not emit light.
  • the turned-on third switching transistor M3 supplies the signal (voltage V ref ) of the reference signal terminal VREF to the first node A, so that the voltage of the first node A is V ref . Since the gate voltage of the driving transistor DTFT changes to V init , the voltage of the second terminal of the second capacitor C2 (which is connected to the gate of the driving transistor DTFT) is discharged from the voltage of the light emitting phase in the previous display frame to V init , It is prepared to write the signal of the data signal terminal Data.
  • the turned-on second switching transistor M2 supplies the data signal of the data signal terminal Data to the first node A. Therefore, the voltage of the first node A is V data and the second capacitor C2 is charged.
  • the turned-on fourth switching transistor M4 can electrically connect the gate m0 of the driving transistor DTFT and the drain m2 of the driving transistor DTFT, thereby causing the driving transistor DTFT to form a diode-connected state.
  • the first power supply terminal VDD charges the gate m0 of the driving transistor DTFT through the driving transistor DTFT until the voltage of the gate m0 of the driving transistor DTFT is V dd +
  • the signal of the leakage control signal terminal CK includes two pulses in the data writing phase T2.
  • the duty ratio in each pulse period is set to be greater than 50%. That is, here, in each pulse period, the duration of the low level period for discharging is smaller than the high level period for charging.
  • the leakage control signal CK charges the first capacitor C1, causing the voltage difference between the two capacitors C1 to become a high potential V ck , thereby causing the gate of the initialization transistor M0 to be high. The potential is turned off. Then, during the low period of the first pulse P1, the first capacitor C1 is discharged. Since the duty ratio is greater than 50% in each pulse period, the first capacitor C1 is not completely discharged during the low period of the first pulse P1, that is, when the first capacitor C1 also has the voltage ⁇ V, it enters the lower One pulse period, thereby charging the first capacitor C1 again.
  • the second pulse (P2) period of the signal of the leakage control signal terminal CK the charging and discharging process of the first capacitor C1 is repeated again.
  • the voltage of the gate m0 of the driving transistor DTFT becomes: V ref +V dd +
  • the operating current I flowing through the driving transistor DTFT and for driving the connected light-emitting device L to emit light satisfies the formula:
  • V gs is the gate-source voltage of the driving transistor DTFT
  • K is a structural parameter, and the value is relatively stable in the same structure, and can be regarded as a constant.
  • the voltage of the drain of the initialization transistor is the gate voltage of the drive transistor.
  • the gate voltage of the initialization transistor in the prior art is only the high voltage of the reset signal terminal ( Compared with V ck )
  • the voltage difference between the gate of the initialization transistor and its drain can be increased, thereby further increasing the off state of the initialization transistor, further avoiding the leakage current of the initialization transistor, thereby avoiding formation by initializing the transistor. Leakage current path, improve the brightness of the light-emitting device and improve flicker.
  • the first capacitor C1 may be completed or may not be completed, which needs to be determined according to the actual application environment.
  • the gate voltage of the initialization transistor is shown to become V ck +2 ⁇ V in the light-emitting phase in which the light-emitting device is driven to emit light
  • the present disclosure is not limited thereto.
  • the second pulse of the CK signal shown in Figure 5a may be omitted in some embodiments, and instead a high potential is applied continuously.
  • the gate voltage of the initialization transistor may be changed to V ck +2 ⁇ V at the stage before the light-emitting phase or the light-emitting phase.
  • the driving transistor is current at saturation is only related to the voltage V data voltage V ref and the data signal terminal a reference signal side, with the drive transistor threshold voltage V th and the first power source The voltage at the terminal is independent of V dd .
  • the threshold voltage V th drift due to the process process of the driving transistor and the long-time operation, and the influence of the IR drop on the current flowing through the light emitting device can be solved, thereby causing the light to be emitted.
  • the operating current of the device L remains stable, thereby ensuring the normal operation of the light-emitting device L.
  • FIG. 4a illustrates a detailed structural diagram of a pixel driving circuit according to further embodiments of the present disclosure.
  • Fig. 5b is a timing chart schematically showing the operation of the pixel driving circuit shown in Fig. 4a.
  • Fig. 5b shows three stages of the initialization phase T1, the data writing phase T2, and the lighting phase T3.
  • Vg(M0) in Fig. 5b represents the gate voltage of the initialization transistor M0.
  • the driving transistor and each switching transistor are implemented with NMOS transistors.
  • the voltage V ck of the low potential of the leakage control signal terminal CK is equal to the low potential voltage of the reset signal terminal Reset as an example.
  • the turned-on first switching transistor M1 supplies the high-potential signal of the reset signal terminal Reset to the gate of the initialization transistor M0, turns on the initialization transistor M0, and supplies the signal of the initialization signal terminal Vinit to the gate of the driving transistor DTFT to The gate voltage of the driving transistor DTFT is initialized. Therefore, the gate voltage of the driving transistor DTFT is V init .
  • the driving transistor DTFT can be in an on state. However, since the sixth switching transistor M6 is turned off, the light-emitting device L does not emit light.
  • the turned-on third switching transistor M3 supplies the voltage V ref of the signal of the reference signal terminal VREF to the first node A, so that the voltage of the first node A is V ref . Since the gate voltage of the driving transistor DTFT changes to V init , the voltage of the second terminal of the second capacitor C2 (which is connected to the gate of the driving transistor DTFT) is discharged from the voltage of the light emitting phase in the previous display frame to V init , It is prepared to write the signal of the data signal terminal Data.
  • the turned-on second switching transistor M2 supplies the signal of the data signal terminal Data to the first node A, so that the voltage of the first node A is V data and the second capacitor C2 is charged.
  • the turned-on fourth switching transistor M4 can turn on the gate m0 of the driving transistor DTFT and the source m2 of the driving transistor DTFT to form a diode-connected state of the driving transistor DTFT.
  • the signal of the leakage control signal terminal CK includes two pulses in the data writing phase T2 as shown in Fig. 5b.
  • the duty ratio in each pulse period is set to be less than 50%. That is, here, in each pulse period, the duration of the low level period for discharging is greater than the high level period for charging.
  • the leakage control signal terminal CK discharges to the first capacitor C1 to V ck , so that the voltage difference between the two capacitors C1 is a low potential V ck , thereby The gate of the control initialization transistor M0 is controlled to be low to keep it off. Then, during the high level period, the first capacitor C1 is charged. Since the duty ratio in each pulse period is less than 50%, the first capacitor C1 is not fully charged during the high period of the first pulse P1, that is, the first capacitor C1 also stores the voltage ⁇ V (relative to the CK signal). The high level, which is a negative value, enters the next pulse period, thereby discharging the first capacitor C1 again.
  • the second pulse (P2) period of the signal of the leakage control signal terminal CK the discharge and charging process of the first capacitor C1 is repeated again.
  • the turned-on fifth switching transistor M5 can electrically connect the reference signal terminal VREF with the first node A, and supply the voltage V ref of the signal of the reference signal terminal VREF to the first node A, so that the voltage of the first node A is V ref . Since the transistor M0 is turned off, the gate m0 of the driving transistor DTFT is in a floating state.
  • ) 2 K[V ref +V dd +
  • ] 2 K[V ref -V data ] 2 ;
  • V gd is the gate drain voltage of the driving transistor DTFT;
  • K is a structural parameter, in the same structure This value is relatively stable and can be counted as a constant.
  • the voltage of the drain of the initialization transistor is the gate voltage of the drive transistor.
  • the gate voltage of the initialization transistor in the prior art is only the high voltage V of the reset signal terminal.
  • the voltage difference between the gate of the initialization transistor and its drain can be reduced, so that the N-type initialization transistor is further turned off, further avoiding the leakage current of the initialization transistor, thereby avoiding formation by initializing the transistor. Leakage current path, improve the brightness of the light-emitting device and improve flicker.
  • the driving transistor is current at saturation is only related to the voltage V data voltage V ref and the data signal terminal a reference signal side, with the drive transistor threshold voltage V th and the first power source The voltage at the terminal is independent of V dd . According to an embodiment of the present disclosure, it is possible to solve the drift of the threshold voltage Vth due to the process process of the driving transistor and the operation for a long time, and the influence of the IR voltage drop on the current flowing through the light emitting device, thereby maintaining the operating current of the light emitting device L Stable, and thus ensure the normal operation of the light-emitting device L.
  • the first capacitor C1 may or may not be fully charged, which may be set according to the actual application.
  • the gate voltage of the initialization transistor is shown to become V ck +2 ⁇ V in the light-emitting phase in which the light-emitting device is driven to emit light
  • the present disclosure is not limited thereto.
  • the second pulse of the CK signal shown in Figure 5b may be omitted in some embodiments, and instead a low potential is applied continuously.
  • the gate voltage of the initialization transistor may be changed to V ck +2 ⁇ V at the stage before the light-emitting phase or the light-emitting phase.
  • control electrode of the first switching transistor is connected to its second electrode to form a diode connection state.
  • the first switching transistor is turned on only during the initialization phase, and in the light emitting phase, the first switching transistor is turned off.
  • the gate voltage of the initialization transistor can be controlled only by the first capacitance and the leakage control signal.
  • Some embodiments of the present disclosure also provide an operation method for any of the pixel driving circuits as illustrated in the accompanying drawings and described above, as shown in FIG. 6, including: an initialization phase, a data writing phase, and illumination Stage;
  • the signal input module supplies the signal of the reset signal end to the control electrode of the initialization transistor under the control of the reset signal end;
  • the reset module provides the signal of the reference signal end to the first node under the control of the reset signal end;
  • the storage module is The signal of the first node is discharged under the control of the signal of the gate of the driving transistor.
  • the data writing module provides the signal of the data signal end to the first node under the control of the scanning signal end; the compensation control module turns on the control electrode of the driving transistor and the driving transistor under the control of the scanning signal end. The two poles; the memory module is charged under the control of the signal of the first node and the signal of the gate of the driving transistor.
  • the leakage suppression module increases the voltage difference between the control electrode of the initialization transistor and the second electrode of the initialization transistor under the control of the leakage control signal end; and the illuminating control module conducts the reference under the control of the illuminating control signal end.
  • Some embodiments of the present disclosure also provide a method of operation for a pixel driving circuit, as shown in FIG.
  • the method may include, during a data writing phase: configuring the reset signal to turn off the signal input module (step S101); charging the leakage suppression module by the leakage control signal to turn off the initialization transistor (step S103) And the voltage difference between the control electrode of the initialization transistor and the second electrode of the initialization transistor is changed by the leakage suppression module under the control of the leakage control signal (step S105).
  • the method may further include: in the illuminating phase: maintaining the signal input module to be turned off by the reset signal (step S107); maintaining charging of the leakage suppression module by the leakage control signal to further cut off the initialization transistor (Step S109); and driving the light emitting device to emit light by the driving transistor (Step S111).
  • the initialization transistor is formed of an N-type transistor, and wherein the changing can include: reducing a voltage difference between a control electrode of the initialization transistor and a second electrode of the initialization transistor ( Step S1051).
  • the leakage control signal includes a pulse signal including a high level period and a low level period in each pulse period of the pulse signal.
  • reducing the voltage difference may include: charging a leakage suppression module by a high level period of the pulse signal, and discharging the leakage suppression module by a low level period of the pulse signal Wherein in the pulse period of the pulse signal, the duration of the low level period for discharging is less than the high level period for charging.
  • the initialization transistor is formed of a P-type transistor, and wherein the changing may include increasing a voltage difference between a control electrode of the initialization transistor and a second electrode of the initialization transistor ( Step S1052).
  • the leakage control signal includes a pulse signal including a high level period and a low level period in each pulse period of the pulse signal.
  • the increasing the voltage difference comprises: charging a leakage suppression module by a high level period of the pulse signal, and discharging the leakage suppression module by a low level period of the pulse signal Wherein in the pulse period, the duration of the low level period for discharging is greater than the high level period for charging.
  • the pixel compensation circuit further includes a data writing module, a reset module, a compensation control module, a storage module, and an illumination control module.
  • the data writing module is respectively connected to the data signal end, the scan signal end and the first node;
  • the reset module is respectively connected to the reset signal end, the reference signal end and the first node;
  • the compensation control module respectively Connected to the scan signal terminal, the control electrode of the driving transistor, and the second electrode of the driving transistor;
  • the memory module is respectively connected to the first node and the control electrode of the driving transistor;
  • the illumination control The module is respectively connected to the light emission control signal end, the reference signal end, the first node, the second pole of the driving transistor, and the first end of the light emitting device.
  • the first pole of the driving transistor is connected to the first power terminal.
  • the method further includes, as shown in FIG. 8a, in an initialization phase: providing the reset signal to the control electrode of the initialization transistor by the signal input module under the control of the reset signal (step S201);
  • the reset module provides a reference signal provided at the reference signal end to the first node under control of the reset signal (step S203); and a signal at the first node and the driving transistor
  • the memory module is discharged under the control of the signal of the gate (step S205).
  • the method may further include, as shown in FIG. 8b, in a data writing phase: providing, by the data writing module, a data signal to the first node under control of a scan signal (step S207);
  • the compensation control module electrically connects the gate electrode of the driving transistor and the second electrode of the driving transistor under the control of the scan signal (step S209); and the signal at the first node and the driving transistor
  • the memory module is charged under the control of the signal at the gate (step S211).
  • the initialization signal may be an initialization signal
  • the reset signal may be a reset signal
  • the third signal may be a leakage control signal
  • the compensation effect of the threshold voltage of the driving transistor can be realized, and the initialization transistor can be prevented from forming a leakage current path, so that the brightness of the light emitting device can be improved, and the flicker phenomenon during display can be improved.
  • Some embodiments of the present disclosure also provide a display panel including: a light emitting device, and a pixel driving circuit for driving the light emitting device according to any of the embodiments of the present disclosure.
  • the display panel may include an organic light emitting display panel.
  • Some embodiments of the present disclosure also contemplate a display device including: a light emitting device, and a pixel driving circuit for driving the light emitting device according to any of the embodiments of the present disclosure.
  • the above display panel can also be considered as a display device.
  • the display device may include, but is not limited to, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like, or any product or component having a display function.
  • the initialization transistor it is possible to prevent the initialization transistor from forming a leakage current path, thereby improving the luminance of the light emitting device and improving the flicker phenomenon during display.
  • modules mentioned in the present disclosure may be implemented in a circuit (or sub-circuit). Accordingly, various modules of the present disclosure may also be referred to as circuits or sub-circuits.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

提供了一种像素驱动电路，包括：像素补偿电路，包括驱动晶体管与初始化晶体管，所述驱动晶体管用于驱动像素中的发光器件，所述初始化晶体管的第一极与初始化信号端相连以接收初始化信号，所述初始化晶体管的第二极与所述驱动晶体管的控制极相连；信号输入子电路，连接在所述复位信号端与所述初始化晶体管的控制极之间，所述信号输入子电路用于在从所述复位信号端接收的复位信号的控制下选择性地将复位信号提供到所述初始化晶体管的控制极；漏电抑制子电路，分别与漏电控制信号端以及所述初始化晶体管的控制极相连，所述漏电抑制子电路被配置为：通过从所述漏电控制信号端接收的漏电控制信号对漏电抑制子电路进行充电或放电，并通过所述充电或放电使得所述初始化晶体管截止。

Description

像素驱动电路及其操作方法以及显示面板
相关申请的交叉引用
本申请要求于2017年4月17日递交的中国专利申请No.201710249921.5的优先权，并通过引用将其全文并入在此。
技术领域
本公开涉及显示技术领域，特别涉及像素驱动电路、操作方法及显示面板。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)是当今平板显示器研究领域的热点之一。与液晶显示器(Liquid Crystal Display，LCD)相比，OLED显示器具有低能耗、生产成本低、自发光、宽视角及响应速度快等优点。目前，在手机、平板电脑、数码相机等显示领域，OLED显示器已经开始取代传统的LCD显示器。但是与LCD利用稳定的电压控制亮度不同，OLED属于电流驱动，需要稳定的电流来控制其发光。由于工艺制程和器件老化等原因，OLED显示器中一般采用具有补偿驱动晶体管的阈值电压V th功能的像素补偿电路作为驱动电路来驱动OLED发光。
目前，像素补偿电路中通常还设置有初始化晶体管，其接收初始化信号，并在驱动晶体管驱动OLED发光完成后的阶段，将初始化信号提供给驱动晶体管的栅极，对驱动晶体管的栅极电压进行初始化。而在像素补偿电路的操作的其余阶段，初始化晶体管均为截止状态。尤其是，在驱动晶体管驱动OLED发光的发光阶段，初始化晶体管要保证截止状态。初始化晶体管一般采用开关晶体管作实现开关功能。然而，开关晶体管可能不能保证无损耗导通或者完全截止，因此在开关晶体管可能会形成泄露电流通路，导致部分用于OLED发光的电流通过初始化晶体管流到初始化信号通路中，从而影响OLED的发光亮度，进而造成闪烁现象。
发明内容
本公开的一些实施例提供了像素驱动电路、其操作方法及显示面板。根据本公开的额实施例，可以避免通过初始化晶体管形成泄露电流通路，提高OLED的发光亮度，改善或消 除了显示时的闪烁现象。
根据本公开一个方面，提供了一种像素驱动电路，包括：像素补偿电路，所述像素补偿电路包括驱动晶体管与初始化晶体管，所述驱动晶体管用于驱动像素中的发光器件，所述初始化晶体管的第一极与初始化信号端相连以接收初始化信号，所述初始化晶体管的第二极与所述驱动晶体管的控制极相连；信号输入子电路，其中，所述信号输入子电路连接在所述复位信号端与所述初始化晶体管的控制极之间，所述信号输入子电路用于在从所述复位信号端接收的复位信号的控制下选择性地将复位信号提供到所述初始化晶体管的控制极；漏电抑制子电路，所述漏电抑制子电路分别与漏电控制信号端以及所述初始化晶体管的控制极相连，所述漏电抑制子电路被配置为：通过从所述漏电控制信号端接收的漏电控制信号对漏电抑制子电路进行充电或放电，并通过所述充电或放电使得所述初始化晶体管截止。
在一个实施例中，所述漏电抑制子电路还被配置用于：在所述漏电控制信号的控制下，使所述初始化晶体管的控制极与所述初始化晶体管的第二极之间的电压差改变，以使得所述初始化晶体管进一步截止。
在一个实施例中，所述初始化晶体管为N型晶体管，并且其中，所述改变包括：使所述初始化晶体管的控制极与所述初始化晶体管的第二极之间的电压差减小。
在一个实施例中，所述初始化晶体管为P型晶体管，并且其中，所述改变包括：使所述初始化晶体管的控制极与所述初始化晶体管的第二极之间的电压差增加。
在一个实施例中，所述漏电控制信号包括脉冲信号，在所述脉冲信号的每个脉冲周期中包括高电平时段和低电平时段；并且其中，所述漏电抑制子电路被配置用于：通过所述脉冲信号的高电平时段对漏电抑制子电路进行充电，以及通过所述脉冲信号的低电平时段对漏电抑制子电路进行放电，其中在所述脉冲周期中，用于放电的低电平时段的时长小于用于充电的高电平时段。
在一个实施例中，所述漏电控制信号包括脉冲信号，在所述脉冲信号的每个脉冲周期中包括高电平时段和低电平时段；并且
其中，所述漏电抑制子电路被配置用于：
通过所述脉冲信号的高电平时段对漏电抑制子电路进行充电，以及
通过所述脉冲信号的低电平时段对漏电抑制子电路进行放电，
其中在所述脉冲周期中，用于放电的低电平时段的时长大于用于充电的高电平时 段。
在一个实施例中，所述信号输入子电路包括：第一开关晶体管，其中，
所述第一开关晶体管的控制极及其第一极均与所述复位信号端相连，所述第一开关晶体管的第二极与所述初始化晶体管的控制极相连。
在一个实施例中，所述第一开关晶体管的有源层包括多晶硅。
在一个实施例中，所述漏电抑制子电路包括：第一电容；其中，
所述第一电容的第一端与所述漏电控制信号端相连，第二端与所述初始化晶体管的控制极相连。
在一个实施例中，所述像素补偿电路还包括数据写入子电路、复位子电路、补偿控制子电路、存储子电路以及发光控制子电路；
其中，所述驱动晶体管的第一极与第一电源端相连；
其中，所述数据写入子电路分别与数据信号端、扫描信号端以及第一节点相连，用于在所述扫描信号端处提供的扫描信号的控制下将所述数据信号端处提供的数据信号提供给所述第一节点；
其中，所述复位子电路分别与所述复位信号端、参考信号端以及所述第一节点相连，用于在所述复位信号的控制下将所述参考信号端处提供的参考信号提供给所述第一节点；
其中，所述补偿控制子电路分别与所述扫描信号端、所述驱动晶体管的控制极以及所述驱动晶体管的第二极相连，用于在所述扫描信号的控制下将所述驱动晶体管的控制极与所述驱动晶体管的第二极电连接；
其中，所述存储子电路分别与所述第一节点以及所述驱动晶体管的控制极相连，用于在所述第一节点的信号和所述驱动晶体管的控制极的信号的控制下充电或放电，以及在所述驱动晶体管的控制极处于浮接状态时，保持所述第一节点与所述驱动晶体管的控制极之间的电压差稳定；
其中，所述发光控制子电路分别与发光控制信号端、所述参考信号端、所述第一节点、所述驱动晶体管的第二极以及所述发光器件的第一端相连，所述发光控制子电路用于在所述发光控制信号端处提供的发光控制信号的控制下电连接所述参考信号端与所述第一节点，以及电连接所述驱动晶体管的第二极和所述发光器件的第一端，从而使得所述驱动晶体管能够驱动发光器件发光。
在一个实施例中，所述数据写入子电路包括：第二开关晶体管；其中，所述第二开关 晶体管的控制极与所述扫描信号端相连，所述第二开关晶体管的第一极与所述数据信号端相连，所述第二开关晶体管的第二极与所述第一节点相连；
其中，所述复位子电路包括：第三开关晶体管；其中，所述第三开关晶体管的控制极与所述复位信号端相连，所述第三开关晶体管的第一极与所述参考信号端相连，所述第三开关晶体管的第二极与所述第一节点相连；
其中，所述补偿控制子电路包括：第四开关晶体管；其中，所述第四开关晶体管的控制极与所述扫描信号端相连，所述第四开关晶体管的第一极与所述驱动晶体管的控制极相连，所述第四开关晶体管的第二极与所述驱动晶体管的第二极相连；
其中，所述存储子电路包括：第二电容，其中，所述第二电容的第一端与所述第一节点相连，第二端与所述驱动晶体管的控制极相连；
其中，所述发光控制子电路包括：第五开关晶体管与第六开关晶体管；其中，所述第五开关晶体管的控制极与所述发光控制信号端相连，所述第五开关晶体管的第一极与所述参考信号端相连，所述第五开关晶体管的第二极与所述第一节点相连；所述第六开关晶体管的控制极与所述发光控制信号端相连，所述第六开关晶体管的第一极与所述驱动晶体管的第二极相连，所述第六开关晶体管的第二极与所述发光器件的第一端相连。
在一个实施例中，在所述驱动晶体管为P型晶体管的情况下，所述数据写入子电路、复位子电路、补偿控制子电路、存储子电路以及发光控制子电路中的一个或多个中的所有开关晶体管均由P型晶体管形成。
在一个实施例中，在所述驱动晶体管为N型晶体管的情况下，所述数据写入子电路、复位子电路、补偿控制子电路、存储子电路以及发光控制子电路中的一个或多个中的所有开关晶体管均由N型晶体管形成。
根据本公开另一方面，提供了一种显示装置，包括：发光器件，以及根据本公开任一实施例所述的像素驱动电路，用于驱动所述发光器件。
根据本公开另一方面，提供了一种用于如权利要求1所述的像素驱动电路的操作方法，所述方法包括：
在数据写入阶段，
配置所述复位信号以使所述信号输入子电路关断，
通过所述漏电控制信号对漏电抑制子电路充电，以使所述初始化晶体管截止，以及
通过所述漏电抑制子电路在所述漏电控制信号的控制下，使所述初始化晶体管的控制极与所述初始化晶体管的第二极之间的电压差发生改变；以及在发光阶段，
通过所述复位信号保持所述信号输入子电路关断，
通过所述漏电控制信号保持对漏电抑制子电路充电，以使所述初始化晶体管进一步截止；
通过所述驱动晶体管驱动发光器件发光。
在一个实施例中，所述初始化晶体管为N型晶体管，并且
其中，所述改变包括：使所述初始化晶体管的控制极与所述初始化晶体管的第二极之间的电压差减小。
在一个实施例中，所述初始化晶体管为P型晶体管，并且
其中，所述改变包括：使所述初始化晶体管的控制极与所述初始化晶体管的第二极之间的电压差增加。
在一个实施例中，所述漏电控制信号包括脉冲信号，在所述脉冲信号的每个脉冲周期中包括高电平时段和低电平时段；并且
其中，使所述电压差减小包括：
通过所述脉冲信号的高电平时段对漏电抑制子电路进行充电，以及
通过所述脉冲信号的低电平时段对漏电抑制子电路进行放电，
其中在所述脉冲周期中，用于放电的低电平时段的时长小于用于充电的高电平时段。
在一个实施例中，所述漏电控制信号包括脉冲信号，在所述脉冲信号的每个脉冲周期中包括高电平时段和低电平时段；并且
其中，使所述电压差增加包括：
通过所述脉冲信号的高电平时段对漏电抑制子电路进行充电，以及
通过所述脉冲信号的低电平时段对漏电抑制子电路进行放电，
其中在所述脉冲周期中，用于放电的低电平时段的时长大于用于充电的高电平时段。
在一个实施例中，所述像素补偿电路还包括数据写入子电路、复位子电路、补偿控制子电路、存储子电路以及发光控制子电路；并且
其中，所述驱动晶体管的第一极与第一电源端相连；所述数据写入子电路分别与数据信号端、扫描信号端以及第一节点相连；所述复位子电路分别与所述复位信号端、参考信号端以及所述第一节点相连；所述补偿控制子电路分别与所述扫描信号端、所述驱动晶体管的控制极以及所述驱动晶体管的第二极相连；所述存储子电路分别与所述第一节点以及所述驱动晶体管的控制极相连；所述发光控制子电路分别与发光控制信号端、所述参考信号端、所述第一节点、所述驱动晶体管的第二极以及所述发光器件的第一端相连，
所述方法还包括：
在初始化阶段，
通过所述信号输入子电路在所述复位信号的控制下将所述复位信号提供给所述初始化晶体管的控制极；
通过所述复位子电路在所述复位信号的控制下将所述参考信号端处提供的参考信号提供给所述第一节点；以及
在所述第一节点处的信号与所述驱动晶体管的控制极的信号的控制下使所述存储子电路进行放电。
在一个实施例中，所述方法还包括：
在数据写入阶段，
通过所述数据写入子电路在扫描信号的控制下将数据信号提供给所述第一节点；
通过所述补偿控制子电路在所述扫描信号的控制下电连接所述驱动晶体管的控制极与所述驱动晶体管的第二极；以及
在所述第一节点处的信号与所述驱动晶体管的控制极处的信号的控制下对所述存储子电路进行充电。
附图说明
图1为根据本公开一些实施例的像素驱动电路的结构示意图；
图2为根据本公开一些实施例的像素驱动电路的结构示意图；
图3a示出了根据本公开一些实施例的像素驱动电路的具体结构示意图；
图3b示出了根据本公开一些实施例的像素驱动电路的具体结构示意图；
图4a示出了根据本公开一些实施例的像素驱动电路的具体结构示意图；
图4b示出了根据本公开一些实施例的像素驱动电路的具体结构示意图；
图5a为示意性地示出图3a所示的像素驱动电路的操作的时序图；
图5b为示意性地示出图4a所示的像素驱动电路的操作的时序图；
图6为根据本公开一些实施例的像素驱动电路的操作方法的流程图；
图7为根据本公开一些实施例的像素驱动电路的操作方法的流程图；
图8a和8b为示出了根据本公开一些实施例的像素驱动电路的操作方法的一些附加步骤的流程图。
具体实施方式
为了使本公开的目的，技术方案和优点更加清楚，下面结合附图，对本公开一些实施例以及具体实施方式进行详细地说明。应当理解，下面所描述的优选实施例仅用于说明和解释本公开，并不用于限定本公开。并且在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。
本公开一些实施例提供了一种像素电路，如图1与图2所示，其可以包括：发光器件L(例如但不限于，OLED)和用于驱动发光器件L的像素驱动电路。在图1和图2中还示出了根据本公开一些实施例的像素驱动电路的结构示意图。图1和图2的主要区别在于所使用的晶体管的类型的不同，因此，下面结合这两个图共同进行说明。
如图1和图2所示，像素驱动电路可以包括像素补偿电路10。像素补偿电路10可以包括驱动晶体管DTFT与初始化晶体管M0。初始化晶体管M0的控制极(例如，栅极)与复位信号端Reset相连。初始化晶体管M0的第一极(例如，源极或漏极)与初始化信号端(第一信号端)Vinit相连。初始化晶体管M0的第二极(例如，漏极或源极)与驱动晶体管DTFT的控制极(例如，栅极)m0相连。在图1所示的实施例中，初始化晶体管M0和驱动晶体管DTFT可以利用P型晶体管(例如，P型MOS晶体管)来实现。而在图2所示的实施例中，初始化晶体管M0和驱动晶体管DTFT可以利用N型晶体管(例如，N型MOS晶体管)来实现。
本领域普通技术人员将明了，在利用不同类型的晶体管来实现初始化晶体管M0和驱动晶体管DTFT的情况下，可以适应性地对其余模块、部件或元件等进行调整或改变以实践本公开的原理和实施例。例如，可以相应使用适当类型的晶体管来实现其余模块、部件或元件。还应理解的是，这里将晶体管的不是控制极的电极(例如漏极或源极，也称作非控制极)称为“第一极”或“第二极”，该术语的使用不是限制性的，仅是为了将其与控制极区分开。还应理解，对于MOS晶体管，一般地，其源极和漏极是可以互换的。
如图1和图2所示，像素驱动电路还可以包括：信号输入模块20与漏电抑制模块30。如图1和图2所示，复位信号端(第二信号端)Reset可以通过信号输入模块20与初始化晶体管M0的控制极相连。信号输入模块20可以被配置用于：在复位信号端Reset提供的复位信号(第二信号)的控制下，选择性地将复位信号端Reset处提供的复位信号提供到初始化晶体管M0的控制极。
如图1和图2所示，漏电抑制模块30可以分别与漏电控制信号端(第三信号端)CK以及初始化晶体管M0的控制极相连。漏电抑制模块30的一端可以与漏电控制信号端(第三信号端)CK相连以接收漏电控制信号(第三信号，也以CK来表示)，另一端可以与初始化晶体管M0的控制极相连。漏电抑制模块30可以被配置用于：通过所述漏电控制信号对漏电抑制模块进行充电或放电，并通过所述充电或放电使得所述初始化晶体管截止，下面将进一步说明。
在本公开一些实施例中，如图1与图2所示，像素补偿电路10还可以包括：数据写入模块11、复位模块12、补偿控制模块13、存储模块14以及发光控制模块15。
如图中所示，数据写入模块11可以分别与数据信号端Data、扫描信号端Scan以及第一节点A相连。数据写入模块11可以被配置用于在扫描信号端Scan提供的扫描信号(也以Scan来指示)的控制下将数据信号端Data提供的数据信号提供到第一节点A。复位模块12可以分别与复位信号端Reset、参考信号端VREF以及第一节点A相连。复位模块12可以被配置用于在复位信号(也以Reset表示)的控制下将参考信号端VREF提供的参考信号(也以VREF来指示)提供到第一节点A。
补偿控制模块13可以分别与扫描信号端Scan、驱动晶体管DTFT的控制极m0以及驱动晶体管DTFT的第二极m2相连。补偿控制模块13可以可以被配置用于在扫描信号Scan的控制下电连通驱动晶体管DTFT的控制极m0与驱动晶体管DTFT的第二极m2。这里，如图中所示，驱动晶体管DTFT的第一极m1可以与第一电源端VDD相连。
存储模块14可以分别与第一节点A以及驱动晶体管DTFT的控制极m0相连。存储模块14可以被配置用于在第一节点A的信号与驱动晶体管DTFT的控制极m0的信号的控制下充电或放电。存储模块14可以被配置用于：在驱动晶体管DTFT的控制极m0处于浮接状态时，保持第一节点A与驱动晶体管DTFT的控制极m0之间的电压差稳定。
发光控制模块15可以分别与发光控制信号端EM、参考信号端VREF、第一节点A、驱动晶体管DTFT的第二极m2以及发光器件L的第一端相连。发光器件L的第二端可以与第二 电源端VSS相连。发光控制模块15可以被配置用于在发光控制信号端EM处提供的发光控制信号(也以EM来指示)控制下，电连接参考信号端VREF与第一节点A，以及电连接驱动晶体管DTFT的第二极m2与发光器件L的第一端。从而，驱动晶体管DTFT能够驱动发光器件L发光。
根据本公开实施例的像素驱动电路中，可以实现对驱动晶体管的阈值电压的补偿，以及可以经避免初始化晶体管形成泄露电流通路。从而，可以提高发光器件的亮度，改善显示时的闪烁现象。
在本公开一些实施例提供的上述像素驱动电路中，如图1所示，驱动晶体管DTFT可以由P型晶体管形成。该P型晶体管的栅极为驱动晶体管DTFT的控制极m0，该P型晶体管的源极为驱动晶体管DTFT的第一极m1，该P型晶体管的漏极为驱动晶体管DTFT的第二极m2。此时驱动发光器件L发光的工作电流由P型晶体管的源极流向其漏极。
在其他实施例中，如图2所示，驱动晶体管DTFT可以由N型晶体管形成。该N型晶体管的栅极为驱动晶体管DTFT的控制极m0，该N型晶体管的漏极为驱动晶体管DTFT的第一极m1，该N型晶体管的源极为驱动晶体管DTFT的第二极m2。此时驱动发光器件L发光的工作电流由N型晶体管的漏极流向其源极。
在本公开一些实施例的像素驱动电路中，如图1所示，初始化晶体管M0可以由P型晶体管形成。或者，如图2所示，初始化晶体管M0也可以由N型晶体管形成。
在本公开一些实施例中，所述漏电抑制模块还被配置用于：在所述漏电控制信号(第三信号)的控制下，使所述初始化晶体管的控制极与所述初始化晶体管的第二极之间的电压差改变，以使得所述初始化晶体管进一步截止。
在一些更具体实现方式中，在初始化晶体管由P型晶体管形成的情况下，漏电抑制模块可以被配置用于：在漏电控制信号端的控制下，使初始化晶体管的控制极与初始化晶体管的第二极之间的电压差增加。例如，该电压差一般可以具有大于P型初始化晶体管的阈值Vth(Vth一般可以为0V或小于0V)的值以使P型初始化晶体管截止。因此，在P型初始化晶体管的阈值为大约0V的情况下，所述“电压差的增加”也可以指的是使初始化晶体管的控制极与初始化晶体管的第二极之间的电压差的绝对值增加。随着该电压差的增加，P型初始化晶体管截止的程度也随之增加。
在本公开一些实施例中，发光器件一般可以为有机电致发光二极管。在一些实施例中，可以在驱动晶体管处于饱和工作状态下提供电流来驱动发光器件实现发光。
在本公开一些实施例中，第一电源端的电压可以设置为高于第二电源端的电压。例如，第一电源端的电压V dd一般可以为正值，第二电源端的电压V ss一般可以接地或为负值。在实际应用中，第一电源端的电压V dd与第二电源端的电压V ss需要根据实际应用环境来设计确定，在此不作限定。
在另外一些实现方式中，在初始化晶体管由N型晶体管形成的情况下，漏电抑制模块可以被配置用于：在漏电控制信号端的控制下，使初始化晶体管的控制极与初始化晶体管的第二极之间的电压差减小。例如，该电压差一般可以具有小于N型初始化晶体管的阈值Vth(Vth一般可以为大于0V的值)的值，以使N型初始化晶体管截止。随着该电压差的减小，N型初始化晶体管截止的程度随之增加。
根据本公开一些实施例，可以使初始化晶体管进一步处于截止状态，从而避免初始化晶体管形成泄露电流通路，进而可以提高发光器件的发光亮度，改善显示时的闪烁现象。
下面将结合更具体实施例，对本公开进行详细说明。需要说明的是，本公开中所描述的各实施例或实现方式是说明性的，而不是限制性的。根据在此所公开的内容，本领域普通技术人员可以容易地构思其他的实施例。因此本公开也不限于这里公开的实施例或实现方式。
图3a和3b示出了根据本公开一些实施例的像素驱动电路的具体结构示意图。图4a和4b示出了根据本公开一些实施例的像素驱动电路的具体结构示意图。图5a为示意性地示出图3a所示的像素驱动电路的操作的时序图。图5b为示意性地示出图4a所示的像素驱动电路的操作的时序图。下面将结合这些附图进行说明。
在本公开一些实施例中，如图中所示，信号输入模块20可以包括第一开关晶体管M1。第一开关晶体管M1的控制极以及其第一极均与复位信号端Reset相连。第一开关晶体管M1的第二极与初始化晶体管M0的控制极相连。
在本公开一些实施例中，如图3a与图4b所示，第一开关晶体管M1可以为P型晶体管；或者，如图3b与图4a所示，第一开关晶体管M1也可以为N型晶体管。
在本公开一些实施例中，当第一开关晶体管在复位信号的控制下处于导通状态时，复位信号端提供的复位信号被提供到初始化晶体管的控制极。例如对于图3a所示的实施例，当复位信号Reset为逻辑低时，P型晶体管M1导通，复位信号Reset被提供到初始化晶体管M0的控制极；而当复位信号Reset为逻辑高时，P型晶体管M1截止。
可以采用多道光刻工艺在衬底基板上形成第一开关晶体管。在一些实施例中，第一开关晶体管的有源层可以由多晶硅(例如，高阻多晶硅)形成。
在本公开一些实施例中，如图3a至图4b所示，漏电抑制模块30具体可以包括：第一电容C1。如图中所示，第一电容C1的第一端可以与漏电控制信号端CK相连以接收漏电控制信号(也以CK来指示)，第二端可以与初始化晶体管M0的控制极相连。
在本公开一些实施例中，漏电控制信号CK可以包括脉冲信号。所述脉冲信号在一个脉冲周期中可以包括高电平时段和低电平时段。所述漏电抑制模块被配置用于：通过所述脉冲信号的高电平时段对漏电抑制模块进行充电，以及通过所述脉冲信号的低电平时段对漏电抑制模块进行放电。
例如，在图3a所示的实施例，在复位信号端的复位信号为低电位(例如，逻辑低)有效。低电位的复位信号使得晶体管M1导通，从而使得低电位的复位信号被提供到初始化晶体管M0的栅极。如此，初始化晶体管M0在复位信号(低电位)的控制下处于导通状态。在一些实现方式中，可以将漏电控制信号设置为具有两个或更多个脉冲。例如，如果漏电控制信号端的信号为高电位(例如，逻辑高)时的电压与复位信号端为高电位时的电压相等，则可以将漏电控制信号设置为具有大于或等于2的脉冲，如图5a中所示。或者，在其他实现方式中，也可以将漏电控制信号设置为具有一个或更多个脉冲。例如，如果漏电控制信号端的漏电控制信号为高电位时的电压大于复位信号端为高电位时的电压，则可以将漏电控制信号设置为具有大于或等于1个的脉冲。漏电控制信号端的信号为高电位(例如，逻辑高)或低电位(逻辑低)时的电压的方向与大小可以根据实际应用的要求来设计。顺带提及，尽管这里以其中以高电位作为逻辑高并以低电位作为逻辑低的实施例为例进行说明，但反之也可以，也可以利用以高电位作为逻辑低并以低电位作为逻辑高的相反逻辑来进行设计。
例如，在图4a所示的实施例中，在复位信号端的复位信号为高电位有效。高电位的复位信号使得晶体管M1导通，从而使得高电位的复位信号被提供到初始化晶体管M0的栅极。如此，初始化晶体管在复位信号端的高电位信号的控制下处于导通状态。类似地，在一些实现方式中，可以将漏电控制信号设置为具有两个或更多个脉冲。例如，在漏电控制信号端的信号为低电位时的电压与复位信号端为低电位时的电压相等时，可以将漏电控制信号端的信号的脉冲个数设置为大于或等于2，如图5b所示。或者，在漏电控制信号端的信号为低电位时的电压小于复位信号端为低电位时的电压时，可以将漏电控制信号端的信号的 脉冲个数设置为大于或等于1。类似地，漏电控制信号端的信号可以根据实际应用来设计。
在本公开一些实施例中，第一电容在漏电控制信号端的信号(即，漏电控制信号)的控制下进行充电或放电。如图5a所示，在T2阶段，在漏电控制信号中提供两个脉冲信号。在第一个脉冲作用下第一电容的充电(在高电平时段P1)完成(设此时其两端电压差为V 1)后，进行放电(在脉冲信号P1的低电平时段)，并且在放电未完成时就对第一电容进行下一次充电。由于第一电容在第一次充电后放电未完全，因此在CK信号的第一个脉冲P1的低电平时段结束时，第一电容具有一定的电压(或电压差)ΔV。此时，进行第二脉冲P2作用下的充电。在第一电容再次充电V 1完成时，根据电容的自举作用，第一电容两端的电压差为V 1+ΔV。与第一脉冲P1类似地，在第二脉冲P2的低电平放电时段结束时，第一电容具有2ΔV的电压差。之后，再次对第一电容充电，并且当充电完成时，由于自举作用第一电容具有V 1+2ΔV的电压差。
在本公开一些实施例中，第一电容可以采用CST结构。该CST结构包括三层导电层以及位于每相邻两层导电层之间的介质层，即，相当于采用两个电容进行串联后得到的结构。这样可以使第一电容的电容值较大且占用的面积较小。该CST结构可以采用现有技术中已知或者未来开发的CST结构。在此不对其进行详细说明。
在本公开一些实施例中，如图3a至图4b所示，数据写入模块11具体可以包括：第二开关晶体管M2。第二开关晶体管M2的控制极与扫描信号端Scan相连，第二开关晶体管M2的第一极与数据信号端Data相连，第二开关晶体管M2的第二极与第一节点A相连。
在本公开一些实施例中，如图3a与图4b所示，第二开关晶体管M2可以为P型晶体管；或者，如图3b与图4a所示，第二开关晶体管M2也可以为N型晶体管。
在本公开一些实施例中，第二开关晶体管可以在扫描信号端的扫描信号的控制下处于导通状态，将数据信号端的数据信号(也以Data指示)提供到第一节点A。
在本公开一些实施例中，如图3a至图4b所示，复位模块12具体可以包括：第三开关晶体管M3。第三开关晶体管M3的控制极与复位信号端Reset相连，第三开关晶体管M2的第一极与参考信号端VREF相连，第三开关晶体管M3的第二极与第一节点A相连。
在本公开一些实施例中，如图3a与图4b所示，第三开关晶体管M3可以为P型晶体管；或者，如图3b与图4a所示，第三开关晶体管M3也可以为N型晶体管。
在本公开一些实施例中，第三开关晶体管可以在复位信号端的复位信号的控制下处于导通状态，将参考信号端的信号提供到第一节点。
在本公开一些实施例中，如图3a至图4b所示，补偿控制模块13具体可以包括：第四开关晶体管M4。第四开关晶体管M4的控制极与扫描信号端Scan相连，第四开关晶体管M4的第一极与驱动晶体管DTFT的控制极m0相连，第四开关晶体管M4的第二极与驱动晶体管DTFT的第二极m2相连。
在本公开一些实施例中，如图3a与图4b所示，第四开关晶体管M4可以为P型晶体管；或者，如图3b与图4a所示，第四开关晶体管M4也可以为N型晶体管。
在本公开一些实施例中，第四开关晶体管可以在扫描信号端的扫描信号的控制下处于导通状态，从而电连接驱动晶体管的控制极与驱动晶体管的第二极。如此，使得驱动晶体管处于二极管连接状态，从而使第一电源端的信号(例如，电源电压)对驱动晶体管的控制极(或者说，对该控制极所连接到的节点)进行充电。
在本公开一些实施例中，如图3a至图4b所示，发光控制模块15具体可以包括：第五开关晶体管M5与第六开关晶体管M6。第五开关晶体管M5的控制极与发光控制信号端EM相连，第五开关晶体管M5的第一极与参考信号端VREF相连，第五开关晶体管M5的第二极与第一节点A相连。第六开关晶体管M6的控制极与发光控制信号端EM相连，第六开关晶体管M6的第一极与驱动晶体管DTFT的第二极m2相连，第六开关晶体管M6的第二极与发光器件L的第一端相连。
在本公开一些实施例中，如图3a与图4b所示，第五开关晶体管M5与第六开关晶体管M6可以为P型晶体管；或者，如图3b与图4a所示，第五开关晶体管M5与第六开关晶体管M6也可以为N型晶体管。
在本公开一些实施例中，第五开关晶体管可以在发光控制信号端的发光控制信号的控制下处于导通状态，以电连接参考信号端与第一节点，从而将参考信号端的参考信号(VREF)提供到第一节点。在第六开关晶体管在发光控制信号的控制下处于导通状态时，可以电连接驱动晶体管的第二极与发光器件的第一端，从而将驱动晶体管的第二极的电流提供到发光器件，来驱动发光器件发光。
在本公开一些实施例中，如图3a至图4b所示，存储模块14具体可以包括：第二电容C2。第二电容C2的第一端与第一节点A相连，第二端与驱动晶体管M0的控制极m0相连。
在本公开一些实施例中，第二电容在第一节点处的信号(或者，电位)与驱动晶体管的控制极的信号(或者，电位)的控制下进行充电或放电。另外，在驱动晶体管的控制极处于浮接状态时，第二电容可以保持第一节点与驱动晶体管的控制极之间的电压差稳定。
在本公开一些实施例中，第二电容可以采用CST结构。这样可以使第二电容占用的面积较小。该CST结构可以采用现有技术中的CST结构，在此不作赘述。
以上仅是举例说明本公开一些实施例提供的像素驱动电路中各模块的具体结构，上述各模块的具体结构并不限于在此公开提供的上述结构，还可以采用本领域技术人员已知的其他结构。
进一步地，在本公开一些实施例中，如图3a所示，上述模块或部件中一个或多个中的所有的开关晶体管可以均为P型晶体管。或者，如图4a所示，上述模块或部件中一个或多个中的所有的开关晶体管可以均为N型晶体管。应理解，图中所示的配置仅仅是示例性的，可以根据需要设置或选择晶体管的类型。
在本公开一些实施例中，如图3a所示，在驱动晶体管DTFT为P型晶体管时，可以将上述模块或部件中一个或多个中的所有开关晶体管设置为P型晶体管。或者，如图4a所示，在驱动晶体管DTFT为N型晶体管时，可以将上述模块或部件中一个或多个中的所有开关晶体管设置为N型晶体管。当所有开关晶体管设置为与驱动晶体管相同类型时，可以使像素驱动电路中的各开关晶体管的工艺统一，简化制作工艺流程。
在本公开一些实施例中，P型晶体管被配置为在高电位作用下截止，在低电位作用下导通；N型晶体管被配置为在高电位作用下导通，在低电位作用下截止。应理解，本公开不限于此。
需要说明的是，在本公开一些实施例中，驱动晶体管、初始化晶体管以及各开关晶体管可以是薄膜晶体管(TFT，Thin Film Transistor)。在本公开一些实施例中，驱动晶体管、初始化晶体管以及各开关晶体管可以是金属氧化物半导体场效应管(MOS，Metal Oxide Scmiconductor)。然而，本公开不限于此。
本领域技术人员容易理解，对于MOS晶体管，其控制极为栅极，其第一极可以为其源极或漏极，以及其第二极可以为漏极或源极。这里，在描述具体实施例时，以驱动晶体管和开关晶体管为MOS管为例进行说明。
下面以图3a和图4a所示的像素驱动电路为例，结合电路时序图对本公开一些实施例的工作过程作以进一步描述。下述描述中以逻辑1表示高电位，逻辑0表示低电位。需要说明的是，1和0是逻辑电平，其仅是为了更好的解释本公开一些实施例的工作过程，而不表示施加在各开关晶体管的栅极上的具体电位。
图3a示出了根据本公开一些实施例的像素驱动电路的具体结构示意图。图5a为示意性地示出图3a所示的像素驱动电路的操作的时序图。如图5a所示，像素驱动电路的一个操作周期可以包括，例如但不限于，初始化阶段T1、数据写入阶段T2以及发光阶段T3三个阶段。图5a中Vg(M0)代表初始化晶体管M0的栅极电压。如前所述的，在该实施例中，以PMOS晶体管实现驱动晶体管和各开关晶体管。另外，在该实施例中，以漏电控制信号端CK的高电位的电压V ck与复位信号端Reset的高电位电压相等为例。
在初始化阶段T1，复位信号Reset＝0，扫描信号Scan＝1，发光控制信号EM＝1，漏电控制信号CK＝0。
由于Reset＝0，因此第一开关晶体管M1与第三开关晶体管M3均导通。由于Scan＝1，因此第二开关晶体管M2与第四开关晶体管M4均截止。由于EM＝1，因此第五开关晶体管M5与第六开关晶体管M6均截止。导通的第一开关晶体管M1将复位信号端Reset的低电位信号(复位信号)提供到初始化晶体管M0的栅极，使初始化晶体管M0导通。从而，将初始化信号端Vinit的信号(初始化信号Vinit)提供到驱动晶体管DTFT的栅极，以对驱动晶体管DTFT的栅极电压初始化，并因此驱动晶体管DTFT的栅极电压为V init。由于驱动晶体管DTFT的源极电压为V dd，驱动晶体管DTFT可以处于导通状态。但是，由于第六开关晶体管M6截止，因此发光器件L不发光。导通的第三开关晶体管M3将参考信号端VREF的信号(电压V ref)提供到第一节点A，因此第一节点A的电压为V ref。由于驱动晶体管DTFT的栅极电压变化为V init，使第二电容C2第二端(其与驱动晶体管DTFT的栅极相连)的电压由上一个显示帧中的发光阶段的电压放电为V init，以为写入数据信号端Data的信号做准备。
在数据写入阶段T2，Reset＝1，Scan＝0，EM＝1。
由于Reset＝1，因此第一开关晶体管M1与第三开关晶体管M3均截止。由于Scan＝0，因此第二开关晶体管M2与第四开关晶体管M4均导通。由于EM＝1，因此第五开关晶体管M5与第六开关晶体管M6均截止。导通的第二开关晶体管M2将数据信号端Data的数据信号提供到第一节点A。因此，第一节点A的电压为V data，第二电容C2充电。导通的第四开关晶体管M4可以将驱动晶体管DTFT的栅极m0与驱动晶体管DTFT的漏极m2电连接，从而使驱动晶体管DTFT形成二极管连接状态。如此，第一电源端VDD通过驱动晶体管DTFT向驱动晶体管DTFT的栅极m0充电，直至驱动晶体管DTFT的栅极m0的电压为V dd+|V th|。因此，第二电容C2两端的电压差为：V dd+|V th|-V data。漏电控制信号端CK的信号在数据写入阶段T2 中包括两个脉冲。这里，每个脉冲周期内的占空比被设置为大于50％。也就是说，这里，在每个脉冲周期内，用于放电的低电平时段的时长小于用于充电的高电平时段。在在第一个脉冲(P1)周期内，漏电控制信号CK向第一电容C1充电，使第一电容C1两个的电压差变为高电位的V ck，从而使得初始化晶体管M0的栅极为高电位以使其截止。然后在第一脉冲P1的低电平时段，第一电容C1进行放电。由于每个脉冲周期内的占空比大于50％，因此在第一脉冲P1的低电平时段第一电容C1并未完全放电，也即，在第一电容C1还具有电压ΔV时就进入下一个脉冲周期，从而再次对第一电容C1进行充电。在漏电控制信号端CK的信号的第二个脉冲(P2)周期内，再次重复对第一电容C1充电和放电过程。
在发光阶段T3，Reset＝1，Scan＝1，EM＝0，CK＝1。
由于Reset＝1，因此第一开关晶体管M1与第三开关晶体管M3均截止。由于Scan＝1，因此第二开关晶体管M2与第四开关晶体管M4均截止。由于EM＝0，因此第五开关晶体管M5与第六开关晶体管M6均导通。导通的第五开关晶体管M5可以导通参考信号端VREF与第一节点A，将参考信号端VREF的信号提供到第一节点A，因此第一节点A的电压为V ref。此时，由于晶体管M0截止，驱动晶体管DTFT的栅极m0处于浮接(floating)状态。由于第二电容C2的自举作用，为了保持其两端的电压差仍为：V dd+|V th|-V data，因此驱动晶体管DTFT的栅极m0的电压变为：V ref+V dd+|V th|-V data。根据饱和状态电流特性可知，流过驱动晶体管DTFT且用于驱动连接的发光器件L发光的工作电流I满足公式：
I＝K(V gs-|V th|) 2＝K[V ref+V dd+|V th|-V data-V dd-|V th|] 2＝K[V ref-V data] 2；其中，V gs为驱动晶体管DTFT的栅源电压；K为结构参数，相同结构中此数值相对稳定，可以算作常量。此阶段第一电容C1充电完成时，第一电容C1两端的电压差为V ck+2ΔV，可以使初始化晶体管M0的栅极电压Vg(M0)为V ck+2ΔV。
初始化晶体管的漏极(即初始化晶体管的第二极)的电压即为驱动晶体管的栅极电压。在本公开一些实施例中，在发光阶段中，由于第一电容可以使初始化晶体管的栅极电压为V ck+2ΔV，与现有技术中初始化晶体管的栅极电压仅为复位信号端的高电压(相当于V ck)相比，可以使初始化晶体管的栅极与其漏极之间的电压差增加，从而使初始化晶体管的截止状态进一步提高，进一步避免初始化晶体管出现泄露电流情况，进而避免通过初始化晶体管形成泄露电流通路，提高发光器件的亮度以及改善闪烁现象。
需要说明的是，在数据写入阶段结束时，第一电容C1可能充电完成也可能未充电完成，这需要根据实际应用环境来设置确定。尽管在图5a所示的实施例中，初始化晶体管的栅极 电压被示出为在驱动发光器件发光的发光阶段变为V ck+2ΔV，然而本公开并不限于此。例如，在某些实施例中可以省略图5a中所示的CK信号的第二个脉冲，而代之以持续施加高电位。或者，根据所使用的元件或部件的不同(例如，电容值的不同)，可以使初始化晶体管的栅极电压在发光阶段或者发光阶段之前的阶段变为V ck+2ΔV。
通过发光阶段的工作电流I满足上述公式可知，驱动晶体管处于饱和状态时的电流仅与参考信号端的电压V ref和数据信号端的电压V data相关，而与驱动晶体管的阈值电压V th和第一电源端的电压V dd无关。如此，根据本公开的实施例，可以解决由于驱动晶体管的工艺制程以及长时间的操作造成的阈值电压V th漂移，以及IR压降(IR Drop)对流过发光器件的电流的影响，从而使发光器件L的工作电流保持稳定，进而保证发光器件L的正常工作。
图4a示出了根据本公开另外一些实施例的像素驱动电路的具体结构示意图。图5b为示意性地示出图4a所示的像素驱动电路的操作的时序图。图5b示出了初始化阶段T1、数据写入阶段T2以及发光阶段T3三个阶段。图5b中Vg(M0)代表初始化晶体管M0的栅极电压。如前所述的，在该实施例中，以NMOS晶体管实现驱动晶体管和各开关晶体管。另外，在本实施例中，以漏电控制信号端CK的低电位的电压V ck与复位信号端Reset的低电位电压相等为例。
在初始化阶段T1，Reset＝1，Scan＝0，EM＝0，CK＝1。
由于Reset＝1，因此第一开关晶体管M1与第三开关晶体管M3均导通。由于Scan＝0，因此第二开关晶体管M2与第四开关晶体管M4均截止。由于EM＝0，因此第五开关晶体管M5与第六开关晶体管M6均截止。导通的第一开关晶体管M1将复位信号端Reset的高电位信号提供到初始化晶体管M0的栅极，使初始化晶体管M0导通并将初始化信号端Vinit的信号提供到驱动晶体管DTFT的栅极以对驱动晶体管DTFT的栅极电压初始化。因此，驱动晶体管DTFT的栅极电压为V init。由于驱动晶体管DTFT的漏极电压为V dd，驱动晶体管DTFT可以处于导通状态。但是由于第六开关晶体管M6截止，因此发光器件L不发光。导通的第三开关晶体管M3将参考信号端VREF的信号的电压V ref提供到第一节点A，因此第一节点A的电压为V ref。由于驱动晶体管DTFT的栅极电压变化为V init，使第二电容C2第二端(其与驱动晶体管DTFT的栅极相连)的电压由上一个显示帧中的发光阶段的电压放电为V init，以为写入数据信号端Data的信号做准备。
在数据写入阶段T2，Reset＝0，Scan＝1，EM＝0。
由于Reset＝0，因此第一开关晶体管M1与第三开关晶体管M3均截止。由于Scan＝1，因此第二开关晶体管M2与第四开关晶体管M4均导通。由于EM＝0，因此第五开关晶体管M5与第六开关晶体管M6均截止。导通的第二开关晶体管M2将数据信号端Data的信号提供到第一节点A，因此第一节点A的电压为V data，第二电容C2充电。导通的第四开关晶体管M4可以导通驱动晶体管DTFT的栅极m0与驱动晶体管DTFT的源极m2，使驱动晶体管DTFT形成二极管连接状态。从而，第一电源VDD通过驱动晶体管DTFT向驱动晶体管DTFT的栅极m0充电，直至驱动晶体管DTFT的栅极m0的电压为V dd+|V th|。因此第二电容C2两端的电压差为：V dd+|V th|-V data。漏电控制信号端CK的信号在数据写入阶段T2中包括两个脉冲，如图5b所示。这里，每个脉冲周期内的占空比被设置为小于50％。也就是说，这里，在每个脉冲周期内，用于放电的低电平时段的时长大于用于充电的高电平时段。在第一个脉冲(P1)周期内，在低电平时段，漏电控制信号端CK向第一电容C1放电至V ck，使第一电容C1两个的电压差为低电位的V ck，从而控制初始化晶体管M0的栅极为低电位以保持其截止。然后，在高电平时段，对第一电容C1进行充电。由于每个脉冲周期内的占空比小于50％，因此在第一脉冲P1的高电平周期，第一电容C1还未充电完全，即第一电容C1还存储有电压ΔV(相对于CK信号的高电平，其为负值)时就进入下一个脉冲周期，从而再次对第一电容C1进行放电。在漏电控制信号端CK的信号的第二个脉冲(P2)周期内，再次重复对第一电容C1放电和充电过程。
在发光阶段T3，Reset＝0，Scan＝0，EM＝1，CK＝0。
由于Reset＝0，因此第一开关晶体管M1与第三开关晶体管M3均截止。由于Scan＝0，因此第二开关晶体管M2与第四开关晶体管M4均截止。由于EM＝1，因此第五开关晶体管M5与第六开关晶体管M6均导通。导通的第五开关晶体管M5可以电连接参考信号端VREF与第一节点A，将参考信号端VREF的信号的电压V ref提供到第一节点A，因此第一节点A的电压为V ref。由于晶体管M0截止，驱动晶体管DTFT的栅极m0处于浮接状态，由于第二电容C2的自举作用，为了保持其两端的电压差仍为：V dd+|V th|-V data，因此驱动晶体管DTFT的栅极m0的电压变为：V ref+V dd+|V th|-V data。根据饱和状态电流特性可知，流过驱动晶体管DTFT且用于驱动连接的发光器件L发光的工作电流I满足公式：I＝K(V gd-|V th|) 2＝K[V ref+V dd+|V th|-V data-V dd-|V th|] 2＝K[V ref-V data] 2；其中，V gd为驱动晶体管DTFT的栅漏电压；K为结构参数，相同结构中此数值相对稳定，可以算作常量。此阶段第一电容C1充电完成时，第一电容C1两端的电压差为V ck+2ΔV，可以使初始化晶体管M0 的栅极电压Vg(M0)为V ck+2ΔV。
初始化晶体管的漏极(即初始化晶体管的第二极)的电压即为驱动晶体管的栅极电压。在本公开一些实施例中，在发光阶段中，由于第一电容可以使初始化晶体管的栅极电压为V ck+2ΔV，与现有技术中初始化晶体管的栅极电压仅为复位信号端的高电压V ck相比，可以使初始化晶体管的栅极与其漏极之间的电压差减小，从而使N型初始化晶体管的处于进一步截止的状态，进一步避免初始化晶体管出现泄露电流情况，进而避免通过初始化晶体管形成泄露电流通路，提高发光器件的亮度以及改善闪烁现象。
通过发光阶段的工作电流I满足上述公式可知，驱动晶体管处于饱和状态时的电流仅与参考信号端的电压V ref和数据信号端的电压V data相关，而与驱动晶体管的阈值电压V th和第一电源端的电压V dd无关。根据本公开的实施例，可以解决由于驱动晶体管的工艺制程以及长时间的操作造成的阈值电压V th漂移，以及IR压降对流过发光器件的电流的影响，从而使发光器件L的工作电流保持稳定，进而保证发光器件L的正常工作。
类似地，在数据写入阶段结束时，第一电容C1可能充电完成也可能未充电完成，这可以根据实际应用来设置。尽管在图5b所示的实施例中，初始化晶体管的栅极电压被示出为在驱动发光器件发光的发光阶段变为V ck+2ΔV，然而本公开并不限于此。例如，在某些实施例中可以省略图5b中所示的CK信号的第二个脉冲，而代之以持续施加低电位。或者，根据所使用的元件或部件的不同(例如，电容值的不同)，可以使初始化晶体管的栅极电压在发光阶段或者发光阶段之前的阶段变为V ck+2ΔV。
在上述实施例中，第一开关晶体管的控制极与其第二极相连，形成二极管连接状态。第一开关晶体管仅在初始化阶段导通，而在发光阶段，第一开关晶体管截止。从而，使得在发光阶段，可以仅通过第一电容和漏电控制信号来控制初始化晶体管的控制极电压。
本公开一些实施例还提供了一种用于如附图所示出并在上面所描述的任一像素驱动电路的操作方法，如图6所示，包括：初始化阶段、数据写入阶段以及发光阶段；其中，
S601、在初始化阶段，信号输入模块在复位信号端的控制下将复位信号端的信号提供到初始化晶体管的控制极；复位模块在复位信号端的控制下将参考信号端的信号提供到第一节点；存储模块在第一节点的信号与驱动晶体管的控制极的信号的控制下放电。
S602、在数据写入阶段，数据写入模块在扫描信号端的控制下将数据信号端的信号提供到第一节点；补偿控制模块在扫描信号端的控制下导通驱动晶体管的控制极与驱动晶体 管的第二极；存储模块在第一节点的信号与驱动晶体管的控制极的信号的控制下充电。
S603、在发光阶段，漏电抑制模块在漏电控制信号端的控制下，使初始化晶体管的控制极与初始化晶体管的第二极之间的电压差增加；发光控制模块在发光控制信号端的控制下导通参考信号端与第一节点，以及导通驱动晶体管的第二极与发光器件的第一端，控制驱动晶体管驱动连接的发光器件发光。
本公开一些实施例还提供了一种用于像素驱动电路的操作方法，如图7所示。所述方法可以包括，在数据写入阶段：配置所述复位信号使信号输入模块关断(步骤S101)；通过所述漏电控制信号对漏电抑制模块充电，以使所述初始化晶体管截止(步骤S103)；以及通过所述漏电抑制模块在所述漏电控制信号的控制下，使所述初始化晶体管的控制极与所述初始化晶体管的第二极之间的电压差发生改变(步骤S105)。所述方法还可以包括，在发光阶段：通过所述复位信号保持所述信号输入模块关断(步骤S107)；通过所述漏电控制信号保持对漏电抑制模块充电，以使所述初始化晶体管进一步截止(步骤S109)；以及通过所述驱动晶体管驱动发光器件发光(步骤S111)。
在一些实现方式中，所述初始化晶体管由N型晶体管形成，并且其中，所述改变可以包括：使所述初始化晶体管的控制极与所述初始化晶体管的第二极之间的电压差减小(步骤S1051)。在一些实施例中，所述漏电控制信号包括脉冲信号，在所述脉冲信号的每个脉冲周期中包括高电平时段和低电平时段。在一些实施例中，使所述电压差减小可以包括：通过所述脉冲信号的高电平时段对漏电抑制模块进行充电，以及通过所述脉冲信号的低电平时段对漏电抑制模块进行放电，其中在所述脉冲信号的脉冲周期中，用于放电的低电平时段的时长小于用于充电的高电平时段。
在其他一些实现方式中，所述初始化晶体管由P型晶体管形成，并且其中，所述改变可以包括：使所述初始化晶体管的控制极与所述初始化晶体管的第二极之间的电压差增加(步骤S1052)。在一些实施例中，所述漏电控制信号包括脉冲信号，所述脉冲信号的每个脉冲周期中包括高电平时段和低电平时段。在一些实施例中，所述使所述电压差增加包括：通过所述脉冲信号的高电平时段对漏电抑制模块进行充电，以及通过所述脉冲信号的低电平时段对漏电抑制模块进行放电，其中在所述脉冲周期中，用于放电的低电平时段的时长大于用于充电的高电平时段。
在一些实施例中，所述像素补偿电路还包括数据写入模块、复位模块、补偿控制模块、存储模块以及发光控制模块。所述数据写入模块分别与数据信号端、扫描信号端以及第一 节点相连；所述复位模块分别与所述复位信号端、参考信号端以及所述第一节点相连；所述补偿控制模块分别与所述扫描信号端、所述驱动晶体管的控制极以及所述驱动晶体管的第二极相连；所述存储模块分别与所述第一节点以及所述驱动晶体管的控制极相连；所述发光控制模块分别与发光控制信号端、所述参考信号端、所述第一节点、所述驱动晶体管的第二极以及所述发光器件的第一端相连。所述驱动晶体管的第一极与第一电源端相连。所述方法还包括，如图8a所示，在初始化阶段：通过所述信号输入模块在所述复位信号的控制下将所述复位信号提供给所述初始化晶体管的控制极(步骤S201)；通过所述复位模块在所述复位信号的控制下将所述参考信号端处提供的参考信号提供给所述第一节点(步骤S203)；以及在所述第一节点处的信号与所述驱动晶体管的控制极的信号的控制下使所述存储模块进行放电(步骤S205)。
所述的方法还可以包括，如图8b所示，在数据写入阶段：通过所述数据写入模块在扫描信号的控制下将数据信号提供给所述第一节点(步骤S207)；通过所述补偿控制模块在所述扫描信号的控制下电连接所述驱动晶体管的控制极与所述驱动晶体管的第二极(步骤S209)；以及在所述第一节点处的信号与所述驱动晶体管的控制极处的信号的控制下对所述存储模块进行充电(步骤S211)。
在一些实施例中，所述初始化信号可以为初始化信号，所述复位信号可以为复位信号，所述第三信号可以为漏电控制信号。
根据本公开实施例提供的上述驱动方法，可以实现对驱动晶体管的阈值电压的补偿效果，以及避免初始化晶体管形成泄露电流通路，从而可以提高发光器件的亮度，改善显示时的闪烁现象。
本公开一些实施例还提供了一种显示面板，其包括：发光器件，以及根据本公开任意实施例像素驱动电路，用于驱动该发光器件。所述显示面板可以包括有机发光显示面板。
本公开一些实施例还构思了一种显示装置，所述显示装置包括：发光器件，以及根据本公开任意实施例像素驱动电路，用于驱动该发光器件。上述的显示面板也可以被认为是一种显示装置。另外，显示装置可以包括但不限于：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
根据本公开的实施例，可以避免初始化晶体管形成泄露电流通路，进而可以提高发光器件的发光亮度，改善显示时的闪烁现象。
此外，应理解，在本公开中所提及的模块可以以电路(或者子电路)来实现。因此，本公开的各种模块也可以被对应地称为电路或子电路。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (21)

  1. 一种像素驱动电路，包括：
    像素补偿电路，所述像素补偿电路包括驱动晶体管与初始化晶体管，所述驱动晶体管用于驱动像素中的发光器件，所述初始化晶体管的第一极与初始化信号端相连以接收初始化信号，所述初始化晶体管的第二极与所述驱动晶体管的控制极相连；
    信号输入子电路，其中，所述信号输入子电路连接在所述复位信号端与所述初始化晶体管的控制极之间，所述信号输入子电路用于在从所述复位信号端接收的复位信号的控制下选择性地将复位信号提供到所述初始化晶体管的控制极；
    漏电抑制子电路，所述漏电抑制子电路分别与漏电控制信号端以及所述初始化晶体管的控制极相连，所述漏电抑制子电路被配置为：
    通过从所述漏电控制信号端接收的漏电控制信号对漏电抑制子电路进行充电或放电，并通过所述充电或放电使得所述初始化晶体管截止。
  2. 如权利要求1所述的像素驱动电路，其中所述漏电抑制子电路还被配置用于：
    在所述漏电控制信号的控制下，使所述初始化晶体管的控制极与所述初始化晶体管的第二极之间的电压差改变，以使得所述初始化晶体管进一步截止。
  3. 如权利要求2所述的像素驱动电路，
    其中，所述初始化晶体管为N型晶体管，并且
    其中，所述改变包括：使所述初始化晶体管的控制极与所述初始化晶体管的第二极之间的电压差减小。
  4. 如权利要求2所述的像素驱动电路，
    其中，所述初始化晶体管为P型晶体管，并且
    其中，所述改变包括：使所述初始化晶体管的控制极与所述初始化晶体管的第二极之间的电压差增加。
  5. 如权利要求3所述的像素驱动电路，
    其中，所述漏电控制信号包括脉冲信号，在所述脉冲信号的每个脉冲周期中包括高电平时段和低电平时段；并且
    其中，所述漏电抑制子电路被配置用于：
    通过所述脉冲信号的高电平时段对漏电抑制子电路进行充电，以及
    通过所述脉冲信号的低电平时段对漏电抑制子电路进行放电，
    其中在所述脉冲周期中，用于放电的低电平时段的时长小于用于充电的高电平时段。
  6. 如权利要求4所述的像素驱动电路，
    其中，所述漏电控制信号包括脉冲信号，在所述脉冲信号的每个脉冲周期中包括高电平时段和低电平时段；并且
    其中，所述漏电抑制子电路被配置用于：
    通过所述脉冲信号的高电平时段对漏电抑制子电路进行充电，以及
    通过所述脉冲信号的低电平时段对漏电抑制子电路进行放电，
    其中在所述脉冲周期中，用于放电的低电平时段的时长大于用于充电的高电平时段。
  7. 如权利要求1所述的像素驱动电路，其中，所述信号输入子电路包括：第一开关晶体管，其中，
    所述第一开关晶体管的控制极及其第一极均与所述复位信号端相连，所述第一开关晶体管的第二极与所述初始化晶体管的控制极相连。
  8. 如权利要求7所述的像素驱动电路，其中，所述第一开关晶体管的有源层包括多晶硅。
  9. 如权利要求1所述的像素驱动电路，其中，所述漏电抑制子电路包括：第一电容；其中，
    所述第一电容的第一端与所述漏电控制信号端相连，第二端与所述初始化晶体管的控制极相连。
  10. 如权利要求1-9中任一项所述的像素驱动电路，
    其中，所述像素补偿电路还包括数据写入子电路、复位子电路、补偿控制子电路、存储子电路以及发光控制子电路；
    其中，所述驱动晶体管的第一极与第一电源端相连；
    其中，所述数据写入子电路分别与数据信号端、扫描信号端以及第一节点相连，用于在所述扫描信号端处提供的扫描信号的控制下将所述数据信号端处提供的数据信号提供给所述第一节点；
    其中，所述复位子电路分别与所述复位信号端、参考信号端以及所述第一节点相连，用于在所述复位信号的控制下将所述参考信号端处提供的参考信号提供给所述第一节点；
    其中，所述补偿控制子电路分别与所述扫描信号端、所述驱动晶体管的控制极以及所述驱动晶体管的第二极相连，用于在所述扫描信号的控制下将所述驱动晶体管的控制极与所述驱动晶体管的第二极电连接；
    其中，所述存储子电路分别与所述第一节点以及所述驱动晶体管的控制极相连，用于在所述第一节点的信号和所述驱动晶体管的控制极的信号的控制下充电或放电，以及在所述驱动晶体管的控制极处于浮接状态时，保持所述第一节点与所述驱动晶体管的控制极之间的电压差稳定；
    其中，所述发光控制子电路分别与发光控制信号端、所述参考信号端、所述第一节点、所述驱动晶体管的第二极以及所述发光器件的第一端相连，所述发光控制子电路用于在所述发光控制信号端处提供的发光控制信号的控制下电连接所述参考信号端与所述第一节点，以及电连接所述驱动晶体管的第二极和所述发光器件的第一端，从而使得所述驱动晶体管能够驱动发光器件发光。
  11. 如权利要求10所述的像素驱动电路，
    其中，所述数据写入子电路包括：第二开关晶体管；其中，所述第二开关晶体管的控制极与所述扫描信号端相连，所述第二开关晶体管的第一极与所述数据信号端相连，所述第二开关晶体管的第二极与所述第一节点相连；
    其中，所述复位子电路包括：第三开关晶体管；其中，所述第三开关晶体管的控制极与所述复位信号端相连，所述第三开关晶体管的第一极与所述参考信号端相连，所述第三 开关晶体管的第二极与所述第一节点相连；
    其中，所述补偿控制子电路包括：第四开关晶体管；其中，所述第四开关晶体管的控制极与所述扫描信号端相连，所述第四开关晶体管的第一极与所述驱动晶体管的控制极相连，所述第四开关晶体管的第二极与所述驱动晶体管的第二极相连；
    其中，所述存储子电路包括：第二电容，其中，所述第二电容的第一端与所述第一节点相连，第二端与所述驱动晶体管的控制极相连；
    其中，所述发光控制子电路包括：第五开关晶体管与第六开关晶体管；其中，所述第五开关晶体管的控制极与所述发光控制信号端相连，所述第五开关晶体管的第一极与所述参考信号端相连，所述第五开关晶体管的第二极与所述第一节点相连；所述第六开关晶体管的控制极与所述发光控制信号端相连，所述第六开关晶体管的第一极与所述驱动晶体管的第二极相连，所述第六开关晶体管的第二极与所述发光器件的第一端相连。
  12. 如权利要求1所述的像素驱动电路，其中：
    在所述驱动晶体管为P型晶体管的情况下，所述数据写入子电路、复位子电路、补偿控制子电路、存储子电路以及发光控制子电路中的一个或多个中的所有开关晶体管均由P型晶体管形成。
  13. 如权利要求1所述的像素驱动电路，其中：
    在所述驱动晶体管为N型晶体管的情况下，所述数据写入子电路、复位子电路、补偿控制子电路、存储子电路以及发光控制子电路中的一个或多个中的所有开关晶体管均由N型晶体管形成。
  14. 一种显示装置，包括：
    发光器件，以及
    如权利要求1-13中任一项所述的像素驱动电路，用于驱动所述发光器件。
  15. 一种用于如权利要求1所述的像素驱动电路的操作方法，所述方法包括：
    在数据写入阶段，
    配置所述复位信号以使所述信号输入子电路关断，
    通过所述漏电控制信号对漏电抑制子电路充电，以使所述初始化晶体管截止，以及
    通过所述漏电抑制子电路在所述漏电控制信号的控制下，使所述初始化晶体管的控制极与所述初始化晶体管的第二极之间的电压差发生改变；以及
    在发光阶段，
    通过所述复位信号保持所述信号输入子电路关断，
    通过所述漏电控制信号保持对漏电抑制子电路充电，以使所述初始化晶体管进一步截止；
    通过所述驱动晶体管驱动发光器件发光。
  16. 如权利要求15所述的方法，
    其中，所述初始化晶体管为N型晶体管，并且
    其中，所述改变包括：使所述初始化晶体管的控制极与所述初始化晶体管的第二极之间的电压差减小。
  17. 如权利要求15所述的方法，
    其中，所述初始化晶体管为P型晶体管，并且
    其中，所述改变包括：使所述初始化晶体管的控制极与所述初始化晶体管的第二极之间的电压差增加。
  18. 如权利要求16所述的方法，
    其中，所述漏电控制信号包括脉冲信号，在所述脉冲信号的每个脉冲周期中包括高电平时段和低电平时段；并且
    其中，使所述电压差减小包括：
    通过所述脉冲信号的高电平时段对漏电抑制子电路进行充电，以及
    通过所述脉冲信号的低电平时段对漏电抑制子电路进行放电，
    其中在所述脉冲周期中，用于放电的低电平时段的时长小于用于充电的高电平时段。
  19. 如权利要求17所述的方法，
    其中，所述漏电控制信号包括脉冲信号，在所述脉冲信号的每个脉冲周期中包括高电平时段和低电平时段；并且
    其中，使所述电压差增加包括：
    通过所述脉冲信号的高电平时段对漏电抑制子电路进行充电，以及
    通过所述脉冲信号的低电平时段对漏电抑制子电路进行放电，
    其中在所述脉冲周期中，用于放电的低电平时段的时长大于用于充电的高电平时段。
  20. 如权利要求15所述的方法，
    其中，所述像素补偿电路还包括数据写入子电路、复位子电路、补偿控制子电路、存储子电路以及发光控制子电路；并且
    其中，所述驱动晶体管的第一极与第一电源端相连；所述数据写入子电路分别与数据信号端、扫描信号端以及第一节点相连；所述复位子电路分别与所述复位信号端、参考信号端以及所述第一节点相连；所述补偿控制子电路分别与所述扫描信号端、所述驱动晶体管的控制极以及所述驱动晶体管的第二极相连；所述存储子电路分别与所述第一节点以及所述驱动晶体管的控制极相连；所述发光控制子电路分别与发光控制信号端、所述参考信号端、所述第一节点、所述驱动晶体管的第二极以及所述发光器件的第一端相连，
    所述方法还包括：
    在初始化阶段，
    通过所述信号输入子电路在所述复位信号的控制下将所述复位信号提供给所述初始化晶体管的控制极；
    通过所述复位子电路在所述复位信号的控制下将所述参考信号端处提供的参考信号提供给所述第一节点；以及
    在所述第一节点处的信号与所述驱动晶体管的控制极的信号的控制下使所述存储子电路进行放电。
  21. 如权利要求20所述的方法，还包括：
    在数据写入阶段，
    通过所述数据写入子电路在扫描信号的控制下将数据信号提供给所述第一节点；
    通过所述补偿控制子电路在所述扫描信号的控制下电连接所述驱动晶体管的控制极与所述驱动晶体管的第二极；以及
    在所述第一节点处的信号与所述驱动晶体管的控制极处的信号的控制下对所述存储子电路进行充电。
PCT/CN2018/081332 2017-04-17 2018-03-30 像素驱动电路及其操作方法以及显示面板 WO2018192353A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/089,875 US20200234633A1 (en) 2017-04-17 2018-03-30 Pixel driving circuit and operating method thereof, and display panel

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710249921.5A CN106935198B (zh) 2017-04-17 2017-04-17 一种像素驱动电路、其驱动方法及有机发光显示面板
CN201710249921.5 2017-04-17

Publications (1)

Publication Number Publication Date
WO2018192353A1 true WO2018192353A1 (zh) 2018-10-25

Family

ID=59437064

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/081332 WO2018192353A1 (zh) 2017-04-17 2018-03-30 像素驱动电路及其操作方法以及显示面板

Country Status (3)

Country Link
US (1) US20200234633A1 (zh)
CN (1) CN106935198B (zh)
WO (1) WO2018192353A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115084165A (zh) * 2022-06-28 2022-09-20 云谷（固安）科技有限公司 阵列基板、显示面板和显示装置

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106935198B (zh) * 2017-04-17 2019-04-26 京东方科技集团股份有限公司 一种像素驱动电路、其驱动方法及有机发光显示面板
CN107316613B (zh) * 2017-07-31 2019-07-09 上海天马有机发光显示技术有限公司 像素电路、其驱动方法、有机发光显示面板及显示装置
CN107342048A (zh) 2017-08-17 2017-11-10 京东方科技集团股份有限公司 像素电路及其驱动方法、显示装置
CN107342049B (zh) * 2017-08-30 2019-10-01 上海天马有机发光显示技术有限公司 显示面板和显示面板的驱动方法
CN108630152A (zh) * 2018-05-08 2018-10-09 京东方科技集团股份有限公司 显示装置及其像素驱动电路和驱动方法
CN108806596A (zh) * 2018-06-26 2018-11-13 京东方科技集团股份有限公司 像素驱动电路及方法、显示装置
CN109637457B (zh) * 2019-02-14 2020-08-18 成都京东方光电科技有限公司 像素电路、显示面板及显示装置
CN112424856B (zh) * 2019-06-03 2023-03-14 京东方科技集团股份有限公司 像素电路、像素电路的驱动方法、显示装置及其驱动方法
CN111445863B (zh) * 2020-05-14 2021-09-14 京东方科技集团股份有限公司 一种像素驱动电路及其驱动方法、显示装置
CN111627387B (zh) 2020-06-24 2022-09-02 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、显示面板及显示装置
CN111696484B (zh) * 2020-07-10 2021-10-08 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、阵列基板及显示装置
CN111710303B (zh) * 2020-07-16 2021-08-10 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、显示装置
CN113963667B (zh) 2020-07-21 2023-04-18 京东方科技集团股份有限公司 一种显示装置及其驱动方法
CN114999396A (zh) * 2020-08-28 2022-09-02 武汉天马微电子有限公司 显示面板及其驱动方法及显示装置
CN112037716B (zh) * 2020-09-21 2022-01-21 京东方科技集团股份有限公司 像素电路、显示面板和显示设备
CN114360440B (zh) * 2020-09-30 2023-06-30 京东方科技集团股份有限公司 像素电路及其驱动方法、发光装置
CN114981874B (zh) * 2020-11-30 2023-11-07 京东方科技集团股份有限公司 驱动电路、其驱动方法及显示装置
CN112909058B (zh) * 2021-01-28 2024-04-16 合肥京东方光电科技有限公司 像素结构、显示基板及其驱动方法、显示装置
JP2024065125A (ja) * 2021-03-11 2024-05-15 ソニーセミコンダクタソリューションズ株式会社 表示装置及び制御方法
CN113066439B (zh) * 2021-03-30 2022-11-29 京东方科技集团股份有限公司 一种像素电路、驱动方法、电致发光显示面板及显示装置
CN115512631A (zh) 2021-06-22 2022-12-23 荣耀终端有限公司 像素驱动电路及其驱动方法、显示面板及终端设备
TWI799055B (zh) * 2022-01-03 2023-04-11 友達光電股份有限公司 畫素電路、其顯示面板及其驅動方法
CN114999368A (zh) * 2022-05-31 2022-09-02 Tcl华星光电技术有限公司 像素驱动电路和显示面板

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130069556A1 (en) * 2011-09-19 2013-03-21 Wen-Chun Wang Light-emitting elemeny driver circuit
CN105869573A (zh) * 2015-02-05 2016-08-17 三星显示有限公司 有机发光二极管显示器
CN106057126A (zh) * 2016-05-26 2016-10-26 上海天马有机发光显示技术有限公司 一种像素电路及其驱动方法
CN106298844A (zh) * 2015-05-13 2017-01-04 三星显示有限公司 显示装置
CN106935198A (zh) * 2017-04-17 2017-07-07 京东方科技集团股份有限公司 一种像素驱动电路、其驱动方法及有机发光显示面板

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003195815A (ja) * 2000-11-07 2003-07-09 Sony Corp アクティブマトリクス型表示装置およびアクティブマトリクス型有機エレクトロルミネッセンス表示装置
GB0307320D0 (en) * 2003-03-29 2003-05-07 Koninkl Philips Electronics Nv Active matrix display device
JP4736954B2 (ja) * 2006-05-29 2011-07-27 セイコーエプソン株式会社 単位回路、電気光学装置、及び電子機器
WO2009084269A1 (ja) * 2007-12-28 2009-07-09 Sharp Kabushiki Kaisha 半導体装置及び表示装置
CN102411917A (zh) * 2011-12-21 2012-04-11 深圳市华星光电技术有限公司 液晶面板的驱动电路及液晶显示器
US20130162508A1 (en) * 2011-12-21 2013-06-27 Shenzhen China Star Optoelectronics Technology Co., Ltd. Driving Circuit of a Liquid Crystal Panel and an LCD
CN103226931B (zh) * 2013-04-27 2015-09-09 京东方科技集团股份有限公司 像素电路和有机发光显示器
CN103886838B (zh) * 2014-03-24 2016-04-06 京东方科技集团股份有限公司 像素补偿电路、阵列基板及显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130069556A1 (en) * 2011-09-19 2013-03-21 Wen-Chun Wang Light-emitting elemeny driver circuit
CN105869573A (zh) * 2015-02-05 2016-08-17 三星显示有限公司 有机发光二极管显示器
CN106298844A (zh) * 2015-05-13 2017-01-04 三星显示有限公司 显示装置
CN106057126A (zh) * 2016-05-26 2016-10-26 上海天马有机发光显示技术有限公司 一种像素电路及其驱动方法
CN106935198A (zh) * 2017-04-17 2017-07-07 京东方科技集团股份有限公司 一种像素驱动电路、其驱动方法及有机发光显示面板

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115084165A (zh) * 2022-06-28 2022-09-20 云谷（固安）科技有限公司 阵列基板、显示面板和显示装置

Also Published As

Publication number Publication date
US20200234633A1 (en) 2020-07-23
CN106935198A (zh) 2017-07-07
CN106935198B (zh) 2019-04-26

Similar Documents

Publication Publication Date Title
WO2018192353A1 (zh) 像素驱动电路及其操作方法以及显示面板
CN107358915B (zh) 一种像素电路、其驱动方法、显示面板及显示装置
US11393373B2 (en) Gate drive circuit and drive method thereof, display device and control method thereof
WO2021043102A1 (zh) 驱动电路及其驱动方法、显示装置
KR101788432B1 (ko) 픽셀 회로, 유기 전계 발광 표시 패널, 표시 장치 및 그 구동 방법
JP7025213B2 (ja) 電子回路及び駆動方法、表示パネル、並びに表示装置
US10565933B2 (en) Pixel circuit, driving method thereof, array substrate, display device
WO2020001026A1 (zh) 像素驱动电路及方法、显示面板
WO2018149167A1 (zh) 像素驱动电路、其驱动方法及显示面板
WO2016161866A1 (zh) 像素电路及其驱动方法、显示装置
WO2016173124A1 (zh) 像素电路、其驱动方法及相关装置
TWI699742B (zh) 畫素電路
WO2020001027A1 (zh) 像素驱动电路及方法、显示装置
US11270638B2 (en) Display compensation circuit and method for controlling the same, and display apparatus
US20150109279A1 (en) Organic Light Emitting Diode Displays with Improved Driver Circuitry
CN110164375B (zh) 像素补偿电路、驱动方法、电致发光显示面板及显示装置
CN111599313B (zh) 像素驱动电路、驱动方法及显示面板
WO2018014645A1 (zh) 像素电路、其驱动方法及显示面板
CN109064975B (zh) 像素电路及其驱动方法、显示面板、显示装置
WO2019037476A1 (zh) 像素补偿电路、其驱动方法、显示面板及显示装置
WO2020140694A1 (en) Pixel-driving circuit and method, and a display utilizing the same
CN115691411A (zh) 像素电路及其驱动方法、显示装置
US11651735B2 (en) Pixel circuit and drive method thereof, and display panel
CN114023262A (zh) 像素驱动电路及显示面板
US7663579B2 (en) Organic electroluminescence display device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18787767

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 30.03.2020)

122 Ep: pct application non-entry in european phase

Ref document number: 18787767

Country of ref document: EP

Kind code of ref document: A1