WO2023039891A1 - 像素电路、驱动方法和显示装置 - Google Patents

像素电路、驱动方法和显示装置 Download PDF

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Publication number
WO2023039891A1
WO2023039891A1 PCT/CN2021/119405 CN2021119405W WO2023039891A1 WO 2023039891 A1 WO2023039891 A1 WO 2023039891A1 CN 2021119405 W CN2021119405 W CN 2021119405W WO 2023039891 A1 WO2023039891 A1 WO 2023039891A1
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Prior art keywords
circuit
node
electrically connected
control
transistor
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PCT/CN2021/119405
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English (en)
French (fr)
Inventor
王本莲
秦成杰
刘聪
王予
黄炜赟
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202180002621.1A priority Critical patent/CN116391219A/zh
Priority to PCT/CN2021/119405 priority patent/WO2023039891A1/zh
Priority to US17/793,718 priority patent/US20240221641A1/en
Publication of WO2023039891A1 publication Critical patent/WO2023039891A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G09G2310/062—Waveforms for resetting a plurality of scan lines at a time
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0257—Reduction of after-image effects
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a pixel circuit, a driving method and a display device.
  • the gate voltage of the driving transistor is initialized to the initial voltage.
  • the source voltage of the transistor changes accordingly.
  • the variation of the gate voltage of the driving transistor is different, so the variation of the source voltage of the driving transistor is also different, which leads to different source voltages of the driving transistor after the reset phase is completed, and the variation of the driving transistor is different.
  • the gate-source voltage Vgs is also different. At the same time, since the gate-source voltage Vgs of the driving transistor will affect its threshold voltage, the afterimage problem will occur in the display panel.
  • an embodiment of the present disclosure provides a pixel circuit, including a light emitting element, a driving circuit, a first reset circuit, a first control circuit and a second control circuit, wherein,
  • the first reset circuit is respectively connected to the first scan line, the first initial voltage terminal and the first node, and is used to control the first initial voltage terminal under the control of the first scan signal provided by the first scan line. writing the first initial voltage provided by the voltage terminal into the first node;
  • the first control circuit is electrically connected to the second light emission control line, the power supply voltage terminal and the second node, and is used to control the power supply voltage under the control of the second light emission control signal provided by the second light emission control line. connected between the terminal and the second node;
  • the second control circuit is respectively electrically connected to the first light emission control line, the third node and the first pole of the light emitting element, and is used to control the first light emission control signal provided by the first light emission control line, controlling the communication between the third node and the first pole of the light emitting element;
  • the control end of the drive circuit is electrically connected to the first node, the first end of the drive circuit is electrically connected to the second node, and the second end of the drive circuit is electrically connected to the third node,
  • the drive circuit is used to control the communication between the second node and the third node under the control of the potential of the first node;
  • the second pole of the light emitting element is electrically connected to the first voltage terminal.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a data writing circuit and a threshold compensation circuit;
  • the threshold compensation circuit is electrically connected to the second scanning line, the first node and the third node, and is used to control the first scanning signal under the control of the second scanning signal provided by the second scanning line.
  • the node is connected with the third node;
  • the data writing circuit is electrically connected to the third scan line, the data line and the second node, and is used to write the data provided by the data line under the control of the third scan signal provided by the third scan line. A data voltage is written into the second node.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a second reset circuit; connected to write the second initial voltage provided by the second initial voltage terminal into the first electrode of the light emitting element under the control of the second scan signal provided by the second scan line.
  • a second reset circuit connected to write the second initial voltage provided by the second initial voltage terminal into the first electrode of the light emitting element under the control of the second scan signal provided by the second scan line.
  • At least one embodiment of the present disclosure further includes a coupling circuit
  • the first end of the coupling circuit is electrically connected to the first node
  • the second end of the coupling circuit is electrically connected to the power supply voltage end
  • the coupling circuit is used to store electric energy and control the first node potential.
  • both the transistors included in the first light emission control circuit and the transistors included in the second light emission control circuit are p-type transistors
  • the first light emission control signal and the second light emission control signal are provided by the same light emission control signal generation circuit
  • the first light emission control signal is the nth level light emission control signal provided by the light emission control signal generation circuit
  • the second light emission control signal is the n+1th level light emission control signal provided by the light emission control signal generation circuit
  • n is a positive integer.
  • the transistors in the first reset circuit, the transistors in the second reset circuit, the transistors in the data writing circuit, and the transistors in the threshold compensation circuit are all p-type transistors;
  • the first scan signal, the second scan signal and the third scan signal are provided by the same scan signal generating circuit;
  • the first scan signal is the mth level scan signal provided by the scan signal generation circuit
  • the second scan signal is the m+1st level scan signal provided by the scan signal generation circuit
  • the third scan signal The (m+2)th level scanning signal provided for the scanning signal generating circuit; m is a positive integer.
  • the transistors in the first reset circuit and the transistors in the threshold compensation circuit are oxide transistors.
  • the first reset circuit includes a first transistor
  • the control electrode of the first transistor is electrically connected to the first scanning line, the first electrode of the first transistor is electrically connected to the first initial voltage terminal, and the second electrode of the first transistor is electrically connected to the The first node is electrically connected.
  • the first control circuit includes a second transistor, and the second control circuit includes a third transistor;
  • the control electrode of the second transistor is electrically connected to the second light-emitting control line, the first electrode of the second transistor is electrically connected to the power supply voltage terminal, and the second electrode of the second transistor is electrically connected to the first One node electrical connection;
  • the control electrode of the third transistor is electrically connected to the first light emission control line
  • the first electrode of the third transistor is electrically connected to the third node
  • the second electrode of the third transistor is electrically connected to the light emission control line.
  • the first poles of the elements are electrically connected.
  • the data writing circuit includes a fourth transistor, and the threshold compensation circuit includes a fifth transistor;
  • the control electrode of the fourth transistor is electrically connected to the third scanning line, the first electrode of the fourth transistor is electrically connected to the data line, and the second electrode of the fourth transistor is electrically connected to the second node electrical connection;
  • the control electrode of the fifth transistor is electrically connected to the second scanning line, the first electrode of the fifth transistor is electrically connected to the first node, the second electrode of the fifth transistor is electrically connected to the third The nodes are electrically connected.
  • the second reset circuit includes a sixth transistor
  • the control electrode of the sixth transistor is electrically connected to the second scanning line, the first electrode of the sixth transistor is electrically connected to the second initial voltage terminal, and the second electrode of the sixth transistor is electrically connected to the The first pole of the light emitting element is electrically connected;
  • the coupling circuit includes a storage capacitor
  • a first end of the storage capacitor is electrically connected to the first node, and a second end of the storage capacitor is electrically connected to the power supply voltage end.
  • the drive circuit includes a drive transistor
  • the control electrode of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the second node, and the second electrode of the driving transistor is electrically connected to the third node.
  • the embodiment of the present disclosure further provides a driving method, which is applied to the above-mentioned pixel circuit, and the display cycle includes a reset phase; the driving method includes:
  • the first reset circuit controls to write the first initial voltage into the first node; under the control of the second light emission control signal, the first control circuit controls the The power supply voltage terminal communicates with the second node.
  • the pixel circuit further includes a data writing circuit, a threshold compensation circuit, a second reset circuit and a coupling circuit;
  • the display period also includes a data writing phase and a light emitting phase arranged after the reset phase; the driving method also includes:
  • the second reset circuit writes a second initial voltage into the first pole of the light-emitting element under the control of the second scan signal, so that the light-emitting element does not emit light;
  • the data writing circuit Under the control of the third scan signal, write the data voltage into the second node;
  • the threshold compensation circuit controls the communication between the first node and the third node;
  • the drive circuit controls the communication between the second node and the third node under the control of the potential of the first node, so as to charge the coupling circuit with the data voltage, so as to change the the potential of the first node until the driving circuit disconnects the connection between the second node and the third node;
  • the first control circuit controls the connection between the power supply voltage terminal and the second node under the control of the second light-emitting control signal; the second control circuit controls the second node under the control of the first light-emitting control signal
  • the three nodes are connected to the first pole of the light emitting element, and the driving circuit drives the light emitting element to emit light.
  • an embodiment of the present disclosure further provides a display device, including the above-mentioned pixel circuit.
  • FIG. 1 is a structural diagram of a pixel circuit described in an embodiment of the present disclosure
  • Fig. 2 is a structural diagram of a pixel circuit described in at least one embodiment of the present disclosure
  • Fig. 3 is a structural diagram of a pixel circuit described in at least one embodiment of the present disclosure.
  • Fig. 4 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG. 5 is a working timing diagram of at least one embodiment of the pixel circuit shown in FIG. 4 of the present disclosure.
  • the transistors used in all the embodiments of the present disclosure may be triodes, thin film transistors or field effect transistors or other devices with the same characteristics.
  • one pole is called the first pole, and the other pole is called the second pole.
  • the first pole when the transistor is a thin film transistor or a field effect transistor, the first pole may be a drain, and the second pole may be a source; or, the first pole may be a source, The second pole may be a drain.
  • the pixel circuit described in the embodiment of the present disclosure includes a light emitting element 10, a driving circuit 11, a first reset circuit 12, a first control circuit 13 and a second control circuit 14, wherein,
  • the first reset circuit 12 is respectively connected to the first scan line G1, the first initial voltage terminal I1 and the first node N1, and is used to control the first scan signal provided by the first scan line G1 to writing the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the first node N1;
  • the first control circuit 13 is electrically connected to the second light emission control line E2, the power supply voltage terminal Vd, and the second node N2 respectively, and is used for controlling the second light emission control signal provided by the second light emission control line E2, controlling the communication between the power supply voltage terminal Vd and the second node N2; the power supply voltage terminal Vd is used to provide a power supply voltage VDD;
  • the second control circuit 14 is electrically connected to the first light emission control line E1, the third node N3 and the first pole of the light emitting element 10 respectively, and is used for the first light emission control provided on the first light emission control line E1. Under the control of the signal, control the communication between the third node N3 and the first pole of the light emitting element 10;
  • the control end of the driving circuit 11 is electrically connected to the first node N1, the first end of the driving circuit 11 is electrically connected to the second node N2, and the second end of the driving circuit 11 is electrically connected to the first node N2.
  • the three nodes N3 are electrically connected, and the drive circuit 11 is configured to control the communication between the second node N2 and the third node N3 under the control of the potential of the first node N1;
  • the second pole of the light emitting element is electrically connected to the first voltage terminal V1.
  • the first voltage terminal V1 may be a low voltage terminal or a ground terminal, but not limited thereto.
  • the display cycle includes a reset phase set before the data writing phase
  • the first reset circuit 12 controls to write the first initial voltage Vi1 into the first node N1; the first control circuit 14 controls the second light emission control signal , controlling the communication between the power supply voltage terminal Vd and the second node N2.
  • the pixel circuit described in the embodiment of the present disclosure includes a first reset circuit 12 and a first control circuit 14.
  • the first reset circuit 12 writes the first initial voltage Vi1 into the drive circuit.
  • the first control circuit 14 controls the power supply voltage VDD to be written into the first terminal of the drive circuit 11 under the control of the second light emission control signal, so as to provide bias voltage to the drive transistor in the drive circuit 11, so that the drive Transistors are kept in their reset state, improving the hysteresis of the drive transistors, thereby eliminating afterimages.
  • the hysteresis of the driving transistor will cause the characteristic response of the driving transistor to be sluggish, but in the embodiment of the present disclosure, before the data voltage is written, the gate-source voltage of the driving transistor is quickly reset, which is beneficial to the recovery speed of the driving transistor, so it will Improve the hysteresis of the driving transistor and increase the hysteresis recovery speed.
  • the first control circuit 13 is electrically connected to the second light emission control line E2, and works under the control of the second light emission control signal provided by the second light emission control line E2, and the second light emission control circuit 13
  • the control circuit 14 is electrically connected to the first light emission control line E1 and works under the control of the first light emission control signal provided by the first light emission control line E1 to ensure the normal operation of the light emission phase sequence and ensure the display effect.
  • the pixel circuit described in at least one embodiment of the present disclosure may further include a data writing circuit 21 and a threshold compensation circuit 22;
  • the threshold compensation circuit 22 is electrically connected to the second scanning line G2, the first node N1 and the third node N3 respectively, and is used for controlling the second scanning signal provided by the second scanning line G2, controlling the communication between the first node N1 and the third node N3;
  • the data writing circuit 21 is respectively electrically connected to the third scanning line G3, the data line D1 and the second node N2, and is used to write the The data voltage Vdata provided by the data line D1 is written into the second node N2.
  • the first reset circuit 12 is electrically connected to the first scan line G1 and works under the control of the first scan signal; It is electrically connected to the second scanning line G2 and works under the control of the second scanning signal; the data writing circuit 21 is electrically connected to the third scanning line G3 and works under the control of the third scanning signal; With cooperation, it can ensure the normal progress of the initialization and data writing sequence, and ensure the effect of initialization and threshold voltage compensation.
  • the pixel circuit described in at least one embodiment of the present disclosure may further include a second reset circuit; the second reset circuit is respectively electrically connected to the second scanning line, the second initial voltage terminal and the first pole of the light emitting element, for Under the control of the second scan signal provided by the second scan line, write the second initial voltage provided by the second initial voltage terminal into the first electrode of the light emitting element, so as to control the light emitting element not to emit light, and clearing the residual charge of the first pole of the light-emitting element.
  • the second reset circuit is respectively electrically connected to the second scanning line, the second initial voltage terminal and the first pole of the light emitting element, for Under the control of the second scan signal provided by the second scan line, write the second initial voltage provided by the second initial voltage terminal into the first electrode of the light emitting element, so as to control the light emitting element not to emit light, and clearing the residual charge of the first pole of the light-emitting element.
  • the pixel circuit described in at least one embodiment of the present disclosure may further include a coupling circuit
  • the first end of the coupling circuit is electrically connected to the first node
  • the second end of the coupling circuit is electrically connected to the power supply voltage end
  • the coupling circuit is used to store electric energy and control the first node potential.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a second reset circuit 31 and a coupling circuit 32 ;
  • the second reset circuit 31 is electrically connected to the second scanning line G2, the second initial voltage terminal I2 and the first pole of the light emitting element 10 respectively, and is used for the second scanning signal provided on the second scanning line G2 Under the control of , write the second initial voltage Vi2 provided by the second initial voltage terminal I2 into the first pole of the light emitting element 10;
  • the first terminal of the coupling circuit 32 is electrically connected to the first node N1
  • the second terminal of the coupling circuit 32 is electrically connected to the power supply voltage terminal Vd
  • the coupling circuit 32 is used for storing electric energy and controlling The potential of the first node N1.
  • the display cycle also includes a data writing phase and a light emitting phase set after the reset phase;
  • the second reset circuit 31 writes the second initial voltage Vi2 into the first pole of the light-emitting element 10 under the control of the second scan signal, so that the light-emitting element 10 does not emit light;
  • the data writing circuit 21 writes the data voltage Vdata into the second node N2 under the control of the third scan signal;
  • the threshold compensation circuit 22 controls the first node N1 and the third node N3 under the control of the second scan signal connection between
  • the drive circuit 11 controls the connection between the second node N2 and the third node N3 under the control of the potential of the first node N1, so that the data voltage Vdata serves as a coupling circuit 32 charging to change the potential of the first node N1 until the drive circuit 11 disconnects the connection between the second node N2 and the third node N3, at this time, the potential of N1 is Vdata+Vth, Vth is the threshold voltage of the driving transistor in the driving circuit 11;
  • the first control circuit 13 controls the communication between the power supply voltage terminal Vd and the second node N2 under the control of the second lighting control signal; the second control circuit 14 controls the connection between the first lighting control signal Next, the connection between the third node N3 and the first pole of the light emitting element 10 is controlled, and the driving circuit 11 drives the light emitting element 10 to emit light.
  • both the transistors included in the first light emission control circuit and the transistors included in the second light emission control circuit are p-type transistors
  • the first light emission control signal and the second light emission control signal are provided by the same light emission control signal generation circuit
  • the first light emission control signal is the nth level light emission control signal provided by the light emission control signal generation circuit
  • the second light emission control signal is the n+1th level light emission control signal provided by the light emission control signal generation circuit
  • n is a positive integer.
  • the first light emission control signal and the second light emission control signal may be adjacent two-level light emission control signals provided by the same light emission control signal generation circuit.
  • the transistors in the first reset circuit, the transistors in the second reset circuit, the transistors in the data writing circuit, and the transistors in the threshold compensation circuit are all p-type transistors;
  • the first scan signal, the second scan signal and the third scan signal are provided by the same scan signal generating circuit;
  • the first scan signal is the mth level scan signal provided by the scan signal generation circuit
  • the second scan signal is the m+1st level scan signal provided by the scan signal generation circuit
  • the third scan signal The (m+2)th level scanning signal provided for the scanning signal generating circuit; m is a positive integer.
  • the first scan signal, the second scan signal and the third scan signal may be adjacent three-level scan signals provided by the same scan signal generating circuit.
  • the transistors in the first reset circuit and the transistors in the threshold compensation circuit are oxide transistors.
  • Oxide transistors have low leakage current and low Mobility. Therefore, at least one embodiment of the present disclosure can set the transistors in the first reset circuit and the transistors in the threshold compensation circuit as oxide thin film transistors to achieve low leakage and ensure the stability of the potential of the control terminal of the driving circuit; but This is not the limit.
  • the first reset circuit includes a first transistor
  • the control electrode of the first transistor is electrically connected to the first scanning line, the first electrode of the first transistor is electrically connected to the first initial voltage terminal, and the second electrode of the first transistor is electrically connected to the The first node is electrically connected.
  • the first control circuit includes a second transistor, and the second control circuit includes a third transistor;
  • the control electrode of the second transistor is electrically connected to the second light-emitting control line, the first electrode of the second transistor is electrically connected to the power supply voltage terminal, and the second electrode of the second transistor is electrically connected to the first One node electrical connection;
  • the control electrode of the third transistor is electrically connected to the first light emission control line
  • the first electrode of the third transistor is electrically connected to the third node
  • the second electrode of the third transistor is electrically connected to the light emission control line.
  • the first poles of the elements are electrically connected.
  • the data writing circuit includes a fourth transistor, and the threshold compensation circuit includes a fifth transistor;
  • the control electrode of the fourth transistor is electrically connected to the third scanning line, the first electrode of the fourth transistor is electrically connected to the data line, and the second electrode of the fourth transistor is electrically connected to the second node electrical connection;
  • the control electrode of the fifth transistor is electrically connected to the second scanning line, the first electrode of the fifth transistor is electrically connected to the first node, the second electrode of the fifth transistor is electrically connected to the third The nodes are electrically connected.
  • the second reset circuit includes a sixth transistor
  • the control electrode of the sixth transistor is electrically connected to the second scanning line, the first electrode of the sixth transistor is electrically connected to the second initial voltage terminal, and the second electrode of the sixth transistor is electrically connected to the The first pole of the light emitting element is electrically connected;
  • the coupling circuit includes a storage capacitor
  • a first end of the storage capacitor is electrically connected to the first node, and a second end of the storage capacitor is electrically connected to the power supply voltage end.
  • the drive circuit includes a drive transistor
  • the control electrode of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the second node, and the second electrode of the driving transistor is electrically connected to the third node.
  • the light emitting element is an organic light emitting diode O1;
  • the first reset circuit 12 includes a first transistor T1;
  • the gate of the first transistor T1 is electrically connected to the first scanning line G1, the source of the first transistor T1 is electrically connected to the first initial voltage terminal I1, and the drain of the first transistor T1 electrically connected to the first node N1;
  • the first control circuit 13 includes a second transistor T2, and the second control circuit 14 includes a third transistor T3;
  • the gate of the second transistor T2 is electrically connected to the second light emission control line E2, the source of the second transistor T2 is electrically connected to the power supply voltage terminal Vd, and the drain of the second transistor T2 is electrically connected to the power supply voltage terminal Vd.
  • the first node N1 is electrically connected; the power supply voltage terminal is used to provide a power supply voltage VDD;
  • the gate of the third transistor T3 is electrically connected to the first light emission control line E1, the source of the third transistor T3 is electrically connected to the third node N3, and the drain of the third transistor T3 is electrically connected to the third node N3.
  • the cathode of O1 is electrically connected to the low voltage terminal Vs, and the low voltage terminal is used to provide a low voltage VSS;
  • the data writing circuit 21 includes a fourth transistor T4, and the threshold compensation circuit 22 includes a fifth transistor T5;
  • the gate of the fourth transistor T4 is electrically connected to the third scan line G3, the source of the fourth transistor T4 is electrically connected to the data line D1, and the drain of the fourth transistor T4 is electrically connected to the The second node N2 is electrically connected;
  • the gate of the fifth transistor T5 is electrically connected to the second scanning line G2, the source of the fifth transistor T5 is electrically connected to the first node N1, and the second electrode of the fifth transistor T5 is electrically connected to the first node N1.
  • the third node is electrically connected;
  • the second reset circuit 31 includes a sixth transistor T6;
  • the gate of the sixth transistor T6 is electrically connected to the second scanning line G2, the source of the sixth transistor T6 is electrically connected to the second initial voltage terminal I2, and the drain of the sixth transistor T6 Electrically connected to the anode of O1;
  • the coupling circuit 32 includes a storage capacitor C1;
  • the first terminal of the storage capacitor C1 is electrically connected to the first node N1, and the second terminal of the storage capacitor C1 is electrically connected to the power supply voltage terminal Vd;
  • the driving circuit 11 includes a driving transistor T0;
  • the gate of the driving transistor T0 is electrically connected to the first node N1, the source of the driving transistor T0 is electrically connected to the second node N2, and the drain of the driving transistor T0 is electrically connected to the third node N3 is electrically connected.
  • all transistors are p-type transistors, and all transistors may be low-temperature polysilicon transistors, but not limited thereto.
  • T2 and T3 respond to different light-emitting control signals
  • T1, T5 and T4 respond to different scanning signals to ensure initialization, data writing and threshold compensation
  • OLED organic light emitting The three timings of light emission of the diode) are carried out normally, so as to ensure threshold voltage compensation and display effect.
  • the display cycle may include an initialization phase t1, a data writing phase t2, and a lighting phase t3 which are set successively;
  • G1 and E2 provide low voltage signals
  • G2, G3 and E1 provide high voltage signals
  • T1 and T2 are turned on to write Vi1 into N1 and VDD into N2 to reset the gate-source voltage of T0 , so that T0 is in the conduction bias state, which can improve the hysteresis effect of T0 and eliminate afterimages;
  • G1 provides a high voltage signal
  • G2 and G3 provide a low voltage signal
  • E1 and E2 provide a high voltage signal
  • D1 provides a data voltage Vdata
  • T5, T4 and T6 are all turned on, and the data voltage Vdata is written into N2 , control the connection between N1 and N3, and write Vi2 into the anode of O1, so that O1 does not emit light, and remove the residual charge of the anode of O1;
  • T0 is turned on to charge C1 through Vdata to increase the potential of N1 until the potential of N1 becomes Vdata+Vth, and T0 is turned off; where Vth is the threshold voltage of T0;
  • G1, G2 and G3 provide high-voltage signals, E1 and E2 provide low-voltage signals, T2 and T3 are turned on, and T0 drives O1 to emit light.
  • the first scanning signal provided by G1, the second scanning signal provided by G2 and the third scanning signal provided by G3 can provide adjacent three-level scanning signals for the same scanning signal generating circuit, and the first luminescence provided by E1
  • the control signal and the second luminescence control signal provided by E2 can be adjacent two-stage luminescence control signals provided by the same luminescence control signal generation circuit, thereby reducing the number of scan signal generation circuits used by the display device, and the number of scan signal generation circuits used by the display device.
  • the number of light-emitting control signal generating circuits simplifies the structure and saves the cost.
  • the pixel driving circuit needs to turn on the driving transistor T0 in the data writing phase, therefore, the voltage difference Vi1-VDD between the first initial voltage Vi1 and the power supply voltage VDD A threshold voltage Vth smaller than T0 is required.
  • the absolute value of VDD can be greater than 1.5 times the absolute value of Vth, for example, the absolute value of VDD can be 1.6 times, 1.8 times, 2 times, etc. setting effect.
  • the voltage value of Vi1 is greater than or equal to -4V and less than or equal to -2V
  • the voltage value of VDD is greater than or equal to 4V and less than or equal to 5.5V
  • the voltage value of Vth is greater than or equal to -3.5V and less than or equal to -2V.
  • the voltage value of Vi2 is greater than or equal to -4V and less than or equal to -2V.
  • the driving method described in the embodiment of the present disclosure is applied to the above-mentioned pixel circuit, and the display period includes a reset phase; the driving method includes:
  • the first reset circuit controls to write the first initial voltage into the first node; under the control of the second light emission control signal, the first control circuit controls the The power supply voltage terminal communicates with the second node.
  • the first reset circuit writes the first initial voltage into the control terminal of the driving circuit
  • the first control circuit writes the first initial voltage into the control terminal of the driving circuit.
  • the power supply voltage is written into the first terminal of the drive circuit to provide bias voltage to the drive transistor in the drive circuit 11, so that the drive transistor remains in the reset state, and the hysteresis of the drive transistor is improved, thereby eliminating afterimages.
  • the pixel circuit further includes a data writing circuit, a threshold compensation circuit, a second reset circuit, and a coupling circuit;
  • the display cycle also includes a data writing phase and a light emitting phase set after the reset phase stage;
  • the driving method also includes:
  • the second reset circuit writes a second initial voltage into the first pole of the light-emitting element under the control of the second scan signal, so that the light-emitting element does not emit light;
  • the data writing circuit Under the control of the third scan signal, write the data voltage into the second node;
  • the threshold compensation circuit controls the communication between the first node and the third node;
  • the drive circuit controls the communication between the second node and the third node under the control of the potential of the first node, so as to charge the coupling circuit with the data voltage, so as to change the the potential of the first node until the driving circuit disconnects the connection between the second node and the third node;
  • the first control circuit controls the connection between the power supply voltage terminal and the second node under the control of the second light-emitting control signal; the second control circuit controls the second node under the control of the first light-emitting control signal
  • the three nodes are connected to the first pole of the light emitting element, and the driving circuit drives the light emitting element to emit light.
  • the display device described in the embodiment of the present disclosure includes the above-mentioned pixel circuit.
  • the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • the display device provided by at least one embodiment of the present disclosure may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.

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Abstract

一种像素电路、驱动方法和显示装置。像素电路包括发光元件（10）、驱动电路（11）、第一复位电路（12）、第一控制电路（13）和第二控制电路（14）；第一复位电路（12）在第一扫描信号的控制下，控制将第一初始电压（Vi1）写入第一节点（N1）；第一控制电路（13）在第二发光控制信号的控制下，控制电源电压端（Vd）与第二节点（N2）之间连通；第二控制电路（14）在第一发光控制信号的控制下，控制第三节点（N3）与发光元件（10）的第一极之间连通；驱动电路（11）在第一节点（N1）的电位的控制下，控制第二节点（N2）与第三节点（N3）之间连通；发光元件（10）的第二极与第一电压端（V1）电连接。

Description

像素电路、驱动方法和显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种像素电路、驱动方法和显示装置。
背景技术
相关技术中，像素驱动电路中驱动晶体管的栅极和源极之间存在寄生电容，像素驱动电路在复位阶段，驱动晶体管的栅极电压被初始化到初始电压，在上述寄生电容耦合作用下，驱动晶体管的源极电压也相应发生变化。复位阶段对不同灰阶复位时，驱动晶体管的栅极电压的变化量不同，从而驱动晶体管的源极电压的变化量也不同，进而导致复位阶段完成后驱动晶体管的源极电压不同，驱动晶体管的栅源电压Vgs也不同。同时由于驱动晶体管的栅源电压Vgs会影响其阈值电压，从而显示面板会发生残像问题。
发明内容
在一个方面中，本公开实施例提供了一种像素电路，包括发光元件、驱动电路、第一复位电路、第一控制电路和第二控制电路，其中，
所述第一复位电路分别与第一扫描线、第一初始电压端和第一节点连接，用于在所述第一扫描线提供的第一扫描信号的控制下，控制将所述第一初始电压端提供的第一初始电压写入所述第一节点；
所述第一控制电路分别与第二发光控制线、电源电压端和第二节点电连接，用于在所述第二发光控制线提供的第二发光控制信号的控制下，控制所述电源电压端与所述第二节点之间连通；
所述第二控制电路分别与第一发光控制线、第三节点和所述发光元件的第一极电连接，用于在所述第一发光控制线提供的第一发光控制信号的控制下，控制所述第三节点与所述发光元件的第一极之间连通；
所述驱动电路的控制端与所述第一节点电连接，所述驱动电路的第一端与所述第二节点电连接，所述驱动电路的第二端与所述第三节点电连接，所 述驱动电路用于在所述第一节点的电位的控制下，控制所述第二节点与所述第三节点之间连通；
所述发光元件的第二极与第一电压端电连接。
可选的，本公开至少一实施例所述的像素电路还包括数据写入电路和阈值补偿电路；
所述阈值补偿电路分别与第二扫描线、所述第一节点和所述第三节点电连接，用于在所述第二扫描线提供的第二扫描信号的控制下，控制所述第一节点与所述第三节点之间连通；
所述数据写入电路分别与第三扫描线、数据线和所述第二节点电连接，用于在所述第三扫描线提供的第三扫描信号的控制下，将所述数据线提供的数据电压写入所述第二节点。
可选的，本公开至少一实施例所述的像素电路还包括第二复位电路；所述第二复位电路分别与第二扫描线、第二初始电压端和所述发光元件的第一极电连接，用于在所述第二扫描线提供的第二扫描信号的控制下，将第二初始电压端提供的第二初始电压写入所述发光元件的第一极。
可选的，本公开至少一实施例还包括耦合电路；
所述耦合电路的第一端与所述第一节点电连接，所述耦合电路的第二端与所述电源电压端电连接，所述耦合电路用于储存电能，并控制所述第一节点的电位。
可选的，所述第一发光控制电路包括的晶体管与所述第二发光控制电路包括的晶体管都为p型晶体管；
所述第一发光控制信号与所述第二发光控制信号由同一发光控制信号生成电路提供；
所述第一发光控制信号为所述发光控制信号生成电路提供的第n级发光控制信号，所述第二发光控制信号为所述发光控制信号生成电路提供的第n+1级发光控制信号；n为正整数。
可选的，所述第一复位电路中的晶体管、所述第二复位电路中的晶体管、所述数据写入电路中的晶体管和所述阈值补偿电路中的晶体管都为p型晶体管；
所述第一扫描信号、所述第二扫描信号和所述第三扫描信号由同一扫描信号生成电路提供；
所述第一扫描信号为所述扫描信号生成电路提供的第m级扫描信号，所述第二扫描信号为所述扫描信号生成电路提供的第m+1级扫描信号，所述第三扫描信号为所述扫描信号生成电路提供的第m+2级扫描信号；m为正整数。
可选的，所述第一复位电路中的晶体管与所述阈值补偿电路中的晶体管为氧化物晶体管。
可选的，所述第一复位电路包括第一晶体管；
所述第一晶体管的控制极与所述第一扫描线电连接，所述第一晶体管的第一极与所述第一初始电压端电连接，所述第一晶体管的第二极与所述第一节点电连接。
可选的，所述第一控制电路包括第二晶体管，所述第二控制电路包括第三晶体管；
所述第二晶体管的控制极与所述第二发光控制线电连接，所述第二晶体管的第一极与所述电源电压端电连接，所述第二晶体管的第二极与所述第一节点电连接；
所述第三晶体管的控制极与所述第一发光控制线电连接，所述第三晶体管的第一极与所述第三节点电连接，所述第三晶体管的第二极与所述发光元件的第一极电连接。
可选的，所述数据写入电路包括第四晶体管，所述阈值补偿电路包括第五晶体管；
所述第四晶体管的控制极与所述第三扫描线电连接，所述第四晶体管的第一极与所述数据线电连接，所述第四晶体管的第二极与所述第二节点电连接；
所述第五晶体管的控制极与所述第二扫描线电连接，所述第五晶体管的第一极与所述第一节点电连接，所述第五晶体管的第二极与所述第三节点电连接。
可选的，所述第二复位电路包括第六晶体管；
所述第六晶体管的控制极与所述第二扫描线电连接，所述第六晶体管的 第一极与所述第二初始电压端电连接，所述第六晶体管的第二极与所述发光元件的第一极电连接；
所述耦合电路包括存储电容；
所述存储电容的第一端与所述第一节点电连接，所述存储电容的第二端与所述电源电压端电连接。
可选的，所述驱动电路包括驱动晶体管；
所述驱动晶体管的控制极与所述第一节点电连接，所述驱动晶体管的第一极与所述第二节点电连接，所述驱动晶体管的第二极与所述第三节点电连接。
在第二个方面中，本公开实施例还提供一种驱动方法，应用于上述的像素电路，显示周期包括复位阶段；所述驱动方法包括：
在所述复位阶段，第一复位电路在第一扫描信号的控制下，控制将第一初始电压写入第一节点；所述第一控制电路在第二发光控制信号的控制下，控制所述电源电压端与所述第二节点之间连通。
可选的，所述像素电路还包括数据写入电路、阈值补偿电路、第二复位电路和耦合电路；
显示周期还包括设置于所述复位阶段之后的数据写入阶段和发光阶段；所述驱动方法还包括：
在所述数据写入阶段，第二复位电路在所述第二扫描信号的控制下，将第二初始电压写入发光元件的第一极，以使得发光元件不发光；所述数据写入电路在第三扫描信号的控制下，将数据电压写入第二节点；所述阈值补偿电路在第二扫描信号的控制下，控制第一节点与第三节点之间连通；
在所述数据写入阶段开始时，驱动电路在第一节点的电位的控制下，控制所述第二节点与所述第三节点之间连通，以通过数据电压为耦合电路充电，以改变所述第一节点的电位，直至所述驱动电路断开所述第二节点与所述第三节点的连接；
在发光阶段，第一控制电路在第二发光控制信号的控制下，控制电源电压端与所述第二节点之间连通；所述第二控制电路在第一发光控制信号的控制下，控制第三节点与发光元件的第一极之间连通，驱动电路驱动发光元件 发光。
在第三个方面中，本公开实施例还提供了一种显示装置，包括上述的像素电路。
附图说明
图1是本公开实施例所述的像素电路的结构图；
图2是本公开至少一实施例所述的像素电路的结构图；
图3是本公开至少一实施例所述的像素电路的结构图；
图4是本公开至少一实施例所述的像素电路的电路图；
图5是本公开如图4所示的像素电路的至少一实施例的工作时序图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为三极管、薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除控制极之外的两极，将其中一极称为第一极，另一极称为第二极。
在实际操作时，当所述晶体管为薄膜晶体管或场效应管时，所述第一极可以为漏极，所述第二极可以为源极；或者，所述第一极可以为源极，所述第二极可以为漏极。
如图1所示，本公开实施例所述的像素电路包括发光元件10、驱动电路11、第一复位电路12、第一控制电路13和第二控制电路14，其中，
所述第一复位电路12分别与第一扫描线G1、第一初始电压端I1和第一节点N1连接，用于在所述第一扫描线G1提供的第一扫描信号的控制下，控制将所述第一初始电压端I1提供的第一初始电压Vi1写入所述第一节点N1；
所述第一控制电路13分别与第二发光控制线E2、电源电压端Vd和第二节点N2电连接，用于在所述第二发光控制线E2提供的第二发光控制信号的 控制下，控制所述电源电压端Vd与所述第二节点N2之间连通；所述电源电压端Vd用于提供电源电压VDD；
所述第二控制电路14分别与第一发光控制线E1、第三节点N3和所述发光元件10的第一极电连接，用于在所述第一发光控制线E1提供的第一发光控制信号的控制下，控制所述第三节点N3与所述发光元件10的第一极之间连通；
所述驱动电路11的控制端与所述第一节点N1电连接，所述驱动电路11的第一端与所述第二节点N2电连接，所述驱动电路11的第二端与所述第三节点N3电连接，所述驱动电路11用于在所述第一节点N1的电位的控制下，控制所述第二节点N2与所述第三节点N3之间连通；
所述发光元件的第二极与第一电压端V1电连接。
在本公开至少一实施例中，所述第一电压端V1可以为低电压端或地端，但不以此为限。
本公开如图1所示的像素电路的实施例在工作时，显示周期包括设置于数据写入阶段之前的复位阶段；
在所述复位阶段，第一复位电路12在第一扫描信号的控制下，控制将第一初始电压Vi1写入第一节点N1；所述第一控制电路14在第二发光控制信号的控制下，控制所述电源电压端Vd与所述第二节点N2之间连通。
本公开实施例所述的像素电路包括第一复位电路12和第一控制电路14，在数据电压写入驱动电路11第一端之前，第一复位电路12将第一初始电压Vi1写入驱动电路11的控制端，第一控制电路14在第二发光控制信号的控制下，控制将电源电压VDD写入驱动电路11的第一端，以对驱动电路11中的驱动晶体管提供偏压，使得驱动晶体管保持复位状态，改善驱动晶体管的迟滞，从而消除残像。
在具体实施时，驱动晶体管的迟滞会导致驱动晶体管的特性反应较迟钝，而本公开实施例在数据电压写入之前，快速复位驱动晶体管的栅源电压，利于驱动晶体管的恢复速度加快，因此会改善驱动晶体管的迟滞现象，提升迟滞恢复速度。
并且，在本公开实施例所述的像素电路中，第一控制电路13与第二发光 控制线E2电连接，在第二发光控制线E2提供的第二发光控制信号的控制下工作，第二控制电路14与第一发光控制线E1电连接，在第一发光控制线E1提供的第一发光控制信号的控制下工作，保证发光阶段时序正常运行，确保显示效果。
如图2所示，在图1所示的像素电路的实施例的基础上，本公开至少一实施例所述的像素电路还可以包括数据写入电路21和阈值补偿电路22；
所述阈值补偿电路22分别与第二扫描线G2、所述第一节点N1和所述第三节点N3电连接，用于在所述第二扫描线G2提供的第二扫描信号的控制下，控制所述第一节点N1与所述第三节点N3之间连通；
所述数据写入电路21分别与第三扫描线G3、数据线D1和所述第二节点N2电连接，用于在所述第三扫描线G3提供的第三扫描信号的控制下，将所述数据线D1提供的数据电压Vdata写入所述第二节点N2。
在本公开如图2所示的像素电路的至少一实施例中，所述第一复位电路12与第一扫描线G1电连接，在第一扫描信号的控制下工作；所述阈值补偿电路22与第二扫描线G2电连接，在第二扫描信号的控制下工作；所述数据写入电路21与第三扫描线G3电连接，在第三扫描信号的控制下工作；通过各扫描信号的配合，可以保证初始化和数据写入时序正常进行，保证初始化及阈值电压补偿效果。
本公开至少一实施例所述的像素电路还可以包括第二复位电路；所述第二复位电路分别与第二扫描线、第二初始电压端和所述发光元件的第一极电连接，用于在所述第二扫描线提供的第二扫描信号的控制下，将第二初始电压端提供的第二初始电压写入所述发光元件的第一极，以控制所述发光元件不发光，清除所述发光元件的第一极残留的电荷。
本公开至少一实施例所述的像素电路还可以包括耦合电路；
所述耦合电路的第一端与所述第一节点电连接，所述耦合电路的第二端与所述电源电压端电连接，所述耦合电路用于储存电能，并控制所述第一节点的电位。
如图3所示，在图2所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还包括第二复位电路31和耦合电路32；
所述第二复位电路31分别与第二扫描线G2、第二初始电压端I2和所述发光元件10的第一极电连接，用于在所述第二扫描线G2提供的第二扫描信号的控制下，将第二初始电压端I2提供的第二初始电压Vi2写入所述发光元件10的第一极；
所述耦合电路32的第一端与所述第一节点N1电连接，所述耦合电路32的第二端与所述电源电压端Vd电连接，所述耦合电路32用于储存电能，并控制所述第一节点N1的电位。
本公开如图3所示的像素电路的至少一实施例在工作时，显示周期还包括设置于所述复位阶段之后的数据写入阶段和发光阶段；
在所述数据写入阶段，第二复位电路31在所述第二扫描信号的控制下，将第二初始电压Vi2写入发光元件10的第一极，以使得发光元件10不发光；所述数据写入电路21在第三扫描信号的控制下，将数据电压Vdata写入第二节点N2；所述阈值补偿电路22在第二扫描信号的控制下，控制第一节点N1与第三节点N3之间连通；
在所述数据写入阶段开始时，驱动电路11在第一节点N1的电位的控制下，控制所述第二节点N2与所述第三节点N3之间连通，以通过数据电压Vdata为耦合电路32充电，以改变所述第一节点N1的电位，直至所述驱动电路11断开所述第二节点N2与所述第三节点N3的连接，此时，N1的电位为Vdata+Vth，Vth为驱动电路11中的驱动晶体管的阈值电压；
在发光阶段，第一控制电路13在第二发光控制信号的控制下，控制电源电压端Vd与所述第二节点N2之间连通；所述第二控制电路14在第一发光控制信号的控制下，控制第三节点N3与发光元件10的第一极之间连通，驱动电路11驱动发光元件10发光。
可选的，所述第一发光控制电路包括的晶体管与所述第二发光控制电路包括的晶体管都为p型晶体管；
所述第一发光控制信号与所述第二发光控制信号由同一发光控制信号生成电路提供；
所述第一发光控制信号为所述发光控制信号生成电路提供的第n级发光控制信号，所述第二发光控制信号为所述发光控制信号生成电路提供的第n+1 级发光控制信号；n为正整数。
在具体实施时，第一发光控制信号和第二发光控制信号可以为同一发光控制信号生成电路提供的相邻两级发光控制信号。
可选的，所述第一复位电路中的晶体管、所述第二复位电路中的晶体管、所述数据写入电路中的晶体管和所述阈值补偿电路中的晶体管都为p型晶体管；
所述第一扫描信号、所述第二扫描信号和所述第三扫描信号由同一扫描信号生成电路提供；
所述第一扫描信号为所述扫描信号生成电路提供的第m级扫描信号，所述第二扫描信号为所述扫描信号生成电路提供的第m+1级扫描信号，所述第三扫描信号为所述扫描信号生成电路提供的第m+2级扫描信号；m为正整数。
在具体实施时，所述第一扫描信号、所述第二扫描信号和所述第三扫描信号可以为同一扫描信号生成电路提供的相邻三级扫描信号。
在本公开至少一实施例中，所述第一复位电路中的晶体管与所述阈值补偿电路中的晶体管为氧化物晶体管。
氧化物晶体管漏电流低，同时Mobility(迁移率)较低。因此本公开至少一实施例可以将所述第一复位电路中的晶体管与所述阈值补偿电路中的晶体管设置为氧化物薄膜晶体管，实现低漏电，保证驱动电路的控制端的电位的稳定性；但不以此为限。
可选的，所述第一复位电路包括第一晶体管；
所述第一晶体管的控制极与所述第一扫描线电连接，所述第一晶体管的第一极与所述第一初始电压端电连接，所述第一晶体管的第二极与所述第一节点电连接。
可选的，所述第一控制电路包括第二晶体管，所述第二控制电路包括第三晶体管；
所述第二晶体管的控制极与所述第二发光控制线电连接，所述第二晶体管的第一极与所述电源电压端电连接，所述第二晶体管的第二极与所述第一节点电连接；
所述第三晶体管的控制极与所述第一发光控制线电连接，所述第三晶体 管的第一极与所述第三节点电连接，所述第三晶体管的第二极与所述发光元件的第一极电连接。
可选的，所述数据写入电路包括第四晶体管，所述阈值补偿电路包括第五晶体管；
所述第四晶体管的控制极与所述第三扫描线电连接，所述第四晶体管的第一极与所述数据线电连接，所述第四晶体管的第二极与所述第二节点电连接；
所述第五晶体管的控制极与所述第二扫描线电连接，所述第五晶体管的第一极与所述第一节点电连接，所述第五晶体管的第二极与所述第三节点电连接。
可选的，所述第二复位电路包括第六晶体管；
所述第六晶体管的控制极与所述第二扫描线电连接，所述第六晶体管的第一极与所述第二初始电压端电连接，所述第六晶体管的第二极与所述发光元件的第一极电连接；
所述耦合电路包括存储电容；
所述存储电容的第一端与所述第一节点电连接，所述存储电容的第二端与所述电源电压端电连接。
可选的，所述驱动电路包括驱动晶体管；
所述驱动晶体管的控制极与所述第一节点电连接，所述驱动晶体管的第一极与所述第二节点电连接，所述驱动晶体管的第二极与所述第三节点电连接。
如图4所示，在图3所示的像素电路的至少一实施例的基础上，在本公开至少一实施例所述的像素电路中，所述发光元件为有机发光二极管O1；
所述第一复位电路12包括第一晶体管T1；
所述第一晶体管T1的栅极与所述第一扫描线G1电连接，所述第一晶体管T1的源极与所述第一初始电压端I1电连接，所述第一晶体管T1的漏极与所述第一节点N1电连接；
所述第一控制电路13包括第二晶体管T2，所述第二控制电路14包括第三晶体管T3；
所述第二晶体管T2的栅极与所述第二发光控制线E2电连接，所述第二晶体管T2的源极与所述电源电压端Vd电连接，所述第二晶体管T2的漏极与所述第一节点N1电连接；所述电源电压端用于提供电源电压VDD；
所述第三晶体管T3的栅极与所述第一发光控制线E1电连接，所述第三晶体管T3的源极与所述第三节点N3电连接，所述第三晶体管T3的漏极与O1的阳极电连接；
O1的阴极与低电压端Vs电连接，所述低电压端用于提供低电压VSS；
所述数据写入电路21包括第四晶体管T4，所述阈值补偿电路22包括第五晶体管T5；
所述第四晶体管T4的栅极与所述第三扫描线G3电连接，所述第四晶体管T4的源极与所述数据线D1电连接，所述第四晶体管T4的漏极与所述第二节点N2电连接；
所述第五晶体管T5的栅极与所述第二扫描线G2电连接，所述第五晶体管T5的源极与所述第一节点N1电连接，所述第五晶体管T5的第二极与所述第三节点电连接；
所述第二复位电路31包括第六晶体管T6；
所述第六晶体管T6的栅极与所述第二扫描线G2电连接，所述第六晶体管T6的源极与所述第二初始电压端I2电连接，所述第六晶体管T6的漏极与O1的阳极电连接；
所述耦合电路32包括存储电容C1；
所述存储电容C1的第一端与所述第一节点N1电连接，所述存储电容C1的第二端与所述电源电压端Vd电连接；
所述驱动电路11包括驱动晶体管T0；
所述驱动晶体管T0的栅极与所述第一节点N1电连接，所述驱动晶体管T0的源极与所述第二节点N2电连接，所述驱动晶体管T0的漏极与所述第三节点N3电连接。
在图4所示的像素电路的至少一实施例中，所有的晶体管都为p型晶体管，所有的晶体管都可以为低温多晶硅晶体管，但不以此为限。
在图4所示的像素电路的至少一实施例中，T2和T3响应不同的发光控 制信号，T1、T5和T4响应不同的扫描信号，保证初始化、数据写入及阈值补偿、OLED(有机发光二极管)发光三个时序正常进行，从而确保阈值电压补偿及显示效果。
如图5所示，本公开如图4所示的像素电路的至少一实施例在工作时，显示周期可以包括先后设置的初始化阶段t1、数据写入阶段t2和发光阶段t3；
在初始化阶段t1，G1和E2提供低电压信号，G2、G3和E1提供高电压信号，T1和T2打开，以将Vi1写入N1，将VDD写入N2，以对T0的栅源电压进行复位，使得T0处于导通偏置状态，可以改善T0的迟滞效应从而消除残像；
在数据写入阶段t2，G1提供高电压信号，G2和G3提供低电压信号，E1和E2提供高电压信号，D1提供数据电压Vdata，T5、T4和T6都打开，将数据电压Vdata写入N2，控制N1和N3之间连通，并将Vi2写入O1的阳极，使得O1不发光，清除O1的阳极残留的电荷；
在数据写入阶段t2开始时，T0打开，以通过Vdata为C1充电，以提升N1的电位，直至N1的电位变为Vdata+Vth，T0关断；其中，Vth为T0的阈值电压；
在发光阶段t3，G1、G2和G3提供高电压信号，E1和E2提供低电压信号，T2和T3打开，T0驱动O1发光。
如图5所示，G1提供的第一扫描信号，G2提供的第二扫描信号和G3提供的第三扫描信号可以为同一扫描信号生成电路提供相邻三级扫描信号，E1提供的第一发光控制信号和E2提供的第二发光控制信号可以为同一发光控制信号生成电路提供的相邻两级发光控制信号，从而可以减少显示装置采用的扫描信号生成电路的个数，以及，显示装置采用的发光控制信号生成电路的个数，简化结构，节省成本。
在图5中，t1与t2之间的第一间隔时间段t01，以及，t2与t3之间的第二间隔时间段t02，为保证G1、G2和G3共用一扫描信号生成电路，保证E1和E2共用一发光控制信号生成电路的冗余时序。
如图4、图5所示，所述像素驱动电路的至少一实施例需要在数据写入阶段导通驱动晶体管T0，因此，第一初始电压Vi1与电源电压VDD之间的 电压差Vi1-VDD需要小于T0的阈值电压Vth。其中，VDD的绝对值可以大于Vth的绝对值的1.5倍，例如，VDD的绝对值可以为Vth的绝对值的1.6倍、1.8倍、2倍等，以保证在较短时间内能够快速达到偏置效果。
可选的，Vi1的电压值大于或等于-4V而小于或等于-2V，VDD的电压值大于或等于4V而小于或等于5.5V，Vth大于或等于-3.5V而小于或等于-2V。
在本公开至少一实施例中，Vi2的电压值大于或等于-4V而小于或等于-2V。
本公开实施例所述的驱动方法，应用于上述的像素电路，显示周期包括复位阶段；所述驱动方法包括：
在所述复位阶段，第一复位电路在第一扫描信号的控制下，控制将第一初始电压写入第一节点；所述第一控制电路在第二发光控制信号的控制下，控制所述电源电压端与所述第二节点之间连通。
本公开实施例所述的驱动方法在数据电压写入驱动电路的第一端之前，在初始化阶段，第一复位电路将第一初始电压写入驱动电路的控制端，第一控制电路在第二发光控制信号的控制下，控制将电源电压写入驱动电路的第一端，以对驱动电路11中的驱动晶体管提供偏压，使得驱动晶体管保持复位状态，改善驱动晶体管的迟滞，从而消除残像。
在本公开至少一实施例中，所述像素电路还包括数据写入电路、阈值补偿电路、第二复位电路和耦合电路；显示周期还包括设置于所述复位阶段之后的数据写入阶段和发光阶段；所述驱动方法还包括：
在所述数据写入阶段，第二复位电路在所述第二扫描信号的控制下，将第二初始电压写入发光元件的第一极，以使得发光元件不发光；所述数据写入电路在第三扫描信号的控制下，将数据电压写入第二节点；所述阈值补偿电路在第二扫描信号的控制下，控制第一节点与第三节点之间连通；
在所述数据写入阶段开始时，驱动电路在第一节点的电位的控制下，控制所述第二节点与所述第三节点之间连通，以通过数据电压为耦合电路充电，以改变所述第一节点的电位，直至所述驱动电路断开所述第二节点与所述第三节点的连接；
在发光阶段，第一控制电路在第二发光控制信号的控制下，控制电源电 压端与所述第二节点之间连通；所述第二控制电路在第一发光控制信号的控制下，控制第三节点与发光元件的第一极之间连通，驱动电路驱动发光元件发光。
本公开实施例所述的显示装置包括上述的像素电路。
本公开实施例所提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开至少一实施例所提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (15)

  1. 一种像素电路，包括发光元件、驱动电路、第一复位电路、第一控制电路和第二控制电路，其中，
    所述第一复位电路分别与第一扫描线、第一初始电压端和第一节点连接，用于在所述第一扫描线提供的第一扫描信号的控制下，控制将所述第一初始电压端提供的第一初始电压写入所述第一节点；
    所述第一控制电路分别与第二发光控制线、电源电压端和第二节点电连接，用于在所述第二发光控制线提供的第二发光控制信号的控制下，控制所述电源电压端与所述第二节点之间连通；
    所述第二控制电路分别与第一发光控制线、第三节点和所述发光元件的第一极电连接，用于在所述第一发光控制线提供的第一发光控制信号的控制下，控制所述第三节点与所述发光元件的第一极之间连通；
    所述驱动电路的控制端与所述第一节点电连接，所述驱动电路的第一端与所述第二节点电连接，所述驱动电路的第二端与所述第三节点电连接，所述驱动电路用于在所述第一节点的电位的控制下，控制所述第二节点与所述第三节点之间连通；
    所述发光元件的第二极与第一电压端电连接。
  2. 如权利要求1所述的像素电路，其中，还包括数据写入电路和阈值补偿电路；
    所述阈值补偿电路分别与第二扫描线、所述第一节点和所述第三节点电连接，用于在所述第二扫描线提供的第二扫描信号的控制下，控制所述第一节点与所述第三节点之间连通；
    所述数据写入电路分别与第三扫描线、数据线和所述第二节点电连接，用于在所述第三扫描线提供的第三扫描信号的控制下，将所述数据线提供的数据电压写入所述第二节点。
  3. 如权利要求2所述的像素电路，其中，还包括第二复位电路；所述第二复位电路分别与第二扫描线、第二初始电压端和所述发光元件的第一极电连接，用于在所述第二扫描线提供的第二扫描信号的控制下，将第二初始电 压端提供的第二初始电压写入所述发光元件的第一极。
  4. 如权利要求1至3中任一权利要求所述的像素电路，其中，还包括耦合电路；
    所述耦合电路的第一端与所述第一节点电连接，所述耦合电路的第二端与所述电源电压端电连接，所述耦合电路用于储存电能，并控制所述第一节点的电位。
  5. 如权利要求1所述的像素电路，其中，所述第一发光控制电路包括的晶体管与所述第二发光控制电路包括的晶体管都为p型晶体管；
    所述第一发光控制信号与所述第二发光控制信号由同一发光控制信号生成电路提供；
    所述第一发光控制信号为所述发光控制信号生成电路提供的第n级发光控制信号，所述第二发光控制信号为所述发光控制信号生成电路提供的第n+1级发光控制信号；n为正整数。
  6. 如权利要求3所述的像素电路，其中，所述第一复位电路中的晶体管、所述第二复位电路中的晶体管、所述数据写入电路中的晶体管和所述阈值补偿电路中的晶体管都为p型晶体管；
    所述第一扫描信号、所述第二扫描信号和所述第三扫描信号由同一扫描信号生成电路提供；
    所述第一扫描信号为所述扫描信号生成电路提供的第m级扫描信号，所述第二扫描信号为所述扫描信号生成电路提供的第m+1级扫描信号，所述第三扫描信号为所述扫描信号生成电路提供的第m+2级扫描信号；m为正整数。
  7. 如权利要求2所述的像素电路，其中，所述第一复位电路中的晶体管与所述阈值补偿电路中的晶体管为氧化物晶体管。
  8. 如权利要求1所述的像素电路，其中，所述第一复位电路包括第一晶体管；
    所述第一晶体管的控制极与所述第一扫描线电连接，所述第一晶体管的第一极与所述第一初始电压端电连接，所述第一晶体管的第二极与所述第一节点电连接。
  9. 如权利要求1所述的像素电路，其中，所述第一控制电路包括第二晶 体管，所述第二控制电路包括第三晶体管；
    所述第二晶体管的控制极与所述第二发光控制线电连接，所述第二晶体管的第一极与所述电源电压端电连接，所述第二晶体管的第二极与所述第一节点电连接；
    所述第三晶体管的控制极与所述第一发光控制线电连接，所述第三晶体管的第一极与所述第三节点电连接，所述第三晶体管的第二极与所述发光元件的第一极电连接。
  10. 如权利要求2所述的像素电路，其中，所述数据写入电路包括第四晶体管，所述阈值补偿电路包括第五晶体管；
    所述第四晶体管的控制极与所述第三扫描线电连接，所述第四晶体管的第一极与所述数据线电连接，所述第四晶体管的第二极与所述第二节点电连接；
    所述第五晶体管的控制极与所述第二扫描线电连接，所述第五晶体管的第一极与所述第一节点电连接，所述第五晶体管的第二极与所述第三节点电连接。
  11. 如权利要求3所述的像素电路，其中，所述第二复位电路包括第六晶体管；
    所述第六晶体管的控制极与所述第二扫描线电连接，所述第六晶体管的第一极与所述第二初始电压端电连接，所述第六晶体管的第二极与所述发光元件的第一极电连接；
    所述耦合电路包括存储电容；
    所述存储电容的第一端与所述第一节点电连接，所述存储电容的第二端与所述电源电压端电连接。
  12. 如权利要求1至3中任一权利要求所述的像素电路，其中，所述驱动电路包括驱动晶体管；
    所述驱动晶体管的控制极与所述第一节点电连接，所述驱动晶体管的第一极与所述第二节点电连接，所述驱动晶体管的第二极与所述第三节点电连接。
  13. 一种驱动方法，应用于如权利要求1至12中任一权利要求所述的像 素电路，显示周期包括复位阶段；所述驱动方法包括：
    在所述复位阶段，第一复位电路在第一扫描信号的控制下，控制将第一初始电压写入第一节点；所述第一控制电路在第二发光控制信号的控制下，控制所述电源电压端与所述第二节点之间连通。
  14. 如权利要求13所述的驱动方法，其中，所述像素电路还包括数据写入电路、阈值补偿电路、第二复位电路和耦合电路；
    显示周期还包括设置于所述复位阶段之后的数据写入阶段和发光阶段；所述驱动方法还包括：
    在所述数据写入阶段，第二复位电路在所述第二扫描信号的控制下，将第二初始电压写入发光元件的第一极，以使得发光元件不发光；所述数据写入电路在第三扫描信号的控制下，将数据电压写入第二节点；所述阈值补偿电路在第二扫描信号的控制下，控制第一节点与第三节点之间连通；
    在所述数据写入阶段开始时，驱动电路在第一节点的电位的控制下，控制所述第二节点与所述第三节点之间连通，以通过数据电压为耦合电路充电，以改变所述第一节点的电位，直至所述驱动电路断开所述第二节点与所述第三节点的连接；
    在发光阶段，第一控制电路在第二发光控制信号的控制下，控制电源电压端与所述第二节点之间连通；所述第二控制电路在第一发光控制信号的控制下，控制第三节点与发光元件的第一极之间连通，驱动电路驱动发光元件发光。
  15. 一种显示装置，包括如权利要求1至12中任一权利要求所述的像素电路。
PCT/CN2021/119405 2021-09-18 2021-09-18 像素电路、驱动方法和显示装置 WO2023039891A1 (zh)

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