WO2023245675A1 - 像素电路、驱动方法和显示装置 - Google Patents

像素电路、驱动方法和显示装置 Download PDF

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Publication number
WO2023245675A1
WO2023245675A1 PCT/CN2022/101321 CN2022101321W WO2023245675A1 WO 2023245675 A1 WO2023245675 A1 WO 2023245675A1 CN 2022101321 W CN2022101321 W CN 2022101321W WO 2023245675 A1 WO2023245675 A1 WO 2023245675A1
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Prior art keywords
control
circuit
terminal
electrically connected
transistor
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PCT/CN2022/101321
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English (en)
French (fr)
Inventor
刘伟星
王新星
彭锦涛
徐智强
张春芳
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/101321 priority Critical patent/WO2023245675A1/zh
Priority to CN202280001911.9A priority patent/CN117882128A/zh
Publication of WO2023245675A1 publication Critical patent/WO2023245675A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a pixel circuit, a driving method and a display device.
  • OLED Organic Light Emitting Diode
  • the related pixel circuit cannot be used for multi-grayscale display, cannot achieve super-conventional 256 grayscale display, and cannot increase the number of displayed grayscales without significantly increasing the cost.
  • an embodiment of the present disclosure provides a pixel circuit including a light emitting element, a first driving circuit, a second driving circuit, a first control circuit, a setting circuit, a first energy storage circuit, a second control circuit and Control data voltage writing circuit;
  • the first drive circuit is configured to generate a drive current flowing from the first end of the first drive circuit to the second end of the first drive circuit under the control of the potential of its control end;
  • the second end of the first driving circuit is electrically connected to the first end of the second driving circuit
  • the first control circuit is electrically connected to the first node, the control terminal of the first driving circuit and the control terminal of the second driving circuit respectively, and is used to control all the voltages under the control of the potential of the first node.
  • the control end of the first drive circuit and the control end of the second drive circuit are connected or disconnected;
  • the setting circuit is electrically connected to the first node, the first setting voltage terminal and the control terminal of the second driving circuit respectively, and is used to set the first setting circuit under the control of the potential of the first node.
  • the first setting voltage provided by the bit voltage terminal is written into the control terminal of the second driving circuit; the first node is electrically connected to the first terminal of the first energy storage circuit, and the first energy storage circuit
  • the second end is electrically connected to the first setting voltage end; the first energy storage circuit is used to store electrical energy;
  • the second control circuit is used to provide the second setting voltage to the control end of the first drive circuit under the control of the control signal provided by the charging control end, and to control the control end of the first drive circuit and the connected node. are connected or disconnected; the connected node is electrically connected to the second end of the second drive circuit, or the connected node is electrically connected to the first end of the first drive circuit;
  • the control data voltage writing circuit is electrically connected to the first writing control terminal, the control data voltage writing terminal and the first node respectively, and is used for the first writing control provided at the first writing control terminal. Under the control of the signal, write the control data voltage provided by the control data voltage writing terminal into the first node;
  • the second driving circuit is used to drive the light-emitting element under the control of the potential of its control terminal, or to control the connection between the first terminal of the second driving circuit and the second terminal of the second driving circuit. or disconnected.
  • the second control circuit includes a first control sub-circuit and a second control sub-circuit;
  • the charging control terminal includes a first control terminal and a second control terminal;
  • the connection node and the second drive circuit The second end is electrically connected;
  • the first control sub-circuit is electrically connected to the first control terminal, the second setting voltage terminal and the control terminal of the first drive circuit respectively, and is used for controlling the first control signal provided at the first control terminal. Next, write the second setting voltage provided by the second setting voltage terminal into the control terminal of the first driving circuit;
  • the second control sub-circuit is electrically connected to the second control terminal, the control terminal of the first driving circuit and the second terminal of the second driving circuit respectively, for providing the second control terminal at the second control terminal. Under the control of the control signal, the control terminal of the first driving circuit and the second terminal of the second driving circuit are controlled to be connected.
  • the second control circuit includes a first control sub-circuit and a second control sub-circuit;
  • the charging control terminal includes a first control terminal and a second control terminal;
  • the connection node and the first drive circuit The first end is electrically connected;
  • the first control sub-circuit is electrically connected to the first control terminal, the second setting voltage terminal and the first terminal of the first drive circuit respectively, and is used for controlling the first control signal provided at the first control terminal. Under control, write the second setting voltage provided by the second setting voltage terminal into the first terminal of the first driving circuit;
  • the second control sub-circuit is electrically connected to the second control terminal, the control terminal of the first driving circuit and the first terminal of the first driving circuit respectively, for providing the second control terminal at the second control terminal. Under the control of the control signal, the control terminal of the first driving circuit is controlled to be connected to the first terminal of the first driving circuit.
  • the pixel circuit also includes a data writing circuit, a first light emission control circuit, a second light emission control circuit and a second energy storage circuit;
  • the data writing circuit is electrically connected to the second writing control terminal, the data line and the first terminal of the first driving circuit respectively, and is used for providing the second writing control signal at the second writing control terminal. Under the control of the data line, write the data voltage provided by the data line into the first end of the first driving circuit;
  • the first lighting control circuit is electrically connected to the lighting control terminal, the power supply voltage terminal and the first terminal of the first driving circuit respectively, and is used to control the lighting control signal under the control of the lighting control signal provided by the lighting control terminal.
  • the power supply voltage terminal is connected or disconnected from the first terminal of the first driving circuit;
  • the second light-emitting control circuit is electrically connected to the light-emitting control terminal, the second terminal of the second driving circuit and the first pole of the light-emitting element respectively, and is used to control the light-emitting control signal under the control of the light-emitting control signal.
  • the second terminal of the second driving circuit is connected to the first pole of the light-emitting element;
  • the first end of the second energy storage circuit is electrically connected to the control end of the first drive circuit, and the second end of the second energy storage circuit is electrically connected to the power supply voltage end.
  • the circuit is used to store electrical energy; the second pole of the light-emitting element is electrically connected to the first voltage terminal.
  • the pixel circuit also includes a light-emitting element, a data writing circuit, a first light-emitting control circuit, a second light-emitting control circuit and a second energy storage circuit; the first light-emitting element The pole is electrically connected to the power supply voltage terminal;
  • the data writing circuit is electrically connected to the second writing control terminal, the data line and the second terminal of the second driving circuit respectively, and is used for providing the second writing control signal at the second writing control terminal. Under the control of the data line, write the data voltage provided by the data line to the second end of the second driving circuit;
  • the first light-emitting control circuit is electrically connected to the light-emitting control terminal, the second pole of the light-emitting element and the first terminal of the first driving circuit respectively, and is used for controlling the light-emitting control signal provided at the light-emitting control terminal. down, controlling the connection between the second pole of the light-emitting element and the first end of the first driving circuit;
  • the second lighting control circuit is electrically connected to the lighting control terminal, the second terminal and the first voltage terminal of the second driving circuit respectively, and is used to control the second lighting control circuit under the control of the lighting control signal.
  • the second terminal of the driving circuit is connected to the first voltage terminal;
  • the first end of the second energy storage circuit is electrically connected to the control end of the first drive circuit, the second end of the second energy storage circuit is electrically connected to the first voltage end, and the second end of the second energy storage circuit is electrically connected to the first voltage end.
  • Energy circuits are used to store electrical energy.
  • the first control circuit includes a first transistor
  • the control electrode of the first transistor is electrically connected to the first node, the first electrode of the first transistor is electrically connected to the control end of the first drive circuit, and the second electrode of the first transistor is electrically connected to the first node.
  • the control terminal of the second driving circuit is electrically connected;
  • the setting circuit includes a second transistor
  • the control electrode of the second transistor is electrically connected to the first node, the first electrode of the second transistor is electrically connected to the first setting voltage terminal, and the second electrode of the second transistor is electrically connected to the first node.
  • the control terminal of the second driving circuit is electrically connected;
  • the control data voltage writing circuit includes a third transistor
  • the control electrode of the third transistor is electrically connected to the first writing control terminal, the first electrode of the third transistor is electrically connected to the control data voltage writing terminal, and the second electrode of the third transistor is electrically connected to the control data voltage writing terminal. electrically connected to the first node;
  • the first energy storage circuit includes a first capacitor
  • the first node is electrically connected to the first terminal of the first capacitor, and the second terminal of the first capacitor is electrically connected to the first setting voltage terminal.
  • the first control sub-circuit includes a fourth transistor, and the second control sub-circuit includes a fifth transistor;
  • the control electrode of the fourth transistor is electrically connected to the first control terminal, the first electrode of the fourth transistor is electrically connected to the second setting voltage terminal, and the second electrode of the fourth transistor is electrically connected to the first control terminal.
  • the control terminal of the first driving circuit is electrically connected;
  • the control electrode of the fifth transistor is electrically connected to the second control terminal
  • the first electrode of the fifth transistor is electrically connected to the control terminal of the first drive circuit
  • the second electrode of the fifth transistor is electrically connected to The second terminal of the second driving circuit is electrically connected.
  • the first control sub-circuit includes a fourth transistor, and the second control sub-circuit includes a fifth transistor;
  • the control electrode of the fourth transistor is electrically connected to the first control terminal, the first electrode of the fourth transistor is electrically connected to the second setting voltage terminal, and the second electrode of the fourth transistor is electrically connected to the first control terminal.
  • the control terminal of the first driving circuit is electrically connected;
  • the control electrode of the fifth transistor is electrically connected to the second control terminal, the first electrode of the fifth transistor is electrically connected to the control terminal of the first drive circuit, and the second electrode of the fifth transistor is electrically connected to The first terminal of the first driving circuit is electrically connected.
  • the light-emitting element is an organic light-emitting diode
  • the data writing circuit includes a sixth transistor
  • the first light-emitting control circuit includes a seventh transistor
  • the second light-emitting control circuit includes an eighth transistor
  • the The second energy storage circuit includes a second capacitor
  • the control electrode of the sixth transistor is electrically connected to the second write control terminal, the first electrode of the sixth transistor is electrically connected to the data line, and the second electrode of the sixth transistor is electrically connected to the third write control terminal.
  • a first terminal of a driving circuit is electrically connected;
  • the control electrode of the seventh transistor is electrically connected to the light-emitting control terminal, the first electrode of the seventh transistor is electrically connected to the power supply voltage terminal, and the second electrode of the seventh transistor is electrically connected to the first drive terminal.
  • the first end of the circuit is electrically connected;
  • the control electrode of the eighth transistor is electrically connected to the light-emitting control terminal, the first electrode of the eighth transistor is electrically connected to the second terminal of the second driving circuit, and the second electrode of the eighth transistor is electrically connected to The anode of the organic light-emitting diode is electrically connected;
  • the first end of the second capacitor is electrically connected to the control end of the first drive circuit, the second end of the second capacitor is electrically connected to the power supply voltage end; the cathode of the organic light emitting diode is electrically connected to the first The voltage terminals are electrically connected.
  • the light-emitting element is an organic light-emitting diode
  • the data writing circuit includes a sixth transistor
  • the first light-emitting control circuit includes a seventh transistor
  • the second light-emitting control circuit includes an eighth transistor
  • the The second energy storage circuit includes a second capacitor
  • the anode of the organic light-emitting diode is electrically connected to the power supply voltage terminal
  • the control electrode of the sixth transistor is electrically connected to the second write control terminal, the first electrode of the sixth transistor is electrically connected to the data line, and the second electrode of the sixth transistor is electrically connected to the third write control terminal.
  • the second terminals of the two driving circuits are electrically connected;
  • the control electrode of the seventh transistor is electrically connected to the light-emitting control terminal, the first electrode of the seventh transistor is electrically connected to the cathode of the organic light-emitting diode, and the second electrode of the seventh transistor is electrically connected to the third electrode.
  • a first terminal of a driving circuit is electrically connected;
  • the control electrode of the eighth transistor is electrically connected to the light-emitting control terminal, the first electrode of the eighth transistor is electrically connected to the second terminal of the second driving circuit, and the second electrode of the eighth transistor is electrically connected to The first voltage terminal is electrically connected;
  • the first end of the second capacitor is electrically connected to the control end of the first drive circuit, and the second end of the second capacitor is electrically connected to the first voltage end.
  • the first driving circuit includes a first driving transistor
  • the second driving circuit includes a second driving transistor
  • the control electrode of the first driving transistor is electrically connected to the control terminal of the first driving circuit, the first electrode of the first driving transistor is electrically connected to the first terminal of the first driving circuit, and the first driving transistor is electrically connected to the control terminal of the first driving circuit.
  • the second pole of the driving transistor is electrically connected to the second terminal of the first driving circuit;
  • the control terminal of the second driving transistor is electrically connected to the control terminal of the second driving circuit
  • the first terminal of the second driving transistor is electrically connected to the first terminal of the second driving circuit
  • the second driving transistor is electrically connected to the control terminal of the second driving circuit.
  • the second pole of the driving transistor is electrically connected to the second terminal of the second driving circuit.
  • an embodiment of the present disclosure provides a driving method applied to the above-mentioned pixel circuit.
  • the driving method includes:
  • the first control circuit controls the connection or disconnection between the control end of the first drive circuit and the control end of the second drive circuit under the control of the potential of the first node;
  • the setting circuit writes the first setting voltage provided by the first setting voltage terminal into the control terminal of the second driving circuit under the control of the potential of the first node;
  • the second control circuit is used to provide the second setting voltage to the control end of the first drive circuit under the control of the control signal provided by the charging control end, and to control the connection between the control end of the first drive circuit and the connected node. Connect or disconnect;
  • the control data voltage writing circuit writes the control data voltage provided by the control data voltage writing terminal into the first node under the control of the first writing control signal
  • the first drive circuit generates a drive current flowing from the first end of the first drive circuit to the second end of the first drive circuit under the control of the potential of its control end;
  • the second driving circuit drives the light-emitting element under the control of the potential of its control terminal, or the second driving circuit controls the first terminal of the second driving circuit and the potential of the second driving circuit under the control of the potential of its control terminal.
  • the second terminals of the second driving circuit are connected or disconnected.
  • the second control circuit includes a first control sub-circuit and a second control sub-circuit; the connecting node is electrically connected to the second end of the second driving circuit; the pixel circuit also includes a light-emitting element and a data writing circuit. , a first light-emitting control circuit, a second light-emitting control circuit and a second energy storage circuit; the display cycle includes a first stage, a second stage and a third stage that are set successively; the driving method includes:
  • the first control sub-circuit writes the second setting voltage provided by the second setting voltage terminal into the control terminal of the first driving circuit under the control of the first control signal; controls the data voltage
  • the writing circuit writes the control data voltage provided by the control data voltage writing terminal into the first node under the control of the first writing control signal provided by the first writing control terminal;
  • the first control circuit controls the control end of the first drive circuit and the second drive circuit under the control of the potential of the first node.
  • the control terminals are connected; when the control data voltage is the third voltage signal, the setting circuit writes the first setting voltage provided by the first setting voltage terminal under the control of the potential of the first node.
  • the control end of the second drive circuit is connected;
  • the data writing circuit writes the data voltage provided by the data line into the first end of the first driving circuit under the control of the second writing control signal;
  • the second control sub-circuit Under the control of the second control signal, control the connection between the control end of the first drive circuit and the second end of the second drive circuit;
  • the first lighting control circuit controls the connection between the power supply voltage terminal and the first terminal of the first driving circuit under the control of the lighting control signal;
  • the second lighting control circuit controls the connection between the power supply voltage terminal and the first terminal of the first driving circuit.
  • the first control circuit controls the connection between the control end of the first drive circuit and the control end of the second drive circuit under the control of the potential of the first node, in the In the third stage, the first driving circuit and the second driving circuit drive the light-emitting element to emit light;
  • the setting circuit When in the first stage, the setting circuit writes the first setting voltage provided by the first setting voltage terminal into the control terminal of the second driving circuit under the control of the potential of the first node.
  • the first driving circuit drives the light-emitting element to emit light
  • the second driving circuit controls the first end of the second driving circuit and the second end of the second driving circuit. connected between.
  • the second control circuit includes a first control sub-circuit and a second control sub-circuit; the connection node is electrically connected to the first end of the first drive circuit; the pixel circuit also includes a light-emitting element, A data writing circuit, a first light-emitting control circuit, a second light-emitting control circuit and a second energy storage circuit; the display cycle includes a first stage, a second stage and a third stage that are set successively; the driving method includes:
  • the first control sub-circuit writes the second setting voltage provided by the second setting voltage terminal into the first terminal of the first driving circuit under the control of the first control signal; Under the control of the second control signal, the second control sub-circuit controls the connection between the control end of the first driving circuit and the first end of the first driving circuit; controls the data voltage writing circuit to perform the first writing operation. Under the control of the first write control signal provided by the control terminal, write the control data voltage provided by the control data voltage writing terminal into the first node;
  • the first control circuit controls the control end of the first drive circuit and the second drive circuit under the control of the potential of the first node.
  • the control terminals are connected; when the control data voltage is the fifth voltage signal, the setting circuit writes the first setting voltage provided by the first setting voltage terminal under the control of the potential of the first node.
  • the control end of the second drive circuit is a fourth voltage signal
  • the data writing circuit writes the data voltage provided by the data line into the second end of the second driving circuit under the control of the second writing control signal;
  • the second control signal The sub-circuit controls the connection between the control end of the first drive circuit and the first end of the first drive circuit under the control of the second control signal;
  • the first light-emitting control circuit controls the connection between the second pole of the light-emitting element and the first end of the first driving circuit under the control of the light-emitting control signal;
  • the second The lighting control circuit controls the connection between the second terminal of the second driving circuit and the first voltage terminal under the control of the lighting control signal;
  • the first control circuit controls the connection between the control end of the first drive circuit and the control end of the second drive circuit under the control of the potential of the first node, in the In the third stage, the first driving circuit and the second driving circuit drive the light-emitting element to emit light;
  • the setting circuit When in the first stage, the setting circuit writes the first setting voltage provided by the first setting voltage terminal into the control terminal of the second driving circuit under the control of the potential of the first node.
  • the first driving circuit drives the light-emitting element to emit light
  • the second driving circuit controls the first end of the second driving circuit and the second end of the second driving circuit. connected between.
  • an embodiment of the present disclosure provides a display device including the above-mentioned pixel circuit.
  • Figure 1 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure
  • Figure 2 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure
  • Figure 3 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 4 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 5 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 6 is an operating timing diagram of at least one embodiment of the pixel circuit shown in Figure 5 of the present disclosure.
  • Figure 7 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG. 8 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 7 of the present disclosure.
  • the transistors used in all embodiments of the present disclosure may be transistors, thin film transistors, field effect transistors, or other devices with the same characteristics.
  • one pole is called the first pole and the other pole is called the second pole.
  • the control electrode when the transistor is a triode, the control electrode may be a base electrode, the first electrode may be a collector, and the second electrode may be an emitter; or, the control electrode may be a base electrode. pole, the first pole may be an emitter, and the second pole may be a collector.
  • the control electrode when the transistor is a thin film transistor or a field effect transistor, the control electrode may be a gate electrode, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, The control electrode may be a gate electrode, the first electrode may be a source electrode, and the second electrode may be a drain electrode.
  • the pixel circuit described in the embodiment of the present disclosure includes a light-emitting element, a first driving circuit, a second driving circuit, a first control circuit, a setting circuit, a first energy storage circuit, a second control circuit and a control data voltage writing circuit;
  • the first drive circuit is configured to generate a drive current flowing from the first end of the first drive circuit to the second end of the first drive circuit under the control of the potential of its control end;
  • the second end of the first driving circuit is electrically connected to the first end of the second driving circuit 12;
  • the first control circuit is electrically connected to the first node m, the control end of the first drive circuit and the control end of the second drive circuit respectively, and is used to control the potential of the first node m, Control the connection or disconnection between the control end of the first drive circuit and the control end of the second drive circuit;
  • the setting circuit is electrically connected to the first node, the first setting voltage terminal and the control terminal of the second driving circuit respectively, and is used to set the first setting circuit under the control of the potential of the first node.
  • the first set voltage provided by the bit voltage terminal is written into the control terminal of the second driving circuit;
  • the first node is electrically connected to the first terminal of the first energy storage circuit, and the first energy storage circuit
  • the second end is electrically connected to the first setting voltage end; the first energy storage circuit is used to store electrical energy;
  • the second control circuit is used to provide the second setting voltage to the control end of the first drive circuit under the control of the control signal provided by the charging control end, and to control the control end of the first drive circuit and the connected node. connected or disconnected; the connected node is electrically connected to the second end of the second drive circuit, or the connected node is electrically connected to the first end of the first drive circuit;
  • the control data voltage writing circuit is electrically connected to the first writing control terminal, the control data voltage writing terminal and the first node respectively, and is used for the first writing control provided at the first writing control terminal. Under the control of the signal, write the control data voltage provided by the control data voltage writing terminal into the first node;
  • the second driving circuit is used to drive the light-emitting element under the control of the potential of its control terminal, or to control the connection between the first terminal of the second driving circuit and the second terminal of the second driving circuit. or disconnected.
  • the first driving circuit and the second driving circuit are used to drive the light-emitting element to emit light during low gray-scale display, and the first driving circuit is used to drive the light-emitting element during high gray-scale display.
  • the second driving transistor included in the second driving circuit is fully turned on;
  • the SS swing (sub-threshold swing) of the first drive transistor included in the first drive circuit is consistent with the SS swing of the second drive transistor included in the second drive circuit, and may share a data voltage value range.
  • the width-to-length ratio of the first driving transistor is different from the width-to-length ratio of the second driving transistor, and the width-to-length ratio of the second driving transistor is greater than that of the first driving transistor.
  • Width-to-length ratio for example, the width-to-length ratio of the second driving transistor may be twice the width-to-length ratio of the first driving transistor, but is not limited to this.
  • the pixel circuit described in the embodiment of the present disclosure can be used for multi-grayscale display, achieving an extraordinary 256 grayscale display, and can increase the number of displayed grayscales without significantly increasing the cost.
  • the second control circuit includes a first control sub-circuit and a second control sub-circuit; the charging control end includes a first control end and a second control end; the connected node is The second terminal of the second driving circuit is electrically connected;
  • the first control sub-circuit is electrically connected to the first control terminal, the second setting voltage terminal and the control terminal of the first drive circuit respectively, and is used for controlling the first control signal provided at the first control terminal.
  • the second control sub-circuit is electrically connected to the second control terminal, the control terminal of the first driving circuit and the second terminal of the second driving circuit respectively, for providing the second control terminal at the second control terminal. Under the control of the control signal, the control terminal of the first driving circuit and the second terminal of the second driving circuit are controlled to be connected.
  • the pixel circuit includes a light-emitting element E0, a first driving circuit 11, a second driving circuit 12, a first control circuit 13, a setting circuit 14, and a first energy storage circuit. 15.
  • the second control circuit includes a first control sub-circuit 161 and a second control sub-circuit 162; the charging control terminal includes a first control terminal S1 and a second control terminal S2; the connecting node and the second drive circuit 12 The second terminal is electrically connected;
  • the first drive circuit 11 is used to generate a drive current flowing from the first end of the first drive circuit 11 to the second end of the first drive circuit 11 under the control of the potential of its control end;
  • the second end of the first driving circuit 11 is electrically connected to the first end of the second driving circuit 12;
  • the first control circuit 13 is electrically connected to the first node m, the control end of the first drive circuit 11 and the control end of the second drive circuit 12 respectively, and is used to adjust the potential of the first node m. Under control, control the connection or disconnection between the control end of the first drive circuit 11 and the control end of the second drive circuit 12;
  • the setting circuit 14 is electrically connected to the first node m, the first setting voltage terminal Vz1 and the control terminal of the second driving circuit 12 respectively, and is used to control the voltage of the first node m under the control of the potential of the first node m.
  • the first setting voltage provided by the first setting voltage terminal Vz1 is written into the control terminal of the second driving circuit 12;
  • the first node m is electrically connected to the first end of the first energy storage circuit 15, and the second end of the first energy storage circuit 15 is electrically connected to the first setting voltage terminal Vz1; the third An energy storage circuit 15 is used to store electrical energy;
  • the first control sub-circuit 161 is electrically connected to the first control terminal S1, the second setting voltage terminal Vz2 and the control terminal of the first drive circuit 11 respectively, for providing the third control terminal S1 at the first control terminal S1. Under the control of a control signal, the second setting voltage provided by the second setting voltage terminal Vz2 is written into the control terminal of the first driving circuit 11 to set the potential of the control terminal of the first driving circuit 11. Bit;
  • the second control sub-circuit 162 is electrically connected to the second control terminal S2, the control terminal of the first driving circuit 11 and the second terminal of the second driving circuit 12, and is used to control the second control terminal S2. Under the control of the second control signal provided by S2, control the connection between the control end of the first drive circuit 11 and the second end of the second drive circuit 12;
  • the control data voltage writing circuit 17 is electrically connected to the first writing control terminal G1, the control data voltage writing terminal D1 and the first node m respectively, and is used to provide the voltage at the first writing control terminal G1. Under the control of the first write control signal, write the control data voltage Vdata1 provided by the control data voltage writing terminal D1 into the first node m to set the potential of the first node m;
  • the second end of the second driving circuit 12 is electrically connected to the light-emitting element E0, and is used to drive the light-emitting element E0 under the control of the potential of its control end, or to control the first end of the second driving circuit 12. It is connected to or disconnected from the second end of the second driving circuit 12 .
  • the first write control terminal may be the same control terminal as the first control terminal
  • the second set voltage terminal may be a first low voltage terminal
  • the first The set voltage terminal can be the second low voltage terminal, but is not limited to this.
  • the pixel circuit according to at least one embodiment of the present disclosure further includes a data writing circuit 21 , a first light emitting control circuit 22 , and a third light emitting control circuit 22 .
  • the data writing circuit 21 is electrically connected to the second writing control terminal G2, the data line D0 and the first end of the first driving circuit 11 respectively, for providing the third writing control terminal G2 at the second writing control terminal G2. Under the control of two write control signals, the data voltage Vdata0 provided by the data line D0 is written into the first end of the first driving circuit 11;
  • the first lighting control circuit 22 is electrically connected to the lighting control terminal E1, the power supply voltage terminal ELVDD and the first terminal of the first driving circuit 11 respectively, and is used to control the lighting control signal provided at the lighting control terminal E1. Next, control the connection or disconnection between the power supply voltage terminal ELVDD and the first terminal of the first driving circuit 11;
  • the second light-emitting control circuit 23 is electrically connected to the light-emitting control terminal E1, the second terminal of the second driving circuit 12 and the first pole of the light-emitting element E0, respectively, for controlling the light-emitting control signal. Under control, control the communication between the second end of the second driving circuit 12 and the first pole of the light-emitting element E0;
  • the first end of the second energy storage circuit 24 is electrically connected to the control end of the first drive circuit 11, and the second end of the second energy storage circuit 24 is electrically connected to the power supply voltage terminal ELVDD.
  • the second energy storage circuit 24 is used to store electrical energy; the second pole of the light-emitting element E0 is electrically connected to the first voltage terminal V1.
  • the first voltage terminal may be a first low voltage terminal, but is not limited thereto.
  • the second write control terminal G2 may be the second control terminal S2, but is not limited thereto.
  • the display cycle includes a first stage, a second stage and a third stage set successively;
  • the first control sub-circuit 161 writes the second setting voltage provided by the second setting voltage terminal Vz1 into the control terminal of the first driving circuit 11 under the control of the first control signal;
  • the control data voltage writing circuit 17 writes the control data voltage Vdata1 provided by the control data voltage writing terminal D1 into the first node m under the control of the first writing control signal provided by the first writing control terminal G1. ;
  • the first control circuit 13 controls the control terminal of the first drive circuit 11 and the first node m under the control of the potential of the first node m.
  • the control terminals of the two driving circuits 12 are connected; when the control data voltage Vdata1 is the third voltage signal, the setting circuit 14 sets the first setting voltage terminal Vz1 under the control of the potential of the first node m.
  • the provided first setting voltage is written into the control terminal of the second driving circuit 12;
  • the data writing circuit 21 writes the data voltage Vdata0 provided by the data line D0 into the first end of the first driving circuit 11 under the control of the second writing control signal;
  • the second The control subcircuit 162 controls the connection between the control end of the first driving circuit 11 and the second end of the second driving circuit 12 under the control of the second control signal;
  • the first lighting control circuit 22 controls the connection between the power supply voltage terminal ELVDD and the first end of the first driving circuit 11 under the control of the lighting control signal; the second lighting control Under the control of the light-emitting control signal, the circuit 23 controls the connection between the second end of the second driving circuit 12 and the first pole of the light-emitting element E0;
  • the first control circuit 13 controls the connection between the control end of the first drive circuit 11 and the control end of the second drive circuit 12 under the control of the potential of the first node m.
  • the first driving circuit 11 and the second driving circuit 12 drive the light-emitting element E0 to emit light;
  • the setting circuit 14 When in the first stage, the setting circuit 14 writes the first setting voltage provided by the first setting voltage terminal Vz1 into the second driving circuit under the control of the potential of the first node m. 12, in the third stage, the first drive circuit 11 drives the light-emitting element E0 to emit light, and the second drive circuit 12 controls the first end of the second drive circuit 12 and the The second terminals of the second driving circuit 12 are connected with each other.
  • the second voltage signal may be a high voltage signal
  • the third voltage signal may be a low voltage signal, but is not limited thereto.
  • the second control circuit includes a first control sub-circuit and a second control sub-circuit; the charging control end includes a first control end and a second control end; the connected node is The first end of the first driving circuit is electrically connected;
  • the first control sub-circuit is electrically connected to the first control terminal, the second setting voltage terminal and the first terminal of the first drive circuit respectively, and is used for controlling the first control signal provided at the first control terminal. Under control, write the second setting voltage provided by the second setting voltage terminal into the first terminal of the first driving circuit to set the potential of the first terminal of the first driving circuit;
  • the second control sub-circuit is electrically connected to the second control terminal, the control terminal of the first driving circuit and the first terminal of the first driving circuit respectively, for providing the second control terminal at the second control terminal. Under the control of the control signal, the control terminal of the first driving circuit is controlled to be connected to the first terminal of the first driving circuit.
  • the pixel circuit includes a light-emitting element E0, a first driving circuit 11, a second driving circuit 12, a first control circuit 13, a setting circuit 14, and a first energy storage circuit. 15.
  • the second control circuit includes a first control sub-circuit 161 and a second control sub-circuit 162; the charging control terminal includes a first control terminal S1 and a second control terminal S2; the connection node and the first drive circuit The first end of 11 is electrically connected;
  • the first drive circuit 11 is used to generate a drive current flowing from the first end of the first drive circuit 11 to the second end of the first drive circuit 11 under the control of the potential of its control end;
  • the first end of the driving circuit 11 is electrically connected to the light-emitting element E0;
  • the second end of the first driving circuit 11 is electrically connected to the first end of the second driving circuit 12;
  • the first control circuit 13 is electrically connected to the first node m, the control end of the first drive circuit 11 and the control end of the second drive circuit 12 respectively, and is used to adjust the potential of the first node m. Under control, control the connection or disconnection between the control end of the first drive circuit 11 and the control end of the second drive circuit 12;
  • the setting circuit 14 is electrically connected to the first node m, the first setting voltage terminal Vz1 and the control terminal of the second driving circuit 12 respectively, and is used to control the voltage of the first node m under the control of the potential of the first node m.
  • the first setting voltage provided by the first setting voltage terminal Vz1 is written into the control terminal of the second driving circuit 12; the first node m is electrically connected to the first terminal of the first energy storage circuit 15 , the second end of the first energy storage circuit 15 is electrically connected to the first setting voltage terminal Vz1; the first energy storage circuit 15 is used to store electrical energy;
  • the first control sub-circuit 161 is electrically connected to the first control terminal S1, the second setting voltage terminal Vz2 and the first terminal of the first driving circuit 11, respectively, for providing the first control terminal S1. Under the control of the first control signal, the second setting voltage provided by the second setting voltage terminal Vz2 is written into the first terminal of the first driving circuit 11 to control the third terminal of the first driving circuit 11 .
  • the potential at one end is set;
  • the second control sub-circuit 162 is electrically connected to the second control terminal S2, the control terminal of the first driving circuit 11 and the first terminal of the first driving circuit 11 respectively, and is used to control the second control terminal S2. Under the control of the second control signal provided by S2, control the connection between the control end of the first drive circuit 11 and the first end of the first drive circuit 11;
  • the control data voltage writing circuit 17 is electrically connected to the first writing control terminal G1, the control data voltage writing terminal D1 and the first node m respectively, and is used to provide the voltage at the first writing control terminal G1. Under the control of the first write control signal, write the control data voltage Vdata1 provided by the control data voltage writing terminal D1 into the first node m to set the potential of the first node m;
  • the second driving circuit 12 is used to drive the light-emitting element under the control of the potential of its control terminal, or to control the first terminal of the second driving circuit 12 and the second terminal of the second driving circuit 12 connected or disconnected.
  • the first writing control terminal may be the same control terminal as the first control terminal, the second setting voltage terminal may be a power supply voltage terminal, and the first setting voltage terminal may be a power supply voltage terminal.
  • the voltage terminal may be a high voltage terminal, but is not limited to this.
  • the pixel circuit according to at least one embodiment of the present disclosure further includes a data writing circuit 21 , a first light emitting control circuit 22 , and a third light emitting control circuit 22 .
  • the data writing circuit 21 is electrically connected to the second writing control terminal G2, the data line D0 and the second end of the second driving circuit 12 respectively, and is used to provide the third writing control terminal G2 at the second writing control terminal G2. Under the control of the second write control signal, the data voltage Vdata0 provided by the data line D0 is written into the second end of the second driving circuit 12;
  • the first light-emitting control circuit 22 is electrically connected to the light-emitting control terminal E1, the second pole of the light-emitting element E0 and the first terminal of the first driving circuit 11, respectively, for providing the light-emitting control terminal E1. Under the control of the light-emitting control signal, the second pole of the light-emitting element E0 is controlled to be connected to the first end of the first driving circuit 11;
  • the second light-emitting control circuit 23 is electrically connected to the light-emitting control terminal E1, the second terminal of the second driving circuit 12 and the first voltage terminal V1 respectively, and is used to control the light-emitting control signal under the control of the light-emitting control signal.
  • the second terminal of the second driving circuit 12 is connected to the first voltage terminal V1;
  • the first end of the second energy storage circuit 24 is electrically connected to the control end of the first drive circuit 11, and the second end of the second energy storage circuit 24 is electrically connected to the first voltage terminal V1, so The second energy storage circuit 24 is used to store electrical energy.
  • the first voltage terminal may be a first low voltage terminal, but is not limited thereto.
  • the second write control terminal G2 may be the second control terminal S2, but is not limited thereto.
  • the display cycle includes a first stage, a second stage and a third stage that are set successively;
  • the driving method includes:
  • the first control sub-circuit 161 writes the second setting voltage provided by the second setting voltage terminal Vz2 into the first terminal of the first driving circuit 11 under the control of the first control signal.
  • the second control sub-circuit 162 controls the connection between the control end of the first drive circuit 11 and the first end of the first drive circuit 11 under the control of the second control signal; controls the writing of data voltage
  • the circuit 17 writes the control data voltage Vdata1 provided by the control data voltage writing terminal D1 into the first node m under the control of the first writing control signal provided by the first writing control terminal G1;
  • the first control circuit 13 controls the control terminal of the first drive circuit 11 and the first node m under the control of the potential of the first node m.
  • the control terminals of the two driving circuits 12 are connected; when the control data voltage Vdata1 is the fifth voltage signal, the setting circuit 14 sets the first setting voltage terminal Vz1 under the control of the potential of the first node m.
  • the provided first setting voltage is written into the control terminal of the second driving circuit 12;
  • the data writing circuit 21 writes the data voltage Vdata0 provided by the data line D0 into the second end of the second driving circuit 12 under the control of the second writing control signal;
  • the second control sub-circuit 162 controls the connection between the control end of the first driving circuit 11 and the first end of the first driving circuit 11 under the control of the second control signal;
  • the first light-emitting control circuit 22 controls the connection between the second pole of the light-emitting element E0 and the first end of the first driving circuit 11 under the control of the light-emitting control signal; so The second lighting control circuit 23 controls the connection between the second terminal of the second driving circuit 12 and the first voltage terminal V1 under the control of the lighting control signal;
  • the first control circuit 13 controls the connection between the control end of the first drive circuit 11 and the control end of the second drive circuit 12 under the control of the potential of the first node m.
  • the first driving circuit 11 and the second driving circuit 12 drive the light-emitting element to emit light;
  • the setting circuit 14 When in the first stage, the setting circuit 14 writes the first setting voltage provided by the first setting voltage terminal Vz1 into the second driving circuit under the control of the potential of the first node m. 12, in the third stage, the first drive circuit 11 drives the light-emitting element E0 to emit light, and the second drive circuit 12 controls the first end of the second drive circuit 12 and the The second terminals of the second driving circuit 12 are connected with each other.
  • the fourth voltage signal may be a high voltage signal
  • the fifth voltage signal may be a low voltage terminal, but is not limited thereto.
  • the first control circuit includes a first transistor
  • the control electrode of the first transistor is electrically connected to the first node, the first electrode of the first transistor is electrically connected to the control end of the first drive circuit, and the second electrode of the first transistor is electrically connected to the first node.
  • the control terminal of the second driving circuit is electrically connected;
  • the setting circuit includes a second transistor
  • the control electrode of the second transistor is electrically connected to the first node, the first electrode of the second transistor is electrically connected to the first setting voltage terminal, and the second electrode of the second transistor is electrically connected to the first node.
  • the control terminal of the second driving circuit is electrically connected;
  • the control data voltage writing circuit includes a third transistor
  • the control electrode of the third transistor is electrically connected to the first writing control terminal, the first electrode of the third transistor is electrically connected to the control data voltage writing terminal, and the second electrode of the third transistor is electrically connected to the control data voltage writing terminal. electrically connected to the first node;
  • the first energy storage circuit includes a first capacitor
  • the first node is electrically connected to the first terminal of the first capacitor, and the second terminal of the first capacitor is electrically connected to the first setting voltage terminal.
  • the first control sub-circuit includes a fourth transistor, and the second control sub-circuit includes a fifth transistor;
  • the control electrode of the fourth transistor is electrically connected to the first control terminal, the first electrode of the fourth transistor is electrically connected to the second setting voltage terminal, and the second electrode of the fourth transistor is electrically connected to the first control terminal.
  • the control terminal of the first driving circuit is electrically connected;
  • the control electrode of the fifth transistor is electrically connected to the second control terminal
  • the first electrode of the fifth transistor is electrically connected to the control terminal of the first drive circuit
  • the second electrode of the fifth transistor is electrically connected to The second terminal of the second driving circuit is electrically connected.
  • the first control sub-circuit includes a fourth transistor, and the second control sub-circuit includes a fifth transistor;
  • the control electrode of the fourth transistor is electrically connected to the first control terminal, the first electrode of the fourth transistor is electrically connected to the second setting voltage terminal, and the second electrode of the fourth transistor is electrically connected to the first control terminal.
  • the control terminal of the first driving circuit is electrically connected;
  • the control electrode of the fifth transistor is electrically connected to the second control terminal, the first electrode of the fifth transistor is electrically connected to the control terminal of the first drive circuit, and the second electrode of the fifth transistor is electrically connected to The first terminal of the first driving circuit is electrically connected.
  • the light-emitting element is an organic light-emitting diode
  • the data writing circuit includes a sixth transistor
  • the first light-emitting control circuit includes a seventh transistor
  • the second light-emitting control circuit includes an eighth transistor
  • the The second energy storage circuit includes a second capacitor
  • the control electrode of the sixth transistor is electrically connected to the second write control terminal, the first electrode of the sixth transistor is electrically connected to the data line, and the second electrode of the sixth transistor is electrically connected to the third write control terminal.
  • a first terminal of a driving circuit is electrically connected;
  • the control electrode of the seventh transistor is electrically connected to the light-emitting control terminal, the first electrode of the seventh transistor is electrically connected to the power supply voltage terminal, and the second electrode of the seventh transistor is electrically connected to the first drive terminal.
  • the first end of the circuit is electrically connected;
  • the control electrode of the eighth transistor is electrically connected to the light-emitting control terminal, the first electrode of the eighth transistor is electrically connected to the second terminal of the second driving circuit, and the second electrode of the eighth transistor is electrically connected to The anode of the organic light-emitting diode is electrically connected;
  • the first end of the second capacitor is electrically connected to the control end of the first drive circuit, the second end of the second capacitor is electrically connected to the power supply voltage end, and the second energy storage circuit is used to store Electric energy; the cathode of the organic light-emitting diode is electrically connected to the first voltage terminal.
  • the light-emitting element is an organic light-emitting diode
  • the data writing circuit includes a sixth transistor
  • the first light-emitting control circuit includes a seventh transistor
  • the second light-emitting control circuit includes an eighth transistor
  • the The second energy storage circuit includes a second capacitor
  • the anode of the organic light-emitting diode is electrically connected to the power supply voltage terminal
  • the control electrode of the sixth transistor is electrically connected to the second write control terminal, the first electrode of the sixth transistor is electrically connected to the data line, and the second electrode of the sixth transistor is electrically connected to the third write control terminal.
  • the second terminals of the two driving circuits are electrically connected;
  • the control electrode of the seventh transistor is electrically connected to the light-emitting control terminal, the first electrode of the seventh transistor is electrically connected to the cathode of the organic light-emitting diode, and the second electrode of the seventh transistor is electrically connected to the third electrode.
  • a first terminal of a driving circuit is electrically connected;
  • the control electrode of the eighth transistor is electrically connected to the light-emitting control terminal, the first electrode of the eighth transistor is electrically connected to the second terminal of the second driving circuit, and the second electrode of the eighth transistor is electrically connected to The first voltage terminal is electrically connected;
  • the first end of the second capacitor is electrically connected to the control end of the first drive circuit, and the second end of the second capacitor is electrically connected to the first voltage end.
  • the first driving circuit includes a first driving transistor
  • the second driving circuit includes a second driving transistor
  • the control electrode of the first driving transistor is electrically connected to the control terminal of the first driving circuit, the first electrode of the first driving transistor is electrically connected to the first terminal of the first driving circuit, and the first driving transistor is electrically connected to the control terminal of the first driving circuit.
  • the second pole of the driving transistor is electrically connected to the second terminal of the first driving circuit;
  • the control terminal of the second driving transistor is electrically connected to the control terminal of the second driving circuit
  • the first terminal of the second driving transistor is electrically connected to the first terminal of the second driving circuit
  • the second driving transistor is electrically connected to the control terminal of the second driving circuit.
  • the second pole of the driving transistor is electrically connected to the second terminal of the second driving circuit.
  • the first control circuit 13 includes a first transistor T1; the first drive circuit 11 includes a first drive transistor T01, The second driving circuit 12 includes a second driving transistor T02;
  • the gate of the first transistor T1 is electrically connected to the first node m, the source of the first transistor T1 is electrically connected to the gate of the first driving transistor T01, and the drain of the first transistor T1 The pole is electrically connected to the gate of the second driving transistor T02;
  • the setting circuit 14 includes a second transistor T2;
  • the gate of the second transistor T2 is electrically connected to the first node m, the source of the second transistor T2 is electrically connected to the second low voltage terminal VGL, and the drain of the second transistor T2 is electrically connected to the first node m.
  • the gate of the second driving transistor T02 is electrically connected; the second low voltage terminal VGL is used to provide a second low voltage;
  • the control data voltage writing circuit 17 includes a third transistor T3;
  • the gate of the third transistor T3 is electrically connected to the first control terminal S1, the source of the third transistor T3 is electrically connected to the control data voltage writing terminal D1, and the drain of the third transistor T3 is electrically connected to the control data voltage writing terminal D1.
  • the first node m is electrically connected;
  • the first energy storage circuit 15 includes a first capacitor C1;
  • the first node m is electrically connected to the first terminal of the first capacitor C1, and the second terminal of the first capacitor C1 is electrically connected to the second low voltage terminal VGL;
  • the first control sub-circuit 161 includes a fourth transistor T4, and the second control sub-circuit 162 includes a fifth transistor T5;
  • the gate of the fourth transistor T4 is electrically connected to the first control terminal S1, the source of the fourth transistor T4 is electrically connected to the first low voltage terminal VS, and the drain of the fourth transistor T4 is electrically connected to the first control terminal S1.
  • the gate of the first driving transistor T01 is electrically connected; the first low voltage terminal is used to provide a first low voltage Vss;
  • the gate of the fifth transistor T5 is electrically connected to the second control terminal S2, and the source of the fifth transistor T5 is electrically connected to the gate of the first driving transistor T01.
  • the drain is electrically connected to the drain of the second driving transistor T02;
  • the light-emitting element is an organic light-emitting diode O1
  • the data writing circuit 21 includes a sixth transistor T6
  • the first light-emitting control circuit 22 includes a seventh transistor T7
  • the second light-emitting control circuit 23 includes an eighth transistor T8.
  • the second energy storage circuit 24 includes a second capacitor C2;
  • the gate of the sixth transistor T6 is electrically connected to the second control terminal S2, the source of the sixth transistor T6 is electrically connected to the data line D0, and the drain of the sixth transistor T6 is electrically connected to the data line D0.
  • the source of the first driving transistor T01 is electrically connected;
  • the gate of the seventh transistor T7 is electrically connected to the light-emitting control terminal E1
  • the source of the seventh transistor T7 is electrically connected to the power supply voltage terminal ELVDD
  • the drain of the seventh transistor T7 is electrically connected to the light-emitting control terminal E1.
  • the source of the first driving transistor T01 is electrically connected;
  • the gate of the eighth transistor T8 is electrically connected to the light-emitting control terminal E1
  • the source of the eighth transistor T8 is electrically connected to the drain of the second driving transistor T02
  • the drain of the eighth transistor T8 The electrode is electrically connected to the anode of the organic light-emitting diode O1;
  • the first end of the second capacitor C2 is electrically connected to the gate of the first driving transistor T01, the second end of the second capacitor C2 is electrically connected to the power supply voltage terminal ELVDD, and the organic light emitting diode O1
  • the cathode is electrically connected to the first low voltage terminal VS; the power supply voltage terminal ELVDD is used to provide the power supply voltage Vdd.
  • T1, T3, and T4 are all n-type transistors, and T2, T5, T6, T7, T8, T01, and T02 are p-type transistors, but they are not limited to this. .
  • the threshold voltage of T01 is equal to the threshold voltage of T02, and the threshold voltage of T01 and the threshold voltage of T02 are Vth.
  • the first writing control terminal and the first control terminal are the same control terminal, and the second writing control terminal and the second control terminal are the same control terminal; the third writing control terminal is the same control terminal.
  • the two set voltage terminals are the first low voltage terminal VS, and the first set voltage terminal is the second low voltage terminal VGL, but it is not limited to this.
  • the display cycle may include a first phase t1, a second phase t2, and a third phase t3 set successively;
  • S1 provides a high voltage signal
  • S2 provides a high voltage signal
  • E1 provides a high voltage signal
  • T4 is turned on to write the first low voltage Vss to the gate of T01
  • T3 is turned on
  • D1 provides the control data voltage Vdata1 , to write Vdata1 to the first node m;
  • S1 provides a low voltage signal
  • S2 provides a low voltage signal
  • E1 provides a high voltage signal
  • T6 is turned on
  • D0 provides the data voltage Vdata0 to write the data voltage Vdata0 to the source of T01
  • T5 is turned on;
  • T01 and T02 are turned on, and Vdata0 charges C2 through T6, T01, T02, and T5 until T01 and T02 turn off. At this time, the potential of the gate of T01 becomes Vdata0+Vth;
  • S1 provides a low voltage signal
  • S2 provides a high voltage signal
  • E1 provides a low voltage signal
  • T5 and T8 are turned on;
  • T1 When in the first stage t1, T1 is turned on, T2 is turned off, and the gate of T01 is connected to T02, in the third stage t3, T01 and T02 jointly drive O1 to emit light;
  • T1 When in the first stage t1, T1 is turned off and T2 is turned on to write the second low voltage to the gate of T02, in the third stage t3, T02 is fully turned on and T01 drives O1 to emit light.
  • the width of the channel of T01 and the width of the channel of T02 are both W, the length of the channel of T01 is L1, and the length of the channel of T02 is L2.
  • T01 and T02 jointly drive O1 to emit light.
  • the current I flowing through O1 is equal to 0.5(W/(L1+L2)) ⁇ Cox ⁇ (Vdata0- Vdd) 2 ; where, Cox is the capacitance of the gate oxide layer per unit area, and ⁇ is the mobility;
  • T02 when performing high grayscale display, T02 is fully turned on, and T01 drives O1 to emit light. At this time, the current I flowing through O1 is equal to 0.5(W/L1) ⁇ Cox ⁇ (Vdata0-Vdd) 2 .
  • the first control circuit 13 includes a first transistor T1; the first driving circuit 11 includes a first driving transistor T01, The second driving circuit 12 includes a second driving transistor T02;
  • the gate of the first transistor T1 is electrically connected to the first node m, the source of the first transistor T1 is electrically connected to the gate of the first driving transistor T01, and the drain of the first transistor T1 The pole is electrically connected to the gate of the second driving transistor T02;
  • the setting circuit includes a second transistor T2;
  • the gate of the second transistor T2 is electrically connected to the first node m, the source of the second transistor T2 is electrically connected to the high voltage terminal VGH, and the drain of the second transistor T2 is electrically connected to the second node m.
  • the gate of the driving transistor T02 is electrically connected; the high voltage terminal VGH is used to provide high voltage;
  • the control data voltage writing circuit 17 includes a third transistor T3;
  • the gate of the third transistor T3 is electrically connected to the first control terminal S1, the source of the third transistor T3 is electrically connected to the control data voltage writing terminal D1, and the drain of the third transistor T3 is electrically connected to the control data voltage writing terminal D1.
  • the first node m is electrically connected;
  • the first energy storage circuit 15 includes a first capacitor C1;
  • the first node m is electrically connected to the first terminal of the first capacitor C1, and the second terminal of the first capacitor C1 is electrically connected to the high voltage terminal VGH;
  • the first control sub-circuit 161 includes a fourth transistor T4, and the second control sub-circuit 162 includes a fifth transistor T5;
  • the gate of the fourth transistor T4 is electrically connected to the first control terminal S1, the source of the fourth transistor T4 is electrically connected to the power supply voltage terminal ELVDD, and the drain of the fourth transistor T4 is electrically connected to the first control terminal S1.
  • the gate of a driving transistor T01 is electrically connected; the power supply voltage terminal is used to provide the power supply voltage Vdd;
  • the gate of the fifth transistor T5 is electrically connected to the second control terminal S2, and the source of the fifth transistor T5 is electrically connected to the gate of the first driving transistor T01.
  • the drain is electrically connected to the source of the first driving transistor T01;
  • the light-emitting element is an organic light-emitting diode O1
  • the data writing circuit 21 includes a sixth transistor T6
  • the first light-emitting control circuit 22 includes a seventh transistor T7
  • the second light-emitting control circuit 23 includes an eighth transistor T8.
  • the second energy storage circuit 24 includes a second capacitor C2; the anode of the organic light-emitting diode O1 is electrically connected to the power supply voltage terminal ELVDD; the power supply voltage terminal is used to provide the power supply voltage Vdd;
  • the gate of the sixth transistor T6 is electrically connected to the second control terminal S2, the source of the sixth transistor T6 is electrically connected to the data line D0, and the drain of the sixth transistor T6 is electrically connected to the data line D0.
  • the drain of the second driving transistor T02 is electrically connected;
  • the gate of the seventh transistor T7 is electrically connected to the light-emitting control terminal E1
  • the source of the seventh transistor T7 is electrically connected to the cathode of the organic light-emitting diode O1
  • the drain of the seventh transistor T7 is electrically connected to the light-emitting control terminal E1.
  • the source of the first driving transistor T01 is electrically connected;
  • the gate of the eighth transistor T8 is electrically connected to the light-emitting control terminal E1, the source of the eighth transistor T8 is electrically connected to the drain of the second driving transistor T02, and the drain of the eighth transistor T8
  • the pole is electrically connected to the first low voltage terminal VS; the first low voltage terminal VS is used to provide the first low voltage Vss;
  • the first terminal of the second capacitor C2 is electrically connected to the gate of the first driving transistor T01, and the second terminal of the second capacitor C2 is electrically connected to the first low voltage terminal VS.
  • the threshold voltage of T01 is equal to the threshold voltage of T02 , and both the threshold voltage of T01 and the threshold voltage of T02 are Vth.
  • the first writing control end and the first control end are the same control end, and the second writing control end and the second control end are are the same control terminal;
  • the second setting voltage terminal may be the power supply voltage terminal ELVDD, and the first setting voltage terminal may be the high voltage terminal VGH, but is not limited to this.
  • T2 is a p-type transistor
  • T1, T3, T4, T5, T6, T7, T8, T01 and T02 are all n-type transistors, but this is not limiting. .
  • the display cycle includes a first phase t1, a second phase t2 and a third phase t3 that are set successively;
  • S1 provides a high voltage signal
  • S2 provides a high voltage signal
  • E1 provides a low voltage signal
  • T4 and T5 are turned on to write the power supply voltage Vdd to the gate of T01
  • T3 is turned on
  • D1 provides the control data voltage Vdata1 to the first node m
  • T1 when Vdata1 is a low-voltage signal, T1 is turned off and T2 is turned on to write the high voltage provided by the high-voltage terminal VGH into the gate of T02;
  • S1 provides a low voltage signal
  • S2 provides a high voltage signal
  • E1 provides a low voltage signal
  • D0 provides the data voltage Vdata0
  • T6 is turned on to write the data voltage Vdata0 to the drain of T02;
  • T01 and T02 are turned on, and Vdata0 charges C2 through T6, T01, T02 and T5 to increase the potential of the gate of T01 until T01 turns off; at this time, the potential of the gate of T01 Change to Vdata0+Vth;
  • S1 provides a low-voltage signal
  • S2 provides a low-voltage signal
  • E1 provides a high-voltage signal.
  • T7 and T8 are turned on; the source potential of T1 is Vdd-Voled, and Voled is the threshold turn-on voltage of O1;
  • T01 and T02 When the gate of T01 and the gate of T02 are connected in the first stage t1, in the third stage t3, T01 and T02 jointly drive O1 to emit light;
  • T1 When in the first stage t1, T1 is turned off and T2 is turned on to write the high voltage provided by the high voltage terminal VGH into the gate of T02, in the third stage t3, T01 drives O1 to emit light and T02 is fully turned on.
  • the width of the channel of T01 and the width of the channel of T02 are both W, the length of the channel of T01 is L1, and the length of the channel of T02 is L2.
  • T01 and T02 jointly drive O1 to emit light.
  • the current I flowing through O1 is equal to 0.5(W/(L1+L2)) ⁇ Cox ⁇ (Vdata0- Vdd+Voled) 2 ; where, Cox is the capacitance of the gate oxide layer per unit area, and ⁇ is the mobility;
  • T02 when performing high grayscale display, T02 is fully turned on, and T01 drives O1 to emit light. At this time, the current I flowing through O1 is equal to 0.5(W/L1) ⁇ Cox ⁇ (Vdata0-Vdd+Voled) 2 .
  • the driving method described in the embodiment of the present disclosure is applied to the above-mentioned pixel circuit.
  • the driving method includes:
  • the first control circuit controls the connection or disconnection between the control end of the first drive circuit and the control end of the second drive circuit under the control of the potential of the first node;
  • the setting circuit writes the first setting voltage provided by the first setting voltage terminal into the control terminal of the second driving circuit under the control of the potential of the first node;
  • the second control circuit is used to provide the second setting voltage to the control end of the first drive circuit under the control of the control signal provided by the charging control end, and to control the connection between the control end of the first drive circuit and the connected node. Connect or disconnect;
  • the control data voltage writing circuit writes the control data voltage provided by the control data voltage writing terminal into the first node under the control of the first writing control signal
  • the first drive circuit generates a drive current flowing from the first end of the first drive circuit to the second end of the first drive circuit under the control of the potential of its control end;
  • the second driving circuit drives the light-emitting element under the control of the potential of its control terminal, or the second driving circuit controls the first terminal of the second driving circuit and the potential of the second driving circuit under the control of the potential of its control terminal.
  • the second terminals of the second driving circuit are connected or disconnected.
  • the second control circuit includes a first control sub-circuit and a second control sub-circuit; the connecting node is electrically connected to the second end of the second driving circuit; the pixel circuit also includes a light-emitting element , data writing circuit, first light-emitting control circuit, second light-emitting control circuit and second energy storage circuit; the display cycle includes a first stage, a second stage and a third stage set successively; the driving method includes:
  • the first control sub-circuit writes the second setting voltage provided by the second setting voltage terminal into the control terminal of the first driving circuit under the control of the first control signal; controls the data voltage
  • the writing circuit writes the control data voltage provided by the control data voltage writing terminal into the first node under the control of the first writing control signal provided by the first writing control terminal;
  • the first control circuit controls the control end of the first drive circuit and the second drive circuit under the control of the potential of the first node.
  • the control terminals are connected; when the control data voltage is the third voltage signal, the setting circuit writes the first setting voltage provided by the first setting voltage terminal under the control of the potential of the first node.
  • the control end of the second drive circuit is connected;
  • the data writing circuit writes the data voltage provided by the data line into the first end of the first driving circuit under the control of the second writing control signal;
  • the second control sub-circuit Under the control of the second control signal, control the connection between the control end of the first drive circuit and the second end of the second drive circuit;
  • the first lighting control circuit controls the connection between the power supply voltage terminal and the first terminal of the first driving circuit under the control of the lighting control signal;
  • the second lighting control circuit controls the connection between the power supply voltage terminal and the first terminal of the first driving circuit.
  • the first control circuit controls the connection between the control end of the first drive circuit and the control end of the second drive circuit under the control of the potential of the first node, in the In the third stage, the first driving circuit and the second driving circuit drive the light-emitting element to emit light;
  • the setting circuit When in the first stage, the setting circuit writes the first setting voltage provided by the first setting voltage terminal into the control terminal of the second driving circuit under the control of the potential of the first node.
  • the first driving circuit drives the light-emitting element to emit light
  • the second driving circuit controls the first end of the second driving circuit and the second end of the second driving circuit. connected between.
  • the second control circuit includes a first control sub-circuit and a second control sub-circuit; the connection node is electrically connected to the first end of the first driving circuit; the pixel circuit It also includes a light-emitting element, a data writing circuit, a first light-emitting control circuit, a second light-emitting control circuit and a second energy storage circuit; the display cycle includes a first stage, a second stage and a third stage set successively; the driving method include:
  • the first control sub-circuit writes the second setting voltage provided by the second setting voltage terminal into the first terminal of the first driving circuit under the control of the first control signal; Under the control of the second control signal, the second control sub-circuit controls the connection between the control end of the first driving circuit and the first end of the first driving circuit; controls the data voltage writing circuit to perform the first writing operation. Under the control of the first write control signal provided by the control terminal, write the control data voltage provided by the control data voltage writing terminal into the first node;
  • the first control circuit controls the control end of the first drive circuit and the second drive circuit under the control of the potential of the first node.
  • the control terminals are connected; when the control data voltage is the fifth voltage signal, the setting circuit writes the first setting voltage provided by the first setting voltage terminal under the control of the potential of the first node.
  • the control end of the second drive circuit is a fourth voltage signal
  • the data writing circuit writes the data voltage provided by the data line into the second end of the second driving circuit under the control of the second writing control signal;
  • the second control signal The sub-circuit controls the connection between the control end of the first drive circuit and the first end of the first drive circuit under the control of the second control signal;
  • the first light-emitting control circuit controls the connection between the second pole of the light-emitting element and the first end of the first driving circuit under the control of the light-emitting control signal;
  • the second The lighting control circuit controls the connection between the second terminal of the second driving circuit and the first voltage terminal under the control of the lighting control signal;
  • the first control circuit controls the connection between the control end of the first drive circuit and the control end of the second drive circuit under the control of the potential of the first node, in the In the third stage, the first driving circuit and the second driving circuit drive the light-emitting element to emit light;
  • the setting circuit When in the first stage, the setting circuit writes the first setting voltage provided by the first setting voltage terminal into the control terminal of the second driving circuit under the control of the potential of the first node.
  • the first driving circuit drives the light-emitting element to emit light
  • the second driving circuit controls the first end of the second driving circuit and the second end of the second driving circuit. connected between.
  • the display device described in the embodiments of the present disclosure includes the above-mentioned pixel circuit.
  • the display device provided in the embodiment of the present disclosure can be any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.

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Abstract

一种用于多灰阶显示，实现超常规256灰阶显示，能够在不大幅提高成本的前提下，增加显示灰阶个数的像素电路、驱动方法和显示装置。像素电路包括发光元件（E0）、第一驱动电路（11）、第二驱动电路（12）、第一控制电路（13）、置位电路（14）、第一储能电路（15）、第二控制电路和控制数据电压写入电路（17）；第一控制电路（13）在第一节点（m）的电位的控制下，控制第一驱动电路（11）的控制端和第二驱动电路（12）的控制端之间连通或断开；第二控制电路在充电控制端提供的控制信号的控制下，将第二置位电压（Vz2）提供至第一驱动电路（11）的控制端，并控制第一驱动电路（11）的控制端与连通节点之间连通或断开；控制数据电压写入电路（17）分在第一写入控制信号的控制下，将控制数据电压，写入第一节点（m）。

Description

像素电路、驱动方法和显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种像素电路、驱动方法和显示装置。
背景技术
近年来，随着智能显示技术的进步，有机发光显示器(Organic Light Emitting Diode，OLED)成为当今显示器研究领域的热点之一，随着显示面板的减薄化，边框变窄化，显示面板优化设计越来越严峻。
相关的像素电路不能用于多灰阶显示，不能实现超常规256灰阶显示，不能在不大幅提高成本的前提下，增加显示灰阶个数。
发明内容
在一个方面中，本公开实施例提供了一种像素电路，包括发光元件、第一驱动电路、第二驱动电路、第一控制电路、置位电路、第一储能电路、第二控制电路和控制数据电压写入电路；
所述第一驱动电路用于在其控制端的电位的控制下，产生从所述第一驱动电路的第一端流向所述第一驱动电路的第二端的驱动电流；
所述第一驱动电路的第二端与所述第二驱动电路的第一端电连接；
所述第一控制电路分别与第一节点、所述第一驱动电路的控制端和所述第二驱动电路的控制端电连接，用于在所述第一节点的电位的控制下，控制所述第一驱动电路的控制端和所述第二驱动电路的控制端之间连通或断开；
所述置位电路分别与第一节点、第一置位电压端和所述第二驱动电路的控制端电连接，用于在所述第一节点的电位的控制下，将所述第一置位电压端提供的第一置位电压写入所述第二驱动电路的控制端；所述第一节点与所述第一储能电路的第一端电连接，所述第一储能电路的第二端与所述第一置位电压端电连接；所述第一储能电路用于储存电能；
所述第二控制电路用于在充电控制端提供的控制信号的控制下，将第二 置位电压提供至第一驱动电路的控制端，并控制所述第一驱动电路的控制端与连通节点之间连通或断开；所述连通节点与所述第二驱动电路的第二端电连接，或者，所述连通节点与所述第一驱动电路的第一端电连接；
所述控制数据电压写入电路分别与第一写入控制端、控制数据电压写入端和所述第一节点电连接，用于在所述第一写入控制端提供的第一写入控制信号的控制下，将所述控制数据电压写入端提供的控制数据电压，写入所述第一节点；
所述第二驱动电路用于在其控制端的电位的控制下，驱动所述发光元件，或者，控制所述第二驱动电路的第一端与所述第二驱动电路的第二端之间连通或断开。
可选的，所述第二控制电路包括第一控制子电路和第二控制子电路；所述充电控制端包括第一控制端和第二控制端；所述连通节点与所述第二驱动电路的第二端电连接；
所述第一控制子电路分别与第一控制端、第二置位电压端和所述第一驱动电路的控制端电连接，用于在所述第一控制端提供的第一控制信号的控制下，将所述第二置位电压端提供的第二置位电压写入所述第一驱动电路的控制端；
所述第二控制子电路分别与第二控制端、所述第一驱动电路的控制端和所述第二驱动电路的第二端电连接，用于在所述第二控制端提供的第二控制信号的控制下，控制所述第一驱动电路的控制端和所述第二驱动电路的第二端之间连通。
可选的，所述第二控制电路包括第一控制子电路和第二控制子电路；所述充电控制端包括第一控制端和第二控制端；所述连通节点与所述第一驱动电路的第一端电连接；
所述第一控制子电路分别与第一控制端、第二置位电压端和所述第一驱动电路的第一端电连接，用于在所述第一控制端提供的第一控制信号的控制下，将所述第二置位电压端提供的第二置位电压写入所述第一驱动电路的第一端；
所述第二控制子电路分别与第二控制端、所述第一驱动电路的控制端和 所述第一驱动电路的第一端电连接，用于在所述第二控制端提供的第二控制信号的控制下，控制所述第一驱动电路的控制端和所述第一驱动电路的第一端之间连通。
可选的，本公开至少一实施例所述的像素电路还包括数据写入电路、第一发光控制电路、第二发光控制电路和第二储能电路；
所述数据写入电路分别与第二写入控制端、数据线和所述第一驱动电路的第一端电连接，用于在所述第二写入控制端提供的第二写入控制信号的控制下，将所述数据线提供的数据电压写入所述第一驱动电路的第一端；
所述第一发光控制电路分别与发光控制端、电源电压端和所述第一驱动电路的第一端电连接，用于在所述发光控制端提供的发光控制信号的控制下，控制所述电源电压端与所述第一驱动电路的第一端之间连通或断开；
所述第二发光控制电路分别与所述发光控制端、所述第二驱动电路的第二端和所述发光元件的第一极电连接，用于在所述发光控制信号的控制下，控制所述第二驱动电路的第二端和所述发光元件的第一极之间连通；
所述第二储能电路的第一端与所述第一驱动电路的控制端电连接，所述第二储能电路的第二端与所述电源电压端电连接，所述第二储能电路用于储存电能；所述发光元件的第二极与第一电压端电连接。
可选的，本公开至少一实施例所述的像素电路还包括发光元件、数据写入电路、第一发光控制电路、第二发光控制电路和第二储能电路；所述发光元件的第一极与电源电压端电连接；
所述数据写入电路分别与第二写入控制端、数据线和所述第二驱动电路的第二端电连接，用于在所述第二写入控制端提供的第二写入控制信号的控制下，将所述数据线提供的数据电压写入所述第二驱动电路的第二端；
所述第一发光控制电路分别与发光控制端、所述发光元件的第二极和所述第一驱动电路的第一端电连接，用于在所述发光控制端提供的发光控制信号的控制下，控制所述发光元件的第二极和所述第一驱动电路的第一端之间连通；
所述第二发光控制电路分别与所述发光控制端、所述第二驱动电路的第二端和第一电压端电连接，用于在所述发光控制信号的控制下，控制所述第 二驱动电路的第二端和第一电压端之间连通；
所述第二储能电路的第一端与所述第一驱动电路的控制端电连接，所述第二储能电路的第二端与所述第一电压端电连接，所述第二储能电路用于储存电能。
可选的，所述第一控制电路包括第一晶体管；
所述第一晶体管的控制极与所述第一节点电连接，所述第一晶体管的第一极与所述第一驱动电路的控制端电连接，所述第一晶体管的第二极与所述第二驱动电路的控制端电连接；
所述置位电路包括第二晶体管；
所述第二晶体管的控制极与所述第一节点电连接，所述第二晶体管的第一极与所述第一置位电压端电连接，所述第二晶体管的第二极与所述第二驱动电路的控制端电连接；
所述控制数据电压写入电路包括第三晶体管；
所述第三晶体管的控制极与所述第一写入控制端电连接，所述第三晶体管的第一极与所述控制数据电压写入端电连接，所述第三晶体管的第二极与所述第一节点电连接；
所述第一储能电路包括第一电容；
所述第一节点与所述第一电容的第一端电连接，所述第一电容的第二端与所述第一置位电压端电连接。
可选的，所述第一控制子电路包括第四晶体管，所述第二控制子电路包括第五晶体管；
所述第四晶体管的控制极与所述第一控制端电连接，所述第四晶体管的第一极与所述第二置位电压端电连接，所述第四晶体管的第二极与所述第一驱动电路的控制端电连接；
所述第五晶体管的控制极与所述第二控制端电连接，所述第五晶体管的第一极与所述第一驱动电路的控制端电连接，所述第五晶体管的第二极与所述第二驱动电路的第二端电连接。
可选的，所述第一控制子电路包括第四晶体管，所述第二控制子电路包括第五晶体管；
所述第四晶体管的控制极与所述第一控制端电连接，所述第四晶体管的第一极与所述第二置位电压端电连接，所述第四晶体管的第二极与所述第一驱动电路的控制端电连接；
所述第五晶体管的控制极与所述第二控制端电连接，所述第五晶体管的第一极与所述第一驱动电路的控制端电连接，所述第五晶体管的第二极与所述第一驱动电路的第一端电连接。
可选的，所述发光元件为有机发光二极管，所述数据写入电路包括第六晶体管，所述第一发光控制电路包括第七晶体管、所述第二发光控制电路包括第八晶体管，所述第二储能电路包括第二电容；
所述第六晶体管的控制极与所述第二写入控制端电连接，所述第六晶体管的第一极与所述数据线电连接，所述第六晶体管的第二极与所述第一驱动电路的第一端电连接；
所述第七晶体管的控制极与所述发光控制端电连接，所述第七晶体管的第一极与所述电源电压端电连接，所述第七晶体管的第二极与所述第一驱动电路的第一端电连接；
所述第八晶体管的控制极与所述发光控制端电连接，所述第八晶体管的第一极与所述第二驱动电路的第二端电连接，所述第八晶体管的第二极与所述有机发光二极管的阳极电连接；
所述第二电容的第一端与所述第一驱动电路的控制端电连接，所述第二电容的第二端与所述电源电压端电连接；所述有机发光二极管的阴极与第一电压端电连接。
可选的，所述发光元件为有机发光二极管，所述数据写入电路包括第六晶体管，所述第一发光控制电路包括第七晶体管、所述第二发光控制电路包括第八晶体管，所述第二储能电路包括第二电容；所述有机发光二极管的阳极与所述电源电压端电连接；
所述第六晶体管的控制极与所述第二写入控制端电连接，所述第六晶体管的第一极与所述数据线电连接，所述第六晶体管的第二极与所述第二驱动电路的第二端电连接；
所述第七晶体管的控制极与所述发光控制端电连接，所述第七晶体管的 第一极与所述有机发光二极管的阴极电连接，所述第七晶体管的第二极与所述第一驱动电路的第一端电连接；
所述第八晶体管的控制极与所述发光控制端电连接，所述第八晶体管的第一极与所述第二驱动电路的第二端电连接，所述第八晶体管的第二极与所述第一电压端电连接；
所述第二电容的第一端与所述第一驱动电路的控制端电连接，所述第二电容的第二端与所述第一电压端电连接。
可选的，所述第一驱动电路包括第一驱动晶体管，所述第二驱动电路包括第二驱动晶体管；
所述第一驱动晶体管的控制极与所述第一驱动电路的控制端电连接，所述第一驱动晶体管的第一极与所述第一驱动电路的第一端电连接，所述第一驱动晶体管的第二极与所述第一驱动电路的第二端电连接；
所述第二驱动晶体管的控制极与所述第二驱动电路的控制端电连接，所述第二驱动晶体管的第一极与所述第二驱动电路的第一端电连接，所述第二驱动晶体管的第二极与所述第二驱动电路的第二端电连接。
在第二个方面中，本公开实施例提供一种驱动方法，应用于上述的像素电路，所述驱动方法包括：
所述第一控制电路在第一节点的电位的控制下，控制第一驱动电路的控制端和第二驱动电路的控制端之间连通或断开；
置位电路在第一节点的电位的控制下，将第一置位电压端提供的第一置位电压写入第二驱动电路的控制端；
第二控制电路用于在充电控制端提供的控制信号的控制下，将第二置位电压提供至第一驱动电路的控制端，并控制所述第一驱动电路的控制端与连通节点之间连通或断开；
控制数据电压写入电路在第一写入控制信号的控制下，将控制数据电压写入端提供的控制数据电压，写入第一节点；
所述第一驱动电路在其控制端的电位的控制下，产生从所述第一驱动电路的第一端流向所述第一驱动电路的第二端的驱动电流；
所述第二驱动电路在其控制端的电位的控制下，驱动所述发光元件，或 者，所述第二驱动电路在其控制端的电位的控制下，控制所述第二驱动电路的第一端与所述第二驱动电路的第二端之间连通或断开。
可选的，所述第二控制电路包括第一控制子电路和第二控制子电路；连通节点与第二驱动电路的第二端电连接；所述像素电路还包括发光元件、数据写入电路、第一发光控制电路、第二发光控制电路和第二储能电路；显示周期包括先后设置的第一阶段、第二阶段和第三阶段；所述驱动方法包括：
在所述第一阶段，所述第一控制子电路在第一控制信号的控制下，将第二置位电压端提供的第二置位电压写入第一驱动电路的控制端；控制数据电压写入电路在第一写入控制端提供的第一写入控制信号的控制下，将控制数据电压写入端提供的控制数据电压，写入所述第一节点；
在所述第一阶段，当所述控制数据电压为第二电压信号时，第一控制电路在所述第一节点的电位的控制下，控制第一驱动电路的控制端和第二驱动电路的控制端之间连通；当所述控制数据电压为第三电压信号时，置位电路在所述第一节点的电位的控制下，将第一置位电压端提供的第一置位电压写入所述第二驱动电路的控制端；
在所述第二阶段，数据写入电路在第二写入控制信号的控制下，将数据线提供的数据电压写入所述第一驱动电路的第一端；所述第二控制子电路在第二控制信号的控制下，控制所述第一驱动电路的控制端和所述第二驱动电路的第二端之间连通；
在所述第三阶段，所述第一发光控制电路在发光控制信号的控制下，控制电源电压端与所述第一驱动电路的第一端之间连通；所述第二发光控制电路在所述发光控制信号的控制下，控制所述第二驱动电路的第二端和所述发光元件的第一极之间连通；
当在所述第一阶段，所述第一控制电路在所述第一节点的电位的控制下，控制第一驱动电路的控制端和第二驱动电路的控制端之间连通时，在所述第三阶段，所述第一驱动电路和所述第二驱动电路驱动所述发光元件发光；
当在所述第一阶段，所述置位电路在所述第一节点的电位的控制下，将第一置位电压端提供的第一置位电压写入所述第二驱动电路的控制端时，在所述第三阶段，所述第一驱动电路驱动所述发光元件发光，所述第二驱动电 路控制所述第二驱动电路的第一端与所述第二驱动电路的第二端之间连通。
可选的，所述第二控制电路包括第一控制子电路和第二控制子电路；所述连通节点与所述第一驱动电路的第一端电连接；所述像素电路还包括发光元件、数据写入电路、第一发光控制电路、第二发光控制电路和第二储能电路；显示周期包括先后设置的第一阶段、第二阶段和第三阶段；所述驱动方法包括：
在所述第一阶段，所述第一控制子电路在第一控制信号的控制下，将第二置位电压端提供的第二置位电压写入第一驱动电路的第一端；所述第二控制子电路在第二控制信号的控制下，控制所述第一驱动电路的控制端和所述第一驱动电路的第一端之间连通；控制数据电压写入电路在第一写入控制端提供的第一写入控制信号的控制下，将控制数据电压写入端提供的控制数据电压，写入所述第一节点；
在所述第一阶段，当所述控制数据电压为第四电压信号时，第一控制电路在所述第一节点的电位的控制下，控制第一驱动电路的控制端和第二驱动电路的控制端之间连通；当所述控制数据电压为第五电压信号时，置位电路在所述第一节点的电位的控制下，将第一置位电压端提供的第一置位电压写入所述第二驱动电路的控制端；
在所述第二发光阶段，所述数据写入电路在第二写入控制信号的控制下，将数据线提供的数据电压写入所述第二驱动电路的第二端；所述第二控制子电路在第二控制信号的控制下，控制所述第一驱动电路的控制端和所述第一驱动电路的第一端之间连通；
在所述第三阶段，所述第一发光控制电路在发光控制信号的控制下，控制所述发光元件的第二极和所述第一驱动电路的第一端之间连通；所述第二发光控制电路在所述发光控制信号的控制下，控制所述第二驱动电路的第二端和第一电压端之间连通；
当在所述第一阶段，所述第一控制电路在所述第一节点的电位的控制下，控制第一驱动电路的控制端和第二驱动电路的控制端之间连通时，在所述第三阶段，所述第一驱动电路和所述第二驱动电路驱动所述发光元件发光；
当在所述第一阶段，所述置位电路在所述第一节点的电位的控制下，将 第一置位电压端提供的第一置位电压写入所述第二驱动电路的控制端时，在所述第三阶段，所述第一驱动电路驱动所述发光元件发光，所述第二驱动电路控制所述第二驱动电路的第一端与所述第二驱动电路的第二端之间连通。
在第三个方面中，本公开实施例提供一种显示装置，包括上述的像素电路。
附图说明
图1是本公开至少一实施例所述的像素电路的结构图；
图2是本公开至少一实施例所述的像素电路的结构图；
图3是本公开至少一实施例所述的像素电路的结构图；
图4是本公开至少一实施例所述的像素电路的结构图；
图5是本公开至少一实施例所述的像素电路的电路图；
图6是本公开如图5所示的像素电路的至少一实施例的工作时序图；
图7是本公开至少一实施例所述的像素电路的电路图；
图8是本公开如图7所示的像素电路的至少一实施例的工作时序图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为三极管、薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除控制极之外的两极，将其中一极称为第一极，另一极称为第二极。
在实际操作时，当所述晶体管为三极管时，所述控制极可以为基极，所述第一极可以为集电极，所述第二极可以发射极；或者，所述控制极可以为基极，所述第一极可以为发射极，所述第二极可以集电极。
在实际操作时，当所述晶体管为薄膜晶体管或场效应管时，所述控制极可以为栅极，所述第一极可以为漏极，所述第二极可以为源极；或者，所述 控制极可以为栅极，所述第一极可以为源极，所述第二极可以为漏极。
本公开实施例所述的像素电路包括发光元件、第一驱动电路、第二驱动电路、第一控制电路、置位电路、第一储能电路、第二控制电路和控制数据电压写入电路；
所述第一驱动电路用于在其控制端的电位的控制下，产生从所述第一驱动电路的第一端流向所述第一驱动电路的第二端的驱动电流；
所述第一驱动电路的第二端与所述第二驱动电路12的第一端电连接；
所述第一控制电路分别与第一节点m、所述第一驱动电路的控制端和所述第二驱动电路的控制端电连接，用于在所述第一节点m的电位的控制下，控制所述第一驱动电路的控制端和所述第二驱动电路的控制端之间连通或断开；
所述置位电路分别与第一节点、第一置位电压端和所述第二驱动电路的控制端电连接，用于在所述第一节点的电位的控制下，将所述第一置位电压端提供的第一置位电压写入所述第二驱动电路的控制端；所述第一节点与所述第一储能电路的第一端电连接，所述第一储能电路的第二端与所述第一置位电压端电连接；所述第一储能电路用于储存电能；
所述第二控制电路用于在充电控制端提供的控制信号的控制下，将第二置位电压提供至第一驱动电路的控制端，并控制所述第一驱动电路的控制端与连通节点之间连通或断开；所述连通节点与所述第二驱动电路的第二端电连接，或者，所述连通节点与所述第一驱动电路的第一端电连接；
所述控制数据电压写入电路分别与第一写入控制端、控制数据电压写入端和所述第一节点电连接，用于在所述第一写入控制端提供的第一写入控制信号的控制下，将所述控制数据电压写入端提供的控制数据电压，写入所述第一节点；
所述第二驱动电路用于在其控制端的电位的控制下，驱动所述发光元件，或者，控制所述第二驱动电路的第一端与所述第二驱动电路的第二端之间连通或断开。
本公开实施例所述的像素电路在工作时，在低灰阶显示时，采用第一驱动电路和第二驱动电路驱动发光元件发光，在高灰阶显示时，采用第一驱动 电路驱动发光元件发光，第二驱动电路包括的第二驱动晶体管完全打开；
所述第一驱动电路包括的第一驱动晶体管的SS摆幅(亚阈值摆幅)和所述第二驱动电路包括的第二驱动晶体管的SS摆幅一致，可以共用一个数据电压取值范围。
在本公开至少一实施例中，所述第一驱动晶体管的宽长比与所述第二驱动晶体管的宽长比不同，所述第二驱动晶体管的宽长比大于所述第一驱动晶体管的宽长比，例如，所述的第二驱动晶体管的宽长比可以为所述第一驱动晶体管的宽长比的两倍，但不以此为限。
本公开实施例所述的像素电路能够用于多灰阶显示，实现超常规256灰阶显示，能够在不大幅提高成本的前提下，增加显示灰阶个数。
在本公开至少一实施例中，所述第二控制电路包括第一控制子电路和第二控制子电路；所述充电控制端包括第一控制端和第二控制端；所述连通节点与所述第二驱动电路的第二端电连接；
所述第一控制子电路分别与第一控制端、第二置位电压端和所述第一驱动电路的控制端电连接，用于在所述第一控制端提供的第一控制信号的控制下，将所述第二置位电压端提供的第二置位电压写入所述第一驱动电路的控制端，以对第一驱动电路的控制端的电位进行置位；
所述第二控制子电路分别与第二控制端、所述第一驱动电路的控制端和所述第二驱动电路的第二端电连接，用于在所述第二控制端提供的第二控制信号的控制下，控制所述第一驱动电路的控制端和所述第二驱动电路的第二端之间连通。
如图1所示，本公开至少一实施例所述的像素电路包括发光元件E0、第一驱动电路11、第二驱动电路12、第一控制电路13、置位电路14、第一储能电路15、第二控制电路和控制数据电压写入电路17；
所述第二控制电路包括第一控制子电路161和第二控制子电路162；所述充电控制端包括第一控制端S1和第二控制端S2；连通节点与所述第二驱动电路12的第二端电连接；
所述第一驱动电路11用于在其控制端的电位的控制下，产生从所述第一驱动电路11的第一端流向所述第一驱动电路11的第二端的驱动电流；
所述第一驱动电路11的第二端与所述第二驱动电路12的第一端电连接；
所述第一控制电路13分别与第一节点m、所述第一驱动电路11的控制端和所述第二驱动电路12的控制端电连接，用于在所述第一节点m的电位的控制下，控制所述第一驱动电路11的控制端和所述第二驱动电路12的控制端之间连通或断开；
所述置位电路14分别与第一节点m、第一置位电压端Vz1和所述第二驱动电路12的控制端电连接，用于在所述第一节点m的电位的控制下，将所述第一置位电压端Vz1提供的第一置位电压写入所述第二驱动电路12的控制端；
所述第一节点m与所述第一储能电路15的第一端电连接，所述第一储能电路15的第二端与所述第一置位电压端Vz1电连接；所述第一储能电路15用于储存电能；
所述第一控制子电路161分别与第一控制端S1、第二置位电压端Vz2和所述第一驱动电路11的控制端电连接，用于在所述第一控制端S1提供的第一控制信号的控制下，将所述第二置位电压端Vz2提供的第二置位电压写入所述第一驱动电路11的控制端，以对第一驱动电路11的控制端的电位进行置位；
所述第二控制子电路162分别与第二控制端S2、所述第一驱动电路11的控制端和所述第二驱动电路12的第二端电连接，用于在所述第二控制端S2提供的第二控制信号的控制下，控制所述第一驱动电路11的控制端和所述第二驱动电路12的第二端之间连通；
所述控制数据电压写入电路17分别与第一写入控制端G1、控制数据电压写入端D1和所述第一节点m电连接，用于在所述第一写入控制端G1提供的第一写入控制信号的控制下，将所述控制数据电压写入端D1提供的控制数据电压Vdata1，写入所述第一节点m，以对所述第一节点m的电位进行置位；
所述第二驱动电路12的第二端与发光元件E0电连接，用于在其控制端的电位的控制下，驱动所述发光元件E0，或者，控制所述第二驱动电路12的第一端与所述第二驱动电路12的第二端之间连通或断开。
在本公开至少一实施例中，所述第一写入控制端可以与所述第一控制端为同一控制端，所述第二置位电压端可以为第一低电压端，所述第一置位电压端可以为第二低电压端，但不以此为限。
如图2所示，在图1所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还包括数据写入电路21、第一发光控制电路22、第二发光控制电路23和第二储能电路24；
所述数据写入电路21分别与第二写入控制端G2、数据线D0和所述第一驱动电路11的第一端电连接，用于在所述第二写入控制端G2提供的第二写入控制信号的控制下，将所述数据线D0提供的数据电压Vdata0写入所述第一驱动电路11的第一端；
所述第一发光控制电路22分别与发光控制端E1、电源电压端ELVDD和所述第一驱动电路11的第一端电连接，用于在所述发光控制端E1提供的发光控制信号的控制下，控制所述电源电压端ELVDD与所述第一驱动电路11的第一端之间连通或断开；
所述第二发光控制电路23分别与所述发光控制端E1、所述第二驱动电路12的第二端和所述发光元件E0的第一极电连接，用于在所述发光控制信号的控制下，控制所述第二驱动电路12的第二端和所述发光元件E0的第一极之间连通；
所述第二储能电路24的第一端与所述第一驱动电路11的控制端电连接，所述第二储能电路24的第二端与所述电源电压端ELVDD电连接，所述第二储能电路24用于储存电能；所述发光元件E0的第二极与第一电压端V1电连接。
在本公开至少一实施例中，所述第一电压端可以为第一低电压端，但不以此为限。
在本公开至少一实施例中，所述第二写入控制端G2可以为第二控制端S2，但不以此为限。
本公开如图2所示的像素电路的至少一实施例在工作时，显示周期包括先后设置的第一阶段、第二阶段和第三阶段；
在所述第一阶段，所述第一控制子电路161在第一控制信号的控制下， 将第二置位电压端Vz1提供的第二置位电压写入第一驱动电路11的控制端；控制数据电压写入电路17在第一写入控制端G1提供的第一写入控制信号的控制下，将控制数据电压写入端D1提供的控制数据电压Vdata1，写入所述第一节点m；
在所述第一阶段，当所述控制数据电压Vdata1为第二电压信号时，第一控制电路13在所述第一节点m的电位的控制下，控制第一驱动电路11的控制端和第二驱动电路12的控制端之间连通；当所述控制数据电压Vdata1为第三电压信号时，置位电路14在所述第一节点m的电位的控制下，将第一置位电压端Vz1提供的第一置位电压写入所述第二驱动电路12的控制端；
在所述第二阶段，数据写入电路21在第二写入控制信号的控制下，将数据线D0提供的数据电压Vdata0写入所述第一驱动电路11的第一端；所述第二控制子电路162在第二控制信号的控制下，控制所述第一驱动电路11的控制端和所述第二驱动电路12的第二端之间连通；
在所述第三阶段，所述第一发光控制电路22在发光控制信号的控制下，控制电源电压端ELVDD与所述第一驱动电路11的第一端之间连通；所述第二发光控制电路23在所述发光控制信号的控制下，控制所述第二驱动电路12的第二端和所述发光元件E0的第一极之间连通；
当在所述第一阶段，所述第一控制电路13在所述第一节点m的电位的控制下，控制第一驱动电路11的控制端和第二驱动电路12的控制端之间连通时，在所述第三阶段，所述第一驱动电路11和所述第二驱动电路12驱动所述发光元件E0发光；
当在所述第一阶段，所述置位电路14在所述第一节点m的电位的控制下，将第一置位电压端Vz1提供的第一置位电压写入所述第二驱动电路12的控制端时，在所述第三阶段，所述第一驱动电路11驱动所述发光元件E0发光，所述第二驱动电路12控制所述第二驱动电路12的第一端与所述第二驱动电路12的第二端之间连通。
在本公开至少一实施例中，第二电压信号可以为高电压信号，第三电压信号可以为低电压信号，但不以此为限。
在本公开至少一实施例中，所述第二控制电路包括第一控制子电路和第 二控制子电路；所述充电控制端包括第一控制端和第二控制端；所述连通节点与所述第一驱动电路的第一端电连接；
所述第一控制子电路分别与第一控制端、第二置位电压端和所述第一驱动电路的第一端电连接，用于在所述第一控制端提供的第一控制信号的控制下，将所述第二置位电压端提供的第二置位电压写入所述第一驱动电路的第一端，以对所述第一驱动电路的第一端的电位进行置位；
所述第二控制子电路分别与第二控制端、所述第一驱动电路的控制端和所述第一驱动电路的第一端电连接，用于在所述第二控制端提供的第二控制信号的控制下，控制所述第一驱动电路的控制端和所述第一驱动电路的第一端之间连通。
如图3所示，本公开至少一实施例所述的像素电路包括发光元件E0、第一驱动电路11、第二驱动电路12、第一控制电路13、置位电路14、第一储能电路15、第二控制电路和控制数据电压写入电路17；
所述第二控制电路包括第一控制子电路161和第二控制子电路162；所述充电控制端包括第一控制端S1和第二控制端S2；所述连通节点与所述第一驱动电路11的第一端电连接；
所述第一驱动电路11用于在其控制端的电位的控制下，产生从所述第一驱动电路11的第一端流向所述第一驱动电路11的第二端的驱动电流；所述第一驱动电路11的第一端与所述发光元件E0电连接；
所述第一驱动电路11的第二端与所述第二驱动电路12的第一端电连接；
所述第一控制电路13分别与第一节点m、所述第一驱动电路11的控制端和所述第二驱动电路12的控制端电连接，用于在所述第一节点m的电位的控制下，控制所述第一驱动电路11的控制端和所述第二驱动电路12的控制端之间连通或断开；
所述置位电路14分别与第一节点m、第一置位电压端Vz1和所述第二驱动电路12的控制端电连接，用于在所述第一节点m的电位的控制下，将所述第一置位电压端Vz1提供的第一置位电压写入所述第二驱动电路12的控制端；所述第一节点m与所述第一储能电路15的第一端电连接，所述第一储能电路15的第二端与所述第一置位电压端Vz1电连接；所述第一储能电路 15用于储存电能；
所述第一控制子电路161分别与第一控制端S1、第二置位电压端Vz2和所述第一驱动电路11的第一端电连接，用于在所述第一控制端S1提供的第一控制信号的控制下，将所述第二置位电压端Vz2提供的第二置位电压写入所述第一驱动电路11的第一端，以对所述第一驱动电路11的第一端的电位进行置位；
所述第二控制子电路162分别与第二控制端S2、所述第一驱动电路11的控制端和所述第一驱动电路11的第一端电连接，用于在所述第二控制端S2提供的第二控制信号的控制下，控制所述第一驱动电路11的控制端和所述第一驱动电路11的第一端之间连通；
所述控制数据电压写入电路17分别与第一写入控制端G1、控制数据电压写入端D1和所述第一节点m电连接，用于在所述第一写入控制端G1提供的第一写入控制信号的控制下，将所述控制数据电压写入端D1提供的控制数据电压Vdata1，写入所述第一节点m，以对所述第一节点m的电位进行置位；
所述第二驱动电路12用于在其控制端的电位的控制下，驱动所述发光元件，或者，控制所述第二驱动电路12的第一端与所述第二驱动电路12的第二端之间连通或断开。
在本公开至少一实施例中，所述第一写入控制端可以与所述第一控制端为同一控制端，所述第二置位电压端可以为电源电压端，所述第一置位电压端可以为高电压端，但不以此为限。
如图4所示，在图3所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还包括数据写入电路21、第一发光控制电路22、第二发光控制电路23和第二储能电路24；所述发光元件E0的第一极与电源电压端ELVDD电连接；
所述数据写入电路21分别与第二写入控制端G2、数据线D0和所述第二驱动电路12的第二端电连接，用于在所述第二写入控制端G2提供的第二写入控制信号的控制下，将所述数据线D0提供的数据电压Vdata0写入所述第二驱动电路12的第二端；
所述第一发光控制电路22分别与发光控制端E1、所述发光元件E0的第二极和所述第一驱动电路11的第一端电连接，用于在所述发光控制端E1提供的发光控制信号的控制下，控制所述发光元件E0的第二极和所述第一驱动电路11的第一端之间连通；
所述第二发光控制电路23分别与所述发光控制端E1、所述第二驱动电路12的第二端和第一电压端V1电连接，用于在所述发光控制信号的控制下，控制所述第二驱动电路12的第二端和第一电压端V1之间连通；
所述第二储能电路24的第一端与所述第一驱动电路11的控制端电连接，所述第二储能电路24的第二端与所述第一电压端V1电连接，所述第二储能电路24用于储存电能。
在本公开至少一实施例中，所述第一电压端可以为第一低电压端，但不以此为限。
在本公开至少一实施例中，所述第二写入控制端G2可以为第二控制端S2，但不以此为限。
本公开如图4所示的像素电路的至少一实施例在工作时，显示周期包括先后设置的第一阶段、第二阶段和第三阶段；所述驱动方法包括：
在所述第一阶段，所述第一控制子电路161在第一控制信号的控制下，将第二置位电压端Vz2提供的第二置位电压写入第一驱动电路11的第一端；所述第二控制子电路162在第二控制信号的控制下，控制所述第一驱动电路11的控制端和所述第一驱动电路11的第一端之间连通；控制数据电压写入电路17在第一写入控制端G1提供的第一写入控制信号的控制下，将控制数据电压写入端D1提供的控制数据电压Vdata1，写入所述第一节点m；
在所述第一阶段，当所述控制数据电压Vdata1为第四电压信号时，第一控制电路13在所述第一节点m的电位的控制下，控制第一驱动电路11的控制端和第二驱动电路12的控制端之间连通；当所述控制数据电压Vdata1为第五电压信号时，置位电路14在所述第一节点m的电位的控制下，将第一置位电压端Vz1提供的第一置位电压写入所述第二驱动电路12的控制端；
在所述第二发光阶段，所述数据写入电路21在第二写入控制信号的控制下，将数据线D0提供的数据电压Vdata0写入所述第二驱动电路12的第二端； 所述第二控制子电路162在第二控制信号的控制下，控制所述第一驱动电路11的控制端和所述第一驱动电路11的第一端之间连通；
在所述第三阶段，所述第一发光控制电路22在发光控制信号的控制下，控制所述发光元件E0的第二极和所述第一驱动电路11的第一端之间连通；所述第二发光控制电路23在所述发光控制信号的控制下，控制所述第二驱动电路12的第二端和第一电压端V1之间连通；
当在所述第一阶段，所述第一控制电路13在所述第一节点m的电位的控制下，控制第一驱动电路11的控制端和第二驱动电路12的控制端之间连通时，在所述第三阶段，所述第一驱动电路11和所述第二驱动电路12驱动所述发光元件发光；
当在所述第一阶段，所述置位电路14在所述第一节点m的电位的控制下，将第一置位电压端Vz1提供的第一置位电压写入所述第二驱动电路12的控制端时，在所述第三阶段，所述第一驱动电路11驱动所述发光元件E0发光，所述第二驱动电路12控制所述第二驱动电路12的第一端与所述第二驱动电路12的第二端之间连通。
在本公开至少一实施例中，所述第四电压信号可以为高电压信号，所述第五电压信号为低电压端，但不以此为限。
可选的，所述第一控制电路包括第一晶体管；
所述第一晶体管的控制极与所述第一节点电连接，所述第一晶体管的第一极与所述第一驱动电路的控制端电连接，所述第一晶体管的第二极与所述第二驱动电路的控制端电连接；
所述置位电路包括第二晶体管；
所述第二晶体管的控制极与所述第一节点电连接，所述第二晶体管的第一极与所述第一置位电压端电连接，所述第二晶体管的第二极与所述第二驱动电路的控制端电连接；
所述控制数据电压写入电路包括第三晶体管；
所述第三晶体管的控制极与所述第一写入控制端电连接，所述第三晶体管的第一极与所述控制数据电压写入端电连接，所述第三晶体管的第二极与所述第一节点电连接；
所述第一储能电路包括第一电容；
所述第一节点与所述第一电容的第一端电连接，所述第一电容的第二端与所述第一置位电压端电连接。
可选的，所述第一控制子电路包括第四晶体管，所述第二控制子电路包括第五晶体管；
所述第四晶体管的控制极与所述第一控制端电连接，所述第四晶体管的第一极与所述第二置位电压端电连接，所述第四晶体管的第二极与所述第一驱动电路的控制端电连接；
所述第五晶体管的控制极与所述第二控制端电连接，所述第五晶体管的第一极与所述第一驱动电路的控制端电连接，所述第五晶体管的第二极与所述第二驱动电路的第二端电连接。
可选的，所述第一控制子电路包括第四晶体管，所述第二控制子电路包括第五晶体管；
所述第四晶体管的控制极与所述第一控制端电连接，所述第四晶体管的第一极与所述第二置位电压端电连接，所述第四晶体管的第二极与所述第一驱动电路的控制端电连接；
所述第五晶体管的控制极与所述第二控制端电连接，所述第五晶体管的第一极与所述第一驱动电路的控制端电连接，所述第五晶体管的第二极与所述第一驱动电路的第一端电连接。
可选的，所述发光元件为有机发光二极管，所述数据写入电路包括第六晶体管，所述第一发光控制电路包括第七晶体管、所述第二发光控制电路包括第八晶体管，所述第二储能电路包括第二电容；
所述第六晶体管的控制极与所述第二写入控制端电连接，所述第六晶体管的第一极与所述数据线电连接，所述第六晶体管的第二极与所述第一驱动电路的第一端电连接；
所述第七晶体管的控制极与所述发光控制端电连接，所述第七晶体管的第一极与所述电源电压端电连接，所述第七晶体管的第二极与所述第一驱动电路的第一端电连接；
所述第八晶体管的控制极与所述发光控制端电连接，所述第八晶体管的 第一极与所述第二驱动电路的第二端电连接，所述第八晶体管的第二极与所述有机发光二极管的阳极电连接；
所述第二电容的第一端与所述第一驱动电路的控制端电连接，所述第二电容的第二端与所述电源电压端电连接，所述第二储能电路用于储存电能；所述有机发光二极管的阴极与第一电压端电连接。
可选的，所述发光元件为有机发光二极管，所述数据写入电路包括第六晶体管，所述第一发光控制电路包括第七晶体管、所述第二发光控制电路包括第八晶体管，所述第二储能电路包括第二电容；所述有机发光二极管的阳极与所述电源电压端电连接；
所述第六晶体管的控制极与所述第二写入控制端电连接，所述第六晶体管的第一极与所述数据线电连接，所述第六晶体管的第二极与所述第二驱动电路的第二端电连接；
所述第七晶体管的控制极与所述发光控制端电连接，所述第七晶体管的第一极与所述有机发光二极管的阴极电连接，所述第七晶体管的第二极与所述第一驱动电路的第一端电连接；
所述第八晶体管的控制极与所述发光控制端电连接，所述第八晶体管的第一极与所述第二驱动电路的第二端电连接，所述第八晶体管的第二极与所述第一电压端电连接；
所述第二电容的第一端与所述第一驱动电路的控制端电连接，所述第二电容的第二端与所述第一电压端电连接。
可选的，所述第一驱动电路包括第一驱动晶体管，所述第二驱动电路包括第二驱动晶体管；
所述第一驱动晶体管的控制极与所述第一驱动电路的控制端电连接，所述第一驱动晶体管的第一极与所述第一驱动电路的第一端电连接，所述第一驱动晶体管的第二极与所述第一驱动电路的第二端电连接；
所述第二驱动晶体管的控制极与所述第二驱动电路的控制端电连接，所述第二驱动晶体管的第一极与所述第二驱动电路的第一端电连接，所述第二驱动晶体管的第二极与所述第二驱动电路的第二端电连接。
如图5所示，在图2所示的像素电路的至少一实施例的基础上，所述第 一控制电路13包括第一晶体管T1；所述第一驱动电路11包括第一驱动晶体管T01，所述第二驱动电路12包括第二驱动晶体管T02；
所述第一晶体管T1的栅极与所述第一节点m电连接，所述第一晶体管T1的源极与所述第一驱动晶体管T01的栅极电连接，所述第一晶体管T1的漏极与所述第二驱动晶体管T02的栅极电连接；
所述置位电路14包括第二晶体管T2；
所述第二晶体管T2的栅极与所述第一节点m电连接，所述第二晶体管T2的源极与第二低电压端VGL电连接，所述第二晶体管T2的漏极与所述第二驱动晶体管T02的栅极电连接；所述第二低电压端VGL用于提供第二低电压；
所述控制数据电压写入电路17包括第三晶体管T3；
所述第三晶体管T3的栅极与第一控制端S1电连接，所述第三晶体管T3的源极与所述控制数据电压写入端D1电连接，所述第三晶体管T3的漏极与所述第一节点m电连接；
所述第一储能电路15包括第一电容C1；
所述第一节点m与所述第一电容C1的第一端电连接，所述第一电容C1的第二端与第二低电压端VGL电连接；
所述第一控制子电路161包括第四晶体管T4，所述第二控制子电路162包括第五晶体管T5；
所述第四晶体管T4的栅极与所述第一控制端S1电连接，所述第四晶体管T4的源极与第一低电压端VS电连接，所述第四晶体管T4的漏极与所述第一驱动晶体管T01的栅极电连接；所述第一低电压端用于提供第一低电压Vss；
所述第五晶体管T5的栅极与所述第二控制端S2电连接，所述第五晶体管T5的源极与所述第一驱动晶体管T01的栅极电连接，所述第五晶体管T5的漏极与所述第二驱动晶体管T02的漏极电连接；
所述发光元件为有机发光二极管O1，所述数据写入电路21包括第六晶体管T6，所述第一发光控制电路22包括第七晶体管T7、所述第二发光控制电路23包括第八晶体管T8，所述第二储能电路24包括第二电容C2；
所述第六晶体管T6的栅极与所述第二控制端S2电连接，所述第六晶体管T6的源极与所述数据线D0电连接，所述第六晶体管T6的漏极与所述第一驱动晶体管T01的源极电连接；
所述第七晶体管T7的栅极与所述发光控制端E1电连接，所述第七晶体管T7的源极与所述电源电压端ELVDD电连接，所述第七晶体管T7的漏极与所述第一驱动晶体管T01的源极电连接；
所述第八晶体管T8的栅极与所述发光控制端E1电连接，所述第八晶体管T8的源极与所述第二驱动晶体管T02的漏极电连接，所述第八晶体管T8的漏极与所述有机发光二极管O1的阳极电连接；
所述第二电容C2的第一端与所述第一驱动晶体管T01的栅极电连接，所述第二电容C2的第二端与所述电源电压端ELVDD电连接，所述有机发光二极管O1的阴极与第一低电压端VS电连接；所述电源电压端ELVDD用于提供电源电压Vdd。
在图5所示的像素电路的至少一实施例中，T1、T3和T4都为n型晶体管，T2、T5、T6、T7、T8、T01和T02为p型晶体管，但不以此为限。
在本公开至少一实施例中，T01的阈值电压与T02的阈值电压相等，T01的阈值电压与T02的阈值电压为Vth。
在图5所示的像素电路的至少一实施例中，第一写入控制端与第一控制端为同一控制端，第二写入控制端与第二控制端为同一控制端；所述第二置位电压端为第一低电压端VS，所述第一置位电压端为第二低电压端VGL，但不以此为限。
如图6所示，本公开如图5所示的像素电路的至少一实施例在工作时，显示周期可以包括先后设置的第一阶段t1、第二阶段t2和第三阶段t3；
在第一阶段t1，S1提供高电压信号，S2提供高电压信号，E1提供高电压信号，T4打开，以将第一低电压Vss写入T01的栅极；T3打开，D1提供控制数据电压Vdata1，以将Vdata1写入第一节点m；
在所述第一阶段t1，当Vdata1为高电压信号时，T1打开，T2关断，T01的栅极与T02的栅极之间连通；
在所述第一阶段t1，当Vdata1为低电压信号时，T1关断，T2打开，以 将第二低电压写入T02的栅极；
在第二阶段t2，S1提供低电压信号，S2提供低电压信号，E1提供高电压信号，T6打开，D0提供数据电压Vdata0，以将数据电压Vdata0写入T01的源极，T5导通；
在第二阶段t2开始时，T01和T02打开，Vdata0通过T6、T01、T02和T5为C2充电，直至T01和T02关断，此时，T01的栅极的电位变为Vdata0+Vth；
在第三阶段t3，S1提供低电压信号，S2提供高电压信号，E1提供低电压信号，T5和T8打开；
当在第一阶段t1，T1打开，T2关断，T01的栅极与T02之间连通时，在第三阶段t3，T01和T02共同驱动O1发光；
当在第一阶段t1，T1关断，T2打开，以将第二低电压写入T02的栅极时，在第三阶段t3，T02完全打开，T01驱动O1发光。
在图5所示的像素电路的至少一实施例中，T01的沟道的宽度和T02的沟道的宽度都为W，T01的沟道的长度为L1，T02的沟道的长度为L2。
本公开如图5所示的像素电路的至少一实施例在工作时，
在第三阶段t3，当在进行低灰阶显示时，T01和T02共同驱动O1发光，此时流过O1的电流I等于0.5(W/(L1+L2))×Cox×μ×(Vdata0-Vdd) 2；其中，Cox为单位面积的栅氧化层电容，μ为迁移率；
在第三阶段，当在进行高灰阶显示时，T02完全打开，T01驱动O1发光，此时流过O1的电流I等于0.5(W/L1)×Cox×μ×(Vdata0-Vdd) 2。
如图7所示，在图4所示的像素电路的至少一实施例的基础上，所述第一控制电路13包括第一晶体管T1；所述第一驱动电路11包括第一驱动晶体管T01，所述第二驱动电路12包括第二驱动晶体管T02；
所述第一晶体管T1的栅极与所述第一节点m电连接，所述第一晶体管T1的源极与所述第一驱动晶体管T01的栅极电连接，所述第一晶体管T1的漏极与所述第二驱动晶体管T02的栅极电连接；
所述置位电路包括第二晶体管T2；
所述第二晶体管T2的栅极与所述第一节点m电连接，所述第二晶体管T2的源极与高电压端VGH电连接，所述第二晶体管T2的漏极与所述第二驱 动晶体管T02的栅极电连接；所述高电压端VGH用于提供高电压；
所述控制数据电压写入电路17包括第三晶体管T3；
所述第三晶体管T3的栅极与第一控制端S1电连接，所述第三晶体管T3的源极与所述控制数据电压写入端D1电连接，所述第三晶体管T3的漏极与所述第一节点m电连接；
所述第一储能电路15包括第一电容C1；
所述第一节点m与所述第一电容C1的第一端电连接，所述第一电容C1的第二端与所述高电压端VGH电连接；
所述第一控制子电路161包括第四晶体管T4，所述第二控制子电路162包括第五晶体管T5；
所述第四晶体管T4的栅极与所述第一控制端S1电连接，所述第四晶体管T4的源极与电源电压端ELVDD电连接，所述第四晶体管T4的漏极与所述第一驱动晶体管T01的栅极电连接；所述电源电压端用于提供电源电压Vdd；
所述第五晶体管T5的栅极与所述第二控制端S2电连接，所述第五晶体管T5的源极与所述第一驱动晶体管T01的栅极电连接，所述第五晶体管T5的漏极与所述第一驱动晶体管T01的源极电连接；
所述发光元件为有机发光二极管O1，所述数据写入电路21包括第六晶体管T6，所述第一发光控制电路22包括第七晶体管T7，所述第二发光控制电路23包括第八晶体管T8，所述第二储能电路24包括第二电容C2；所述有机发光二极管O1的阳极与所述电源电压端ELVDD电连接；所述电源电压端用于提供电源电压Vdd；
所述第六晶体管T6的栅极与所述第二控制端S2电连接，所述第六晶体管T6的源极与所述数据线D0电连接，所述第六晶体管T6的漏极与所述第二驱动晶体管T02的漏极电连接；
所述第七晶体管T7的栅极与所述发光控制端E1电连接，所述第七晶体管T7的源极与所述有机发光二极管O1的阴极电连接，所述第七晶体管T7的漏极与所述第一驱动晶体管T01的源极电连接；
所述第八晶体管T8的栅极与所述发光控制端E1电连接，所述第八晶体 管T8的源极与所述第二驱动晶体管T02的漏极电连接，所述第八晶体管T8的漏极与第一低电压端VS电连接；所述第一低电压端VS用于提供第一低电压Vss；
所述第二电容C2的第一端与所述第一驱动晶体管T01的栅极电连接，所述第二电容C2的第二端与所述第一低电压端VS电连接。
在图7所示的像素电路的至少一实施例中，T01的阈值电压与T02的阈值电压相等，T01的阈值电压与T02的阈值电压都为Vth。
在图7所示的像素电路的至少一实施例中，所述第一写入控制端与所述第一控制端为同一控制端，所述第二写入控制端与所述第二控制端为同一控制端；所述第二置位电压端可以为电源电压端ELVDD，所述第一置位电压端可以为高电压端VGH，但不以此为限。
在图7所示的像素电路的至少一实施例中，T2是p型晶体管，T1、T3、T4、T5、T6、T7、T8、T01和T02都为n型晶体管，但不以此为限。
如图8所示，本公开如图7所示的像素电路的至少一实施例在工作时，显示周期包括先后设置的第一阶段t1、第二阶段t2和第三阶段t3；
在第一阶段t1，S1提供高电压信号，S2提供高电压信号，E1提供低电压信号，T4和T5打开，以将电源电压Vdd写入T01的栅极；T3导通，D1提供控制数据电压Vdata1至第一节点m；
在第一阶段t1，当Vdata1为高电压信号时，T1打开，T2关断，以使得T01的栅极与T02的栅极之间连通；
在第一阶段t1，当Vdata1为低电压信号时，T1关断，T2打开，以将所述高电压端VGH提供的高电压写入T02的栅极；
在第二阶段t2，S1提供低电压信号，S2提供高电压信号，E1提供低电压信号，D0提供数据电压Vdata0，T6打开，以将所述数据电压Vdata0写入T02的漏极；
在第二阶段t2开始时，T01和T02导通，Vdata0通过T6、T01、T02和T5为C2充电，以提升T01的栅极的电位，直至T01关断；此时，T01的栅极的电位变为Vdata0+Vth；
在第三阶段t3，S1提供低电压信号，S2提供低电压信号，E1提供高电 压信号，T7和T8都打开；T1的源极电位为Vdd-Voled，Voled为O1的阈值开启电压；
当在第一阶段t1，T01的栅极与T02的栅极之间连通时，在第三阶段t3，T01和T02共同驱动O1发光；
当在第一阶段t1，T1关断，T2打开，以将所述高电压端VGH提供的高电压写入T02的栅极时，在第三阶段t3，T01驱动O1发光，T02完全打开。
在图7所示的像素电路的至少一实施例中，T01的沟道的宽度和T02的沟道的宽度都为W，T01的沟道的长度为L1，T02的沟道的长度为L2。
本公开如图7所示的像素电路的至少一实施例在工作时，
在第三阶段t3，当在进行低灰阶显示时，T01和T02共同驱动O1发光，此时流过O1的电流I等于0.5(W/(L1+L2))×Cox×μ×(Vdata0-Vdd+Voled) 2；其中，Cox为单位面积的栅氧化层电容，μ为迁移率；
在第三阶段，当在进行高灰阶显示时，T02完全打开，T01驱动O1发光，此时流过O1的电流I等于0.5(W/L1)×Cox×μ×(Vdata0-Vdd+Voled) 2。
本公开实施例所述的驱动方法，应用于上述的像素电路，所述驱动方法包括：
所述第一控制电路在第一节点的电位的控制下，控制第一驱动电路的控制端和第二驱动电路的控制端之间连通或断开；
置位电路在第一节点的电位的控制下，将第一置位电压端提供的第一置位电压写入第二驱动电路的控制端；
第二控制电路用于在充电控制端提供的控制信号的控制下，将第二置位电压提供至第一驱动电路的控制端，并控制所述第一驱动电路的控制端与连通节点之间连通或断开；
控制数据电压写入电路在第一写入控制信号的控制下，将控制数据电压写入端提供的控制数据电压，写入第一节点；
所述第一驱动电路在其控制端的电位的控制下，产生从所述第一驱动电路的第一端流向所述第一驱动电路的第二端的驱动电流；
所述第二驱动电路在其控制端的电位的控制下，驱动所述发光元件，或者，所述第二驱动电路在其控制端的电位的控制下，控制所述第二驱动电路 的第一端与所述第二驱动电路的第二端之间连通或断开。
在本公开至少一实施例中，所述第二控制电路包括第一控制子电路和第二控制子电路；连通节点与第二驱动电路的第二端电连接；所述像素电路还包括发光元件、数据写入电路、第一发光控制电路、第二发光控制电路和第二储能电路；显示周期包括先后设置的第一阶段、第二阶段和第三阶段；所述驱动方法包括：
在所述第一阶段，所述第一控制子电路在第一控制信号的控制下，将第二置位电压端提供的第二置位电压写入第一驱动电路的控制端；控制数据电压写入电路在第一写入控制端提供的第一写入控制信号的控制下，将控制数据电压写入端提供的控制数据电压，写入所述第一节点；
在所述第一阶段，当所述控制数据电压为第二电压信号时，第一控制电路在所述第一节点的电位的控制下，控制第一驱动电路的控制端和第二驱动电路的控制端之间连通；当所述控制数据电压为第三电压信号时，置位电路在所述第一节点的电位的控制下，将第一置位电压端提供的第一置位电压写入所述第二驱动电路的控制端；
在所述第二阶段，数据写入电路在第二写入控制信号的控制下，将数据线提供的数据电压写入所述第一驱动电路的第一端；所述第二控制子电路在第二控制信号的控制下，控制所述第一驱动电路的控制端和所述第二驱动电路的第二端之间连通；
在所述第三阶段，所述第一发光控制电路在发光控制信号的控制下，控制电源电压端与所述第一驱动电路的第一端之间连通；所述第二发光控制电路在所述发光控制信号的控制下，控制所述第二驱动电路的第二端和所述发光元件的第一极之间连通；
当在所述第一阶段，所述第一控制电路在所述第一节点的电位的控制下，控制第一驱动电路的控制端和第二驱动电路的控制端之间连通时，在所述第三阶段，所述第一驱动电路和所述第二驱动电路驱动所述发光元件发光；
当在所述第一阶段，所述置位电路在所述第一节点的电位的控制下，将第一置位电压端提供的第一置位电压写入所述第二驱动电路的控制端时，在所述第三阶段，所述第一驱动电路驱动所述发光元件发光，所述第二驱动电 路控制所述第二驱动电路的第一端与所述第二驱动电路的第二端之间连通。
在本公开至少一实施例中，所述第二控制电路包括第一控制子电路和第二控制子电路；所述连通节点与所述第一驱动电路的第一端电连接；所述像素电路还包括发光元件、数据写入电路、第一发光控制电路、第二发光控制电路和第二储能电路；显示周期包括先后设置的第一阶段、第二阶段和第三阶段；所述驱动方法包括：
在所述第一阶段，所述第一控制子电路在第一控制信号的控制下，将第二置位电压端提供的第二置位电压写入第一驱动电路的第一端；所述第二控制子电路在第二控制信号的控制下，控制所述第一驱动电路的控制端和所述第一驱动电路的第一端之间连通；控制数据电压写入电路在第一写入控制端提供的第一写入控制信号的控制下，将控制数据电压写入端提供的控制数据电压，写入所述第一节点；
在所述第一阶段，当所述控制数据电压为第四电压信号时，第一控制电路在所述第一节点的电位的控制下，控制第一驱动电路的控制端和第二驱动电路的控制端之间连通；当所述控制数据电压为第五电压信号时，置位电路在所述第一节点的电位的控制下，将第一置位电压端提供的第一置位电压写入所述第二驱动电路的控制端；
在所述第二发光阶段，所述数据写入电路在第二写入控制信号的控制下，将数据线提供的数据电压写入所述第二驱动电路的第二端；所述第二控制子电路在第二控制信号的控制下，控制所述第一驱动电路的控制端和所述第一驱动电路的第一端之间连通；
在所述第三阶段，所述第一发光控制电路在发光控制信号的控制下，控制所述发光元件的第二极和所述第一驱动电路的第一端之间连通；所述第二发光控制电路在所述发光控制信号的控制下，控制所述第二驱动电路的第二端和第一电压端之间连通；
当在所述第一阶段，所述第一控制电路在所述第一节点的电位的控制下，控制第一驱动电路的控制端和第二驱动电路的控制端之间连通时，在所述第三阶段，所述第一驱动电路和所述第二驱动电路驱动所述发光元件发光；
当在所述第一阶段，所述置位电路在所述第一节点的电位的控制下，将 第一置位电压端提供的第一置位电压写入所述第二驱动电路的控制端时，在所述第三阶段，所述第一驱动电路驱动所述发光元件发光，所述第二驱动电路控制所述第二驱动电路的第一端与所述第二驱动电路的第二端之间连通。
本公开在实施例所述的显示装置包括上述的像素电路。
本公开实施例所提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (15)

  1. 一种像素电路，包括发光元件、第一驱动电路、第二驱动电路、第一控制电路、置位电路、第一储能电路、第二控制电路和控制数据电压写入电路；
    所述第一驱动电路用于在其控制端的电位的控制下，产生从所述第一驱动电路的第一端流向所述第一驱动电路的第二端的驱动电流；
    所述第一驱动电路的第二端与所述第二驱动电路的第一端电连接；
    所述第一控制电路分别与第一节点、所述第一驱动电路的控制端和所述第二驱动电路的控制端电连接，用于在所述第一节点的电位的控制下，控制所述第一驱动电路的控制端和所述第二驱动电路的控制端之间连通或断开；
    所述置位电路分别与第一节点、第一置位电压端和所述第二驱动电路的控制端电连接，用于在所述第一节点的电位的控制下，将所述第一置位电压端提供的第一置位电压写入所述第二驱动电路的控制端；所述第一节点与所述第一储能电路的第一端电连接，所述第一储能电路的第二端与所述第一置位电压端电连接；所述第一储能电路用于储存电能；
    所述第二控制电路用于在充电控制端提供的控制信号的控制下，将第二置位电压提供至第一驱动电路的控制端，并控制所述第一驱动电路的控制端与连通节点之间连通或断开；所述连通节点与所述第二驱动电路的第二端电连接，或者，所述连通节点与所述第一驱动电路的第一端电连接；
    所述控制数据电压写入电路分别与第一写入控制端、控制数据电压写入端和所述第一节点电连接，用于在所述第一写入控制端提供的第一写入控制信号的控制下，将所述控制数据电压写入端提供的控制数据电压，写入所述第一节点；
    所述第二驱动电路用于在其控制端的电位的控制下，驱动所述发光元件，或者，控制所述第二驱动电路的第一端与所述第二驱动电路的第二端之间连通或断开。
  2. 如权利要求1所述的像素电路，其中，所述第二控制电路包括第一控制子电路和第二控制子电路；所述充电控制端包括第一控制端和第二控制端； 所述连通节点与所述第二驱动电路的第二端电连接；
    所述第一控制子电路分别与第一控制端、第二置位电压端和所述第一驱动电路的控制端电连接，用于在所述第一控制端提供的第一控制信号的控制下，将所述第二置位电压端提供的第二置位电压写入所述第一驱动电路的控制端；
    所述第二控制子电路分别与第二控制端、所述第一驱动电路的控制端和所述第二驱动电路的第二端电连接，用于在所述第二控制端提供的第二控制信号的控制下，控制所述第一驱动电路的控制端和所述第二驱动电路的第二端之间连通。
  3. 如权利要求1所述的像素电路，其中，所述第二控制电路包括第一控制子电路和第二控制子电路；所述充电控制端包括第一控制端和第二控制端；所述连通节点与所述第一驱动电路的第一端电连接；
    所述第一控制子电路分别与第一控制端、第二置位电压端和所述第一驱动电路的第一端电连接，用于在所述第一控制端提供的第一控制信号的控制下，将所述第二置位电压端提供的第二置位电压写入所述第一驱动电路的第一端；
    所述第二控制子电路分别与第二控制端、所述第一驱动电路的控制端和所述第一驱动电路的第一端电连接，用于在所述第二控制端提供的第二控制信号的控制下，控制所述第一驱动电路的控制端和所述第一驱动电路的第一端之间连通。
  4. 如权利要求2所述的像素电路，其中，还包括数据写入电路、第一发光控制电路、第二发光控制电路和第二储能电路；
    所述数据写入电路分别与第二写入控制端、数据线和所述第一驱动电路的第一端电连接，用于在所述第二写入控制端提供的第二写入控制信号的控制下，将所述数据线提供的数据电压写入所述第一驱动电路的第一端；
    所述第一发光控制电路分别与发光控制端、电源电压端和所述第一驱动电路的第一端电连接，用于在所述发光控制端提供的发光控制信号的控制下，控制所述电源电压端与所述第一驱动电路的第一端之间连通或断开；
    所述第二发光控制电路分别与所述发光控制端、所述第二驱动电路的第 二端和所述发光元件的第一极电连接，用于在所述发光控制信号的控制下，控制所述第二驱动电路的第二端和所述发光元件的第一极之间连通；
    所述第二储能电路的第一端与所述第一驱动电路的控制端电连接，所述第二储能电路的第二端与所述电源电压端电连接，所述第二储能电路用于储存电能；所述发光元件的第二极与第一电压端电连接。
  5. 如权利要求3所述的像素电路，其中，还包括发光元件、数据写入电路、第一发光控制电路、第二发光控制电路和第二储能电路；所述发光元件的第一极与电源电压端电连接；
    所述数据写入电路分别与第二写入控制端、数据线和所述第二驱动电路的第二端电连接，用于在所述第二写入控制端提供的第二写入控制信号的控制下，将所述数据线提供的数据电压写入所述第二驱动电路的第二端；
    所述第一发光控制电路分别与发光控制端、所述发光元件的第二极和所述第一驱动电路的第一端电连接，用于在所述发光控制端提供的发光控制信号的控制下，控制所述发光元件的第二极和所述第一驱动电路的第一端之间连通；
    所述第二发光控制电路分别与所述发光控制端、所述第二驱动电路的第二端和第一电压端电连接，用于在所述发光控制信号的控制下，控制所述第二驱动电路的第二端和第一电压端之间连通；
    所述第二储能电路的第一端与所述第一驱动电路的控制端电连接，所述第二储能电路的第二端与所述第一电压端电连接，所述第二储能电路用于储存电能。
  6. 如权利要求1所述的像素电路，其中，所述第一控制电路包括第一晶体管；
    所述第一晶体管的控制极与所述第一节点电连接，所述第一晶体管的第一极与所述第一驱动电路的控制端电连接，所述第一晶体管的第二极与所述第二驱动电路的控制端电连接；
    所述置位电路包括第二晶体管；
    所述第二晶体管的控制极与所述第一节点电连接，所述第二晶体管的第一极与所述第一置位电压端电连接，所述第二晶体管的第二极与所述第二驱 动电路的控制端电连接；
    所述控制数据电压写入电路包括第三晶体管；
    所述第三晶体管的控制极与所述第一写入控制端电连接，所述第三晶体管的第一极与所述控制数据电压写入端电连接，所述第三晶体管的第二极与所述第一节点电连接；
    所述第一储能电路包括第一电容；
    所述第一节点与所述第一电容的第一端电连接，所述第一电容的第二端与所述第一置位电压端电连接。
  7. 如权利要求2所述的像素电路，其中，所述第一控制子电路包括第四晶体管，所述第二控制子电路包括第五晶体管；
    所述第四晶体管的控制极与所述第一控制端电连接，所述第四晶体管的第一极与所述第二置位电压端电连接，所述第四晶体管的第二极与所述第一驱动电路的控制端电连接；
    所述第五晶体管的控制极与所述第二控制端电连接，所述第五晶体管的第一极与所述第一驱动电路的控制端电连接，所述第五晶体管的第二极与所述第二驱动电路的第二端电连接。
  8. 如权利要求3所述的像素电路，其中，所述第一控制子电路包括第四晶体管，所述第二控制子电路包括第五晶体管；
    所述第四晶体管的控制极与所述第一控制端电连接，所述第四晶体管的第一极与所述第二置位电压端电连接，所述第四晶体管的第二极与所述第一驱动电路的控制端电连接；
    所述第五晶体管的控制极与所述第二控制端电连接，所述第五晶体管的第一极与所述第一驱动电路的控制端电连接，所述第五晶体管的第二极与所述第一驱动电路的第一端电连接。
  9. 如权利要求4所述的像素电路，其中，所述发光元件为有机发光二极管，所述数据写入电路包括第六晶体管，所述第一发光控制电路包括第七晶体管、所述第二发光控制电路包括第八晶体管，所述第二储能电路包括第二电容；
    所述第六晶体管的控制极与所述第二写入控制端电连接，所述第六晶体 管的第一极与所述数据线电连接，所述第六晶体管的第二极与所述第一驱动电路的第一端电连接；
    所述第七晶体管的控制极与所述发光控制端电连接，所述第七晶体管的第一极与所述电源电压端电连接，所述第七晶体管的第二极与所述第一驱动电路的第一端电连接；
    所述第八晶体管的控制极与所述发光控制端电连接，所述第八晶体管的第一极与所述第二驱动电路的第二端电连接，所述第八晶体管的第二极与所述有机发光二极管的阳极电连接；
    所述第二电容的第一端与所述第一驱动电路的控制端电连接，所述第二电容的第二端与所述电源电压端电连接；所述有机发光二极管的阴极与第一电压端电连接。
  10. 如权利要求5所述的像素电路，其中，所述发光元件为有机发光二极管，所述数据写入电路包括第六晶体管，所述第一发光控制电路包括第七晶体管、所述第二发光控制电路包括第八晶体管，所述第二储能电路包括第二电容；所述有机发光二极管的阳极与所述电源电压端电连接；
    所述第六晶体管的控制极与所述第二写入控制端电连接，所述第六晶体管的第一极与所述数据线电连接，所述第六晶体管的第二极与所述第二驱动电路的第二端电连接；
    所述第七晶体管的控制极与所述发光控制端电连接，所述第七晶体管的第一极与所述有机发光二极管的阴极电连接，所述第七晶体管的第二极与所述第一驱动电路的第一端电连接；
    所述第八晶体管的控制极与所述发光控制端电连接，所述第八晶体管的第一极与所述第二驱动电路的第二端电连接，所述第八晶体管的第二极与所述第一电压端电连接；
    所述第二电容的第一端与所述第一驱动电路的控制端电连接，所述第二电容的第二端与所述第一电压端电连接。
  11. 如权利要求1至10中任一权利要求所述的像素电路，其中，所述第一驱动电路包括第一驱动晶体管，所述第二驱动电路包括第二驱动晶体管；
    所述第一驱动晶体管的控制极与所述第一驱动电路的控制端电连接，所 述第一驱动晶体管的第一极与所述第一驱动电路的第一端电连接，所述第一驱动晶体管的第二极与所述第一驱动电路的第二端电连接；
    所述第二驱动晶体管的控制极与所述第二驱动电路的控制端电连接，所述第二驱动晶体管的第一极与所述第二驱动电路的第一端电连接，所述第二驱动晶体管的第二极与所述第二驱动电路的第二端电连接。
  12. 一种驱动方法，应用于如权利要求1至11中任一权利要求所述的像素电路，所述驱动方法包括：
    所述第一控制电路在第一节点的电位的控制下，控制第一驱动电路的控制端和第二驱动电路的控制端之间连通或断开；
    置位电路在第一节点的电位的控制下，将第一置位电压端提供的第一置位电压写入第二驱动电路的控制端；
    第二控制电路用于在充电控制端提供的控制信号的控制下，将第二置位电压提供至第一驱动电路的控制端，并控制所述第一驱动电路的控制端与连通节点之间连通或断开；
    控制数据电压写入电路在第一写入控制信号的控制下，将控制数据电压写入端提供的控制数据电压，写入第一节点；
    所述第一驱动电路在其控制端的电位的控制下，产生从所述第一驱动电路的第一端流向所述第一驱动电路的第二端的驱动电流；
    所述第二驱动电路在其控制端的电位的控制下，驱动所述发光元件，或者，所述第二驱动电路在其控制端的电位的控制下，控制所述第二驱动电路的第一端与所述第二驱动电路的第二端之间连通或断开。
  13. 如权利要求12所述的驱动方法，其中，所述第二控制电路包括第一控制子电路和第二控制子电路；连通节点与第二驱动电路的第二端电连接；所述像素电路还包括发光元件、数据写入电路、第一发光控制电路、第二发光控制电路和第二储能电路；显示周期包括先后设置的第一阶段、第二阶段和第三阶段；所述驱动方法包括：
    在所述第一阶段，所述第一控制子电路在第一控制信号的控制下，将第二置位电压端提供的第二置位电压写入第一驱动电路的控制端；控制数据电压写入电路在第一写入控制端提供的第一写入控制信号的控制下，将控制数 据电压写入端提供的控制数据电压，写入所述第一节点；
    在所述第一阶段，当所述控制数据电压为第二电压信号时，第一控制电路在所述第一节点的电位的控制下，控制第一驱动电路的控制端和第二驱动电路的控制端之间连通；当所述控制数据电压为第三电压信号时，置位电路在所述第一节点的电位的控制下，将第一置位电压端提供的第一置位电压写入所述第二驱动电路的控制端；
    在所述第二阶段，数据写入电路在第二写入控制信号的控制下，将数据线提供的数据电压写入所述第一驱动电路的第一端；所述第二控制子电路在第二控制信号的控制下，控制所述第一驱动电路的控制端和所述第二驱动电路的第二端之间连通；
    在所述第三阶段，所述第一发光控制电路在发光控制信号的控制下，控制电源电压端与所述第一驱动电路的第一端之间连通；所述第二发光控制电路在所述发光控制信号的控制下，控制所述第二驱动电路的第二端和所述发光元件的第一极之间连通；
    当在所述第一阶段，所述第一控制电路在所述第一节点的电位的控制下，控制第一驱动电路的控制端和第二驱动电路的控制端之间连通时，在所述第三阶段，所述第一驱动电路和所述第二驱动电路驱动所述发光元件发光；
    当在所述第一阶段，所述置位电路在所述第一节点的电位的控制下，将第一置位电压端提供的第一置位电压写入所述第二驱动电路的控制端时，在所述第三阶段，所述第一驱动电路驱动所述发光元件发光，所述第二驱动电路控制所述第二驱动电路的第一端与所述第二驱动电路的第二端之间连通。
  14. 如权利要求12所述的驱动方法，其中，所述第二控制电路包括第一控制子电路和第二控制子电路；所述连通节点与所述第一驱动电路的第一端电连接；所述像素电路还包括发光元件、数据写入电路、第一发光控制电路、第二发光控制电路和第二储能电路；显示周期包括先后设置的第一阶段、第二阶段和第三阶段；所述驱动方法包括：
    在所述第一阶段，所述第一控制子电路在第一控制信号的控制下，将第二置位电压端提供的第二置位电压写入第一驱动电路的第一端；所述第二控制子电路在第二控制信号的控制下，控制所述第一驱动电路的控制端和所述 第一驱动电路的第一端之间连通；控制数据电压写入电路在第一写入控制端提供的第一写入控制信号的控制下，将控制数据电压写入端提供的控制数据电压，写入所述第一节点；
    在所述第一阶段，当所述控制数据电压为第四电压信号时，第一控制电路在所述第一节点的电位的控制下，控制第一驱动电路的控制端和第二驱动电路的控制端之间连通；当所述控制数据电压为第五电压信号时，置位电路在所述第一节点的电位的控制下，将第一置位电压端提供的第一置位电压写入所述第二驱动电路的控制端；
    在所述第二发光阶段，所述数据写入电路在第二写入控制信号的控制下，将数据线提供的数据电压写入所述第二驱动电路的第二端；所述第二控制子电路在第二控制信号的控制下，控制所述第一驱动电路的控制端和所述第一驱动电路的第一端之间连通；
    在所述第三阶段，所述第一发光控制电路在发光控制信号的控制下，控制所述发光元件的第二极和所述第一驱动电路的第一端之间连通；所述第二发光控制电路在所述发光控制信号的控制下，控制所述第二驱动电路的第二端和第一电压端之间连通；
    当在所述第一阶段，所述第一控制电路在所述第一节点的电位的控制下，控制第一驱动电路的控制端和第二驱动电路的控制端之间连通时，在所述第三阶段，所述第一驱动电路和所述第二驱动电路驱动所述发光元件发光；
    当在所述第一阶段，所述置位电路在所述第一节点的电位的控制下，将第一置位电压端提供的第一置位电压写入所述第二驱动电路的控制端时，在所述第三阶段，所述第一驱动电路驱动所述发光元件发光，所述第二驱动电路控制所述第二驱动电路的第一端与所述第二驱动电路的第二端之间连通。
  15. 一种显示装置，包括如权利要求1至11中任一权利要求所述的像素电路。
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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060093954A (ko) * 2005-02-23 2006-08-28 삼성에스디아이 주식회사 유기전계발광장치의 화소 회로
CN101174381A (zh) * 2006-10-31 2008-05-07 Lg.菲利浦Lcd株式会社 有机发光二极管显示器及其驱动方法
JP2009069644A (ja) * 2007-09-14 2009-04-02 Toshiba Matsushita Display Technology Co Ltd アクティブマトリクス型表示装置およびその駆動方法
CN107342043A (zh) * 2017-08-15 2017-11-10 上海天马微电子有限公司 像素驱动电路及其控制方法、显示面板和显示装置
CN108470544A (zh) * 2017-02-23 2018-08-31 昆山国显光电有限公司 一种像素驱动电路及其驱动方法、阵列基板和显示装置
CN109448636A (zh) * 2018-12-29 2019-03-08 昆山国显光电有限公司 一种像素驱动电路、显示装置及像素驱动电路的驱动方法
CN112562589A (zh) * 2020-12-25 2021-03-26 厦门天马微电子有限公司 一种像素驱动电路、显示面板和像素驱动电路的驱动方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060093954A (ko) * 2005-02-23 2006-08-28 삼성에스디아이 주식회사 유기전계발광장치의 화소 회로
CN101174381A (zh) * 2006-10-31 2008-05-07 Lg.菲利浦Lcd株式会社 有机发光二极管显示器及其驱动方法
JP2009069644A (ja) * 2007-09-14 2009-04-02 Toshiba Matsushita Display Technology Co Ltd アクティブマトリクス型表示装置およびその駆動方法
CN108470544A (zh) * 2017-02-23 2018-08-31 昆山国显光电有限公司 一种像素驱动电路及其驱动方法、阵列基板和显示装置
CN107342043A (zh) * 2017-08-15 2017-11-10 上海天马微电子有限公司 像素驱动电路及其控制方法、显示面板和显示装置
CN109448636A (zh) * 2018-12-29 2019-03-08 昆山国显光电有限公司 一种像素驱动电路、显示装置及像素驱动电路的驱动方法
CN112562589A (zh) * 2020-12-25 2021-03-26 厦门天马微电子有限公司 一种像素驱动电路、显示面板和像素驱动电路的驱动方法

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