WO2023201616A1 - 像素电路、像素驱动方法和显示装置 - Google Patents

像素电路、像素驱动方法和显示装置 Download PDF

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Publication number
WO2023201616A1
WO2023201616A1 PCT/CN2022/088124 CN2022088124W WO2023201616A1 WO 2023201616 A1 WO2023201616 A1 WO 2023201616A1 CN 2022088124 W CN2022088124 W CN 2022088124W WO 2023201616 A1 WO2023201616 A1 WO 2023201616A1
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Prior art keywords
circuit
control
electrically connected
transistor
light
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PCT/CN2022/088124
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English (en)
French (fr)
Inventor
黄耀
胡明
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280000831.1A priority Critical patent/CN117546227A/zh
Priority to PCT/CN2022/088124 priority patent/WO2023201616A1/zh
Publication of WO2023201616A1 publication Critical patent/WO2023201616A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a pixel circuit, a pixel driving method and a display device.
  • AMOLED Active Matrix Organic Light-Emitting Diode
  • an embodiment of the present disclosure provides a pixel circuit, including a light-emitting element, a driving circuit, a first light-emitting control circuit, a first initialization circuit, an energy storage circuit, a compensation control circuit and a data writing circuit;
  • the first light-emitting control circuit is electrically connected to the light-emitting control line, the first end of the driving circuit and the light-emitting element respectively, and is used to control the driving under the control of the light-emitting control signal provided by the light-emitting control line.
  • the first end of the circuit is connected to the light-emitting element;
  • the first initialization circuit is electrically connected to the reset control line, the first initial voltage terminal and the control terminal of the drive circuit respectively, and is used to control the first initialization circuit under the control of the reset control signal provided by the reset control line.
  • the first initial voltage provided by the initial voltage terminal is written into the control terminal of the driving circuit;
  • the first end of the energy storage circuit is electrically connected to the control end of the drive circuit, the second end of the energy storage circuit is electrically connected to the first pole of the light emitting element, and the energy storage circuit is used to store electrical energy. ;
  • the data writing circuit is electrically connected to the writing control line, the data line and the first end of the driving circuit respectively, and is used to write the data under the control of the writing control signal provided by the writing control line.
  • the data voltage provided by the line is written into the first terminal of the driving circuit;
  • the compensation control circuit is electrically connected to the compensation control line, the control end of the drive circuit and the second end of the drive circuit respectively, and is used to control the compensation control signal under the control of the compensation control signal provided by the compensation control line.
  • the control terminal of the driving circuit is connected to the second terminal of the driving circuit.
  • the pixel circuit according to at least one embodiment of the present disclosure further includes a second light emission control circuit
  • the second lighting control circuit is electrically connected to the lighting control line, the first voltage terminal and the second terminal of the driving circuit respectively, and is used to control the first voltage terminal under the control of the lighting control signal. Communicated with the second end of the driving circuit;
  • the first light emitting control circuit is electrically connected to the first pole of the light emitting element, and the second pole of the light emitting element is electrically connected to the second voltage terminal.
  • the pixel circuit according to at least one embodiment of the present disclosure further includes a second initialization circuit
  • the second initialization circuit is respectively connected to the initial control line, the second initial voltage terminal and the first pole of the light-emitting element, and is used to set the The second initial voltage provided by the second initial voltage terminal is written into the first pole of the light-emitting element.
  • the data writing circuit includes a first transistor
  • the compensation control circuit includes a second transistor
  • the energy storage circuit includes a storage capacitor
  • the driving circuit includes a driving transistor
  • the control electrode of the first transistor is electrically connected to the write control line, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the drive circuit.
  • the first end is electrically connected;
  • the control electrode of the second transistor is electrically connected to the compensation control line, the first electrode of the second transistor is electrically connected to the control end of the drive circuit, and the second electrode of the second transistor is electrically connected to the drive circuit.
  • the second end of the circuit is electrically connected;
  • the first end of the storage capacitor is electrically connected to the control end of the driving circuit, and the second end of the storage capacitor is electrically connected to the first pole of the light-emitting element;
  • the control pole of the drive transistor is the control end of the drive circuit
  • the first pole of the drive transistor is the first end of the drive circuit
  • the second pole of the drive transistor is the second end of the drive circuit.
  • the second light emission control circuit includes a third transistor, and the first light emission control circuit includes a fourth transistor;
  • the control electrode of the third transistor is electrically connected to the light-emitting control line, the first electrode of the third transistor is electrically connected to the first voltage terminal, and the second electrode of the third transistor is electrically connected to the driving circuit. The second end is electrically connected;
  • the control electrode of the fourth transistor is electrically connected to the light-emitting control line
  • the first electrode of the fourth transistor is electrically connected to the first terminal of the driving circuit
  • the second electrode of the fourth transistor is electrically connected to the The first electrode of the light-emitting element is electrically connected.
  • the first initialization circuit includes a fifth transistor
  • the control electrode of the fifth transistor is electrically connected to the reset control line, the first electrode of the fifth transistor is electrically connected to the first initial voltage terminal, and the second electrode of the fifth transistor is electrically connected to the drive The control terminal of the circuit is electrically connected.
  • the second initialization circuit includes a sixth transistor
  • the control electrode of the sixth transistor is electrically connected to the initial control line
  • the first electrode of the sixth transistor is electrically connected to the second initial voltage terminal
  • the second electrode of the sixth transistor is electrically connected to the light emitting terminal.
  • the first pole of the component is electrically connected.
  • the pixel circuit according to at least one embodiment of the present disclosure further includes a third initialization circuit
  • the third initialization circuit is electrically connected to the reset control line and the third initial voltage terminal respectively, and the third initialization circuit is electrically connected to the first end of the drive circuit or the second end of the drive circuit, so The third initialization circuit is used to write the third initial voltage provided by the third initial voltage terminal into the first terminal of the driving circuit or the driving circuit under the control of the reset control signal provided by the reset control line. the second end of the circuit.
  • the third initialization circuit includes a seventh transistor
  • the control electrode of the seventh transistor is electrically connected to the reset control line, the first electrode of the seventh transistor is electrically connected to the third initial voltage terminal, and the second electrode of the seventh transistor is electrically connected to the drive The first end of the circuit or the second end of the drive circuit is electrically connected.
  • the transistors included in the second initialization circuit and the transistors included in the third initialization circuit are both oxide thin film transistors.
  • an embodiment of the present disclosure provides a pixel driving method, which is applied to the above-mentioned pixel circuit.
  • the display frame includes a first initialization stage and a compensation stage that are set successively; the pixel driving method includes:
  • the first initialization circuit writes the first initial voltage provided by the first initial voltage terminal into the control terminal of the driving circuit under the control of the reset control signal;
  • the data line provides data voltage
  • the data writing circuit writes the data voltage to the first end of the driving circuit under the control of the writing control signal
  • the compensation control circuit controls the connection between the control end of the drive circuit and the second end of the drive circuit under the control of the compensation control signal
  • the driving circuit controls the connection between the first end of the driving circuit and the second end of the driving circuit under the control of the potential of its control end, and the data voltage is the charging the energy storage circuit to change the potential of the control terminal of the driving circuit until the first terminal of the driving circuit is disconnected from the second terminal of the driving circuit;
  • the data writing time period and the compensation phase are the same time period, or the data writing time period is included in the compensation phase.
  • the pixel circuit includes a second light emission control circuit; the display period also includes a first light emission stage set after the compensation stage; and the pixel driving method further includes:
  • the first light-emitting control circuit controls the connection between the first end of the driving circuit and the light-emitting element under the control of the light-emitting control signal
  • the second light-emitting control circuit controls the connection between the first end of the driving circuit and the light-emitting element under the control of the light-emitting control signal.
  • the first voltage terminal is controlled to be connected to the second terminal of the driving circuit, and the driving circuit drives the light-emitting element to emit light.
  • the pixel circuit further includes a second initialization circuit; the pixel driving method further includes:
  • the second initialization circuit writes the second initial voltage provided by the second initial voltage terminal into the first pole of the light-emitting element under the control of the initial control signal to control whether the light-emitting element does not Emitting light, resetting the potential of the first pole of the light-emitting element, and clearing the residual charge on the first pole of the light-emitting element.
  • the pixel circuit also includes a third initialization circuit; the pixel driving method further includes:
  • the third initialization circuit writes the third initial voltage provided by the third initial voltage terminal into the second terminal of the driving circuit under the control of the reset control signal.
  • the display frame is a refresh frame
  • the display cycle also includes a holding frame
  • the holding frame includes a second initialization phase and a second lighting phase that are set successively
  • the pixel driving method also includes:
  • the second initialization circuit under the control of the reset control signal, writes the second initial voltage provided by the second initial voltage terminal into the first pole of the light-emitting element to control the light-emitting element not to emit light, Reset the potential of the first electrode of the light-emitting element and clear the residual charge on the first electrode of the light-emitting element;
  • the first light-emitting control circuit controls the connection between the first end of the driving circuit and the light-emitting element under the control of the light-emitting control signal
  • the second light-emitting control circuit controls the communication between the light-emitting element Under the control of the control signal
  • the first voltage terminal is controlled to be connected to the second terminal of the driving circuit
  • the driving circuit drives the light-emitting element to emit light
  • an embodiment of the present disclosure provides a display device including the above-mentioned pixel circuit.
  • Figure 1 is a structural diagram of a pixel circuit according to an embodiment of the present disclosure
  • Figure 2 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure
  • Figure 3 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 4 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 5 is an operating timing diagram of at least one embodiment of the pixel circuit shown in Figure 4 of the present disclosure
  • Figure 6 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 7 is a first operating timing diagram of at least one embodiment of the pixel circuit shown in Figure 6 of the present disclosure.
  • Figure 8 is a second operating timing diagram of at least one embodiment of the pixel circuit shown in Figure 6 of the present disclosure.
  • Figure 9 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 10 is a first operating timing diagram of at least one embodiment of the pixel circuit shown in Figure 9 of the present disclosure.
  • Figure 11 is a second operating timing diagram of at least one embodiment of the pixel circuit shown in Figure 9 of the present disclosure.
  • Figure 12 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG. 13 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • the transistors used in all embodiments of the present disclosure may be transistors, thin film transistors, field effect transistors, or other devices with the same characteristics.
  • one pole is called the first electrode and the other pole is called the second electrode.
  • the first electrode when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, The second electrode may be a drain electrode.
  • the pixel circuit includes a light-emitting element 10, a driving circuit 11, a first light-emitting control circuit 12, a first initialization circuit 13, an energy storage circuit 14, a compensation control circuit 15 and a data writing circuit. circuit 16;
  • the first light-emitting control circuit 12 is electrically connected to the light-emitting control line E1 and the first end of the driving circuit 11 and the light-emitting element 10 respectively, for controlling the light-emitting control signal provided by the light-emitting control line E1 , controlling the communication between the first end of the driving circuit 11 and the light-emitting element 10;
  • the first initialization circuit 13 is electrically connected to the reset control line R1, the first initial voltage terminal I1 and the control terminal of the drive circuit 11 respectively, and is used for controlling the reset control signal provided by the reset control line R1, Write the first initial voltage Vint1 provided by the first initial voltage terminal I1 into the control terminal of the driving circuit 11;
  • the first end of the energy storage circuit 14 is electrically connected to the control end of the driving circuit 11, and the second end of the energy storage circuit 14 is electrically connected to the first pole of the light emitting element 10.
  • the energy storage circuit 14 Used to store electrical energy
  • the data writing circuit 16 is electrically connected to the writing control line X1, the data line D1 and the first end of the driving circuit 11, respectively, for controlling the writing control signal provided by the writing control line X1. , writing the data voltage Vdata provided by the data line D1 to the first end of the driving circuit 11;
  • the compensation control circuit 15 is electrically connected to the compensation control line B1, the control end of the drive circuit 11 and the second end of the drive circuit 11 respectively, and is used to control the compensation control signal provided on the compensation control line B1. Next, the control terminal of the driving circuit 11 is controlled to be connected to the second terminal of the driving circuit 11 .
  • the compensation control line B1 and the write control line X1 may be connected to the same control signal, and the compensation control line B1 and The write control line X1 may be the same control line; or, the compensation control line B1 and the write control line X2 may be connected to different control signals, and the compensation control line B1 and the write control line Line X1 can be a different control line;
  • the compensation control line B1 and the write control line X1 are connected to different control signals.
  • the compensation control line B1 and the write control line X1 may be different control line.
  • the pixel circuit operating in a high-frequency driving mode means that the refresh frequency of the pixel circuit is relatively high.
  • the refresh frequency may be greater than a predetermined frequency, and the predetermined frequency may be, for example, It can be greater than or equal to 30Hz and less than or equal to 50Hz, but is not limited to this;
  • the fact that the pixel circuit operates in a low-frequency driving mode means that the refresh frequency of the pixel circuit is relatively low.
  • the refresh frequency may be less than a predetermined frequency.
  • the structure of the pixel circuit described in the embodiment of the present disclosure is different from the structure of the related pixel circuit, and can complete threshold voltage compensation, and is suitable for low-frequency driving.
  • the display frame may include a first initialization stage and a compensation stage set successively;
  • the first initialization circuit 13 writes the first initial voltage Vint1 provided by the first initial voltage terminal I1 into the control terminal of the driving circuit 11 under the control of the reset control signal;
  • the data line D1 provides the data voltage Vdata
  • the data writing circuit 16 writes the data voltage Vdata into the first end of the driving circuit 11 under the control of the writing control signal
  • the compensation control circuit 15 controls the connection between the control end of the drive circuit 11 and the second end of the drive circuit 11 under the control of the compensation control signal;
  • the driving circuit 11 controls the connection between the first end of the driving circuit 11 and the second end of the driving circuit 11 under the control of the potential of its control end, and passes the data voltage
  • the energy storage circuit 14 is charged to change the potential of the control terminal of the driving circuit 11 until the first terminal of the driving circuit 11 and the second terminal of the driving circuit 11 are disconnected, so that the threshold voltage can be determined. compensate;
  • the data writing time period and the compensation phase are the same time period, or the data writing time period is included in the compensation phase.
  • the display frame when the pixel circuit operates in a low-frequency driving mode, the display frame may be a refresh frame included in the display cycle; when the pixel circuit operates in a high-frequency driving mode, the display frame may is the display period.
  • the pixel circuit described in at least one embodiment of the present disclosure may further include a second light emission control circuit 21;
  • the second lighting control circuit 21 is electrically connected to the lighting control line E1, the first voltage terminal V1 and the second end of the driving circuit 11, respectively, and is used to control the lighting control signal under the control of the lighting control signal.
  • the first voltage terminal V1 is connected to the second terminal of the driving circuit 11;
  • the first light-emitting control circuit 12 is electrically connected to the first electrode of the light-emitting element 10
  • the second electrode of the light-emitting element 10 is electrically connected to the second voltage terminal V2 .
  • the first voltage terminal V1 may be a high voltage terminal VDD
  • the second voltage terminal V2 may be a low voltage terminal VSS, but is not limited thereto.
  • the display period may further include a first light-emitting phase arranged after the compensation phase;
  • the first light-emitting control circuit 12 controls the connection between the first end of the driving circuit 11 and the light-emitting element 10 under the control of the light-emitting control signal. Under the control of the control signal, the first voltage terminal V1 is controlled to be connected to the second terminal of the driving circuit 11, and the driving circuit 11 drives the light-emitting element 10 to emit light.
  • the pixel circuit described in at least one embodiment of the present disclosure also includes a second initialization circuit 31;
  • the second initialization circuit 31 is respectively connected with the initial control line R2, the second initial voltage terminal I2 and the first pole of the light emitting element 10, and is used for controlling the initial control signal provided by the initial control line R2. , write the second initial voltage Vint2 provided by the second initial voltage terminal I2 into the first pole of the light-emitting element 10 to control the light-emitting element 10 not to emit light.
  • the potential of the light-emitting element 10 is reset and the residual charge on the first electrode of the light-emitting element 10 is cleared.
  • the second initialization circuit 31 under the control of the initial control signal, supplies the second initial voltage terminal I2 to Two initial voltages Vint2 are written into the first pole of the light-emitting element 10 to control the light-emitting element 10 not to emit light and to clear the residual charge on the first pole of the light-emitting element 10 .
  • the initial control line R2 may be connected to the same control signal as the compensation control line B1.
  • the initial control line R2 It can be the same control line as the compensation control line B1; but it is not limited to this;
  • the initial control line R2 and the compensation control line B1 may be connected to different control signals.
  • the initial control line R2 and the compensation control line B1 The compensation control line B1 may be a different control line.
  • the display frame when the pixel circuit operates in a low-frequency driving mode, the display frame may be a refresh frame, and the display period may also include a holding frame; the holding frame may include a second initialization stage set successively and the second luminous stage;
  • the second initialization circuit 31 writes the second initial voltage Vint2 provided by the second initial voltage terminal I2 into the first pole of the light-emitting element 10 to control the light emission.
  • the element 10 does not emit light, and the residual charge on the first pole of the light-emitting element 10 is cleared;
  • the first light-emitting control circuit 12 controls the connection between the first end of the driving circuit 11 and the light-emitting element 10 under the control of the light-emitting control signal.
  • the second light-emitting control circuit 21 Under the control of the light-emitting control signal, the first voltage terminal V1 is controlled to be connected to the second terminal of the driving circuit 11, and the driving circuit 11 drives the light-emitting element to emit light.
  • the data writing circuit includes a first transistor
  • the compensation control circuit includes a second transistor
  • the energy storage circuit includes a storage capacitor
  • the driving circuit includes a driving transistor
  • the control electrode of the first transistor is electrically connected to the write control line, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the drive circuit.
  • the first end is electrically connected;
  • the control electrode of the second transistor is electrically connected to the compensation control line, the first electrode of the second transistor is electrically connected to the control end of the drive circuit, and the second electrode of the second transistor is electrically connected to the drive circuit.
  • the second end of the circuit is electrically connected;
  • the first end of the storage capacitor is electrically connected to the control end of the driving circuit, and the second end of the storage capacitor is electrically connected to the first pole of the light-emitting element;
  • the control pole of the drive transistor is the control end of the drive circuit
  • the first pole of the drive transistor is the first end of the drive circuit
  • the second pole of the drive transistor is the second end of the drive circuit.
  • the second light emission control circuit includes a third transistor, and the first light emission control circuit includes a fourth transistor;
  • the control electrode of the third transistor is electrically connected to the light-emitting control line, the first electrode of the third transistor is electrically connected to the first voltage terminal, and the second electrode of the third transistor is electrically connected to the driving circuit. The second end is electrically connected;
  • the control electrode of the fourth transistor is electrically connected to the light-emitting control line
  • the first electrode of the fourth transistor is electrically connected to the first terminal of the driving circuit
  • the second electrode of the fourth transistor is electrically connected to the The first electrode of the light-emitting element is electrically connected.
  • the first initialization circuit includes a fifth transistor
  • the control electrode of the fifth transistor is electrically connected to the reset control line, the first electrode of the fifth transistor is electrically connected to the first initial voltage terminal, and the second electrode of the fifth transistor is electrically connected to the drive The control terminal of the circuit is electrically connected.
  • the second initialization circuit includes a sixth transistor
  • the control electrode of the sixth transistor is electrically connected to the initial control line
  • the first electrode of the sixth transistor is electrically connected to the second initial voltage terminal
  • the second electrode of the sixth transistor is electrically connected to the light emitting terminal.
  • the first pole of the component is electrically connected.
  • the data writing circuit 16 includes a first transistor T1, and the compensation control circuit 15 includes a second transistor T2;
  • the energy storage circuit 14 includes a storage capacitor C1;
  • the driving circuit 11 includes a driving transistor T0;
  • the light-emitting element is an organic light-emitting diode O1;
  • the gate of the first transistor T1 is electrically connected to the first scan control line G1, the drain of the first transistor T1 is electrically connected to the data line D1, and the source of the first transistor T1 is electrically connected to the driving line G1.
  • the source of transistor T0 is electrically connected;
  • the gate of the second transistor T2 is electrically connected to the first scan control line G1
  • the drain of the second transistor T2 is electrically connected to the gate of the driving transistor T0
  • the source of the second transistor T2 The pole is electrically connected to the drain of the driving transistor T0;
  • the first end of the storage capacitor C1 is electrically connected to the gate of the driving transistor T0, and the second end of the storage capacitor C1 is electrically connected to the anode of the organic light-emitting diode O1;
  • the second light emission control circuit 21 includes a third transistor T3, and the first light emission control circuit 12 includes a fourth transistor T4;
  • the gate of the third transistor T3 is electrically connected to the light-emitting control line E1
  • the drain of the third transistor T3 is electrically connected to the high voltage terminal VDD
  • the source of the third transistor T3 is electrically connected to the driving transistor.
  • the drain of T0 is electrically connected;
  • the gate of the fourth transistor T4 is electrically connected to the light-emitting control line E1
  • the drain of the fourth transistor T4 is electrically connected to the source of the driving transistor T0
  • the source of the fourth transistor T4 is electrically connected to the light-emitting control line E1.
  • the anode of the organic light-emitting diode O1 is electrically connected;
  • the first initialization circuit 13 includes a fifth transistor T5;
  • the gate of the fifth transistor T5 is electrically connected to the reset control line R1
  • the drain of the fifth transistor T5 is electrically connected to the first initial voltage terminal I1
  • the source of the fifth transistor T5 is electrically connected to the reset control line R1.
  • the gate of the driving transistor T0 is electrically connected;
  • the second initialization circuit 32 includes a sixth transistor T6;
  • the gate of the sixth transistor T6 is electrically connected to the first scan control line G1, the drain of the sixth transistor T6 is electrically connected to the second initial voltage terminal I2, and the source of the sixth transistor T6
  • the electrode is electrically connected to the anode of the organic light-emitting diode O1;
  • the cathode of the organic light emitting diode O1 is electrically connected to the low voltage terminal VSS.
  • At least one embodiment of the pixel circuit shown in FIG. 4 of the present disclosure is a brand new 7T1C pixel circuit, which can effectively support the characteristics of all-oxide devices.
  • T1, T2, T3, T4, T5, T6 and T0 are all oxide transistors
  • T1, T2, T3, T4, T5, T6 and T0 All are NMOS transistors (N-type metal-oxide-semiconductor transistors), but are not limited to this.
  • the compensation control line, the write control line and the initial control line are the same control lines, which are all the first scan control lines G1.
  • the present disclosure is shown in FIG. 4 At least one embodiment of the illustrated pixel circuit is capable of operating in a high frequency drive mode.
  • the node labeled N1 is the first node, and the first node N1 is electrically connected to the gate of T0; the node labeled N2 is the second node, and the second node N2 is electrically connected to the drain of T0; the node labeled N3 is the third node, and the third node N3 is electrically connected to the source of T0; the one labeled N4 is the fourth node, and the fourth node N4 is electrically connected to the anode of O1.
  • the display frame may include a first initialization phase S11 , a compensation phase S12 and a first light emission that are set successively.
  • E1 provides a low voltage signal
  • R1 provides a high voltage signal
  • G1 provides a low voltage signal
  • T5 is turned on
  • I1 provides the first initial voltage Vint1
  • the first initial voltage Vint1 is written into the first node N1 , so that T0 can be turned on at the beginning of the compensation phase S12;
  • E1 provides a low voltage signal
  • R1 provides a low voltage signal
  • G1 provides a high voltage signal
  • T1, T2 and T6 are all turned on
  • T5 is turned off
  • the data line D1 provides the data voltage Vdata
  • I2 provides the second initial Voltage terminal Vint2, write the data voltage Vdata into the third node N3, and control the connection between the first node N1 and the second node N2; write Vint2 into the fourth node N4, so that O1 does not emit light, and clear The charge remaining on the anode of O1;
  • T0 is turned on, charging C1 through the data voltage Vdata, and changing the potential of the first node N1 until T0 is turned off.
  • the potential of the third node N3 is Vdata
  • the potential of the first node N1 are both Vdata+Vth
  • the potential of the fourth node N4 is VINT2
  • Vth is the threshold voltage of T0;
  • E1 provides a high-voltage signal
  • R1 and G1 provide low-voltage signals
  • T3 and T4 are turned on, and T0 drives O1 to emit light
  • the potential of the fourth node N4 is Vo+Vs; the potential of the first node N1 becomes Vdata+Vth+Vo+Vs-Vini2, and Vgs is equal to Vdata+Vth-Vint2; where, Vo is the lighting voltage of O1, Vs is the voltage value of the low-voltage signal provided by the low-voltage terminal VSS;
  • the driving current Io used by T0 to drive O1 to emit light is equal to 0.5K(Vdata-Vint2) 2 ; where K is the current coefficient of T0; from the formula of Io, it can be seen that Io has nothing to do with the threshold voltage Vth of T0 , capable of threshold voltage compensation.
  • VN1 is the potential of the first node N1
  • VN2 is the potential of the second node N2
  • VN3 is the potential of the third node N3
  • VN4 is the potential of the fourth node N4.
  • Vint1 may be greater than or equal to 0V and less than or equal to 10V.
  • Vint1 may be 0V, 2V, 4V, 5V, 6V, 8V or 10V;
  • Vint2 can be greater than or equal to -10V and less than or equal to 0V.
  • Vint2 can be -10V, -8V, -7V, -6V, -4V, -2V or 0V;
  • Vint2 may be the same as the voltage value of the low voltage signal provided by the low voltage terminal VSS, but is not limited to this.
  • the data writing circuit 16 includes a first transistor T1, and the compensation control circuit 15 includes a second transistor T2;
  • the energy storage circuit 14 includes a storage capacitor C1;
  • the driving circuit 11 includes a driving transistor T0;
  • the light-emitting element is an organic light-emitting diode O1;
  • the gate of the first transistor T1 is electrically connected to the second scan control line G2, the drain of the first transistor T1 is electrically connected to the data line D1, and the source of the first transistor T1 is electrically connected to the driving line G2.
  • the source of transistor T0 is electrically connected;
  • the gate of the second transistor T2 is electrically connected to the first scan control line G1
  • the drain of the second transistor T2 is electrically connected to the gate of the driving transistor T0
  • the source of the second transistor T2 The pole is electrically connected to the drain of the driving transistor T0;
  • the first end of the storage capacitor C1 is electrically connected to the gate of the driving transistor T0, and the second end of the storage capacitor C1 is electrically connected to the anode of the organic light-emitting diode O1;
  • the second light emission control circuit 21 includes a third transistor T3, and the first light emission control circuit 12 includes a fourth transistor T4;
  • the gate of the third transistor T3 is electrically connected to the light-emitting control line E1
  • the drain of the third transistor T3 is electrically connected to the high voltage terminal VDD
  • the source of the third transistor T3 is electrically connected to the driving transistor.
  • the drain of T0 is electrically connected;
  • the gate of the fourth transistor T4 is electrically connected to the light-emitting control line E1
  • the drain of the fourth transistor T4 is electrically connected to the source of the driving transistor T0
  • the source of the fourth transistor T4 is electrically connected to the light-emitting control line E1.
  • the anode of the organic light-emitting diode O1 is electrically connected;
  • the first initialization circuit 13 includes a fifth transistor T5;
  • the gate of the fifth transistor T5 is electrically connected to the reset control line R1
  • the drain of the fifth transistor T5 is electrically connected to the first initial voltage terminal I1
  • the source of the fifth transistor T5 is electrically connected to the reset control line R1.
  • the gate of the driving transistor T0 is electrically connected;
  • the second initialization circuit 32 includes a sixth transistor T6;
  • the gate of the sixth transistor T6 is electrically connected to the first scan control line G1, the drain of the sixth transistor T6 is electrically connected to the second initial voltage terminal I2, and the source of the sixth transistor T6
  • the electrode is electrically connected to the anode of the organic light-emitting diode O1;
  • the cathode of the organic light emitting diode O1 is electrically connected to the low voltage terminal VSS.
  • At least one embodiment of the pixel circuit shown in FIG. 6 of the present disclosure is a brand new 7T1C pixel circuit, which can effectively support the characteristics of all-oxide devices.
  • T1, T2, T3, T4, T5, T6 and T0 are all oxide transistors
  • T1, T2, T3, T4, T5, T6 and T0 All are NMOS transistors (N-type metal-oxide-semiconductor transistors), but are not limited to this.
  • the compensation control line and the initial control line are the same control line, both are the first scan control line G1, and the write control line is the second scan control line.
  • G2 at least one embodiment of the pixel circuit shown in FIG. 6 of the present disclosure can operate in a high-frequency driving mode and a low-frequency driving mode.
  • the node labeled N1 is the first node, and the first node N1 is electrically connected to the gate of T0; the node labeled N2 is the second node, and the second node N2 is electrically connected to the drain of T0; the node labeled N3 is is the third node, and the third node N3 is electrically connected to the source of T0; the one labeled N4 is the fourth node, and the fourth node N4 is electrically connected to the anode of O1.
  • the fifth transistor T5 operates under the control of the reset control signal provided by the reset control line R1 to be able to freely adjust the first initial voltage terminal I1 The time during which the first initial voltage Vint1 provided resets the potential of the gate of the driving transistor T0; the sixth transistor T6 operates under the control of the first scan control signal provided by the first scan control line G1 and can operate at low frequency.
  • the first transistor T1 works under the control of the second scan control signal provided by the second scan control line G2 to write the data voltage
  • the first transistor T1 and the first transistor T1 The six transistors T6 work under the control of different control signals to be able to control when working in the low-frequency driving mode.
  • the control T1 is continuously turned off, and in the second initial stage included in the hold frame, the control T6 is turned on.
  • the display frame may include a first initialization phase S11 , a compensation phase S12 and a first light emission that are set successively.
  • E1 provides a low voltage signal
  • R1 provides a high voltage signal
  • G1 provides a low voltage signal
  • G2 provides a low voltage signal
  • T5 is turned on
  • I1 provides the first initial voltage Vint1
  • the first initial voltage Vint1 Write the first node N1 so that T0 can be turned on at the beginning of the data writing period S0;
  • E1 provides a low voltage signal
  • R1 provides a low voltage signal
  • G1 provides a high voltage signal
  • T2 and T6 are turned on
  • T5 is turned off
  • I2 provides the second initial voltage terminal Vint2
  • the first node N1 and the second The nodes N2 are connected
  • Vint2 is written to the fourth node N4, so that O1 does not emit light and the charge remaining on the anode of O1 is cleared;
  • G2 provides a high voltage signal
  • R1 and E1 both provide low voltage signals
  • the data line D1 provides the data voltage Vdata to write the data voltage Vdata to the third node N3;
  • T0 is turned on to charge C1 with the data voltage Vdata, thereby changing the potential of the first node N1 until T0 is turned off.
  • the potential of the third node N3 is Vdata
  • the potential of the first node N1 and the potential of the second node N2 are both Vdata+Vth
  • the potential of the fourth node N4 is VINT2
  • Vth is the threshold voltage of T0;
  • E1 provides a high-voltage signal
  • R1, G1 and G2 provide low-voltage signals
  • T3 and T4 are turned on, and T0 drives O1 to emit light
  • the potential of the fourth node N4 is Vo+Vs; the potential of the first node N1 becomes Vdata+Vth+Vo+Vs-Vini2, and Vgs is equal to Vdata+Vth-Vint2; where, Vo is the lighting voltage of O1, Vs is the voltage value of the low-voltage signal provided by the low-voltage terminal VSS;
  • the driving current Io used by T0 to drive O1 to emit light is equal to 0.5K(Vdata-Vint2) 2 ; where K is the current coefficient of T0; from the formula of Io, it can be seen that Io has nothing to do with the threshold voltage Vth of T0 , capable of threshold voltage compensation.
  • the display cycle may include a refresh frame F1 and at least one holding frame F2;
  • the refresh frame F1 may include The first initialization phase S11, the compensation phase S12 and the first lighting phase S13 are set successively;
  • the compensation phase S12 includes the data writing period S0;
  • the holding frame F2 includes the second initialization phase S21 and the second lighting phase S22;
  • E1 provides a low voltage signal
  • R1 provides a high voltage signal
  • G1 provides a low voltage signal
  • G2 provides a low voltage signal
  • T5 is turned on
  • I1 provides the first initial voltage Vint1
  • the first initial voltage Vint1 Write the first node N1 so that T0 can be turned on at the beginning of the data writing period S0;
  • E1 provides a low voltage signal
  • R1 provides a low voltage signal
  • G1 provides a high voltage signal
  • T2 and T6 are turned on
  • T5 is turned off
  • I2 provides the second initial voltage terminal Vint2
  • the first node N1 and the second The nodes N2 are connected
  • Vint2 is written to the fourth node N4, so that O1 does not emit light and the charge remaining on the anode of O1 is cleared;
  • G2 provides a high voltage signal
  • R1 and E1 both provide low voltage signals
  • the data line D1 provides the data voltage Vdata to write the data voltage Vdata to the third node N3;
  • T0 is turned on to charge C1 with the data voltage Vdata, thereby changing the potential of the first node N1 until T0 is turned off.
  • the potential of the third node N3 is Vdata
  • the potential of the first node N1 and the potential of the second node N2 are both Vdata+Vth
  • the potential of the fourth node N4 is VINT2
  • Vth is the threshold voltage of T0;
  • E1 provides a high-voltage signal
  • R1, G1 and G2 provide low-voltage signals
  • T3 and T4 are turned on, and T0 drives O1 to emit light
  • the potential of the fourth node N4 is Vo+Vs; the potential of the first node N1 becomes Vdata+Vth+Vo+Vs-Vini2, and Vgs is equal to Vdata+Vth-Vint2; where, Vo is the lighting voltage of O1, Vs is the voltage value of the low-voltage signal provided by the low-voltage terminal VSS;
  • the driving current Io used by T0 to drive O1 to emit light is equal to 0.5K(Vdata-Vint2) 2 ; where K is the current coefficient of T0; from the formula of Io, it can be seen that Io has nothing to do with the threshold voltage Vth of T0 , capable of threshold voltage compensation;
  • E1 provides a low voltage signal
  • R1 and G2 provide a low voltage signal
  • G1 provides a high voltage signal
  • T6 and T2 are turned on
  • I2 provides the second initial voltage Vint2 to write the second initial voltage Vint2
  • the anode of O1 is used to control O1 not to emit light, reset the potential of the anode of O1, and clear the residual charge of the anode of O1; and since T3 and T4 are turned off at this time, turning on T2 will not affect the display;
  • E1 provides a high-voltage signal
  • R1, G1, G2 and G3 all provide low-voltage signals
  • T3 and T4 are turned on, and T0 drives O1 to emit light
  • G2 In the holding frame F2, G2 outputs a low voltage signal, so that T1 is turned off and data voltage writing is stopped, so that the brightness display of the refresh frame can be maintained.
  • T6 is turned on to reset the potential of the anode of O1, so that in each hold frame, before T0 drives O1 to emit light, the potential of the anode of O1 is maintained at the same potential to avoid flickering during low-frequency display.
  • the data writing circuit 16 includes a first transistor T1, and the compensation control circuit 15 includes a second transistor T2;
  • the energy storage circuit 14 includes a storage capacitor C1;
  • the driving circuit 11 includes a driving transistor T0;
  • the light-emitting element is an organic light-emitting diode O1;
  • the gate of the first transistor T1 is electrically connected to the second scan control line G2, the drain of the first transistor T1 is electrically connected to the data line D1, and the source of the first transistor T1 is electrically connected to the driving line G2.
  • the source of transistor T0 is electrically connected;
  • the gate of the second transistor T2 is electrically connected to the first scan control line G1
  • the drain of the second transistor T2 is electrically connected to the gate of the driving transistor T0
  • the source of the second transistor T2 The pole is electrically connected to the drain of the driving transistor T0;
  • the first end of the storage capacitor C1 is electrically connected to the gate of the driving transistor T0, and the second end of the storage capacitor C1 is electrically connected to the anode of the organic light-emitting diode O1;
  • the second light emission control circuit 21 includes a third transistor T3, and the first light emission control circuit 12 includes a fourth transistor T4;
  • the gate of the third transistor T3 is electrically connected to the light-emitting control line E1
  • the drain of the third transistor T3 is electrically connected to the high voltage terminal VDD
  • the source of the third transistor T3 is electrically connected to the driving transistor.
  • the drain of T0 is electrically connected;
  • the gate of the fourth transistor T4 is electrically connected to the light-emitting control line E1
  • the drain of the fourth transistor T4 is electrically connected to the source of the driving transistor T0
  • the source of the fourth transistor T4 is electrically connected to the light-emitting control line E1.
  • the anode of the organic light-emitting diode O1 is electrically connected;
  • the first initialization circuit 13 includes a fifth transistor T5;
  • the gate of the fifth transistor T5 is electrically connected to the reset control line R1
  • the drain of the fifth transistor T5 is electrically connected to the first initial voltage terminal I1
  • the source of the fifth transistor T5 is electrically connected to the reset control line R1.
  • the gate of the driving transistor T0 is electrically connected;
  • the second initialization circuit 32 includes a sixth transistor T6;
  • the gate of the sixth transistor T6 is electrically connected to the third scan control line G3, the drain of the sixth transistor T6 is electrically connected to the second initial voltage terminal I2, and the source of the sixth transistor T6
  • the electrode is electrically connected to the anode of the organic light-emitting diode O1;
  • the cathode of the organic light emitting diode O1 is electrically connected to the low voltage terminal VSS.
  • At least one embodiment of the pixel circuit shown in FIG. 9 of the present disclosure is a brand new 7T1C pixel circuit, which can effectively support the characteristics of all-oxide devices.
  • T1, T2, T3, T4, T5, T6 and T0 are all oxide transistors
  • T1, T2, T3, T4, T5, T6 and T0 All are NMOS transistors (N-type metal-oxide-semiconductor transistors), but are not limited to this.
  • the node labeled N1 is the first node, and the first node N1 is electrically connected to the gate of T0; the node labeled N2 is the second node, and the second node N2 is electrically connected to the drain of T0; the node labeled N3 is the third node, and the third node N3 is electrically connected to the source of T0; the one labeled N4 is the fourth node, and the fourth node N4 is electrically connected to the anode of O1.
  • the compensation control line, the write control line and the initial control line are different control lines
  • the compensation control line is the first scan control line G1
  • the write control line The line is the second scan control line G2
  • the initial control line is the third scan control line G3; at least one embodiment of the pixel circuit shown in FIG. 9 of the present disclosure can operate in a high-frequency driving mode and a low-frequency driving mode.
  • the fifth transistor T5 operates under the control of the reset control signal provided by the reset control line R1 to be able to freely adjust the first initial voltage terminal I1
  • the first initial voltage Vint1 provided resets the potential of the gate of the driving transistor T0
  • the sixth transistor T6 operates under the control of the third scan control signal provided by the third scan control line G3 to be able to Work in low-frequency driving mode to reset the anode of O1
  • the first transistor T1 works under the control of the second scan control signal provided by the second scan control line G2 to write data voltage
  • the sixth transistor T6 operates under the control of different control signals to be able to control when operating in the low-frequency driving mode.
  • the control T1 is continuously turned off, and in the second initial stage included in the hold frame, the sixth transistor T6 is controlled to be turned on.
  • the display frame may include a first initialization phase S11 , a compensation phase S12 and a first light emission set in sequence.
  • E1 provides a low voltage signal
  • R1 provides a high voltage signal
  • G1, G2 and G3 provide low voltage signals
  • T5 is turned on
  • I1 provides the first initial voltage Vint1
  • the first node N1 is such that T0 can be turned on at the beginning of the data writing period S0;
  • E1 provides a low voltage signal
  • R1 provides a low voltage signal
  • G1 provides a high voltage signal
  • G3 provides a high voltage signal
  • T2 and T6 are turned on
  • T5 is turned off
  • I2 provides the second initial voltage terminal Vint2
  • the first node N1 is connected to the second node N2, and Vint2 is written to the fourth node N4 so that O1 does not emit light, the potential of the anode of O1 is reset, and the charge remaining on the anode of O1 is cleared;
  • G2 provides a high voltage signal
  • R1 and E1 both provide low voltage signals
  • the data line D1 provides the data voltage Vdata to write the data voltage Vdata to the third node N3;
  • T0 is turned on to charge C1 with the data voltage Vdata, thereby changing the potential of the first node N1 until T0 is turned off.
  • the potential of the third node N3 is Vdata
  • the potential of the first node N1 and the potential of the second node N2 are both Vdata+Vth
  • the potential of the fourth node N4 is VINT2
  • Vth is the threshold voltage of T0;
  • E1 provides a high-voltage signal
  • R1, G1 and G2 provide low-voltage signals
  • T3 and T4 are turned on, and T0 drives O1 to emit light
  • the potential of the fourth node N4 is Vo+Vs; the potential of the first node N1 becomes Vdata+Vth+Vo+Vs-Vini2, and Vgs is equal to Vdata+Vth-Vint2; where, Vo is the lighting voltage of O1, Vs is the voltage value of the low-voltage signal provided by the low-voltage terminal VSS;
  • the driving current Io used by T0 to drive O1 to emit light is equal to 0.5K(Vdata-Vint2) 2 ; where K is the current coefficient of T0; from the formula of Io, it can be seen that Io has nothing to do with the threshold voltage Vth of T0 , capable of threshold voltage compensation.
  • the display cycle may include a refresh frame F1 and at least one holding frame F2;
  • the refresh frame F1 may include The first initialization phase S11, the compensation phase S12 and the first lighting phase S13 are set successively;
  • the compensation phase S12 includes the data writing period S0;
  • the holding frame F2 includes the second initialization phase S21 and the second lighting phase S22;
  • E1 provides a low voltage signal
  • R1 provides a high voltage signal
  • G1, G2 and G3 provide low voltage signals
  • T5 is turned on
  • I1 provides the first initial voltage Vint1
  • the first node N1 is such that T0 can be turned on at the beginning of the data writing period S0;
  • E1 provides a low voltage signal
  • R1 provides a low voltage signal
  • G1 provides a high voltage signal
  • G3 provides a high voltage signal
  • T2 and T6 are turned on
  • T5 is turned off
  • G1 provides a high voltage signal
  • T2 and T6 are turned on.
  • T5 is turned off
  • I2 provides the second initial voltage terminal Vint2
  • the first node N1 and the second node N2 are connected
  • Vint2 is written to the fourth node N4, so that O1 does not emit light, and the potential of the anode of O1 is adjusted. Reset and clear the charge remaining on the anode of O1;
  • G2 provides a high voltage signal
  • R1 and E1 both provide low voltage signals
  • the data line D1 provides the data voltage Vdata to write the data voltage Vdata to the third node N3;
  • T0 is turned on to charge C1 with the data voltage Vdata, thereby changing the potential of the first node N1 until T0 is turned off.
  • the potential of the third node N3 is Vdata
  • the potential of the first node N1 and the potential of the second node N2 are both Vdata+Vth
  • the potential of the fourth node N4 is VINT2
  • Vth is the threshold voltage of T0;
  • E1 provides a high-voltage signal
  • R1, G1 and G2 provide low-voltage signals
  • T3 and T4 are turned on, and T0 drives O1 to emit light
  • the potential of the fourth node N4 is Vo+Vs; the potential of the first node N1 becomes Vdata+Vth+Vo+Vs-Vini2, and Vgs is equal to Vdata+Vth-Vint2; where, Vo is the lighting voltage of O1, Vs is the voltage value of the low-voltage signal provided by the low-voltage terminal VSS;
  • the driving current Io used by T0 to drive O1 to emit light is equal to 0.5K(Vdata-Vint2)2; where K is the current coefficient of T0; from the formula of Io, it can be seen that Io has nothing to do with the threshold voltage Vth of T0 , capable of threshold voltage compensation;
  • E1 provides a low voltage signal
  • G3 provides a high voltage signal
  • R1, G1 and G2 all provide low voltage signals
  • T6 is turned on
  • I2 provides the second initial voltage Vint2 to write the second initial voltage Vint2 Insert the anode of O1 to control O1 not to emit light, reset the potential of the anode of O1, and clear the residual charge of the anode of O1;
  • E1 provides a high voltage signal
  • R1, G1, G2 and G3 all provide low voltage signals
  • T3 and T4 are turned on
  • T0 drives O1 to emit light.
  • T6 is turned on to reset the potential of the anode of O1, so that in each hold frame, before T0 drives O1 to emit light, the potential of the anode of O1 is maintained at the same potential to avoid flickering during low-frequency display.
  • the pixel circuit according to at least one embodiment of the present disclosure may further include a third initialization circuit
  • the third initialization circuit is electrically connected to the reset control line and the third initial voltage terminal respectively, and the third initialization circuit is electrically connected to the first end of the drive circuit or the second end of the drive circuit, so The third initialization circuit is used to write the third initial voltage provided by the third initial voltage terminal into the first terminal of the driving circuit or the driving circuit under the control of the reset control signal provided by the reset control line. the second end of the circuit.
  • the pixel circuit may further include a third initialization circuit.
  • the third initialization circuit may change the third initial voltage to Writing to the first end of the driving circuit or the second end of the driving circuit increases the bias voltage of the driving transistor included in the driving circuit to improve the hysteresis phenomenon of the driving transistor.
  • the third initial voltage Vint3 when the first initial voltage Vint1 is a positive value, the third initial voltage Vint3 may be a negative value, so that the first initialization circuit controls the first initial voltage Vint1 to be written into the gate of the driving transistor.
  • the gate-source voltage of the driving transistor when the third initialization circuit controls to write the third initial voltage Vint3 into the first pole of the driving transistor or the second pole of the driving transistor, the gate-source voltage of the driving transistor is much greater than the threshold voltage Vth of the driving transistor, and increases The bias voltage of the drive transistor.
  • the third initialization circuit includes a seventh transistor
  • the control electrode of the seventh transistor is electrically connected to the reset control line, the first electrode of the seventh transistor is electrically connected to the third initial voltage terminal, and the second electrode of the seventh transistor is electrically connected to the drive The first end of the circuit or the second end of the drive circuit is electrically connected.
  • the pixel circuit described in at least one embodiment of the present disclosure may further include a third initialization circuit 110;
  • the third initialization circuit 110 is electrically connected to the reset control line R1 and the third initial voltage terminal I3 respectively.
  • the third initialization circuit 110 is electrically connected to the second end of the drive circuit 11.
  • the third initialization circuit 110 is electrically connected to the second terminal of the drive circuit 11.
  • the circuit 110 is used to write the third initial voltage Vint3 provided by the third initial voltage terminal I3 into the second terminal of the driving circuit 11 under the control of the reset control signal provided by the reset control line R1.
  • the third initialization circuit 110 sets the third initial voltage terminal to The third initial voltage Vi3 provided by I3 is written into the second terminal of the driving circuit 11 .
  • the pixel circuit described in at least one embodiment of the present disclosure also includes a third initialization circuit 110;
  • the third initialization circuit 110 includes a seventh transistor T7;
  • the gate of the seventh transistor T7 is electrically connected to the reset control line R1
  • the drain of the seventh transistor T7 is electrically connected to the third initial voltage terminal I3
  • the source of the seventh transistor T7 is electrically connected to the reset control line R1.
  • the second node N2 is electrically connected.
  • all transistors are oxide transistors, and all transistors are NMOS transistors.
  • R1 provides a high voltage signal
  • T7 is turned on
  • the third initial voltage terminal I3 provides the third initial voltage Vint3, so as to
  • the third initial voltage Vint3 is written into the second node N2
  • T5 is turned on
  • the first initial voltage terminal Vint1 provides the first initial voltage Vint1 to write the first initial voltage Vint1 into the gate of T0, thereby increasing the power of the driving transistor T0.
  • Bias voltage to improve the hysteresis of the driving transistor T0.
  • the transistors included in the circuit, the transistors included in the second initialization circuit, and the transistors included in the third initialization circuit may all be oxide thin film transistors.
  • a display device includes the above-mentioned pixel circuit.
  • the display device provided in the embodiment of the present disclosure can be any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.

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Abstract

本公开提供一种像素电路、像素驱动方法和显示装置。像素电路包括发光元件、驱动电路、第一发光控制电路、第一初始化电路、储能电路、补偿控制电路和数据写入电路；储能电路的第一端与驱动电路的控制端电连接，储能电路的第二端与发光元件的第一极电连接；数据写入电路在写入控制信号的控制下，将数据电压写入驱动电路的第一端；补偿控制电路在补偿控制信号的控制下，控制驱动电路的控制端与驱动电路的第二端之间连通。本公开实施例所述的像素电路的结构与相关的像素电路的结构不同，并能够完成阈值电压补偿，并适用于低频驱动。

Description

像素电路、像素驱动方法和显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种像素电路、像素驱动方法和显示装置。
背景技术
随着显示技术领域的不断发展，有源矩阵有机发光二极管(Active Matrix Organic Light-Emitting Diode，简称AMOLED)显示装置凭借其全面屏、窄边框、高分辨率、卷曲穿戴、折叠等特点，得到广泛的应用。在相关技术中，不能提供一种全新的像素电路，以能够适用于低频驱动，并能够进行阈值电压补偿。
发明内容
在一个方面中，本公开实施例提供了一种像素电路，包括发光元件、驱动电路、第一发光控制电路、第一初始化电路、储能电路、补偿控制电路和数据写入电路；
所述第一发光控制电路分别与发光控制线、所述驱动电路的第一端与所述发光元件电连接，用于在所述发光控制线提供的发光控制信号的控制下，控制所述驱动电路的第一端与所述发光元件之间连通；
所述第一初始化电路分别与复位控制线、第一初始电压端和所述驱动电路的控制端电连接，用于在所述复位控制线提供的复位控制信号的控制下，将所述第一初始电压端提供的第一初始电压写入所述驱动电路的控制端；
所述储能电路的第一端与所述驱动电路的控制端电连接，所述储能电路的第二端与所述发光元件的第一极电连接，所述储能电路用于储存电能；
所述数据写入电路分别与写入控制线、数据线和所述驱动电路的第一端电连接，用于在所述写入控制线提供的写入控制信号的控制下，将所述数据线提供的数据电压写入所述驱动电路的第一端；
所述补偿控制电路分别与补偿控制线、所述驱动电路的控制端和所述驱 动电路的第二端电连接，用于在所述补偿控制线提供的补偿控制信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间连通。
可选的，本公开至少一实施例所述的像素电路还包括第二发光控制电路；
所述第二发光控制电路分别与所述发光控制线、第一电压端和所述驱动电路的第二端电连接，用于在所述发光控制信号的控制下，控制所述第一电压端与所述驱动电路的第二端之间连通；
所述第一发光控制电路与所述发光元件的第一极电连接，所述发光元件的第二极与第二电压端电连接。
可选的，本公开至少一实施例所述的像素电路还包括第二初始化电路；
所述第二初始化电路分别与初始控制线、第二初始电压端和所述发光元件的第一极之间连通，用于在所述初始控制线提供的初始控制信号的控制下，将所述第二初始电压端提供的第二初始电压写入所述发光元件的第一极。
可选的，所述数据写入电路包括第一晶体管，所述补偿控制电路包括第二晶体管；所述储能电路包括存储电容；所述驱动电路包括驱动晶体管；
所述第一晶体管的控制极与所述写入控制线电连接，所述第一晶体管的第一极与所述数据线电连接，所述第一晶体管的第二极与所述驱动电路的第一端电连接；
所述第二晶体管的控制极与所述补偿控制线电连接，所述第二晶体管的第一极与所述驱动电路的控制端电连接，所述第二晶体管的第二极与所述驱动电路的第二端电连接；
所述存储电容的第一端与所述驱动电路的控制端电连接，所述存储电容的第二端与所述发光元件的第一极电连接；
所述驱动晶体管的控制极为所述驱动电路的控制端，所述驱动晶体管的第一极为所述驱动电路的第一端，所述驱动晶体管的第二极为所述驱动电路的第二端。
可选的，所述第二发光控制电路包括第三晶体管，所述第一发光控制电路包括第四晶体管；
所述第三晶体管的控制极与所述发光控制线电连接，所述第三晶体管的第一极与所述第一电压端电连接，所述第三晶体管的第二极与所述驱动电路 的第二端电连接；
所述第四晶体管的控制极与所述发光控制线电连接，所述第四晶体管的第一极与所述驱动电路的第一端电连接，所述第四晶体管的第二极与所述发光元件的第一极电连接。
可选的，所述第一初始化电路包括第五晶体管；
所述第五晶体管的控制极与所述复位控制线电连接，所述第五晶体管的第一极与所述第一初始电压端电连接，所述第五晶体管的第二极与所述驱动电路的控制端电连接。
可选的，所述第二初始化电路包括第六晶体管；
所述第六晶体管的控制极与所述初始控制线电连接，所述第六晶体管的第一极与所述第二初始电压端电连接，所述第六晶体管的第二极与所述发光元件的第一极电连接。
可选的，本公开至少一实施例所述的像素电路还包括第三初始化电路；
所述第三初始化电路分别与所述复位控制线和第三初始电压端电连接，所述第三初始化电路与所述驱动电路的第一端或所述驱动电路的第二端电连接，所述第三初始化电路用于在所述复位控制线提供的复位控制信号的控制下，将所述第三初始电压端提供的第三初始电压写入所述驱动电路的第一端或所述驱动电路的第二端。
可选的，所述第三初始化电路包括第七晶体管；
所述第七晶体管的控制极与所述复位控制线电连接，所述第七晶体管的第一极与所述第三初始电压端电连接，所述第七晶体管的第二极与所述驱动电路的第一端或所述驱动电路的第二端电连接。
可选的，所述发光控制电路包括的晶体管、所述数据写入电路包括的晶体管、所述补偿控制电路包括的晶体管、所述驱动电路包括的晶体管、所述第一初始化电路包括的晶体管、所述第二初始化电路包括的晶体管和所述第三初始化电路包括的晶体管都为氧化物薄膜晶体管。
在第二个方面中，本公开实施例提供一种像素驱动方法，应用于上述的像素电路，显示帧包括先后设置的第一初始化阶段和补偿阶段；所述像素驱动方法包括：
在第一初始化阶段，第一初始化电路在复位控制信号的控制下，将第一初始电压端提供的第一初始电压写入驱动电路的控制端；
在数据写入时间段，数据线提供数据电压，数据写入电路在写入控制信号的控制下，将所述数据电压写入驱动电路的第一端；
在补偿阶段，补偿控制电路在补偿控制信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间连通；
在数据写入时间段开始时，驱动电路在其控制端的电位的控制下，控制所述驱动电路的第一端与所述驱动电路的第二端之间连通，通过所述数据电压为所述储能电路充电，以改变所述驱动电路的控制端的电位，直至所述驱动电路的第一端与所述驱动电路的第二端之间断开；
所述数据写入时间段与所述补偿阶段为同一时间段，或者，所述数据写入时间段包含于所述补偿阶段。
可选的，所述像素电路包括第二发光控制电路；所述显示周期还包括设置于所述补偿阶段之后的第一发光阶段，所述像素驱动方法还包括：
在所述第一发光阶段，第一发光控制电路在发光控制信号的控制下，控制所述驱动电路的第一端与发光元件之间连通，第二发光控制电路在所述发光控制信号的控制下，控制第一电压端与所述驱动电路的第二端之间连通，所述驱动电路驱动所述发光元件发光。
可选的，所述像素电路还包括第二初始化电路；所述像素驱动方法还包括：
在所述补偿阶段，所述第二初始化电路在初始控制信号的控制下，将第二初始电压端提供的第二初始电压写入所述发光元件的第一极，以控制所述发光元件不发光，对所述发光元件的第一极的电位进行重置，清除所述发光元件的第一极残留的电荷。
可选的，所述像素电路还包括第三初始化电路；所述像素驱动方法还包括：
在所述第一初始化阶段，所述第三初始化电路在复位控制信号的控制下，将第三初始电压端提供的第三初始电压写入所述驱动电路的第二端。
可选的，所述显示帧为刷新帧，显示周期还包括保持帧；所述保持帧包 括先后设置的第二初始化阶段和第二发光阶段；所述像素驱动方法还包括：
在所述第二初始化阶段，第二初始化电路在复位控制信号的控制下，将第二初始电压端提供的第二初始电压写入发光元件的第一极，以控制所述发光元件不发光，对所述发光元件的第一极的电位进行重置，清除所述发光元件的第一极残留的电荷；
在所述第二发光阶段，所述第一发光控制电路在发光控制信号的控制下，控制所述驱动电路的第一端与发光元件之间连通，所述第二发光控制电路在所述发光控制信号的控制下，控制第一电压端与所述驱动电路的第二端之间连通，所述驱动电路驱动所述发光元件发光。
在第三个方面中，本公开实施例提供一种显示装置，包括上述的像素电路。
附图说明
图1是本公开实施例所述的像素电路的结构图；
图2是本公开至少一实施例所述的像素电路的结构图；
图3是本公开至少一实施例所述的像素电路的结构图；
图4是本公开至少一实施例所述的像素电路的电路图；
图5是本公开图4所示的像素电路的至少一实施例的工作时序图；
图6是本公开至少一实施例所述的像素电路的电路图；
图7是本公开图6所示的像素电路的至少一实施例的第一工作时序图；
图8是本公开图6所示的像素电路的至少一实施例的第二工作时序图；
图9是本公开至少一实施例所述的像素电路的电路图；
图10是本公开图9所示的像素电路的至少一实施例的第一工作时序图；
图11是本公开图9所示的像素电路的至少一实施例的第二工作时序图；
图12是本公开至少一实施例所述的像素电路的结构图；
图13是本公开至少一实施例所述的像素电路的电路图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行 清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为三极管、薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除控制极之外的两极，将其中一极称为第一电极，另一极称为第二电极。
在实际操作时，当所述晶体管为薄膜晶体管或场效应管时，所述第一电极可以为漏极，所述第二电极可以为源极；或者，所述第一电极可以为源极，所述第二电极可以为漏极。
如图1所示，本公开实施例所述的像素电路包括发光元件10、驱动电路11、第一发光控制电路12、第一初始化电路13、储能电路14、补偿控制电路15和数据写入电路16；
所述第一发光控制电路12分别与发光控制线E1、所述驱动电路11的第一端与所述发光元件10电连接，用于在所述发光控制线E1提供的发光控制信号的控制下，控制所述驱动电路11的第一端与所述发光元件10之间连通；
所述第一初始化电路13分别与复位控制线R1、第一初始电压端I1和所述驱动电路11的控制端电连接，用于在所述复位控制线R1提供的复位控制信号的控制下，将所述第一初始电压端I1提供的第一初始电压Vint1写入所述驱动电路11的控制端；
所述储能电路14的第一端与所述驱动电路11的控制端电连接，所述储能电路14的第二端与所述发光元件10的第一极电连接，所述储能电路14用于储存电能；
所述数据写入电路16分别与写入控制线X1、数据线D1和所述驱动电路11的第一端电连接，用于在所述写入控制线X1提供的写入控制信号的控制下，将所述数据线D1提供的数据电压Vdata写入所述驱动电路11的第一端；
所述补偿控制电路15分别与补偿控制线B1、所述驱动电路11的控制端和所述驱动电路11的第二端电连接，用于在所述补偿控制线B1提供的补偿控制信号的控制下，控制所述驱动电路11的控制端与所述驱动电路11的第二端之间连通。
在本公开至少一实施例中，当所述像素电路工作于高频驱动模式时，所述补偿控制线B1和所述写入控制线X1可以接入同一控制信号，所述补偿控制线B1和所述写入控制线X1可以为相同的控制线；或者，所述补偿控制线B1和所述写入控制线X2可以接入不同的控制信号，所述补偿控制线B1和所述写入控制线X1可以为不同的控制线；
当所述像素电路工作于低频驱动模式时，所述补偿控制线B1和所述写入控制线X1接入不同的控制信号，所述补偿控制线B1和所述写入控制线X1可以为不同的控制线。
在本公开至少一实施例中，所述像素电路工作于高频驱动模式指的是：所述像素电路的刷新频率相对较高，例如，所述刷新频率可以大于预定频率，所述预定频率例如可以大于等于30Hz而小于等于50Hz，但不以此为限；
所述像素电路工作于低频驱动模式指的是：所述像素电路的刷新频率相对较低，例如，所述刷新频率可以小于预定频率。
本公开实施例所述的像素电路的结构与相关的像素电路的结构不同，并能够完成阈值电压补偿，并适用于低频驱动。
本公开实施例所述的像素电路在工作时，显示帧可以包括先后设置的第一初始化阶段和补偿阶段；
在第一初始化阶段，第一初始化电路13在复位控制信号的控制下，将第一初始电压端I1提供的第一初始电压Vint1写入驱动电路11的控制端；
在数据写入时间段，数据线D1提供数据电压Vdata，数据写入电路16在写入控制信号的控制下，将所述数据电压Vdata写入驱动电路11的第一端；
在补偿阶段，补偿控制电路15在补偿控制信号的控制下，控制所述驱动电路11的控制端与所述驱动电路11的第二端之间连通；
在数据写入时间段开始时，驱动电路11在其控制端的电位的控制下，控制所述驱动电路11的第一端与所述驱动电路11的第二端之间连通，通过所述数据电压为所述储能电路14充电，以改变所述驱动电路11的控制端的电位，直至所述驱动电路11的第一端与所述驱动电路11的第二端之间断开，以能够进行阈值电压补偿；
所述数据写入时间段与所述补偿阶段为同一时间段，或者，所述数据写 入时间段包含于所述补偿阶段。
在具体实施时，当所述像素电路工作于低频驱动模式下时，所述显示帧可以为显示周期包括的刷新帧；当所述像素电路工作于高频驱动模式下时，所述显示帧可以为显示周期。
如图2所示，在图1所示的像素电路的实施例的基础上，本公开至少一实施例所述的像素电路还可以包括第二发光控制电路21；
所述第二发光控制电路21分别与所述发光控制线E1、第一电压端V1和所述驱动电路11的第二端电连接，用于在所述发光控制信号的控制下，控制所述第一电压端V1与所述驱动电路11的第二端之间连通；
所述第一发光控制电路12与所述发光元件10的第一极电连接，所述发光元件10的第二极与第二电压端V2电连接。
可选的，所述第一电压端V1可以为高电压端VDD，所述第二电压端V2可以为低电压端VSS，但不以此为限。
本公开如图2所示的像素电路的至少一实施例在工作时，所述显示周期还可以包括设置于所述补偿阶段之后的第一发光阶段；
在所述第一发光阶段，第一发光控制电路12在发光控制信号的控制下，控制所述驱动电路11的第一端与发光元件10之间连通，第二发光控制电路21在所述发光控制信号的控制下，控制第一电压端V1与所述驱动电路11的第二端之间连通，所述驱动电路11驱动所述发光元件10发光。
如图3所示，在图2所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还包括第二初始化电路31；
所述第二初始化电路31分别与初始控制线R2、第二初始电压端I2和所述发光元件10的第一极之间连通，用于在所述初始控制线R2提供的初始控制信号的控制下，将所述第二初始电压端I2提供的第二初始电压Vint2写入所述发光元件10的第一极，以控制所述发光元件10不发光，对所述发光元件10的第一极的电位进行重置，并清除所述发光元件10的第一极残留的电荷。
本公开如图3所示的像素电路的至少一实施例在工作时，在所述补偿阶段，所述第二初始化电路31在初始控制信号的控制下，将第二初始电压端I2 提供的第二初始电压Vint2写入所述发光元件10的第一极，以控制所述发光元件10不发光，并清除所述发光元件10的第一极残留的电荷。
在本公开图3所示的像素电路的至少一实施例工作于高频驱动模式时，所述初始控制线R2可以与所述补偿控制线B1接入相同的控制信号，所述初始控制线R2和所述补偿控制线B1可以为相同的控制线；但不以此为限；
在本公开图3所示的像素电路的至少一实施例工作于低频驱动模式时，所述初始控制线R2可以与所述补偿控制线B1接入不同的控制信号，所述初始控制线R2和所述补偿控制线B1可以为不同的控制线。
在本公开至少一实施例中，当所述像素电路工作于低频驱动模式时，所述显示帧可以为刷新帧，显示周期还包括保持帧；所述保持帧可以包括先后设置的第二初始化阶段和第二发光阶段；
在所述第二初始化阶段，第二初始化电路31在复位控制信号的控制下，将第二初始电压端I2提供的第二初始电压Vint2写入发光元件10的第一极，以控制所述发光元件10不发光，并清除所述发光元件10的第一极残留的电荷；
在所述第二发光阶段，所述第一发光控制电路12在发光控制信号的控制下，控制所述驱动电路11的第一端与发光元件10之间连通，所述第二发光控制电路21在所述发光控制信号的控制下，控制第一电压端V1与所述驱动电路11的第二端之间连通，所述驱动电路11驱动所述发光元件发光。
可选的，所述数据写入电路包括第一晶体管，所述补偿控制电路包括第二晶体管；所述储能电路包括存储电容；所述驱动电路包括驱动晶体管；
所述第一晶体管的控制极与所述写入控制线电连接，所述第一晶体管的第一极与所述数据线电连接，所述第一晶体管的第二极与所述驱动电路的第一端电连接；
所述第二晶体管的控制极与所述补偿控制线电连接，所述第二晶体管的第一极与所述驱动电路的控制端电连接，所述第二晶体管的第二极与所述驱动电路的第二端电连接；
所述存储电容的第一端与所述驱动电路的控制端电连接，所述存储电容的第二端与所述发光元件的第一极电连接；
所述驱动晶体管的控制极为所述驱动电路的控制端，所述驱动晶体管的第一极为所述驱动电路的第一端，所述驱动晶体管的第二极为所述驱动电路的第二端。
可选的，所述第二发光控制电路包括第三晶体管，所述第一发光控制电路包括第四晶体管；
所述第三晶体管的控制极与所述发光控制线电连接，所述第三晶体管的第一极与所述第一电压端电连接，所述第三晶体管的第二极与所述驱动电路的第二端电连接；
所述第四晶体管的控制极与所述发光控制线电连接，所述第四晶体管的第一极与所述驱动电路的第一端电连接，所述第四晶体管的第二极与所述发光元件的第一极电连接。
可选的，所述第一初始化电路包括第五晶体管；
所述第五晶体管的控制极与所述复位控制线电连接，所述第五晶体管的第一极与所述第一初始电压端电连接，所述第五晶体管的第二极与所述驱动电路的控制端电连接。
可选的，所述第二初始化电路包括第六晶体管；
所述第六晶体管的控制极与所述初始控制线电连接，所述第六晶体管的第一极与所述第二初始电压端电连接，所述第六晶体管的第二极与所述发光元件的第一极电连接。
如图4所示，在图3所示的像素电路的至少一实施例的基础上，所述数据写入电路16包括第一晶体管T1，所述补偿控制电路15包括第二晶体管T2；所述储能电路14包括存储电容C1；所述驱动电路11包括驱动晶体管T0；所述发光元件为有机发光二极管O1；
所述第一晶体管T1的栅极与第一扫描控制线G1电连接，所述第一晶体管T1的漏极与所述数据线D1电连接，所述第一晶体管T1的源极与所述驱动晶体管T0的源极电连接；
所述第二晶体管T2的栅极与所述第一扫描控制线G1电连接，所述第二晶体管T2的漏极与所述驱动晶体管T0的栅极电连接，所述第二晶体管T2的源极与所述驱动晶体管T0的漏极电连接；
所述存储电容C1的第一端与所述驱动晶体管T0的栅极电连接，所述存储电容C1的第二端与所述有机发光二极管O1的阳极电连接；
所述第二发光控制电路21包括第三晶体管T3，所述第一发光控制电路12包括第四晶体管T4；
所述第三晶体管T3的栅极与所述发光控制线E1电连接，所述第三晶体管T3的漏极与高电压端VDD电连接，所述第三晶体管T3的源极与所述驱动晶体管T0的漏极电连接；
所述第四晶体管T4的栅极与所述发光控制线E1电连接，所述第四晶体管T4的漏极与所述驱动晶体管T0的源极电连接，所述第四晶体管T4的源极与所述有机发光二极管O1的阳极电连接；
所述第一初始化电路13包括第五晶体管T5；
所述第五晶体管T5的栅极与所述复位控制线R1电连接，所述第五晶体管T5的漏极与所述第一初始电压端I1电连接，所述第五晶体管T5的源极与所述驱动晶体管T0的栅极电连接；
所述第二初始化电路32包括第六晶体管T6；
所述第六晶体管T6的栅极与所述第一扫描控制线G1电连接，所述第六晶体管T6的漏极与所述第二初始电压端I2电连接，所述第六晶体管T6的源极与所述有机发光二极管O1的阳极电连接；
所述有机发光二极管O1的阴极与低电压端VSS电连接。
本公开如图4所示的像素电路的至少一实施例为全新的7T1C像素电路，能够有效的支撑全氧化物器件特性。
在本公开如图4所示的像素电路的至少一实施例中，T1、T2、T3、T4、T5、T6和T0都为氧化物晶体管，T1、T2、T3、T4、T5、T6和T0都为NMOS晶体管(N型金属-氧化物-半导体晶体管)，但不以此为限。
在本公开如图4所示的像素电路的至少一实施例中，补偿控制线、写入控制线和初始控制线为相同的控制线，都为第一扫描控制线G1，本公开如图4所示的像素电路的至少一实施例能够在高频驱动模式下工作。
在图4中，标号为N1的为第一节点，第一节点N1与T0的栅极电连接；标号为N2的为第二节点，第二节点N2与T0的漏极电连接；标号为N3的 为第三节点，第三节点N3与T0的源极电连接；标号为N4的为第四节点，第四节点N4与O1的阳极电连接。
如图5所示，本公开如图4所示的像素电路的至少一实施例在高频驱动模式下工作时，显示帧可以包括先后设置的第一初始化阶段S11、补偿阶段S12和第一发光阶段S13；
在所述第一初始化阶段S11，E1提供低电压信号，R1提供高电压信号，G1提供低电压信号，T5打开，I1提供第一初始电压Vint1，将第一初始电压Vint1写入第一节点N1，以使得在补偿阶段S12开始时，T0能够导通；
在所述补偿阶段S12，E1提供低电压信号，R1提供低电压信号，G1提供高电压信号，T1、T2和T6都打开，T5关断，数据线D1提供数据电压Vdata，I2提供第二初始电压端Vint2，将所述数据电压Vdata写入第三节点N3，并控制第一节点N1与第二节点N2之间连通；并将Vint2写入第四节点N4，以使得O1不发光，并清除残留于O1的阳极的电荷；
在所述补偿阶段S12开始时，T0打开，通过数据电压Vdata为C1充电，而改变第一节点N1的电位，直至T0关断，此时，第三节点N3的电位为Vdata，第一节点N1的电位和第二节点N2的电位都为Vdata+Vth；第四节点N4的电位为VINT2；Vth为T0的阈值电压；
在所述第一发光阶段S13，E1提供高电压信号，R1和G1提供低电压信号，T3和T4打开，T0驱动O1发光；
在所述第一发光阶段S13，第四节点N4的电位为Vo+Vs；所述第一节点N1的电位变为Vdata+Vth+Vo+Vs-Vini2，Vgs等于Vdata+Vth-Vint2；其中，Vo为O1的起亮电压，Vs为所述低电压端VSS提供的低电压信号的电压值；
在所述第一发光阶段S13，T0驱动O1发光的驱动电流Io等于0.5K(Vdata-Vint2) 2；其中，K为T0的电流系数；由Io的公式可知，Io与T0的阈值电压Vth无关，能够进行阈值电压补偿。
在图5中，VN1为第一节点N1的电位，VN2为第二节点N2的电位，VN3为第三节点N3的电位，VN4为第四节点N4的电位。
在本公开至少一实施例中，Vint1可以大于等于0V而小于等于10V，例如，Vint1可以为0V、2V、4V、5V、6V、8V或10V；
Vint2可以大于等于-10V而小于等于0V，例如，Vint2可以为-10V、-8V、-7V、-6V、-4V、-2V或0V；
但不以此为限。
可选的，Vint2可以与所述低电压端VSS提供的低电压信号的电压值相同，但并不以此为限。
如图6所示，在图3所示的像素电路的至少一实施例的基础上，所述数据写入电路16包括第一晶体管T1，所述补偿控制电路15包括第二晶体管T2；所述储能电路14包括存储电容C1；所述驱动电路11包括驱动晶体管T0；所述发光元件为有机发光二极管O1；
所述第一晶体管T1的栅极与第二扫描控制线G2电连接，所述第一晶体管T1的漏极与所述数据线D1电连接，所述第一晶体管T1的源极与所述驱动晶体管T0的源极电连接；
所述第二晶体管T2的栅极与所述第一扫描控制线G1电连接，所述第二晶体管T2的漏极与所述驱动晶体管T0的栅极电连接，所述第二晶体管T2的源极与所述驱动晶体管T0的漏极电连接；
所述存储电容C1的第一端与所述驱动晶体管T0的栅极电连接，所述存储电容C1的第二端与所述有机发光二极管O1的阳极电连接；
所述第二发光控制电路21包括第三晶体管T3，所述第一发光控制电路12包括第四晶体管T4；
所述第三晶体管T3的栅极与所述发光控制线E1电连接，所述第三晶体管T3的漏极与高电压端VDD电连接，所述第三晶体管T3的源极与所述驱动晶体管T0的漏极电连接；
所述第四晶体管T4的栅极与所述发光控制线E1电连接，所述第四晶体管T4的漏极与所述驱动晶体管T0的源极电连接，所述第四晶体管T4的源极与所述有机发光二极管O1的阳极电连接；
所述第一初始化电路13包括第五晶体管T5；
所述第五晶体管T5的栅极与所述复位控制线R1电连接，所述第五晶体管T5的漏极与所述第一初始电压端I1电连接，所述第五晶体管T5的源极与所述驱动晶体管T0的栅极电连接；
所述第二初始化电路32包括第六晶体管T6；
所述第六晶体管T6的栅极与所述第一扫描控制线G1电连接，所述第六晶体管T6的漏极与所述第二初始电压端I2电连接，所述第六晶体管T6的源极与所述有机发光二极管O1的阳极电连接；
所述有机发光二极管O1的阴极与低电压端VSS电连接。
本公开如图6所示的像素电路的至少一实施例为全新的7T1C像素电路，能够有效的支撑全氧化物器件特性。
在本公开如图6所示的像素电路的至少一实施例中，T1、T2、T3、T4、T5、T6和T0都为氧化物晶体管，T1、T2、T3、T4、T5、T6和T0都为NMOS晶体管(N型金属-氧化物-半导体晶体管)，但不以此为限。
在本公开如图6所示的像素电路的至少一实施例中，补偿控制线和初始控制线为相同的控制线，都为第一扫描控制线G1，写入控制线为第二扫描控制线G2，本公开如图6所示的像素电路的至少一实施例能够在高频驱动模式和低频驱动模式下工作。
在图6中，标号为N1的为第一节点，第一节点N1与T0的栅极电连接；标号为N2的为第二节点，第二节点N2与T0的漏极电连接；标号为N3的为第三节点，第三节点N3与T0的源极电连接；标号为N4的为第四节点，第四节点N4与O1的阳极电连接。
在本公开如图6所示的像素电路的至少一实施例中，第五晶体管T5在所述复位控制线R1提供的复位控制信号的控制下工作，以能够自由调节通过第一初始电压端I1提供的第一初始电压Vint1对所述驱动晶体管T0的栅极的电位进行重置的时间；第六晶体管T6在第一扫描控制线G1提供的第一扫描控制信号的控制下工作，能够在低频驱动模式下工作，对O1的阳极进行复位；第一晶体管T1在所述第二扫描控制线G2提供的第二扫描控制信号的控制下工作，以进行数据电压写入，第一晶体管T1和第六晶体管T6在不同的控制信号的控制下工作，以能够控制在低频驱动模式下工作时，在保持帧，控制T1持续关断，并在保持帧包括的第二初始阶段，控制T6打开。
如图7所示，本公开如图6所示的像素电路的至少一实施例在高频驱动模式下工作时，显示帧可以包括先后设置的第一初始化阶段S11、补偿阶段 S12和第一发光阶段S13；所述补偿阶段S12包括数据写入时间段S0；
在所述第一初始化阶段S11，E1提供低电压信号，R1提供高电压信号，G1提供低电压信号，G2提供低电压信号，T5打开，I1提供第一初始电压Vint1，将第一初始电压Vint1写入第一节点N1，以使得在所述数据写入时间段S0开始时，T0能够导通；
在所述补偿阶段S12，E1提供低电压信号，R1提供低电压信号，G1提供高电压信号，T2和T6打开，T5关断，I2提供第二初始电压端Vint2，第一节点N1与第二节点N2之间连通，并将Vint2写入第四节点N4，以使得O1不发光，并清除残留于O1的阳极的电荷；
在所述数据写入时间段S0，G2提供高电压信号，R1和E1都提供低电压信号，数据线D1提供数据电压Vdata，以将数据电压Vdata写入第三节点N3；
在所述数据写入时间段S0开始时，T0打开，以通过数据电压Vdata为C1充电，而改变第一节点N1的电位，直至T0关断，此时，第三节点N3的电位为Vdata，第一节点N1的电位和第二节点N2的电位都为Vdata+Vth；第四节点N4的电位为VINT2；Vth为T0的阈值电压；
在所述第一发光阶段S13，E1提供高电压信号，R1、G1和G2提供低电压信号，T3和T4打开，T0驱动O1发光；
在所述第一发光阶段S13，第四节点N4的电位为Vo+Vs；所述第一节点N1的电位变为Vdata+Vth+Vo+Vs-Vini2，Vgs等于Vdata+Vth-Vint2；其中，Vo为O1的起亮电压，Vs为所述低电压端VSS提供的低电压信号的电压值；
在所述第一发光阶段S13，T0驱动O1发光的驱动电流Io等于0.5K(Vdata-Vint2) 2；其中，K为T0的电流系数；由Io的公式可知，Io与T0的阈值电压Vth无关，能够进行阈值电压补偿。
如图8所示，本公开如图6所示的像素电路的至少一实施例工作于低频驱动模式下时，显示周期可以包括刷新帧F1和至少一个保持帧F2；所述刷新帧F1可以包括先后设置的第一初始化阶段S11、补偿阶段S12和第一发光阶段S13；所述补偿阶段S12包括数据写入时间段S0；所述保持帧F2包括第二初始化阶段S21和第二发光阶段S22；
在所述第一初始化阶段S11，E1提供低电压信号，R1提供高电压信号，G1提供低电压信号，G2提供低电压信号，T5打开，I1提供第一初始电压Vint1，将第一初始电压Vint1写入第一节点N1，以使得在所述数据写入时间段S0开始时，T0能够导通；
在所述补偿阶段S12，E1提供低电压信号，R1提供低电压信号，G1提供高电压信号，T2和T6打开，T5关断，I2提供第二初始电压端Vint2，第一节点N1与第二节点N2之间连通，并将Vint2写入第四节点N4，以使得O1不发光，并清除残留于O1的阳极的电荷；
在所述数据写入时间段S0，G2提供高电压信号，R1和E1都提供低电压信号，数据线D1提供数据电压Vdata，以将数据电压Vdata写入第三节点N3；
在所述数据写入时间段S0开始时，T0打开，以通过数据电压Vdata为C1充电，而改变第一节点N1的电位，直至T0关断，此时，第三节点N3的电位为Vdata，第一节点N1的电位和第二节点N2的电位都为Vdata+Vth；第四节点N4的电位为VINT2；Vth为T0的阈值电压；
在所述第一发光阶段S13，E1提供高电压信号，R1、G1和G2提供低电压信号，T3和T4打开，T0驱动O1发光；
在所述第一发光阶段S13，第四节点N4的电位为Vo+Vs；所述第一节点N1的电位变为Vdata+Vth+Vo+Vs-Vini2，Vgs等于Vdata+Vth-Vint2；其中，Vo为O1的起亮电压，Vs为所述低电压端VSS提供的低电压信号的电压值；
在所述第一发光阶段S13，T0驱动O1发光的驱动电流Io等于0.5K(Vdata-Vint2) 2；其中，K为T0的电流系数；由Io的公式可知，Io与T0的阈值电压Vth无关，能够进行阈值电压补偿；
在所述二初始化阶段S21，E1提供低电压信号，R1和G2提供低电压信号，G1提供高电压信号，T6和T2打开，I2提供第二初始电压Vint2，以将第二初始电压Vint2写入O1的阳极，以控制O1不发光，对O1的阳极的电位进行重置，并清除O1的阳极残留的电荷；并由于此时T3和T4关断，因此T2的打开不会对显示产生影响；
在所述第二发光阶段S22，E1提供高电压信号，R1、G1、G2和G3都 提供低电压信号，T3和T4打开，T0驱动O1发光；
在所述保持帧F2，G2输出低电压信号，以使得T1关断，停止数据电压写入，以能够保持以刷新帧的亮度显示。
本公开如图6所示的像素电路的至少一实施例工作于低频驱动模式下时，在所述保持帧F1包括的第二发光阶段之前，在所述保持帧F1包括的第二初始化阶段，T6打开，以对O1的阳极的电位进行重置，以使得在每一保持帧，T0驱动O1发光之前，O1的阳极的电位都维持为相同电位，避免在低频显示时产生闪烁现象。
如图9所示，在图3所示的像素电路的至少一实施例的基础上，所述数据写入电路16包括第一晶体管T1，所述补偿控制电路15包括第二晶体管T2；所述储能电路14包括存储电容C1；所述驱动电路11包括驱动晶体管T0；所述发光元件为有机发光二极管O1；
所述第一晶体管T1的栅极与第二扫描控制线G2电连接，所述第一晶体管T1的漏极与所述数据线D1电连接，所述第一晶体管T1的源极与所述驱动晶体管T0的源极电连接；
所述第二晶体管T2的栅极与所述第一扫描控制线G1电连接，所述第二晶体管T2的漏极与所述驱动晶体管T0的栅极电连接，所述第二晶体管T2的源极与所述驱动晶体管T0的漏极电连接；
所述存储电容C1的第一端与所述驱动晶体管T0的栅极电连接，所述存储电容C1的第二端与所述有机发光二极管O1的阳极电连接；
所述第二发光控制电路21包括第三晶体管T3，所述第一发光控制电路12包括第四晶体管T4；
所述第三晶体管T3的栅极与所述发光控制线E1电连接，所述第三晶体管T3的漏极与高电压端VDD电连接，所述第三晶体管T3的源极与所述驱动晶体管T0的漏极电连接；
所述第四晶体管T4的栅极与所述发光控制线E1电连接，所述第四晶体管T4的漏极与所述驱动晶体管T0的源极电连接，所述第四晶体管T4的源极与所述有机发光二极管O1的阳极电连接；
所述第一初始化电路13包括第五晶体管T5；
所述第五晶体管T5的栅极与所述复位控制线R1电连接，所述第五晶体管T5的漏极与所述第一初始电压端I1电连接，所述第五晶体管T5的源极与所述驱动晶体管T0的栅极电连接；
所述第二初始化电路32包括第六晶体管T6；
所述第六晶体管T6的栅极与所述第三扫描控制线G3电连接，所述第六晶体管T6的漏极与所述第二初始电压端I2电连接，所述第六晶体管T6的源极与所述有机发光二极管O1的阳极电连接；
所述有机发光二极管O1的阴极与低电压端VSS电连接。
本公开如图9所示的像素电路的至少一实施例为全新的7T1C像素电路，能够有效的支撑全氧化物器件特性。
在本公开如图9所示的像素电路的至少一实施例中，T1、T2、T3、T4、T5、T6和T0都为氧化物晶体管，T1、T2、T3、T4、T5、T6和T0都为NMOS晶体管(N型金属-氧化物-半导体晶体管)，但不以此为限。
在图9中，标号为N1的为第一节点，第一节点N1与T0的栅极电连接；标号为N2的为第二节点，第二节点N2与T0的漏极电连接；标号为N3的为第三节点，第三节点N3与T0的源极电连接；标号为N4的为第四节点，第四节点N4与O1的阳极电连接。
在本公开如图9所示的像素电路的至少一实施例中，补偿控制线、写入控制线和初始控制线为不同的控制线，补偿控制线为第一扫描控制线G1，写入控制线为第二扫描控制线G2，初始控制线为第三扫描控制线G3；本公开如图9所示的像素电路的至少一实施例能够在高频驱动模式和低频驱动模式下工作。
在本公开如图9所示的像素电路的至少一实施例中，第五晶体管T5在所述复位控制线R1提供的复位控制信号的控制下工作，以能够自由调节通过第一初始电压端I1提供的第一初始电压Vint1对所述驱动晶体管T0的栅极的电位进行重置的时间；第六晶体管T6在第三扫描控制线G3提供的第三扫描控制信号的控制下工作，以能够在低频驱动模式下工作，对O1的阳极进行复位；第一晶体管T1在所述第二扫描控制线G2提供的第二扫描控制信号的控制下工作，以进行数据电压写入，第一晶体管T1和第六晶体管T6在不同的 控制信号的控制下工作，以能够控制在低频驱动模式下工作时，在保持帧，控制T1持续关断，并在保持帧包括的第二初始阶段，控制T6打开。
如图10所示，本公开如图9所示的像素电路的至少一实施例工作于高频驱动模式下时，显示帧可以包括先后设置的第一初始化阶段S11、补偿阶段S12和第一发光阶段S13；所述补偿阶段S12包括数据写入时间段S0；
在所述第一初始化阶段S11，E1提供低电压信号，R1提供高电压信号，G1、G2和G3提供低电压信号，T5打开，I1提供第一初始电压Vint1，将第一初始电压Vint1写入第一节点N1，以使得在所述数据写入时间段S0开始时，T0能够导通；
在所述补偿阶段S12，E1提供低电压信号，R1提供低电压信号，G1提供高电压信号，G3提供高电压信号，T2和T6打开，T5关断，I2提供第二初始电压端Vint2，第一节点N1与第二节点N2之间连通，并将Vint2写入第四节点N4，以使得O1不发光，对O1的阳极的电位进行重置，并清除残留于O1的阳极的电荷；
在所述数据写入时间段S0，G2提供高电压信号，R1和E1都提供低电压信号，数据线D1提供数据电压Vdata，以将数据电压Vdata写入第三节点N3；
在所述数据写入时间段S0开始时，T0打开，以通过数据电压Vdata为C1充电，而改变第一节点N1的电位，直至T0关断，此时，第三节点N3的电位为Vdata，第一节点N1的电位和第二节点N2的电位都为Vdata+Vth；第四节点N4的电位为VINT2；Vth为T0的阈值电压；
在所述第一发光阶段S13，E1提供高电压信号，R1、G1和G2提供低电压信号，T3和T4打开，T0驱动O1发光；
在所述第一发光阶段S13，第四节点N4的电位为Vo+Vs；所述第一节点N1的电位变为Vdata+Vth+Vo+Vs-Vini2，Vgs等于Vdata+Vth-Vint2；其中，Vo为O1的起亮电压，Vs为所述低电压端VSS提供的低电压信号的电压值；
在所述第一发光阶段S13，T0驱动O1发光的驱动电流Io等于0.5K(Vdata-Vint2) 2；其中，K为T0的电流系数；由Io的公式可知，Io与T0的阈值电压Vth无关，能够进行阈值电压补偿。
如图11所示，本公开如图9所示的像素电路的至少一实施例工作于低频驱动模式下时，显示周期可以包括刷新帧F1和至少一个保持帧F2；所述刷新帧F1可以包括先后设置的第一初始化阶段S11、补偿阶段S12和第一发光阶段S13；所述补偿阶段S12包括数据写入时间段S0；所述保持帧F2包括第二初始化阶段S21和第二发光阶段S22；
在所述第一初始化阶段S11，E1提供低电压信号，R1提供高电压信号，G1、G2和G3提供低电压信号，T5打开，I1提供第一初始电压Vint1，将第一初始电压Vint1写入第一节点N1，以使得在所述数据写入时间段S0开始时，T0能够导通；
在所述补偿阶段S12，E1提供低电压信号，R1提供低电压信号，G1提供高电压信号，G3提供高电压信号，T2和T6打开，T5关断，G1提供高电压信号，T2和T6打开，T5关断，I2提供第二初始电压端Vint2，第一节点N1与第二节点N2之间连通，并将Vint2写入第四节点N4，以使得O1不发光，对O1的阳极的电位进行重置，并清除残留于O1的阳极的电荷；
在所述数据写入时间段S0，G2提供高电压信号，R1和E1都提供低电压信号，数据线D1提供数据电压Vdata，以将数据电压Vdata写入第三节点N3；
在所述数据写入时间段S0开始时，T0打开，以通过数据电压Vdata为C1充电，而改变第一节点N1的电位，直至T0关断，此时，第三节点N3的电位为Vdata，第一节点N1的电位和第二节点N2的电位都为Vdata+Vth；第四节点N4的电位为VINT2；Vth为T0的阈值电压；
在所述第一发光阶段S13，E1提供高电压信号，R1、G1和G2提供低电压信号，T3和T4打开，T0驱动O1发光；
在所述第一发光阶段S13，第四节点N4的电位为Vo+Vs；所述第一节点N1的电位变为Vdata+Vth+Vo+Vs-Vini2，Vgs等于Vdata+Vth-Vint2；其中，Vo为O1的起亮电压，Vs为所述低电压端VSS提供的低电压信号的电压值；
在所述第一发光阶段S13，T0驱动O1发光的驱动电流Io等于0.5K(Vdata-Vint2)2；其中，K为T0的电流系数；由Io的公式可知，Io与T0的阈值电压Vth无关，能够进行阈值电压补偿；
在所述二初始化阶段S21，E1提供低电压信号，G3提供高电压信号，R1、G1和G2都提供低电压信号，T6打开，I2提供第二初始电压Vint2，以将第二初始电压Vint2写入O1的阳极，以控制O1不发光，对O1的阳极的电位进行重置，清除O1的阳极残留的电荷；
在所述第二发光阶段S22，E1提供高电压信号，R1、G1、G2和G3都提供低电压信号，T3和T4打开，T0驱动O1发光。
本公开如图9所示的像素电路的至少一实施例工作于低频驱动模式下时，在所述保持帧F1包括的第二发光阶段之前，在所述保持帧F1包括的第二初始化阶段，T6打开，以对O1的阳极的电位进行重置，以使得在每一保持帧，T0驱动O1发光之前，O1的阳极的电位都维持为相同电位，避免在低频显示时产生闪烁现象。
可选的，本公开至少一实施例所述的像素电路还可以包括第三初始化电路；
所述第三初始化电路分别与所述复位控制线和第三初始电压端电连接，所述第三初始化电路与所述驱动电路的第一端或所述驱动电路的第二端电连接，所述第三初始化电路用于在所述复位控制线提供的复位控制信号的控制下，将所述第三初始电压端提供的第三初始电压写入所述驱动电路的第一端或所述驱动电路的第二端。
在本公开至少一实施例中，所述像素电路还可以包括第三初始化电路，所述第三初始化电路可以在第一初始化电路对驱动电路的控制端的电位进行重置时，将第三初始电压写入所述驱动电路的第一端或所述驱动电路的第二端，增大驱动电路包括的驱动晶体管的偏压，以改善所述驱动晶体管的磁滞现象。
在本公开至少一实施例中，当第一初始电压Vint1为正值时，第三初始电压Vint3可以为负值，使得在第一初始化电路控制将第一初始电压Vint1写入驱动晶体管的栅极，第三初始化电路控制将第三初始电压Vint3写入驱动晶体管的第一极或驱动晶体管的第二极时，所述驱动晶体管的栅源电压远大于所述驱动晶体管的阈值电压Vth，增大所述驱动晶体管的偏压。
可选的，所述第三初始化电路包括第七晶体管；
所述第七晶体管的控制极与所述复位控制线电连接，所述第七晶体管的第一极与所述第三初始电压端电连接，所述第七晶体管的第二极与所述驱动电路的第一端或所述驱动电路的第二端电连接。
如图12所示，在图3所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还可以包括第三初始化电路110；
所述第三初始化电路110分别与所述复位控制线R1和第三初始电压端I3电连接，所述第三初始化电路110与所述驱动电路11的第二端电连接，所述第三初始化电路110用于在所述复位控制线R1提供的复位控制信号的控制下，将所述第三初始电压端I3提供的第三初始电压Vint3写入所述驱动电路11的第二端。
本公开如图12所示的像素电路的至少一实施例在工作时，在所述第一初始化阶段，所述第三初始化电路110在所述复位控制信号的控制下，将第三初始电压端I3提供的第三初始电压Vi3写入所述驱动电路11的第二端。
如图13所示，在图9所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还包括第三初始化电路110；
所述第三初始化电路110包括第七晶体管T7；
所述第七晶体管T7的栅极与所述复位控制线R1电连接，所述第七晶体管T7的漏极与所述第三初始电压端I3电连接，所述第七晶体管T7的源极与第二节点N2电连接。
在图13所示的像素电路的至少一实施例中，所有的晶体管都为氧化物晶体管，所有晶体管都为NMOS晶体管。
本公开如图13所示的像素电路的至少一实施例在工作时，在第一初始化阶段，R1提供高电压信号，T7打开，第三初始电压端I3提供第三初始电压Vint3，以将所述第三初始电压Vint3写入第二节点N2，T5导通，第一初始电压端Vint1提供第一初始电压Vint1，以将第一初始电压Vint1写入T0的栅极，增大驱动晶体管T0的偏压，以改善所述驱动晶体管T0的磁滞现象。
在本公开至少一实施例中，所述发光控制电路包括的晶体管、所述数据写入电路包括的晶体管、所述补偿控制电路包括的晶体管、所述驱动电路包括的晶体管、所述第一初始化电路包括的晶体管、所述第二初始化电路包括 的晶体管和所述第三初始化电路包括的晶体管可以都为氧化物薄膜晶体管。
本公开至少一实施例所述的显示装置包括上述的像素电路。
本公开实施例所提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (16)

  1. 一种像素电路，包括发光元件、驱动电路、第一发光控制电路、第一初始化电路、储能电路、补偿控制电路和数据写入电路；
    所述第一发光控制电路分别与发光控制线、所述驱动电路的第一端与所述发光元件电连接，用于在所述发光控制线提供的发光控制信号的控制下，控制所述驱动电路的第一端与所述发光元件之间连通；
    所述第一初始化电路分别与复位控制线、第一初始电压端和所述驱动电路的控制端电连接，用于在所述复位控制线提供的复位控制信号的控制下，将所述第一初始电压端提供的第一初始电压写入所述驱动电路的控制端；
    所述储能电路的第一端与所述驱动电路的控制端电连接，所述储能电路的第二端与所述发光元件的第一极电连接，所述储能电路用于储存电能；
    所述数据写入电路分别与写入控制线、数据线和所述驱动电路的第一端电连接，用于在所述写入控制线提供的写入控制信号的控制下，将所述数据线提供的数据电压写入所述驱动电路的第一端；
    所述补偿控制电路分别与补偿控制线、所述驱动电路的控制端和所述驱动电路的第二端电连接，用于在所述补偿控制线提供的补偿控制信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间连通。
  2. 如权利要求1所述的像素电路，其中，还包括第二发光控制电路；
    所述第二发光控制电路分别与所述发光控制线、第一电压端和所述驱动电路的第二端电连接，用于在所述发光控制信号的控制下，控制所述第一电压端与所述驱动电路的第二端之间连通；
    所述第一发光控制电路与所述发光元件的第一极电连接，所述发光元件的第二极与第二电压端电连接。
  3. 如权利要求2所述的像素电路，其中，还包括第二初始化电路；
    所述第二初始化电路分别与初始控制线、第二初始电压端和所述发光元件的第一极之间连通，用于在所述初始控制线提供的初始控制信号的控制下，将所述第二初始电压端提供的第二初始电压写入所述发光元件的第一极。
  4. 如权利要求1所述的像素电路，其中，所述数据写入电路包括第一晶 体管，所述补偿控制电路包括第二晶体管；所述储能电路包括存储电容；所述驱动电路包括驱动晶体管；
    所述第一晶体管的控制极与所述写入控制线电连接，所述第一晶体管的第一极与所述数据线电连接，所述第一晶体管的第二极与所述驱动电路的第一端电连接；
    所述第二晶体管的控制极与所述补偿控制线电连接，所述第二晶体管的第一极与所述驱动电路的控制端电连接，所述第二晶体管的第二极与所述驱动电路的第二端电连接；
    所述存储电容的第一端与所述驱动电路的控制端电连接，所述存储电容的第二端与所述发光元件的第一极电连接；
    所述驱动晶体管的控制极为所述驱动电路的控制端，所述驱动晶体管的第一极为所述驱动电路的第一端，所述驱动晶体管的第二极为所述驱动电路的第二端。
  5. 如权利要求2所述的像素电路，其中，所述第二发光控制电路包括第三晶体管，所述第一发光控制电路包括第四晶体管；
    所述第三晶体管的控制极与所述发光控制线电连接，所述第三晶体管的第一极与所述第一电压端电连接，所述第三晶体管的第二极与所述驱动电路的第二端电连接；
    所述第四晶体管的控制极与所述发光控制线电连接，所述第四晶体管的第一极与所述驱动电路的第一端电连接，所述第四晶体管的第二极与所述发光元件的第一极电连接。
  6. 如权利要求1所述的像素电路，其中，所述第一初始化电路包括第五晶体管；
    所述第五晶体管的控制极与所述复位控制线电连接，所述第五晶体管的第一极与所述第一初始电压端电连接，所述第五晶体管的第二极与所述驱动电路的控制端电连接。
  7. 如权利要求3所述的像素电路，其中，所述第二初始化电路包括第六晶体管；
    所述第六晶体管的控制极与所述初始控制线电连接，所述第六晶体管的 第一极与所述第二初始电压端电连接，所述第六晶体管的第二极与所述发光元件的第一极电连接。
  8. 如权利要求3所述的像素电路，其中，还包括第三初始化电路；
    所述第三初始化电路分别与所述复位控制线和第三初始电压端电连接，所述第三初始化电路与所述驱动电路的第一端或所述驱动电路的第二端电连接，所述第三初始化电路用于在所述复位控制线提供的复位控制信号的控制下，将所述第三初始电压端提供的第三初始电压写入所述驱动电路的第一端或所述驱动电路的第二端。
  9. 如权利要求8所述的像素电路，其中，所述第三初始化电路包括第七晶体管；
    所述第七晶体管的控制极与所述复位控制线电连接，所述第七晶体管的第一极与所述第三初始电压端电连接，所述第七晶体管的第二极与所述驱动电路的第一端或所述驱动电路的第二端电连接。
  10. 如权利要求8所述的像素电路，其中，所述发光控制电路包括的晶体管、所述数据写入电路包括的晶体管、所述补偿控制电路包括的晶体管、所述驱动电路包括的晶体管、所述第一初始化电路包括的晶体管、所述第二初始化电路包括的晶体管和所述第三初始化电路包括的晶体管都为氧化物薄膜晶体管。
  11. 一种像素驱动方法，应用于如权利要求1至10中任一权利要求所述的像素电路，显示帧包括先后设置的第一初始化阶段和补偿阶段；所述像素驱动方法包括：
    在第一初始化阶段，第一初始化电路在复位控制信号的控制下，将第一初始电压端提供的第一初始电压写入驱动电路的控制端；
    在数据写入时间段，数据线提供数据电压，数据写入电路在写入控制信号的控制下，将所述数据电压写入驱动电路的第一端；
    在补偿阶段，补偿控制电路在补偿控制信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间连通；
    在数据写入时间段开始时，驱动电路在其控制端的电位的控制下，控制所述驱动电路的第一端与所述驱动电路的第二端之间连通，通过所述数据电 压为所述储能电路充电，以改变所述驱动电路的控制端的电位，直至所述驱动电路的第一端与所述驱动电路的第二端之间断开；
    所述数据写入时间段与所述补偿阶段为同一时间段，或者，所述数据写入时间段包含于所述补偿阶段。
  12. 如权利要求11所述的像素驱动方法，其中，所述像素电路包括第二发光控制电路；所述显示周期还包括设置于所述补偿阶段之后的第一发光阶段，所述像素驱动方法还包括：
    在所述第一发光阶段，第一发光控制电路在发光控制信号的控制下，控制所述驱动电路的第一端与发光元件之间连通，第二发光控制电路在所述发光控制信号的控制下，控制第一电压端与所述驱动电路的第二端之间连通，所述驱动电路驱动所述发光元件发光。
  13. 如权利要求12所述的像素驱动方法，其中，所述像素电路还包括第二初始化电路；所述像素驱动方法还包括：
    在所述补偿阶段，所述第二初始化电路在初始控制信号的控制下，将第二初始电压端提供的第二初始电压写入所述发光元件的第一极，以控制所述发光元件不发光，对所述发光元件的第一极的电位进行重置，清除所述发光元件的第一极残留的电荷。
  14. 如权利要求12所述的像素驱动方法，其中，所述像素电路还包括第三初始化电路；所述像素驱动方法还包括：
    在所述第一初始化阶段，所述第三初始化电路在复位控制信号的控制下，将第三初始电压端提供的第三初始电压写入所述驱动电路的第二端。
  15. 如权利要求13所述的像素驱动方法，其中，所述显示帧为刷新帧，显示周期还包括保持帧；所述保持帧包括先后设置的第二初始化阶段和第二发光阶段；所述像素驱动方法还包括：
    在所述第二初始化阶段，第二初始化电路在复位控制信号的控制下，将第二初始电压端提供的第二初始电压写入发光元件的第一极，以控制所述发光元件不发光，对所述发光元件的第一极的电位进行重置，清除所述发光元件的第一极残留的电荷；
    在所述第二发光阶段，所述第一发光控制电路在发光控制信号的控制下， 控制所述驱动电路的第一端与发光元件之间连通，所述第二发光控制电路在所述发光控制信号的控制下，控制第一电压端与所述驱动电路的第二端之间连通，所述驱动电路驱动所述发光元件发光。
  16. 一种显示装置，包括如权利要求1至10中任一权利要求所述的像素电路。
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160063922A1 (en) * 2014-08-26 2016-03-03 Apple Inc. Organic Light-Emitting Diode Display
CN109559686A (zh) * 2019-01-18 2019-04-02 京东方科技集团股份有限公司 像素电路、驱动方法、电致发光显示面板及显示装置
CN112530341A (zh) * 2020-06-04 2021-03-19 友达光电股份有限公司 像素电路
CN112992070A (zh) * 2021-02-25 2021-06-18 合肥维信诺科技有限公司 像素电路及其驱动方法、显示面板及显示装置
CN113270067A (zh) * 2021-06-28 2021-08-17 深圳市华星光电半导体显示技术有限公司 像素电路及显示面板
CN113744683A (zh) * 2021-09-03 2021-12-03 北京京东方技术开发有限公司 像素电路、驱动方法和显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160063922A1 (en) * 2014-08-26 2016-03-03 Apple Inc. Organic Light-Emitting Diode Display
CN109559686A (zh) * 2019-01-18 2019-04-02 京东方科技集团股份有限公司 像素电路、驱动方法、电致发光显示面板及显示装置
CN112530341A (zh) * 2020-06-04 2021-03-19 友达光电股份有限公司 像素电路
CN112992070A (zh) * 2021-02-25 2021-06-18 合肥维信诺科技有限公司 像素电路及其驱动方法、显示面板及显示装置
CN113270067A (zh) * 2021-06-28 2021-08-17 深圳市华星光电半导体显示技术有限公司 像素电路及显示面板
CN113744683A (zh) * 2021-09-03 2021-12-03 北京京东方技术开发有限公司 像素电路、驱动方法和显示装置

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