WO2023039893A1 - 像素电路、驱动方法和显示装置 - Google Patents

像素电路、驱动方法和显示装置 Download PDF

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Publication number
WO2023039893A1
WO2023039893A1 PCT/CN2021/119407 CN2021119407W WO2023039893A1 WO 2023039893 A1 WO2023039893 A1 WO 2023039893A1 CN 2021119407 W CN2021119407 W CN 2021119407W WO 2023039893 A1 WO2023039893 A1 WO 2023039893A1
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WIPO (PCT)
Prior art keywords
control
circuit
node
electrically connected
transistor
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PCT/CN2021/119407
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English (en)
French (fr)
Inventor
王本莲
秦成杰
刘聪
黄耀
龙跃
黄炜赟
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2021/119407 priority Critical patent/WO2023039893A1/zh
Priority to CN202180002613.7A priority patent/CN116547738A/zh
Publication of WO2023039893A1 publication Critical patent/WO2023039893A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a pixel circuit, a driving method and a display device.
  • the gate voltage of the driving transistor is initialized to the initial voltage.
  • the source voltage of the transistor changes accordingly.
  • the variation of the gate voltage of the driving transistor is different, so the variation of the source voltage of the driving transistor is also different, which leads to different source voltages of the driving transistor after the reset phase is completed, and the variation of the driving transistor is different.
  • the gate-source voltage Vgs is also different. At the same time, since the gate-source voltage Vgs of the driving transistor will affect its threshold voltage, the afterimage problem will occur in the display panel.
  • an embodiment of the present disclosure provides a pixel circuit, including a light-emitting element, a driving circuit, a first light-emitting control circuit, a first control circuit, a first initialization circuit, and a second light-emitting control circuit, wherein,
  • the first control circuit is electrically connected to the first scan line, the first node and the control node, and is used to control the first node and the control node under the control of the first scan signal provided by the first scan line. Connectivity between control nodes;
  • the first initialization circuit is respectively electrically connected to the second light emission control line, the first initial voltage terminal and the control node, and is used to control the writing the first initial voltage provided by the first initial voltage terminal into the control node;
  • the second light emission control circuit is respectively electrically connected to the first light emission control line, the third node and the first pole of the light emitting element, and is used for controlling the first light emission control signal provided by the first light emission control line , controlling the communication between the third node and the first pole of the light emitting element;
  • the control end of the driving circuit is electrically connected to the first node, the first end of the driving circuit is electrically connected to the second node, the second end of the driving circuit is electrically connected to the third node, and the driving circuit is used for Under the control of the potential of the first node, controlling the communication between the second node and the third node;
  • the second pole of the light emitting element is electrically connected to the first voltage terminal.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a compensation control circuit and a data writing circuit;
  • the compensation control circuit is electrically connected to the first scan line, the control node and the third node, and is used to control the control node and the third node under the control of the first scan signal provided by the first scan line.
  • the third nodes are connected;
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a second initialization circuit
  • the second initialization circuit is electrically connected to the second scanning line, the second initial voltage terminal and the first electrode of the light-emitting element respectively, and is used for controlling the second scanning signal provided by the second scanning line , writing the second initial voltage provided by the second initial voltage terminal into the first electrode of the light emitting element.
  • the transistors included in the first light emission control circuit, the transistors included in the second light emission control circuit, and the transistors included in the first initialization circuit are all p-type transistors, and the first light emission control signal The same light emission control signal generation circuit as the second light emission control signal is provided, the first light emission control signal is the nth level light emission control signal provided by the light emission control signal generation circuit, and the second light emission control signal is the The n+1th stage light emission control signal provided by the above light emission control signal generation circuit, n is a positive integer.
  • the transistors included in the first control circuit, the transistors included in the data writing circuit, and the transistors included in the compensation control circuit are all p-type transistors, and the first scan signal and the second scan signal The signal is provided by the same scanning signal generating circuit;
  • the first scan signal is the mth level scan signal provided by the scan signal generation circuit
  • the second scan signal is the m+1st level scan signal provided by the scan signal generation circuit
  • m is a positive integer.
  • the first control circuit includes a first transistor, and the first initialization circuit includes a second transistor;
  • the control electrode of the first transistor is electrically connected to the first scan line, the first electrode of the first transistor is electrically connected to the control node, and the second electrode of the first transistor is electrically connected to the first node. electrical connection;
  • the control electrode of the second transistor is electrically connected to the second light emission control line, the first electrode of the second transistor is electrically connected to the first initial voltage terminal, and the second electrode of the second transistor is electrically connected to the The control node is electrically connected.
  • the first transistor is a double-gate transistor; or, the first transistor is an oxide transistor.
  • the first light emission control circuit includes a third transistor, and the second light emission control circuit includes a fourth transistor;
  • the control electrode of the third transistor is electrically connected to the second light-emitting control line, the first electrode of the third transistor is electrically connected to the power supply voltage terminal, and the second electrode of the third transistor is electrically connected to the first light emitting control line.
  • the control electrode of the fourth transistor is electrically connected to the first light-emitting control line, the first electrode of the fourth transistor is electrically connected to the third node, and the second electrode of the fourth transistor is electrically connected to the light-emitting
  • the first poles of the elements are electrically connected.
  • the compensation control circuit includes a fifth transistor, and the data writing circuit includes a sixth transistor;
  • the control electrode of the fifth transistor is electrically connected to the first scanning line, the first electrode of the fifth transistor is electrically connected to the control node, and the second electrode of the fifth transistor is electrically connected to the third node. electrical connection;
  • the control electrode of the sixth transistor is electrically connected to the second scan line, the first electrode of the sixth transistor is electrically connected to the data line, and the second electrode of the sixth transistor is electrically connected to the second node. electrical connection.
  • the second initialization circuit includes a seventh transistor
  • the control electrode of the seventh transistor is electrically connected to the second scanning line, the first electrode of the seventh transistor is electrically connected to the second initial voltage terminal, and the second electrode of the seventh transistor is electrically connected to the The first poles of the light emitting elements are electrically connected.
  • the energy storage circuit includes a storage capacitor
  • the drive circuit includes a drive transistor
  • the control electrode of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the second node, and the second electrode of the driving transistor is electrically connected to the third node;
  • a first end of the storage capacitor is electrically connected to the first node, and a second end of the storage capacitor is electrically connected to the power supply voltage end.
  • the embodiment of the present disclosure also provides a driving method, which is applied to the above-mentioned pixel circuit, and the display cycle includes an initialization phase; the driving method includes:
  • the first light-emitting control circuit controls the communication between the power supply terminal and the second node; under the control of the second light-emitting control signal, the first initialization circuit The initial voltage is written into the control node, and the first control circuit controls the communication between the first node and the control node under the control of the first scan signal, so as to write the first initial voltage into the first node.
  • the pixel circuit further includes a compensation control circuit, a data writing circuit, and an energy storage circuit;
  • the display cycle also includes a data writing phase and a light emitting phase set after the initialization phase;
  • the driving method further includes:
  • the data writing circuit writes the data voltage into the second node under the control of the second scanning signal, and the compensation control circuit controls the communication between the third node and the control node under the control of the first scanning signal. ;
  • the drive circuit controls the connection between the second node and the third node under the control of the potential of the first node, so as to charge the energy storage circuit with the data voltage and change the potential of the first node , until the drive circuit is turned off;
  • the first light-emitting control circuit controls the connection between the power supply voltage terminal and the first end of the drive circuit under the control of the second light-emitting control signal
  • the second light-emitting control circuit controls the The second end of the driving circuit communicates with the first pole of the light emitting element, and the driving circuit drives the light emitting element to emit light.
  • the pixel circuit further includes a second initialization circuit
  • the driving method further includes:
  • the second initialization circuit writes a second initial voltage into the first pole of the light emitting element, so that the light emitting element does not emit light.
  • the second light emission control circuit controls the second terminal of the driving circuit and the first light emission element under the control of the first light emission control signal. One pole is disconnected.
  • an embodiment of the present disclosure further provides a display device, including the above-mentioned pixel circuit.
  • FIG. 1 is a structural diagram of a pixel circuit described in an embodiment of the present disclosure
  • Fig. 2 is a structural diagram of a pixel circuit described in at least one embodiment of the present disclosure
  • Fig. 3 is a structural diagram of a pixel circuit described in at least one embodiment of the present disclosure.
  • Fig. 4 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG. 5 is a working timing diagram of at least one embodiment of the pixel circuit shown in FIG. 4 of the present disclosure
  • FIG. 6 is another working timing diagram of at least one embodiment of the pixel circuit shown in FIG. 4 of the present disclosure.
  • FIG. 7 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • the transistors used in all the embodiments of the present disclosure may be triodes, thin film transistors or field effect transistors or other devices with the same characteristics.
  • one pole is called the first pole, and the other pole is called the second pole.
  • the first pole when the transistor is a thin film transistor or a field effect transistor, the first pole may be a drain, and the second pole may be a source; or, the first pole may be a source, The second pole may be a drain.
  • the pixel circuit described in the embodiment of the present disclosure includes a light emitting element 10 , a driving circuit 11 , a first light emitting control circuit 12 , a first control circuit 13 , a first initialization circuit 14 and a second light emitting control circuit 15 , in,
  • the first control circuit 13 is electrically connected to the first scanning line G1, the first node N1 and the control node N0, and is used to control the first scanning signal provided by the first scanning line G1.
  • a node N1 is connected to the control node N0;
  • the first initialization circuit 14 is electrically connected to the second light emission control line E2, the first initial voltage terminal I1 and the control node N0 respectively, and is used for the second light emission control signal provided on the second light emission control line E2. Under control, write the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the control node N0;
  • the first light emission control circuit 12 is electrically connected to the second light emission control line E2, the power supply voltage terminal Vd and the second node N2, and is used to control the power supply voltage under the control of the second light emission control signal.
  • the terminal Vd is connected to the second node N2; the power supply voltage terminal Vd is used to provide a power supply voltage VDD;
  • the second light emission control circuit 15 is electrically connected to the first light emission control line E1, the third node N3 and the first pole of the light emitting element 10 respectively, and is used for the first light emission provided by the first light emission control line E1. Under the control of a control signal, controlling the communication between the third node N3 and the first pole of the light emitting element 10;
  • the control end of the driving circuit 11 is electrically connected to the first node N1, the first end of the driving circuit 11 is electrically connected to the second node N2, and the second end of the driving circuit 11 is electrically connected to the third node N3,
  • the drive circuit 11 is configured to control the communication between the second node N2 and the third node N3 under the control of the potential of the first node N3;
  • the second pole of the light emitting element 10 is electrically connected to the first voltage terminal V1.
  • the first voltage terminal V1 may be a low voltage terminal or a ground terminal, but not limited thereto.
  • the light-emitting element 10 may be an organic light-emitting diode, the first pole of the light-emitting element 10 may be an anode, and the second pole of the light-emitting element 10 may be a cathode; but not limited thereto.
  • the first control circuit 13 is directly electrically connected to the first node N1
  • the first initialization circuit 14 is not directly electrically connected to the first node N1, so as to reduce the leakage of the first node N1
  • the path can ensure the stability of the voltage of the first node when working at a low frequency, which is beneficial to improving display quality, improving display uniformity, and reducing flicker (flicker).
  • the display cycle includes an initialization stage set before the data writing stage;
  • the first control circuit 13 controls the connection between the first node N1 and the control node N0 under the control of the first scanning signal, and the first initialization circuit 14 emits light in the second Under the control of the control signal, the first initial voltage Vi1 is controlled to be written into the control node N0, so as to initialize the potential of N1 to Vi1; the first light emission control circuit 12 controls all The power supply voltage terminal Vd is connected to the second node N2 to initialize the potential of the second node N2 to VDD.
  • the pixel circuit described in the embodiment of the present disclosure includes a first control circuit 13, a first initialization circuit 14, and a first light emission control circuit 12.
  • the first control circuit 13 and the first initialization circuit 14 controls to write the first initial voltage Vi1 into the control node N0, so as to initialize the potential of N1 to Vi1;
  • the first light emission control circuit 12 controls the
  • the power supply voltage VDD is written into the first terminal of the driving circuit 11 to provide a bias voltage to the driving transistor in the driving circuit 11, so that the driving transistor remains in a reset state, and the hysteresis of the driving transistor is improved, thereby eliminating afterimages.
  • the hysteresis of the driving transistor will cause the characteristic response of the driving transistor to be sluggish, but in the embodiment of the present disclosure, before the data voltage is written, the gate-source voltage of the driving transistor is quickly reset, which is beneficial to the recovery speed of the driving transistor, so it will Improve the hysteresis of the driving transistor and increase the hysteresis recovery speed.
  • the first light emission control circuit 12 is electrically connected to the second light emission control line E2, and works under the control of the second light emission control signal provided by the second light emission control line E2.
  • the second light emission control circuit 15 is electrically connected to the first light emission control line E1 and works under the control of the first light emission control signal provided by the first light emission control line E1 to ensure normal operation of the light emission phase sequence and display effect.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a compensation control circuit 21 and a data writing circuit 22;
  • the data writing circuit 22 is respectively electrically connected to the second scan line G2, the data line D1 and the second node N2, and is used to write the data on the data line D1 under the control of the second scan signal.
  • the voltage Vdata is written into the second node N2.
  • the pixel circuit shown in FIG. Work under the control of the first scanning signal provided by the line G1, and the data writing circuit 22 works under the control of the second scanning signal provided by the second scanning line G2. Through the cooperation of each scanning signal, the timing of initialization and data writing can be guaranteed. Perform normally to ensure the effect of initialization and threshold voltage compensation.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a second initialization circuit
  • the second initialization circuit is electrically connected to the second scanning line, the second initial voltage terminal and the first electrode of the light-emitting element respectively, and is used for controlling the second scanning signal provided by the second scanning line and writing the second initial voltage provided by the second initial voltage terminal into the first pole of the light emitting element, so as to control the light emitting element not to emit light, and to clear the residual charge of the first pole of the light emitting element.
  • the pixel circuit described in at least one embodiment of the present disclosure may further include an energy storage circuit
  • the first end of the energy storage circuit is electrically connected to the first node, the second end of the energy storage circuit is electrically connected to the power supply voltage end, and the energy storage circuit is used to store electric energy and control the first Potential of a node.
  • the second initialization circuit 31 is electrically connected to the second scanning line G2, the second initial voltage terminal I2 and the first pole of the light emitting element 10 respectively, and is used for the second initialization provided on the second scanning line G2. Under the control of the scanning signal, the second initial voltage Vi2 provided by the second initial voltage terminal I2 is written into the first electrode of the light emitting element 10, so as to control the light emitting element 10 not to emit light and clear the light emitting element 10 The residual charge of the first pole of ;
  • the first end of the energy storage circuit 32 is electrically connected to the first node N1
  • the second end of the energy storage circuit 32 is electrically connected to the power supply voltage terminal Vd
  • the energy storage circuit 32 is used to store electric energy And control the potential of the first node N1.
  • the first initial voltage terminal I1 and the second initial voltage terminal I2 may be different initial voltage terminals, or may be the same initial voltage terminal.
  • the number of voltage terminals used can be reduced to save space.
  • the display cycle also includes a data writing phase and a light emitting phase set after the initialization phase;
  • the second initialization circuit 32 writes the second initial voltage Vi2 into the first pole of the light emitting element 10 under the control of the second scanning signal, so that the light emitting element 10 does not emit light;
  • the data writing circuit 22 writes the data voltage Vdata into the second node N2 under the control of the second scan signal;
  • the compensation control circuit 21 controls the connection between the third node N3 and the control node N0 under the control of the first scan signal.
  • the first control circuit 13 controls the communication between the first node N1 and the control node N0 under the control of the first scan signal, so as to control the communication between the first node N1 and the third node N3 ;
  • the second initialization circuit 31 writes the second initial voltage Vi2 into the first pole of the light emitting element 10, so as to control the light emitting element 10 not to emit light;
  • the drive circuit 11 controls the connection between the second node N2 and the third node N3 under the control of the potential of the first node N1, so as to use the data voltage Vdata as energy storage
  • the circuit 32 is charged to change the potential of the first node N1 until the driving circuit 11 disconnects the connection between the second node N2 and the third node N3, at this time, the potential of N1 is Vdata+Vth, Vth is the threshold voltage of the driving transistor in the driving circuit 11;
  • the first light-emitting control circuit 12 controls the connection between the power supply voltage terminal Vd and the second node N2 under the control of the second light-emitting control signal; the second light-emitting control circuit 15 Under the control of the first light emission control signal, the connection between the third node N3 and the first pole of the light emitting element 10 is controlled; the driving circuit 11 drives the light emitting element 10 to emit light.
  • the transistors included in the first light emission control circuit, the transistors included in the second light emission control circuit, and the transistors included in the first initialization circuit are all p-type transistors, and the The first light emission control signal and the second light emission control signal are provided by the same light emission control signal generation circuit, the first light emission control signal is the nth level light emission control signal provided by the light emission control signal generation circuit, and the second light emission control signal is provided by the light emission control signal generation circuit.
  • the light emission control signal is the n+1th stage light emission control signal provided by the light emission control signal generation circuit, where n is a positive integer.
  • the first light emission control signal and the second light emission control signal may be adjacent two-level light emission control signals provided by the same light emission control signal generation circuit.
  • the transistors included in the first control circuit, the transistors included in the data writing circuit, and the transistors included in the compensation control circuit are all p-type transistors, and the first scan signal and The second scanning signal is provided by the same scanning signal generating circuit;
  • the first scan signal is the mth level scan signal provided by the scan signal generation circuit
  • the second scan signal is the m+1st level scan signal provided by the scan signal generation circuit
  • m is a positive integer.
  • the first scan signal and the second scan signal may be adjacent two-level scan signals provided by the same scan signal generation circuit.
  • the first control circuit includes a first transistor, and the first initialization circuit includes a second transistor;
  • the control electrode of the first transistor is electrically connected to the first scan line, the first electrode of the first transistor is electrically connected to the control node, and the second electrode of the first transistor is electrically connected to the first node. electrical connection;
  • the first transistor is a double-gate transistor; or, the first transistor is an oxide transistor.
  • the leakage current of the double-gate transistor and the leakage current of the oxide transistor are low, so at least one embodiment of the present disclosure can set the transistor in the first control circuit as a double-gate transistor or an oxide thin film transistor to achieve low leakage and ensure driving The stability of the potential of the control terminal of the circuit; but not limited thereto.
  • the first light emission control circuit includes a third transistor, and the second light emission control circuit includes a fourth transistor;
  • the control electrode of the third transistor is electrically connected to the second light-emitting control line, the first electrode of the third transistor is electrically connected to the power supply voltage terminal, and the second electrode of the third transistor is electrically connected to the first light emitting control line.
  • the control electrode of the fourth transistor is electrically connected to the first light-emitting control line, the first electrode of the fourth transistor is electrically connected to the third node, and the second electrode of the fourth transistor is electrically connected to the light-emitting
  • the first poles of the elements are electrically connected.
  • the compensation control circuit includes a fifth transistor, and the data writing circuit includes a sixth transistor;
  • the control electrode of the fifth transistor is electrically connected to the first scanning line, the first electrode of the fifth transistor is electrically connected to the control node, and the second electrode of the fifth transistor is electrically connected to the third node. electrical connection;
  • the control electrode of the sixth transistor is electrically connected to the second scan line, the first electrode of the sixth transistor is electrically connected to the data line, and the second electrode of the sixth transistor is electrically connected to the second node. electrical connection.
  • the second initialization circuit includes a seventh transistor
  • the control electrode of the seventh transistor is electrically connected to the second scanning line, the first electrode of the seventh transistor is electrically connected to the second initial voltage terminal, and the second electrode of the seventh transistor is electrically connected to the The first poles of the light emitting elements are electrically connected.
  • the energy storage circuit includes a storage capacitor
  • the drive circuit includes a drive transistor
  • a first end of the storage capacitor is electrically connected to the first node, and a second end of the storage capacitor is electrically connected to the power supply voltage end.
  • the light-emitting element 10 is an organic light-emitting diode O1;
  • the cathode is electrically connected to the low voltage terminal Vs, and the low voltage terminal Vs is used to provide a low voltage VSS;
  • the first control circuit 13 includes a first transistor T1, and the first initialization circuit 14 includes a second transistor T2;
  • the gate of the first transistor T1 is electrically connected to the first scanning line G1, the source of the first transistor T1 is electrically connected to the control node N0, and the drain of the first transistor T1 is electrically connected to the The first node N1 is electrically connected;
  • the gate of the second transistor T2 is electrically connected to the second light emission control line E2, the source of the second transistor T2 is electrically connected to the first initial voltage terminal I1, and the drain of the second transistor T2 The pole is electrically connected to the control node N0;
  • the first light emission control circuit 12 includes a third transistor T3, and the second light emission control circuit 15 includes a fourth transistor T4;
  • the gate of the third transistor T3 is electrically connected to the second light emission control line E2, the source of the third transistor T3 is electrically connected to the power supply voltage terminal Vd, and the drain of the third transistor T3 is electrically connected to the power supply voltage terminal Vd.
  • the second node N3 is electrically connected;
  • the gate of the fourth transistor T4 is electrically connected to the first light emission control line E1, the source of the fourth transistor T4 is electrically connected to the third node N3, and the drain of the fourth transistor T4 is electrically connected to the third node N3.
  • the compensation control circuit 21 includes a fifth transistor T5, and the data writing circuit 22 includes a sixth transistor T6;
  • the gate of the fifth transistor T5 is electrically connected to the first scanning line G1, the source of the fifth transistor T5 is electrically connected to the control node N0, the drain of the fifth transistor T5 is electrically connected to the The third node N3 is electrically connected;
  • the gate of the sixth transistor T6 is electrically connected to the second scanning line G2, the source of the sixth transistor T6 is electrically connected to the data line Data, and the drain of the sixth transistor T6 is electrically connected to the The second node N2 is electrically connected;
  • the second initialization circuit 31 includes a seventh transistor T7;
  • the gate of the seventh transistor T7 is electrically connected to the second scanning line G2, the source of the seventh transistor T7 is electrically connected to the second initial voltage terminal I2, and the drain of the seventh transistor T7 Electrically connected to the anode of O1;
  • the energy storage circuit 32 includes a storage capacitor C1, and the driving circuit 10 includes a driving transistor T0;
  • the gate of the driving transistor T0 is electrically connected to the first node N1, the source of the driving transistor T0 is electrically connected to the second node N2, and the drain of the driving transistor T0 is electrically connected to the third node N3 electrical connection;
  • a first terminal of the storage capacitor C1 is electrically connected to the first node N1, and a second terminal of the storage capacitor C1 is electrically connected to the power supply voltage terminal Vd.
  • all transistors are p-type transistors, and all transistors may be low-temperature polysilicon transistors, but not limited thereto.
  • T1 can be a double-gate transistor to reduce leakage current
  • T2 and T5 can be single-gate transistors to optimize layout (layout) space.
  • T3 and T4 respond to different light-emitting control signals
  • T5 and T6 respond to different scanning signals to ensure initialization, data writing and threshold compensation
  • OLED organic light-emitting diode
  • the display cycle may include an initialization phase t1, a data writing phase t2, and a lighting phase t3 which are set successively;
  • G1 provides a low-voltage signal
  • G2 provides a high-voltage signal
  • E1 provides a high-voltage signal
  • E2 provides a low-voltage signal
  • T1, T2, and T3 are all turned on to write the power supply voltage VDD provided by Vd into N2
  • the first initial voltage Vi1 provided by I1 is written into N1 to reset the gate-source voltage of T0, so that T0 is in a conduction bias state, which can improve the hysteresis effect of T0 and eliminate afterimages;
  • both G1 and G2 provide low voltage signals
  • EM1 and EM2 provide high voltage signals
  • data line D1 provides data voltage Vdata
  • T1, T5 and T6 are all turned on to write Vdata into N2
  • control N0 It is connected with N3, and the connection between N0 and N1 is controlled, so that the connection between N1 and N3 is made;
  • T0 is turned on to charge C1 through Vdata to increase the potential of N1 until the potential of N1 becomes Vdata+Vth, and T0 is turned off;
  • both G1 and G2 provide high-voltage signals
  • E1 and E2 both provide low-voltage signals
  • T0, T3 and T4 are turned on
  • the first interval period t01 between t2 and t3 is to ensure that G1, G2 and G3 share a scanning signal generating circuit, and ensure that E1 and E2 share a light-emitting control signal generating circuit for redundant timing.
  • the pixel driving circuit needs to turn on the driving transistor T0 in the data writing phase, therefore, the voltage difference Vi1-VDD between the first initial voltage Vi1 and the power supply voltage VDD A threshold voltage Vth smaller than T0 is required.
  • the absolute value of VDD can be greater than 1.5 times the absolute value of Vth, for example, the absolute value of VDD can be 1.6 times, 1.8 times, 2 times, etc. setting effect.
  • the voltage value of Vi2 is greater than or equal to -4V and less than or equal to -2V.
  • the display cycle may include a pre-stage t0, an initialization stage t1, a data writing stage t2, and a light-emitting stage t3 that are set successively. ;
  • G1 and G2 provide high-voltage signals
  • E1 provides high-voltage signals
  • E2 provides low-voltage signals
  • T4 is turned off, so that in the initialization stage t1, the operation of resetting the gate-source voltage of T0 is not affected;
  • T1, T5 and T6 are turned off, and T2 and T3 are turned on;
  • G1 provides a low-voltage signal
  • G2 provides a high-voltage signal
  • E1 provides a high-voltage signal
  • E2 provides a low-voltage signal
  • T1, T2, and T3 are all turned on to write the power supply voltage VDD provided by Vd into N2
  • the first initial voltage Vi1 provided by I1 is written into N1 to reset the gate-source voltage of T0, so that T0 is in a conduction bias state, which can improve the hysteresis effect of T0 and eliminate afterimages;
  • both G1 and G2 provide low voltage signals
  • EM1 and EM2 provide high voltage signals
  • data line D1 provides data voltage Vdata
  • T1, T5 and T6 are all turned on to write Vdata into N2
  • control N0 It is connected with N3, and the connection between N0 and N1 is controlled, so that the connection between N1 and N3 is made;
  • T0 is turned on to charge C1 through Vdata to increase the potential of N1 until the potential of N1 becomes Vdata+Vth, and T0 is turned off;
  • both G1 and G2 provide high-voltage signals
  • E1 and E2 both provide low-voltage signals
  • T0, T3 and T4 are turned on
  • the pre-stage t0 is adjacent to the initialization stage t1.
  • the first light emission control signal provided by E1 and the second light emission control signal provided by E2 may be light emission control signals provided by different light emission control signal generating circuits;
  • the first scanning signal provided by G1 and the second scanning signal provided by G2 can provide adjacent two-level scanning signals for the same scanning signal generating circuit, thereby reducing the number of scanning signal generating circuits used in the display device, simplifying the structure, and saving costs .
  • the first control circuit 13 includes a first transistor T1, and the first initialization circuit 14 includes a second transistor T2;
  • the gate of the first transistor T1 is electrically connected to the first scanning line G1, the source of the first transistor T1 is electrically connected to the control node N0, and the drain of the first transistor T1 is electrically connected to the The first node N1 is electrically connected;
  • the gate of the second transistor T2 is electrically connected to the second light emission control line E2, the source of the second transistor T2 is electrically connected to the first initial voltage terminal I1, and the drain of the second transistor T2 The pole is electrically connected to the control node N0;
  • the first light emission control circuit 12 includes a third transistor T3, and the second light emission control circuit 15 includes a fourth transistor T4;
  • the gate of the third transistor T3 is electrically connected to the second light emission control line E2, the source of the third transistor T3 is electrically connected to the power supply voltage terminal Vd, and the drain of the third transistor T3 is electrically connected to the power supply voltage terminal Vd.
  • the second node N3 is electrically connected;
  • the compensation control circuit 21 includes a fifth transistor T5, and the data writing circuit 22 includes a sixth transistor T6;
  • the gate of the fifth transistor T5 is electrically connected to the first scanning line G1, the source of the fifth transistor T5 is electrically connected to the control node N0, the drain of the fifth transistor T5 is electrically connected to the The third node N3 is electrically connected;
  • the gate of the sixth transistor T6 is electrically connected to the second scanning line G2, the source of the sixth transistor T6 is electrically connected to the data line Data, and the drain of the sixth transistor T6 is electrically connected to the The second node N2 is electrically connected;
  • the second initialization circuit 31 includes a seventh transistor T7;
  • the gate of the seventh transistor T7 is electrically connected to the second scanning line G2, the source of the seventh transistor T7 is electrically connected to the first initial voltage terminal I1, and the drain of the seventh transistor T7 Electrically connected to the anode of O1;
  • the energy storage circuit 32 includes a storage capacitor C1, and the driving circuit 10 includes a driving transistor T0;
  • the gate of the driving transistor T0 is electrically connected to the first node N1, the source of the driving transistor T0 is electrically connected to the second node N2, and the drain of the driving transistor T0 is electrically connected to the third node N3 electrical connection;
  • a first terminal of the storage capacitor C1 is electrically connected to the first node N1, and a second terminal of the storage capacitor C1 is electrically connected to the power supply voltage terminal Vd.
  • all transistors are p-type transistors, and all transistors may be low-temperature polysilicon transistors, but not limited thereto.
  • the difference between at least one embodiment of the pixel circuit shown in FIG. 7 and at least one embodiment of the pixel circuit shown in FIG. 4 is that: the source of the seventh transistor T7 is electrically connected to the first initial voltage terminal I1, The second initial voltage terminal and the first initial voltage terminal I1 are the same initial voltage terminal.
  • the working process of at least one embodiment of the pixel circuit shown in FIG. 7 may be consistent with the working process of at least one embodiment of the pixel circuit shown in FIG. 4 .
  • the first light-emitting control circuit controls the communication between the power supply terminal and the second node; under the control of the second light-emitting control signal, the first initialization circuit The initial voltage is written into the control node, and the first control circuit controls the communication between the first node and the control node under the control of the first scan signal, so as to write the first initial voltage into the first node.
  • the first control circuit and the first initialization circuit control the writing of the first initial voltage into the control node , to initialize the potential of the first node to the first initial voltage; under the control of the second light emission control signal, the first light emission control circuit controls to write the power supply voltage into the first terminal of the drive circuit, so as to control the drive in the drive circuit
  • the transistor provides a bias voltage to keep the driving transistor in a reset state, improving the hysteresis of the driving transistor, thereby eliminating afterimages.
  • the pixel circuit further includes a compensation control circuit, a data writing circuit, and an energy storage circuit;
  • the display cycle further includes a data writing phase and a light emitting phase set after the initialization phase;
  • the drive method also includes:
  • the data writing circuit writes the data voltage into the second node under the control of the second scanning signal, and the compensation control circuit controls the communication between the third node and the control node under the control of the first scanning signal. ;
  • the first light-emitting control circuit controls the connection between the power supply voltage terminal and the first end of the drive circuit under the control of the second light-emitting control signal
  • the second light-emitting control circuit controls the The second end of the driving circuit communicates with the first pole of the light emitting element, and the driving circuit drives the light emitting element to emit light.
  • the pixel circuit described in at least one embodiment of the present disclosure may further include a compensation control circuit, a data writing circuit and an energy storage circuit, the data writing circuit controls data voltage writing, and the compensation control circuit controls threshold voltage compensation.
  • the second initializing circuit writes a second initial voltage into the first pole of the light emitting element, so that the light emitting element does not emit light, and eliminates the residual charge of the first pole of the light emitting element.
  • the second light emission control circuit controls the second terminal of the driving circuit to interrupt the first electrode of the light emitting element under the control of the first light emission control signal. open.
  • the second light emitting control circuit controls the disconnection between the second terminal of the driving circuit and the first pole of the light emitting element, so that in the initializing stage, the The gate-to-source voltage of the drive transistor is reset and the operation is not affected.
  • the display device described in the embodiment of the present disclosure includes the above-mentioned pixel circuit.
  • the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.

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Abstract

一种像素电路、驱动方法和显示装置。像素电路包括发光元件（10）、驱动电路（11）、第一发光控制电路（12）、第一控制电路（13）、第一初始化电路（14）和第二发光控制电路（15）。第一控制电路（13）在第一扫描信号的控制下，控制第一节点（N1）与控制节点（N0）之间连通；第一初始化电路（14）在第二发光控制信号的控制下，控制将第一初始电压（Vi1）写入控制节点；第一发光控制电路（12）在第二发光控制信号的控制下，控制电源电压端（Vd）与第二节点（N2）之间连通。

Description

像素电路、驱动方法和显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种像素电路、驱动方法和显示装置。
背景技术
相关技术中，像素驱动电路中驱动晶体管的栅极和源极之间存在寄生电容，像素驱动电路在复位阶段，驱动晶体管的栅极电压被初始化到初始电压，在上述寄生电容耦合作用下，驱动晶体管的源极电压也相应发生变化。复位阶段对不同灰阶复位时，驱动晶体管的栅极电压的变化量不同，从而驱动晶体管的源极电压的变化量也不同，进而导致复位阶段完成后驱动晶体管的源极电压不同，驱动晶体管的栅源电压Vgs也不同。同时由于驱动晶体管的栅源电压Vgs会影响其阈值电压，从而显示面板会发生残像问题。
发明内容
在一个方面中，本公开实施例提供了一种像素电路，包括发光元件、驱动电路、第一发光控制电路、第一控制电路、第一初始化电路和第二发光控制电路，其中，
所述第一控制电路分别与第一扫描线、第一节点和控制节点电连接，用于在所述第一扫描线提供的第一扫描信号的控制下，控制所述第一节点与所述控制节点之间连通；
所述第一初始化电路分别与第二发光控制线、第一初始电压端和所述控制节点电连接，用于在所述第二发光控制线提供的第二发光控制信号的控制下，控制将第一初始电压端提供的第一初始电压写入所述控制节点；
所述第一发光控制电路分别与所述第二发光控制线、电源电压端和第二节点电连接，用于在所述第二发光控制信号的控制下，控制所述电源电压端与所述第二节点之间连通；
所述第二发光控制电路分别与第一发光控制线、第三节点和所述发光元 件的第一极电连接，用于在所述第一发光控制线提供的第一发光控制信号的控制下，控制所述第三节点与所述发光元件的第一极之间连通；
所述驱动电路的控制端与第一节点电连接，所述驱动电路的第一端与第二节点电连接，所述驱动电路的第二端与第三节点电连接，所述驱动电路用于在所述第一节点的电位的控制下，控制所述第二节点与所述第三节点之间连通；
所述发光元件的第二极与第一电压端电连接。
可选的，本公开至少一实施例所述的像素电路还包括补偿控制电路和数据写入电路；
所述补偿控制电路分别与第一扫描线、所述控制节点和所述第三节点电连接，用于在所述第一扫描线提供的第一扫描信号的控制下，控制所述控制节点与所述第三节点之间连通；
所述数据写入电路分别与第二扫描线、数据线和所述第二节点电连接，用于在所述第二扫描信号的控制下，将所述数据线上的数据电压写入所述第二节点。
可选的，本公开至少一实施例所述的像素电路还包括第二初始化电路；
所述第二初始化电路分别与所述第二扫描线、第二初始电压端和所述发光元件的第一极电连接，用于在所述第二扫描线提供的第二扫描信号的控制下，将所述第二初始电压端提供的第二初始电压写入所述发光元件的第一极。
可选的，本公开至少一实施例所述的像素电路还包括储能电路；
所述储能电路的第一端与所述第一节点电连接，所述储能电路的第二端与所述电源电压端电连接，所述储能电路用于储存电能并控制所述第一节点的电位。
可选的，所述第一发光控制电路包括的晶体管、所述第二发光控制电路包括的晶体管，以及，所述第一初始化电路包括的晶体管都为p型晶体管，所述第一发光控制信号与所述第二发光控制信号由同一发光控制信号生成电路提供，所述第一发光控制信号为所述发光控制信号生成电路提供的第n级发光控制信号，所述第二发光控制信号为所述发光控制信号生成电路提供的第n+1级发光控制信号，n为正整数。
可选的，所述第一控制电路包括的晶体管、所述数据写入电路包括的晶体管和所述补偿控制电路包括的晶体管都为p型晶体管，所述第一扫描信号和所述第二扫描信号由同一扫描信号生成电路提供；
所述第一扫描信号为所述扫描信号生成电路提供的第m级扫描信号，所述第二扫描信号为所述扫描信号生成电路提供的第m+1级扫描信号，m为正整数。
可选的，所述第一控制电路包括第一晶体管，所述第一初始化电路包括第二晶体管；
所述第一晶体管的控制极与所述第一扫描线电连接，所述第一晶体管的第一极与所述控制节点电连接，所述第一晶体管的第二极与所述第一节点电连接；
所述第二晶体管的控制极与所述第二发光控制线电连接，所述第二晶体管的第一极与所述第一初始电压端电连接，所述第二晶体管的第二极与所述控制节点电连接。
可选的，所述第一晶体管为双栅晶体管；或者，所述第一晶体管为氧化物晶体管。
可选的，所述第一发光控制电路包括第三晶体管，所述第二发光控制电路包括第四晶体管；
所述第三晶体管的控制极与所述第二发光控制线电连接，所述第三晶体管的第一极与所述电源电压端电连接，所述第三晶体管的第二极与所述第二节点电连接；
所述第四晶体管的控制极与所述第一发光控制线电连接，所述第四晶体管的第一极与所述第三节点电连接，所述第四晶体管的第二极与所述发光元件的第一极电连接。
可选的，所述补偿控制电路包括第五晶体管，所述数据写入电路包括第六晶体管；
所述第五晶体管的控制极与所述第一扫描线电连接，所述第五晶体管的第一极与所述控制节点电连接，所述第五晶体管的第二极与所述第三节点电连接；
所述第六晶体管的控制极与所述第二扫描线电连接，所述第六晶体管的第一极与所述数据线电连接，所述第六晶体管的第二极与所述第二节点电连接。
可选的，所述第二初始化电路包括第七晶体管；
所述第七晶体管的控制极与所述第二扫描线电连接，所述第七晶体管的第一极与所述第二初始电压端电连接，所述第七晶体管的第二极与所述发光元件的第一极电连接。
可选的，所述储能电路包括存储电容，所述驱动电路包括驱动晶体管；
所述驱动晶体管的控制极与所述第一节点电连接，所述驱动晶体管的第一极与所述第二节点电连接，所述驱动晶体管的第二极与所述第三节点电连接；
所述存储电容的第一端与所述第一节点电连接，所述存储电容的第二端与所述电源电压端电连接。
在第二个方面中，本公开实施例还提供一种驱动方法，应用于上述的像素电路，显示周期包括初始化阶段；所述驱动方法包括：
在所述初始化阶段，第一发光控制电路在第二发光控制信号的控制下，控制电源电源端与第二节点之间连通；第一初始化电路在第二发光控制信号的控制下，将第一初始电压写入控制节点，第一控制电路在第一扫描信号的控制下，控制第一节点与控制节点之间连通，以将所述第一初始电压写入所述第一节点。
可选的，所述像素电路还包括补偿控制电路、数据写入电路和储能电路；显示周期还包括设置于所述初始化阶段之后的数据写入阶段和发光阶段；所述驱动方法还包括：
在数据写入阶段，数据写入电路在第二扫描信号的控制下，将数据电压写入第二节点，补偿控制电路在第一扫描信号的控制下，控制第三节点与控制节点之间连通；
在所述数据写入阶段开始时，驱动电路在第一节点的电位的控制下，控制第二节点与第三节点之间连通，以通过数据电压为储能电路充电，改变第一节点的电位，直至所述驱动电路关断；
在发光阶段，第一发光控制电路在第二发光控制信号的控制下，控制电源电压端与驱动电路的第一端之间连通，第二发光控制电路在第一发光控制信号的控制下，控制驱动电路的第二端与发光元件的第一极之间连通，驱动电路驱动发光元件发光。
可选的，所述像素电路还包括第二初始化电路，所述驱动方法还包括：
在数据写入阶段，所述第二初始化电路将第二初始电压写入发光元件的第一极，以使得所述发光元件不发光。
可选的，所述显示周期还包括设置于所述初始化阶段之前，并与所述初始化阶段紧邻的前置阶段，所述驱动方法还包括：
在所述前置阶段、所述初始化阶段和所述数据写入阶段，所述第二发光控制电路在所述第一发光控制信号的控制下，控制驱动电路的第二端与发光元件的第一极之间断开。
在第三个方面中，本公开实施例还提供一种显示装置，包括上述的像素电路。
附图说明
图1是本公开实施例所述的像素电路的结构图；
图2是本公开至少一实施例所述的像素电路的结构图；
图3是本公开至少一实施例所述的像素电路的结构图；
图4是本公开至少一实施例所述的像素电路的电路图；
图5是本公开如图4所示的像素电路的至少一实施例的工作时序图；
图6是本公开如图4所示的像素电路的至少一实施例的另一工作时序图；
图7是本公开至少一实施例所述的像素电路的电路图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为三极管、薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除控制极之外的两极，将其中一极称为第一极，另一极称为第二极。
在实际操作时，当所述晶体管为薄膜晶体管或场效应管时，所述第一极可以为漏极，所述第二极可以为源极；或者，所述第一极可以为源极，所述第二极可以为漏极。
如图1所示，本公开实施例所述的像素电路包括发光元件10、驱动电路11、第一发光控制电路12、第一控制电路13、第一初始化电路14和第二发光控制电路15，其中，
所述第一控制电路13分别与第一扫描线G1、第一节点N1和控制节点N0电连接，用于在所述第一扫描线G1提供的第一扫描信号的控制下，控制所述第一节点N1与所述控制节点N0之间连通；
所述第一初始化电路14分别与第二发光控制线E2、第一初始电压端I1和所述控制节点N0电连接，用于在所述第二发光控制线E2提供的第二发光控制信号的控制下，控制将第一初始电压端I1提供的第一初始电压Vi1写入所述控制节点N0；
所述第一发光控制电路12分别与所述第二发光控制线E2、电源电压端Vd和第二节点N2电连接，用于在所述第二发光控制信号的控制下，控制所述电源电压端Vd与所述第二节点N2之间连通；所述电源电压端Vd用于提供电源电压VDD；
所述第二发光控制电路15分别与第一发光控制线E1、第三节点N3和所述发光元件10的第一极电连接，用于在所述第一发光控制线E1提供的第一发光控制信号的控制下，控制所述第三节点N3与所述发光元件10的第一极之间连通；
所述驱动电路11的控制端与第一节点N1电连接，所述驱动电路11的第一端与第二节点N2电连接，所述驱动电路11的第二端与第三节点N3电连接，所述驱动电路11用于在所述第一节点N3的电位的控制下，控制所述第二节点N2与所述第三节点N3之间连通；
所述发光元件10的第二极与第一电压端V1电连接。
在本公开至少一实施例中，所述第一电压端V1可以为低电压端或地端，但不以此为限。
在具体实施时，所述发光元件10可以为有机发光二极管，所述发光元件10的第一极可以为阳极，所述发光元件10的第二极可以为阴极；但不以此为限。
在本公开实施例所述的像素电路中，第一控制电路13与直接与第一节点N1电连接，第一初始化电路14不直接与第一节点N1电连接，以减少第一节点N1的漏电路径，以能够在低频工作时保证第一节点的电压的稳定性，利于提升显示质量，提升显示均一性，减轻Flicker(闪烁)。
本公开如图1所示的像素电路的实施例在工作时，显示周期包括设置于数据写入阶段之前的初始化阶段；
在所述初始化阶段，所述第一控制电路13在第一扫描信号的控制下，控制所述第一节点N1与所述控制节点N0之间连通，所述第一初始化电路14在第二发光控制信号的控制下，控制将第一初始电压Vi1写入所述控制节点N0，以将N1的电位初始化为Vi1；所述第一发光控制电路12在第二发光控制信号的控制下，控制所述电源电压端Vd与所述第二节点N2之间连通，以将第二节点N2的电位初始化为VDD。
本公开实施例所述的像素电路包括第一控制电路13、第一初始化电路14和第一发光控制电路12，在数据电压写入驱动电路11的第一端之前，所述第一控制电路13和所述第一初始化电路14控制将第一初始电压Vi1写入所述控制节点N0，以将N1的电位初始化为Vi1；第一发光控制电路12在第二发光控制信号的控制下，控制将电源电压VDD写入驱动电路11的第一端，以对驱动电路11中的驱动晶体管提供偏压，使得驱动晶体管保持复位状态，改善驱动晶体管的迟滞，从而消除残像。
在具体实施时，驱动晶体管的迟滞会导致驱动晶体管的特性反应较迟钝，而本公开实施例在数据电压写入之前，快速复位驱动晶体管的栅源电压，利于驱动晶体管的恢复速度加快，因此会改善驱动晶体管的迟滞现象，提升迟滞恢复速度。
并且，在本公开实施例所述的像素电路中，第一发光控制电路12与第二 发光控制线E2电连接，在第二发光控制线E2提供的第二发光控制信号的控制下工作，第二发光控制电路15与第一发光控制线E1电连接，在第一发光控制线E1提供的第一发光控制信号的控制下工作，保证发光阶段时序正常运行，确保显示效果。
如图2所示，在图1所示的像素电路的实施例的基础上，本公开至少一实施例所述的像素电路还包括补偿控制电路21和数据写入电路22；
所述补偿控制电路21分别与第一扫描线G1、所述控制节点N0和所述第三节点N3电连接，用于在所述第一扫描线G1提供的第一扫描信号的控制下，控制所述控制节点N0与所述第三节点N3之间连通；
所述数据写入电路22分别与第二扫描线G2、数据线D1和所述第二节点N2电连接，用于在所述第二扫描信号的控制下，将所述数据线D1上的数据电压Vdata写入所述第二节点N2。
在本公开如图2所示的像素电路的至少一实施例中，所述第一控制电路13在第一扫描线G1提供的第一扫描信号的控制下工作，补偿控制电路21在第一扫描线G1提供的第一扫描信号的控制下工作，数据写入电路22在第二扫描线G2提供的第二扫描信号的控制下工作，通过各扫描信号的配合，可以保证初始化和数据写入时序正常进行，保证初始化及阈值电压补偿效果。
可选的，本公开至少一实施例所述的像素电路还包括第二初始化电路；
所述第二初始化电路分别与所述第二扫描线、第二初始电压端和所述发光元件的第一极电连接，用于在所述第二扫描线提供的第二扫描信号的控制下，将所述第二初始电压端提供的第二初始电压写入所述发光元件的第一极，以控制所述发光元件不发光，清除发光元件的第一极残留的电荷。
本公开至少一实施例所述的像素电路还可以包括储能电路；
所述储能电路的第一端与所述第一节点电连接，所述储能电路的第二端与所述电源电压端电连接，所述储能电路用于储存电能并控制所述第一节点的电位。
如图3所示，在图2所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还包括第二初始化电路31和储能电路32；
所述第二初始化电路31分别与所述第二扫描线G2、第二初始电压端I2 和所述发光元件10的第一极电连接，用于在所述第二扫描线G2提供的第二扫描信号的控制下，将所述第二初始电压端I2提供的第二初始电压Vi2写入所述发光元件10的第一极，以控制所述发光元件10不发光，清除所述发光元件10的第一极残留的电荷；
所述储能电路32的第一端与所述第一节点N1电连接，所述储能电路32的第二端与所述电源电压端Vd电连接，所述储能电路32用于储存电能并控制所述第一节点N1的电位。
在本公开至少一实施例中，所述第一初始电压端I1和所述第二初始电压端I2可以为不同的初始电压端，也可以为同一初始电压端。
当所述第一初始电压端I1和所述第二初始电压端I2为同一初始电压端时，可以减少采用的电压端子的个数，节省空间。
本公开如图3所示的像素电路的至少一实施例在工作时，显示周期还包括设置于所述初始化阶段之后的数据写入阶段和发光阶段；
在所述数据写入阶段，第二初始化电路32在所述第二扫描信号的控制下，将第二初始电压Vi2写入发光元件10的第一极，以使得发光元件10不发光；所述数据写入电路22在第二扫描信号的控制下，将数据电压Vdata写入第二节点N2；所述补偿控制电路21在第一扫描信号的控制下，控制第三节点N3与控制节点N0之间连通；所述第一控制电路13在第一扫描信号的控制下，控制所述第一节点N1与所述控制节点N0之间连通，以控制第一节点N1与第三节点N3之间连通；所述第二初始化电路31在第二扫描信号的控制下，将第二初始电压Vi2写入所述发光元件10的第一极，以控制所述发光元件10不发光；
在所述数据写入阶段开始时，驱动电路11在第一节点N1的电位的控制下，控制所述第二节点N2与所述第三节点N3之间连通，以通过数据电压Vdata为储能电路32充电，以改变所述第一节点N1的电位，直至所述驱动电路11断开所述第二节点N2与所述第三节点N3的连接，此时，N1的电位为Vdata+Vth，Vth为驱动电路11中的驱动晶体管的阈值电压；
在发光阶段，所述第一发光控制电路12在第二发光控制信号的控制下，控制所述电源电压端Vd与所述第二节点N2之间连通；所述第二发光控制电 路15在所述第一发光控制信号的控制下，控制所述第三节点N3与所述发光元件10的第一极之间连通；驱动电路11驱动发光元件10发光。
在本公开至少一实施例中，所述第一发光控制电路包括的晶体管、所述第二发光控制电路包括的晶体管，以及，所述第一初始化电路包括的晶体管都为p型晶体管，所述第一发光控制信号与所述第二发光控制信号由同一发光控制信号生成电路提供，所述第一发光控制信号为所述发光控制信号生成电路提供的第n级发光控制信号，所述第二发光控制信号为所述发光控制信号生成电路提供的第n+1级发光控制信号，n为正整数。
在具体实施时，第一发光控制信号和第二发光控制信号可以为同一发光控制信号生成电路提供的相邻两级发光控制信号。
在本公开至少一实施例中，所述第一控制电路包括的晶体管、所述数据写入电路包括的晶体管和所述补偿控制电路包括的晶体管都为p型晶体管，所述第一扫描信号和所述第二扫描信号由同一扫描信号生成电路提供；
所述第一扫描信号为所述扫描信号生成电路提供的第m级扫描信号，所述第二扫描信号为所述扫描信号生成电路提供的第m+1级扫描信号，m为正整数。
在具体实施时，所述第一扫描信号和所述第二扫描信号可以为同一扫描信号生成电路提供的相邻两级扫描信号。
可选的，所述第一控制电路包括第一晶体管，所述第一初始化电路包括第二晶体管；
所述第一晶体管的控制极与所述第一扫描线电连接，所述第一晶体管的第一极与所述控制节点电连接，所述第一晶体管的第二极与所述第一节点电连接；
所述第二晶体管的控制极与所述第二发光控制线电连接，所述第二晶体管的第一极与所述第一初始电压端电连接，所述第二晶体管的第二极与所述控制节点电连接。
可选的，所述第一晶体管为双栅晶体管；或者，所述第一晶体管为氧化物晶体管。
双栅晶体管的漏电流和氧化物晶体管的漏电流低，因此本公开至少一实 施例可以将所述第一控制电路中的晶体管设置为双栅晶体管或氧化物薄膜晶体管，实现低漏电，保证驱动电路的控制端的电位的稳定性；但不以此为限。
可选的，所述第一发光控制电路包括第三晶体管，所述第二发光控制电路包括第四晶体管；
所述第三晶体管的控制极与所述第二发光控制线电连接，所述第三晶体管的第一极与所述电源电压端电连接，所述第三晶体管的第二极与所述第二节点电连接；
所述第四晶体管的控制极与所述第一发光控制线电连接，所述第四晶体管的第一极与所述第三节点电连接，所述第四晶体管的第二极与所述发光元件的第一极电连接。
可选的，所述补偿控制电路包括第五晶体管，所述数据写入电路包括第六晶体管；
所述第五晶体管的控制极与所述第一扫描线电连接，所述第五晶体管的第一极与所述控制节点电连接，所述第五晶体管的第二极与所述第三节点电连接；
所述第六晶体管的控制极与所述第二扫描线电连接，所述第六晶体管的第一极与所述数据线电连接，所述第六晶体管的第二极与所述第二节点电连接。
可选的，所述第二初始化电路包括第七晶体管；
所述第七晶体管的控制极与所述第二扫描线电连接，所述第七晶体管的第一极与所述第二初始电压端电连接，所述第七晶体管的第二极与所述发光元件的第一极电连接。
可选的，所述储能电路包括存储电容，所述驱动电路包括驱动晶体管；
所述驱动晶体管的控制极与所述第一节点电连接，所述驱动晶体管的第一极与所述第二节点电连接，所述驱动晶体管的第二极与所述第三节点电连接；
所述存储电容的第一端与所述第一节点电连接，所述存储电容的第二端与所述电源电压端电连接。
如图4所示，在图3所示的像素电路的至少一实施例的基础上，在本公 开至少一实施例所述的像素电路中，所述发光元件10为有机发光二极管O1；O1的阴极与低电压端Vs电连接，所述低电压端Vs用于提供低电压VSS；
所述第一控制电路13包括第一晶体管T1，所述第一初始化电路14包括第二晶体管T2；
所述第一晶体管T1的栅极与所述第一扫描线G1电连接，所述第一晶体管T1的源极与所述控制节点N0电连接，所述第一晶体管T1的漏极与所述第一节点N1电连接；
所述第二晶体管T2的栅极与所述第二发光控制线E2电连接，所述第二晶体管T2的源极与所述第一初始电压端I1电连接，所述第二晶体管T2的漏极与所述控制节点N0电连接；
所述第一发光控制电路12包括第三晶体管T3，所述第二发光控制电路15包括第四晶体管T4；
所述第三晶体管T3的栅极与所述第二发光控制线E2电连接，所述第三晶体管T3的源极与所述电源电压端Vd电连接，所述第三晶体管T3的漏极与所述第二节点N3电连接；
所述第四晶体管T4的栅极与所述第一发光控制线E1电连接，所述第四晶体管T4的源极与所述第三节点N3电连接，所述第四晶体管T4的漏极与O1的阳极电连接；
所述补偿控制电路21包括第五晶体管T5，所述数据写入电路22包括第六晶体管T6；
所述第五晶体管T5的栅极与所述第一扫描线G1电连接，所述第五晶体管T5的源极与所述控制节点N0电连接，所述第五晶体管T5的漏极与所述第三节点N3电连接；
所述第六晶体管T6的栅极与所述第二扫描线G2电连接，所述第六晶体管T6的源极与所述数据线Data电连接，所述第六晶体管T6的漏极与所述第二节点N2电连接；
所述第二初始化电路31包括第七晶体管T7；
所述第七晶体管T7的栅极与所述第二扫描线G2电连接，所述第七晶体管T7的源极与所述第二初始电压端I2电连接，所述第七晶体管T7的漏极与 O1的阳极电连接；
所述储能电路32包括存储电容C1，所述驱动电路10包括驱动晶体管T0；
所述驱动晶体管T0的栅极与所述第一节点N1电连接，所述驱动晶体管T0的源极与所述第二节点N2电连接，所述驱动晶体管T0的漏极与所述第三节点N3电连接；
所述存储电容C1的第一端与所述第一节点N1电连接，所述存储电容C1的第二端与所述电源电压端Vd电连接。
在图4所示的像素电路的至少一实施例中，所有的晶体管都为p型晶体管，所有的晶体管可以都为低温多晶硅晶体管，但不以此为限。
在图4所示的像素电路的至少一实施例中，T1可以为双栅晶体管，以减少漏电流，T2和T5可以为单栅晶体管，以优化layout(布局)空间。
在图4所示的像素电路的至少一实施例中，T3和T4响应不同的发光控制信号，T5和T6响应不同的扫描信号，保证初始化、数据写入及阈值补偿、OLED(有机发光二极管)发光三个时序正常进行，从而确保阈值电压补偿及显示效果。
如图5所示，本公开如图4所示的像素电路的至少一实施例在工作时，显示周期可以包括先后设置的初始化阶段t1、数据写入阶段t2和发光阶段t3；
在初始化阶段t1，G1提供低电压信号，G2提供高电压信号，E1提供高电压信号，E2提供低电压信号，T1、T2和T3都打开，以将Vd提供的电源电压VDD写入N2，将I1提供的第一初始电压Vi1写入N1，以对T0的栅源电压进行复位，使得T0处于导通偏置状态，可以改善T0的迟滞效应从而消除残像；
在数据写入阶段t2，G1和G2都提供低电压信号，EM1和EM2提供高电压信号，数据线D1提供数据电压Vdata，T1、T5和T6都打开，以将Vdata写入N2，并控制N0和N3之间连通，控制N0与N1之间连通，从而使得N1与N3之间连通；
在数据写入阶段t2开始时，T0导通，以通过Vdata为C1充电，以提升N1的电位，直至N1的电位变为Vdata+Vth，T0关断；
在发光阶段t3，G1和G2都提供高电压信号，E1和E2都提供低电压信号，T0、T3和T4打开，T0驱动O1发光。
如图5所示，G1提供的第一扫描信号和G2提供的第二扫描信号可以为同一扫描信号生成电路提供相邻两级扫描信号，E1提供的第一发光控制信号和E2提供的第二发光控制信号可以为同一发光控制信号生成电路提供的相邻两级发光控制信号，从而可以减少显示装置采用的扫描信号生成电路的个数，以及，显示装置采用的发光控制信号生成电路的个数，简化结构，节省成本。
在图5中，t2与t3之间的第一间隔时间段t01，为保证G1、G2和G3共用一扫描信号生成电路，保证E1和E2共用一发光控制信号生成电路的冗余时序。
如图4、图5所示，所述像素驱动电路的至少一实施例需要在数据写入阶段导通驱动晶体管T0，因此，第一初始电压Vi1与电源电压VDD之间的电压差Vi1-VDD需要小于T0的阈值电压Vth。其中，VDD的绝对值可以大于Vth的绝对值的1.5倍，例如，VDD的绝对值可以为Vth的绝对值的1.6倍、1.8倍、2倍等，以保证在较短时间内能够快速达到偏置效果。
可选的，Vi1的电压值大于或等于-4V而小于或等于-2V，VDD的电压值大于或等于4V而小于或等于5.5V，Vth大于或等于-3.5V而小于或等于-2V。
在本公开至少一实施例中，Vi2的电压值大于或等于-4V而小于或等于-2V。
如图6所示，本公开如图4所示的像素电路的至少一实施例在工作时，显示周期可以包括先后设置的前置阶段t0、初始化阶段t1、数据写入阶段t2和发光阶段t3；
在前置阶段t0，G1和G2提供高电压信号，E1提供高电压信号，E2提供低电压信号，T4关断，使得在初始化阶段t1，对T0的栅源电压进行复位的操作不受影响；
在前置阶段t0，T1、T5和T6关断，T2和T3打开；
在初始化阶段t1，G1提供低电压信号，G2提供高电压信号，E1提供高电压信号，E2提供低电压信号，T1、T2和T3都打开，以将Vd提供的电源 电压VDD写入N2，将I1提供的第一初始电压Vi1写入N1，以对T0的栅源电压进行复位，使得T0处于导通偏置状态，可以改善T0的迟滞效应从而消除残像；
在数据写入阶段t2，G1和G2都提供低电压信号，EM1和EM2提供高电压信号，数据线D1提供数据电压Vdata，T1、T5和T6都打开，以将Vdata写入N2，并控制N0和N3之间连通，控制N0与N1之间连通，从而使得N1与N3之间连通；
在数据写入阶段t2开始时，T0导通，以通过Vdata为C1充电，以提升N1的电位，直至N1的电位变为Vdata+Vth，T0关断；
在发光阶段t3，G1和G2都提供高电压信号，E1和E2都提供低电压信号，T0、T3和T4打开，T0驱动O1发光。
如图6所示，所述前置阶段t0与所述初始化阶段t1紧邻。
如图6所示，E1提供的第一发光控制信号和E2提供的第二发光控制信号可以为不同的发光控制信号生成电路提供的发光控制信号；
G1提供的第一扫描信号和G2提供的第二扫描信号可以为同一扫描信号生成电路提供相邻两级扫描信号，从而可以减少显示装置采用的扫描信号生成电路的个数，简化结构，节省成本。
如图7所示，在图3所示的像素电路的至少一实施例的基础上，在本公开至少一实施例所述的像素电路中，所述发光元件10为有机发光二极管O1；O1的阴极与低电压端Vs电连接，所述低电压端Vs用于提供低电压VSS；
所述第一控制电路13包括第一晶体管T1，所述第一初始化电路14包括第二晶体管T2；
所述第一晶体管T1的栅极与所述第一扫描线G1电连接，所述第一晶体管T1的源极与所述控制节点N0电连接，所述第一晶体管T1的漏极与所述第一节点N1电连接；
所述第二晶体管T2的栅极与所述第二发光控制线E2电连接，所述第二晶体管T2的源极与所述第一初始电压端I1电连接，所述第二晶体管T2的漏极与所述控制节点N0电连接；
所述第一发光控制电路12包括第三晶体管T3，所述第二发光控制电路 15包括第四晶体管T4；
所述第三晶体管T3的栅极与所述第二发光控制线E2电连接，所述第三晶体管T3的源极与所述电源电压端Vd电连接，所述第三晶体管T3的漏极与所述第二节点N3电连接；
所述第四晶体管T4的栅极与所述第一发光控制线E1电连接，所述第四晶体管T4的源极与所述第三节点N3电连接，所述第四晶体管T4的漏极与O1的阳极电连接；
所述补偿控制电路21包括第五晶体管T5，所述数据写入电路22包括第六晶体管T6；
所述第五晶体管T5的栅极与所述第一扫描线G1电连接，所述第五晶体管T5的源极与所述控制节点N0电连接，所述第五晶体管T5的漏极与所述第三节点N3电连接；
所述第六晶体管T6的栅极与所述第二扫描线G2电连接，所述第六晶体管T6的源极与所述数据线Data电连接，所述第六晶体管T6的漏极与所述第二节点N2电连接；
所述第二初始化电路31包括第七晶体管T7；
所述第七晶体管T7的栅极与所述第二扫描线G2电连接，所述第七晶体管T7的源极与所述第一初始电压端I1电连接，所述第七晶体管T7的漏极与O1的阳极电连接；
所述储能电路32包括存储电容C1，所述驱动电路10包括驱动晶体管T0；
所述驱动晶体管T0的栅极与所述第一节点N1电连接，所述驱动晶体管T0的源极与所述第二节点N2电连接，所述驱动晶体管T0的漏极与所述第三节点N3电连接；
所述存储电容C1的第一端与所述第一节点N1电连接，所述存储电容C1的第二端与所述电源电压端Vd电连接。
在图7所示的像素电路的至少一实施例中，所有的晶体管都为p型晶体管，所有的晶体管可以都为低温多晶硅晶体管，但不以此为限。
图7所示的像素电路的至少一实施例与图4所示的像素电路的至少一实 施例的区别在于：所述第七晶体管T7的源极与所述第一初始电压端I1电连接，所述第二初始电压端与所述第一初始电压端I1为同一初始电压端。图7所示的像素电路的至少一实施例的工作过程可以与图4所示的像素电路的至少一实施例的工作过程一致。
本公开实施例所述的驱动方法，应用于上述的像素电路，显示周期包括初始化阶段；所述驱动方法包括：
在所述初始化阶段，第一发光控制电路在第二发光控制信号的控制下，控制电源电源端与第二节点之间连通；第一初始化电路在第二发光控制信号的控制下，将第一初始电压写入控制节点，第一控制电路在第一扫描信号的控制下，控制第一节点与控制节点之间连通，以将所述第一初始电压写入所述第一节点。
在本公开实施例所述的驱动方法中，在数据电压写入驱动电路的第一端之前，所述第一控制电路和所述第一初始化电路控制将第一初始电压写入所述控制节点，以将第一节点的电位初始化为第一初始电压；第一发光控制电路在第二发光控制信号的控制下，控制将电源电压写入驱动电路的第一端，以对驱动电路中的驱动晶体管提供偏压，使得驱动晶体管保持复位状态，改善驱动晶体管的迟滞，从而消除残像。
在本公开至少一实施例中，所述像素电路还包括补偿控制电路、数据写入电路和储能电路；显示周期还包括设置于所述初始化阶段之后的数据写入阶段和发光阶段；所述驱动方法还包括：
在数据写入阶段，数据写入电路在第二扫描信号的控制下，将数据电压写入第二节点，补偿控制电路在第一扫描信号的控制下，控制第三节点与控制节点之间连通；
在所述数据写入阶段开始时，驱动电路在第一节点的电位的控制下，控制第二节点与第三节点之间连通，以通过数据电压为储能电路充电，改变第一节点的电位，直至所述驱动电路关断，此时第一节点的电位与驱动电路中的驱动晶体管的阈值电压相关；
在发光阶段，第一发光控制电路在第二发光控制信号的控制下，控制电源电压端与驱动电路的第一端之间连通，第二发光控制电路在第一发光控制 信号的控制下，控制驱动电路的第二端与发光元件的第一极之间连通，驱动电路驱动发光元件发光。
在具体实施时，本公开至少一实施例所述的像素电路还可以补偿控制电路、数据写入电路和储能电路，数据写入电路控制数据电压写入，补偿控制电路控制阈值电压补偿。
可选的，所述像素电路还包括第二初始化电路，本公开至少一实施例所述的驱动方法还包括：
在数据写入阶段，所述第二初始化电路将第二初始电压写入发光元件的第一极，以使得所述发光元件不发光，并消除发光元件的第一极残留的电荷。
可选的，所述显示周期还包括设置于所述初始化阶段之前，并与所述初始化阶段紧邻的前置阶段，本公开至少一实施例所述的驱动方法还包括：
在所述前置阶段、所述初始化阶段和所述数据写入阶段，第二发光控制电路在第一发光控制信号的控制下，控制驱动电路的第二端与发光元件的第一极之间断开。
在所述前置阶段，第二发光控制电路在第一发光控制信号的控制下，控制驱动电路的第二端与发光元件的第一极之间断开，以使得在初始化阶段，对驱动电路中的驱动晶体管的栅源电压进行复位的操作不受影响。
本公开实施例所述的显示装置包括上述的像素电路。
本公开实施例所提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (17)

  1. 一种像素电路，包括发光元件、驱动电路、第一发光控制电路、第一控制电路、第一初始化电路和第二发光控制电路，其中，
    所述第一控制电路分别与第一扫描线、第一节点和控制节点电连接，用于在所述第一扫描线提供的第一扫描信号的控制下，控制所述第一节点与所述控制节点之间连通；
    所述第一初始化电路分别与第二发光控制线、第一初始电压端和所述控制节点电连接，用于在所述第二发光控制线提供的第二发光控制信号的控制下，控制将第一初始电压端提供的第一初始电压写入所述控制节点；
    所述第一发光控制电路分别与所述第二发光控制线、电源电压端和第二节点电连接，用于在所述第二发光控制信号的控制下，控制所述电源电压端与所述第二节点之间连通；
    所述第二发光控制电路分别与第一发光控制线、第三节点和所述发光元件的第一极电连接，用于在所述第一发光控制线提供的第一发光控制信号的控制下，控制所述第三节点与所述发光元件的第一极之间连通；
    所述驱动电路的控制端与第一节点电连接，所述驱动电路的第一端与第二节点电连接，所述驱动电路的第二端与第三节点电连接，所述驱动电路用于在所述第一节点的电位的控制下，控制所述第二节点与所述第三节点之间连通；
    所述发光元件的第二极与第一电压端电连接。
  2. 如权利要求1所述的像素电路，其中，还包括补偿控制电路和数据写入电路；
    所述补偿控制电路分别与第一扫描线、所述控制节点和所述第三节点电连接，用于在所述第一扫描线提供的第一扫描信号的控制下，控制所述控制节点与所述第三节点之间连通；
    所述数据写入电路分别与第二扫描线、数据线和所述第二节点电连接，用于在所述第二扫描信号的控制下，将所述数据线上的数据电压写入所述第二节点。
  3. 如权利要求1或2所述的像素电路，其中，还包括第二初始化电路；
    所述第二初始化电路分别与所述第二扫描线、第二初始电压端和所述发光元件的第一极电连接，用于在所述第二扫描线提供的第二扫描信号的控制下，将所述第二初始电压端提供的第二初始电压写入所述发光元件的第一极。
  4. 如权利要求1或2所述的像素电路，其中，还包括储能电路；
    所述储能电路的第一端与所述第一节点电连接，所述储能电路的第二端与所述电源电压端电连接，所述储能电路用于储存电能并控制所述第一节点的电位。
  5. 如权利要求1所述的像素电路，其中，所述第一发光控制电路包括的晶体管、所述第二发光控制电路包括的晶体管，以及，所述第一初始化电路包括的晶体管都为p型晶体管，所述第一发光控制信号与所述第二发光控制信号由同一发光控制信号生成电路提供，所述第一发光控制信号为所述发光控制信号生成电路提供的第n级发光控制信号，所述第二发光控制信号为所述发光控制信号生成电路提供的第n+1级发光控制信号，n为正整数。
  6. 如权利要求2所述的像素电路，其中，所述第一控制电路包括的晶体管、所述数据写入电路包括的晶体管和所述补偿控制电路包括的晶体管都为p型晶体管，所述第一扫描信号和所述第二扫描信号由同一扫描信号生成电路提供；
    所述第一扫描信号为所述扫描信号生成电路提供的第m级扫描信号，所述第二扫描信号为所述扫描信号生成电路提供的第m+1级扫描信号，m为正整数。
  7. 如权利要求1所述的像素电路，其中，所述第一控制电路包括第一晶体管，所述第一初始化电路包括第二晶体管；
    所述第一晶体管的控制极与所述第一扫描线电连接，所述第一晶体管的第一极与所述控制节点电连接，所述第一晶体管的第二极与所述第一节点电连接；
    所述第二晶体管的控制极与所述第二发光控制线电连接，所述第二晶体管的第一极与所述第一初始电压端电连接，所述第二晶体管的第二极与所述控制节点电连接。
  8. 如权利要求7所述的像素电路，其中，所述第一晶体管为双栅晶体管；或者，所述第一晶体管为氧化物晶体管。
  9. 如权利要求1所述的像素电路，其中，所述第一发光控制电路包括第三晶体管，所述第二发光控制电路包括第四晶体管；
    所述第三晶体管的控制极与所述第二发光控制线电连接，所述第三晶体管的第一极与所述电源电压端电连接，所述第三晶体管的第二极与所述第二节点电连接；
    所述第四晶体管的控制极与所述第一发光控制线电连接，所述第四晶体管的第一极与所述第三节点电连接，所述第四晶体管的第二极与所述发光元件的第一极电连接。
  10. 如权利要求2所述的像素电路，其中，所述补偿控制电路包括第五晶体管，所述数据写入电路包括第六晶体管；
    所述第五晶体管的控制极与所述第一扫描线电连接，所述第五晶体管的第一极与所述控制节点电连接，所述第五晶体管的第二极与所述第三节点电连接；
    所述第六晶体管的控制极与所述第二扫描线电连接，所述第六晶体管的第一极与所述数据线电连接，所述第六晶体管的第二极与所述第二节点电连接。
  11. 如权利要求3所述的像素电路，其中，所述第二初始化电路包括第七晶体管；
    所述第七晶体管的控制极与所述第二扫描线电连接，所述第七晶体管的第一极与所述第二初始电压端电连接，所述第七晶体管的第二极与所述发光元件的第一极电连接。
  12. 如权利要求4所述的像素电路，其中，所述储能电路包括存储电容，所述驱动电路包括驱动晶体管；
    所述驱动晶体管的控制极与所述第一节点电连接，所述驱动晶体管的第一极与所述第二节点电连接，所述驱动晶体管的第二极与所述第三节点电连接；
    所述存储电容的第一端与所述第一节点电连接，所述存储电容的第二端 与所述电源电压端电连接。
  13. 一种驱动方法，应用于如权利要求1至12中任一权利要求所述的像素电路，显示周期包括初始化阶段；所述驱动方法包括：
    在所述初始化阶段，第一发光控制电路在第二发光控制信号的控制下，控制电源电源端与第二节点之间连通；第一初始化电路在第二发光控制信号的控制下，将第一初始电压写入控制节点，第一控制电路在第一扫描信号的控制下，控制第一节点与控制节点之间连通，以将所述第一初始电压写入所述第一节点。
  14. 如权利要求13所述的驱动方法，其中，所述像素电路还包括补偿控制电路、数据写入电路和储能电路；显示周期还包括设置于所述初始化阶段之后的数据写入阶段和发光阶段；所述驱动方法还包括：
    在数据写入阶段，数据写入电路在第二扫描信号的控制下，将数据电压写入第二节点，补偿控制电路在第一扫描信号的控制下，控制第三节点与控制节点之间连通；
    在所述数据写入阶段开始时，驱动电路在第一节点的电位的控制下，控制第二节点与第三节点之间连通，以通过数据电压为储能电路充电，改变第一节点的电位，直至所述驱动电路关断；
    在发光阶段，第一发光控制电路在第二发光控制信号的控制下，控制电源电压端与驱动电路的第一端之间连通，第二发光控制电路在第一发光控制信号的控制下，控制驱动电路的第二端与发光元件的第一极之间连通，驱动电路驱动发光元件发光。
  15. 如权利要求14所述的驱动方法，其中，所述像素电路还包括第二初始化电路，所述驱动方法还包括：
    在数据写入阶段，所述第二初始化电路将第二初始电压写入发光元件的第一极，以使得所述发光元件不发光。
  16. 如权利要求14或15所述的驱动方法，其中，所述显示周期还包括设置于所述初始化阶段之前，并与所述初始化阶段紧邻的前置阶段，所述驱动方法还包括：
    在所述前置阶段、所述初始化阶段和所述数据写入阶段，所述第二发光 控制电路在所述第一发光控制信号的控制下，控制所述驱动电路的第二端与所述发光元件的第一极之间断开。
  17. 一种显示装置，包括如权利要求1至12中任一权利要求所述的像素电路。
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