WO2020215430A1 - 像素驱动电路及显示面板 - Google Patents

像素驱动电路及显示面板 Download PDF

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Publication number
WO2020215430A1
WO2020215430A1 PCT/CN2019/088329 CN2019088329W WO2020215430A1 WO 2020215430 A1 WO2020215430 A1 WO 2020215430A1 CN 2019088329 W CN2019088329 W CN 2019088329W WO 2020215430 A1 WO2020215430 A1 WO 2020215430A1
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WIPO (PCT)
Prior art keywords
transistor
electrically connected
control signal
node
potential
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Application number
PCT/CN2019/088329
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English (en)
French (fr)
Inventor
聂诚磊
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Publication of WO2020215430A1 publication Critical patent/WO2020215430A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element

Definitions

  • This application relates to the field of display technology, in particular to a pixel drive circuit and a display panel.
  • the gate of the second transistor is electrically connected to the first control signal
  • the source of the second transistor is electrically connected to the second node
  • the drain of the second transistor is electrically connected to the first control signal.
  • the anode terminal of the light emitting device is electrically connected to the third node, and the cathode terminal of the light emitting device is electrically connected to a second power signal;
  • the first control signal in the initialization phase, is at a low potential, the second control signal is at a high potential, the third control signal is at a high potential, and the first control signal is at a high potential.
  • the fourth control signal is high.
  • the first control signal in the programming phase, is at a low potential, the second control signal is at a high potential, the third control signal is at a low potential, and the first control signal is at a low potential.
  • the fourth control signal is low level.
  • the gate of the first transistor is electrically connected to a first node, the source of the first transistor is electrically connected to a second node, and the drain of the first transistor is electrically connected to a third node;
  • the gate of the second transistor is electrically connected to the first control signal
  • the source of the second transistor is electrically connected to the second node
  • the drain of the second transistor is electrically connected to the first control signal.
  • the gate of the fourth transistor is electrically connected to the second control signal, the source of the fourth transistor is electrically connected to the first power signal, and the drain of the fourth transistor is electrically connected to the Fourth node
  • the gate of the seventh transistor is electrically connected to the third control signal, the source of the seventh transistor is electrically connected to the data signal, and the drain of the seventh transistor is electrically connected to the third capacitor. Second end; the first end of the third capacitor is electrically connected to the first node;
  • a first end of the first capacitor is electrically connected to the second node, and a second end of the first capacitor is electrically connected to the fourth node;
  • a first end of the second capacitor is electrically connected to the first node, and a second end of the second capacitor is electrically connected to the third node;
  • the anode terminal of the light emitting device is electrically connected to the third node, and the cathode terminal of the light emitting device is electrically connected to a second power signal.
  • the combination of the first control signal, the second control signal, the third control signal, and the fourth control signal sequentially corresponds to the initialization phase, signal input, and threshold Voltage detection phase, data signal input phase, programming phase, and light-emitting phase; wherein the data signal includes a reference potential and a display potential.
  • the potential of the data signal Is the reference potential; in the data signal input stage, the potential of the data signal is the display potential.
  • the first control signal is at a low level
  • the second control signal is at a high level
  • the third control signal is at a high level.
  • Potential the fourth control signal is a low potential.
  • the first control signal in the data signal input stage, is at a low potential, the second control signal is at a high potential, and the third control signal is at a high potential.
  • the fourth control signal is a low level.
  • the first control signal in the programming phase, is at a low potential, the second control signal is at a high potential, the third control signal is at a low potential, and the first control signal is at a low potential.
  • the fourth control signal is low level.
  • the first control signal in the light-emitting phase, is at a high potential, the second control signal is at a low potential, the third control signal is at a low potential, and the first control signal is at a low potential.
  • the fourth control signal is low level.
  • the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the first transistor are all low-temperature polysilicon thin film transistors, oxide semiconductor thin film transistors or amorphous silicon thin film transistors.
  • the light-emitting device is an organic light-emitting diode.
  • An embodiment of the present application also provides a display panel, which includes a pixel drive circuit.
  • the pixel drive circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor.
  • the gate of the first transistor is electrically connected to a first node, the source of the first transistor is electrically connected to a second node, and the drain of the first transistor is electrically connected to a third node;
  • the gate of the second transistor is electrically connected to the first control signal
  • the source of the second transistor is electrically connected to the second node
  • the drain of the second transistor is electrically connected to the first control signal.
  • the gate of the third transistor is electrically connected to the fourth node, the source of the third transistor is electrically connected to the first power signal, and the drain of the third transistor is electrically connected to the second node ;
  • the gate of the fourth transistor is electrically connected to the second control signal, the source of the fourth transistor is electrically connected to the first power signal, and the drain of the fourth transistor is electrically connected to the Fourth node
  • the gate of the fifth transistor is electrically connected to the first control signal, the source of the fifth transistor is electrically connected to the first node, and the drain of the fifth transistor is electrically connected to the The third node;
  • the gate of the sixth transistor is electrically connected to the fourth control signal, the source of the sixth transistor is electrically connected to the second node, and the drain of the sixth transistor is electrically connected to the first node.
  • the gate of the seventh transistor is electrically connected to the third control signal, the source of the seventh transistor is electrically connected to the data signal, and the drain of the seventh transistor is electrically connected to the third capacitor. Second end; the first end of the third capacitor is electrically connected to the first node;
  • a first end of the first capacitor is electrically connected to the second node, and a second end of the first capacitor is electrically connected to the fourth node;
  • a first end of the second capacitor is electrically connected to the first node, and a second end of the second capacitor is electrically connected to the third node;
  • the anode terminal of the light emitting device is electrically connected to the third node, and the cathode terminal of the light emitting device is electrically connected to a second power signal.
  • the combination of the first control signal, the second control signal, the third control signal, and the fourth control signal sequentially corresponds to the initialization phase, the signal input, and the threshold voltage
  • the first control signal in the initialization phase, is at a low potential, the second control signal is at a high potential, the third control signal is at a high potential, and the fourth The control signal is high.
  • the first control signal is at a low potential
  • the second control signal is at a high potential
  • the third control signal is at a high potential
  • the fourth control signal is a low level.
  • the pixel drive circuit and display panel provided by the embodiments of the present application adopt a pixel drive circuit with a 7T3C structure to effectively compensate the threshold voltage of the drive transistor in each pixel.
  • the compensation structure of the pixel drive circuit is relatively simple and the operation difficulty is relatively low.
  • the light-emitting device emits light in the programming phase and the light-emitting phase, which increases the light-emitting time of the light-emitting device, thereby improving the brightness and lifetime of the display panel.
  • FIG. 1 is a schematic structural diagram of a pixel driving circuit provided by an embodiment of the application
  • FIG. 2 is a timing diagram of a pixel driving circuit provided by an embodiment of the application.
  • FIG. 3 is a schematic diagram of the path of the pixel driving circuit provided by the embodiment of the application in the initialization phase under the driving timing shown in FIG. 2;
  • FIG. 4 is a schematic diagram of the signal input and threshold voltage detection stages of the pixel driving circuit provided by the application embodiment in the driving timing shown in FIG. 2;
  • FIG. 5 is a schematic diagram of a data signal input path of the pixel driving circuit provided by the application embodiment under the driving timing shown in FIG. 2;
  • FIG. 6 is a schematic diagram of the programming phase of the pixel driving circuit provided by the application embodiment in the driving sequence shown in FIG. 2;
  • FIG. 7 is a schematic diagram of the path of the pixel driving circuit provided by the application embodiment in the light-emitting phase under the driving timing shown in FIG. 2.
  • the transistors used in all the embodiments of this application can be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistor used here are symmetrical, the source and drain can be interchanged of. In the embodiments of the present application, in order to distinguish the two poles of the transistor except the gate, one of the poles is called the source and the other is called the drain. According to the form in the figure, it is stipulated that the middle end of the switching transistor is the gate, the signal input end is the source, and the output end is the drain.
  • the transistors used in the embodiments of the present application may include P-type transistors and/or N-type transistors. The P-type transistor is turned on when the gate is at a low level, and turned off when the gate is at a high level. The gate is turned on when the gate is high, and it is turned off when the gate is low.
  • FIG. 1 is a schematic structural diagram of a pixel driving circuit provided by an embodiment of the application.
  • the pixel driving circuit provided by the embodiment of the present application includes: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor.
  • the light emitting device D may be an organic light emitting diode.
  • the embodiment of the present application adopts the pixel driving circuit of the 7T3C structure to effectively compensate the threshold voltage of the driving transistor in each pixel, uses fewer components, has a simple and stable structure, and saves costs.
  • the first transistor T1 in the pixel driving circuit is a driving transistor.
  • the gate of the first transistor T1 is electrically connected to the first node a1, the source of the first transistor T1 is electrically connected to the second node a2, and the drain of the first transistor T1 is electrically connected to the third node a3.
  • the gate of the second transistor T2 is electrically connected to the first control signal EM2, the source of the second transistor T2 is electrically connected to the second node a2, and the drain of the second transistor T2 is electrically connected to the third node a3.
  • the gate of the third transistor T3 is electrically connected to the fourth node a4, the source of the third transistor T3 is electrically connected to the first power signal VDD, and the drain of the third transistor T3 is electrically connected to the second node a2.
  • the gate of the fourth transistor T4 is electrically connected to the second control signal EM1, the source of the fourth transistor T4 is electrically connected to the first power signal VDD, and the drain of the fourth transistor T4 is electrically connected to the fourth node a4.
  • the gate of the fifth transistor T5 is electrically connected to the first control signal EM2, the source of the fifth transistor T5 is electrically connected to the first node a1, and the drain of the fifth transistor T5 is electrically connected to the third node a3.
  • the gate of the sixth transistor T6 is electrically connected to the fourth control signal CTR, the source of the sixth transistor T6 is electrically connected to the second node a2, and the drain of the sixth transistor T6 is electrically connected to the first node a1.
  • the gate of the seventh transistor T7 is electrically connected to the third control signal G, the source of the seventh transistor T7 is electrically connected to the data signal Data, and the drain of the seventh transistor T7 is electrically connected to the second of the third capacitor C3. end.
  • the first terminal of the third capacitor C3 is electrically connected to the first node a1.
  • the first terminal of the first capacitor C1 is electrically connected to the second node a2, and the second terminal of the first capacitor C1 is electrically connected to the fourth node a4.
  • the first end of the second capacitor C2 is electrically connected to the first node a1, and the second end of the second capacitor C2 is electrically connected to the third node a3.
  • the anode terminal of the light emitting device D is electrically connected to the third node a3, and the cathode terminal of the light emitting device D is electrically connected to the second power signal Vss.
  • the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are all low temperature polysilicon thin film transistors, oxide semiconductors. Thin film transistors or amorphous silicon thin film transistors.
  • the transistors in the pixel driving circuit provided by the embodiments of the present application are the same type of transistors, so as to avoid the influence of the difference between different types of transistors on the pixel driving circuit.
  • FIG. 2 is a timing diagram of the pixel driving circuit provided by an embodiment of the application.
  • the combination of the first control signal EM2, the second control signal EM1, the third control signal G, and the fourth control signal CTR corresponds to the initialization phase t1, the signal input and threshold voltage detection phase t2, and the data signal input.
  • the data signal Data includes a reference potential Vref and a display potential Vdata, and the value of the reference potential Vref is smaller than the value of the display potential Vdata.
  • the potential of the data signal Data is the reference potential Vref.
  • the potential of the data signal Data is the display potential Vdata.
  • the light-emitting device D of the embodiment of the present application emits light in the programming phase t4 and the light-emitting phase t5, which increases the light-emitting time of the light-emitting device D, thereby improving the brightness and lifetime of the display panel.
  • the first control signal EM2 is at a low level
  • the second control signal EM1 is at a high level
  • the third control signal G is at a high level
  • the fourth control signal CTR is at a high level.
  • the first control signal EM2 is at a low level
  • the second control signal EM1 is at a high level
  • the third control signal G is at a high level
  • the fourth control signal CTR is at a low level. Potential.
  • the first control signal EM2 is at a low level
  • the second control signal EM1 is at a high level
  • the third control signal G is at a high level
  • the fourth control signal CTR is at a low level.
  • the first control signal EM2 is at a low level
  • the second control signal EM1 is at a high level
  • the third control signal G is at a low level
  • the fourth control signal CTR is at a low level.
  • the first control signal EM2 is at a high level
  • the second control signal EM1 is at a low level
  • the third control signal G is at a low level
  • the fourth control signal CTR is at a low level.
  • first power signal VDD and the second power signal Vss are both DC voltage sources, and the potential of the first power signal VDD is greater than the potential of the second power signal Vss.
  • FIG. 3 is a schematic diagram of the path of the pixel driving circuit provided by the application embodiment in the initialization phase of the driving timing shown in FIG. 2.
  • the first control signal EM2 is at a low level
  • the second control signal EM1 is at a high level
  • the third control signal G is at a high level
  • the fourth control signal CTR is at a high level. Potential.
  • the first transistor T1, the third transistor T3, the fourth transistor T4, the sixth transistor T6, and the seventh transistor T7 are turned on
  • the second transistor T2 and the fifth transistor T5 are turned off.
  • the sixth transistor T6 is turned on, and the gate and source of the first transistor T1 are short-circuited, and the potential is basically equal.
  • the fourth transistor T4 Since the second control signal EM1 is at a high potential, the fourth transistor T4 is turned on, and the first power signal VDD is output to the fourth node a4 through the fourth transistor T4 and stored in the first capacitor C1. Since the fourth node a4 is electrically connected to the gate of the third transistor T3, the third transistor T3 is turned on at this time, and the first power signal VDD is output to the second node a2 through the third transistor T3 and stored in the first capacitor C1 on. That is, at this time, the third transistor T3 and the fourth transistor T4 provide corresponding voltages to the gate and source of the first transistor T1, and at this time, the first transistor T1 is turned on.
  • the seventh transistor T7 Since the third control signal G is at a high potential, the seventh transistor T7 is turned on, and the reference potential Vref of the data signal Data is output to the second end of the third capacitor C3 through the seventh transistor T7 and stored in the third capacitor C3. In addition, since the first control signal EM2 is at a low level, the second transistor T2 and the fifth transistor T5 are turned off.
  • FIG. 4 is a schematic diagram of the signal input and threshold voltage detection phases of the pixel driving circuit provided by the application embodiment in the driving sequence shown in FIG. 2.
  • the first control signal EM2 is at a low level
  • the second control signal EM1 is at a high level
  • the third control signal G is at a high level
  • the fourth control signal CTR is low.
  • the third transistor T3, the fourth transistor T4, and the seventh transistor T7 are turned on
  • the fifth transistor T5, and the sixth transistor T6 are turned off.
  • the first transistor T1 is turned off. That is, the first transistor T1 changes from the on state to the off state during the signal input and threshold voltage detection phase t2.
  • the seventh transistor T7 since the third control signal G is at a high potential, the seventh transistor T7 is turned on, and the reference potential Vref of the data signal Data is output to the second end of the third capacitor C3 through the seventh transistor T7, and is stored in the third capacitor C3 on. That is, at this time, the potential of the second end of the third capacitor C3 remains unchanged at the second end of the third capacitor C3 during the initialization phase t1.
  • the fourth transistor T4 Since the second control signal EM1 is at a high potential, the fourth transistor T4 is turned on, and the first power signal VDD is output to the fourth node a4 through the fourth transistor T4 and stored in the first capacitor C1. Since the fourth node a4 is electrically connected to the gate of the third transistor T3, the third transistor T3 is turned on at this time, and the first power signal VDD is output to the second node a2 through the third transistor T3 and stored in the first capacitor C1 on. That is, at this time, the third transistor T3 and the fourth transistor T4 provide corresponding voltages to the gate and source of the first transistor T1, and at this time, the first transistor T1 is turned on.
  • the first transistor T1 is turned off, where Voled is the threshold voltage of the light-emitting device D, and Vth is the voltage of the first transistor T1 Threshold voltage. That is, at this time, the threshold voltage of the first transistor T1 is successfully detected and stored in the gate of the first transistor T1. And at this time, the voltage difference between the first terminal and the second terminal of the third capacitor C3 is Vref-Voled-Vth.
  • the second transistor T2 since the first control signal EM2 and the fourth control signal CTR are both low, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 are turned off.
  • FIG. 5 is a schematic diagram of the data signal input phase of the pixel driving circuit provided by the embodiment of the application in the driving sequence shown in FIG. 2.
  • the first control signal EM2 is at a low level
  • the second control signal EM1 is at a high level
  • the third control signal G is at a high level
  • the fourth control signal CTR is at a low level. Potential.
  • the third transistor T3, the fourth transistor T4, and the seventh transistor T7 are turned on, and the second transistor T2, the fifth transistor T5, and the sixth transistor T6 are turned off.
  • the first transistor T1 changes from a closed state to an open state during the data signal input phase t3.
  • the seventh transistor T7 is turned on, and the display potential Vdata of the data signal Data is output to the second end of the third capacitor C3 through the seventh transistor T7. Due to the capacitive coupling effect, the first terminal of the third capacitor C3 should also change accordingly.
  • the voltage of the first terminal of the third capacitor C3 is Vdata-Vref+Voled+Vth. That is, the voltage of the gate of the first transistor T1 is Vdata-Vref+Voled+Vth. So far, the threshold voltage of the first transistor T1 and the display potential Vdata of the data signal Data are successfully stored on the gate of the first transistor T1. .
  • FIG. 6 is a schematic diagram of the programming phase of the pixel driving circuit provided by the application embodiment in the driving sequence shown in FIG. 2.
  • the first control signal EM2 is at a low level
  • the second control signal EM1 is at a high level
  • the third control signal G is at a low level
  • the fourth control signal CTR is at a low level.
  • the first transistor T1, the third transistor T3, and the fourth transistor T4 are turned on
  • the second transistor T2 the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned off.
  • the potential of the gate of the first transistor T1 remains at the potential of the gate of the first transistor T1 when the data signal Data is input to the measurement phase, that is, at this time, the potential of the first transistor T1
  • the potential of the gate is still Vdata-Vref+Voled+Vth.
  • the fourth transistor T4 Since the second control signal EM1 is at a high potential, the fourth transistor T4 is turned on, and the first power signal VDD is output to the fourth node a4 through the fourth transistor T4 and stored in the first capacitor C1. Since the fourth node a4 is electrically connected to the gate of the third transistor T3, the third transistor T3 is turned on at this time, and the first power signal VDD is output to the second node a2 through the third transistor T3 and stored in the first capacitor C1 Above, the voltage difference between the gate and the drain of the third transistor T3 is slowly adjusted to be compatible with the current of the light-emitting device D. At this time, the light-emitting device D can emit light normally. In addition, since the first control signal EM2, the third control signal G, and the fourth control signal CTR are all low potentials, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned off.
  • FIG. 7 is a schematic diagram of the light-emitting phase of the pixel driving circuit provided by the application embodiment in the driving sequence shown in FIG. 2.
  • the first control signal EM2 is at a high level
  • the second control signal EM1 is at a low level
  • the third control signal G is at a low level
  • the fourth control signal CTR is at a low level.
  • the second transistor T2, the third transistor T3, and the fifth transistor T5 are turned on
  • the first transistor T1, the fourth transistor T4, the sixth transistor T6, and the seventh transistor T7 are turned off.
  • the sixth transistor T6 is turned off. Because the first control signal EM2 is at a high potential, the fifth transistor T5 is turned on, and the first node a1 and the third node a3 are short-circuited, and the first transistor T1 is turned off.
  • the fourth transistor T4 Since the second control signal EM1 is at a low level, the fourth transistor T4 is turned off. However, due to the function of the first capacitor C1, the potential of the fourth node a4 still maintains the potential of the fourth node in the programming phase t4. Since the fourth node a4 is electrically connected to the gate of the third transistor T3, the third transistor T3 is also turned on at this time, and the first power signal VDD is output to the second node a2 through the third transistor T3. That is, at this time, the voltage difference between the gate and drain of the third transistor T3 is maintained by the first capacitor C1, and the voltage difference between the gate and the drain of the third transistor T3 is still at the time of the programming phase t4 The voltage difference between the gate and drain of the third transistor T3. This ensures that the current flowing through the light-emitting device D remains unchanged.
  • the second transistor T2 and the fifth transistor T5 are turned on. Since the fifth transistor T5 is turned on, the gate and drain of the first transistor T1 are short-circuited, so that the voltage difference between the gate and the drain of the first transistor T1 approaches zero. At this time, the first transistor T1 There is no stress effect. That is, the current flowing through the light emitting device D is independent of the threshold voltage of the first transistor T1. Since the fifth transistor T5 is turned on, the current originally flowing through the first transistor T1 now flows to the light-emitting device D through the fifth transistor T5, which does not affect the normal light emission of the light-emitting device D.
  • An embodiment of the present application also provides a display panel, which includes the above-mentioned pixel driving circuit.
  • a display panel which includes the above-mentioned pixel driving circuit.
  • pixel driving circuit please refer to the above description of the pixel driving circuit, which will not be repeated here.
  • the pixel drive circuit and display panel provided by the embodiments of the present application adopt a pixel drive circuit with a 7T3C structure to effectively compensate the threshold voltage of the drive transistor in each pixel.
  • the compensation structure of the pixel drive circuit is relatively simple and the operation difficulty is relatively low.
  • the light-emitting device emits light in the programming phase and the light-emitting phase, which increases the light-emitting time of the light-emitting device, thereby improving the brightness and lifetime of the display panel.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

一种像素驱动电路及显示面板，采用7T3C结构的像素驱动电路对每一像素中的驱动晶体管（T1）的阈值电压进行有效补偿，该像素驱动电路的补偿结构较为简单，操作难度较低，且发光器件（D）在编程阶段（t4）以及发光阶段（t5）发光，增加了发光器件（D）的发光时间，从而提升显示面板的亮度和寿命。

Description

像素驱动电路及显示面板 技术领域
本申请涉及显示技术领域，具体涉及一种像素驱动电路及显示面板。
 背景技术
OLED(Organic Light Emitting Diode，有机发光二极管)显示面板具有高亮度、宽视角、响应速度快、低功耗等优点，目前已被广泛地应用于高性能显示领域中。其中，在OLED显示器面板中，像素被设置成包括多行、多列的矩阵状，每一像素通常采用由两个晶体管与一个电容构成，俗称2T1C电路，但晶体管存在阈值电压漂移的问题，因此，OLED像素驱动电路需要相应的补偿结构。目前，OLED像素驱动电路的补偿结构较为复杂，其操作难度较大，且发光器件的发光时间较短。
 技术问题
本申请实施例的目的在于提供一种像素驱动电路及显示面板，能够解决现有的像素驱动电路的补偿结构较为复杂，其操作难度较大，且发光器件的发光时间较短的技术问题。
 技术解决方案
本申请实施例提供一种像素驱动电路，包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、第一电容、第二电容、第三电容以及发光器件；
所述第一晶体管的栅极电性连接于第一节点，所述第一晶体管的源极电性连接于第二节点，所述第一晶体管的漏极电性连接于第三节点；
所述第二晶体管的栅极电性连接于第一控制信号，所述第二晶体管的源极电性连接于所述第二节点，所述第二晶体管的漏极电性连接于所述第三节点；
所述第三晶体管的栅极电性连接于第四节点，所述第三晶体管的源极电性连接于第一电源信号，所述第三晶体管的漏极电性连接于所述第二节点；
所述第四晶体管的栅极电性连接于第二控制信号，所述第四晶体管的源极电性连接于所述第一电源信号，所述第四晶体管的漏极电性连接于所述第四节点；
所述第五晶体管的栅极电性连接于所述第一控制信号，所述第五晶体管的源极电性连接于所述第一节点，所述第五晶体管的漏极电性连接于所述第三节点；
所述第六晶体管的栅极电性连接于第四控制信号，所述第六晶体管的源极电性连接于所述第二节点，所述第六晶体管的漏极电性连接于所述第一节点；
所述第七晶体管的栅极电性连接于第三控制信号，所述第七晶体管的源极电性连接于数据信号，所述第七晶体管的漏极电性连接于所述第三电容的第二端；所述第三电容的第一端电性连接于所述第一节点；
所述第一电容的第一端电性连接于所述第二节点，所述第一电容的第二端电性连接于所述第四节点；
所述第二电容的第一端电性连接于所述第一节点，所述第二电容的第二端电性连接于所述第三节点；
所述发光器件的阳极端电性连接于所述第三节点，所述发光器件的阴极端电性连接于第二电源信号；
所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管以及所述第七晶体管均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管；所述发光器件为有机发光二极管。
在本申请所述的像素驱动电路中，所述第一控制信号、所述第二控制信号、所述第三控制信号以及所述第四控制信号相组合先后对应于初始化阶段、信号输入与阈值电压探测阶段、数据信号输入阶段、编程阶段以及发光阶段；其中，所述数据信号包括参考电位和显示电位，在所述初始化阶段和所述信号输入与阈值电压探测阶段，所述数据信号的电位为所述参考电位；在所述数据信号输入阶段，所述数据信号的电位为所述显示电位。
在本申请所述的像素驱动电路中，在所述初始化阶段，所述第一控制信号为低电位，所述第二控制信号为高电位，所述第三控制信号为高电位，所述第四控制信号为高电位。
在本申请所述的像素驱动电路中，在所述信号输入与阈值电压探测阶段，所述第一控制信号为低电位，所述第二控制信号为高电位，所述第三控制信号为高电位，所述第四控制信号为低电位。
在本申请所述的像素驱动电路中，在所述数据信号输入阶段，所述第一控制信号为低电位，所述第二控制信号为高电位，所述第三控制信号为高电位，所述第四控制信号为低电位。
在本申请所述的像素驱动电路中，在所述编程阶段，所述第一控制信号为低电位，所述第二控制信号为高电位，所述第三控制信号为低电位，所述第四控制信号为低电位。
在本申请所述的像素驱动电路中，在所述发光阶段，所述第一控制信号为高电位，所述第二控制信号为低电位，所述第三控制信号为低电位，所述第四控制信号为低电位。
本申请实施例还提供一种像素驱动电路，包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、第一电容、第二电容、第三电容以及发光器件；
所述第一晶体管的栅极电性连接于第一节点，所述第一晶体管的源极电性连接于第二节点，所述第一晶体管的漏极电性连接于第三节点；
所述第二晶体管的栅极电性连接于第一控制信号，所述第二晶体管的源极电性连接于所述第二节点，所述第二晶体管的漏极电性连接于所述第三节点；
所述第三晶体管的栅极电性连接于第四节点，所述第三晶体管的源极电性连接于第一电源信号，所述第三晶体管的漏极电性连接于所述第二节点；
所述第四晶体管的栅极电性连接于第二控制信号，所述第四晶体管的源极电性连接于所述第一电源信号，所述第四晶体管的漏极电性连接于所述第四节点；
所述第五晶体管的栅极电性连接于所述第一控制信号，所述第五晶体管的源极电性连接于所述第一节点，所述第五晶体管的漏极电性连接于所述第三节点；
所述第六晶体管的栅极电性连接于第四控制信号，所述第六晶体管的源极电性连接于所述第二节点，所述第六晶体管的漏极电性连接于所述第一节点；
所述第七晶体管的栅极电性连接于第三控制信号，所述第七晶体管的源极电性连接于数据信号，所述第七晶体管的漏极电性连接于所述第三电容的第二端；所述第三电容的第一端电性连接于所述第一节点；
所述第一电容的第一端电性连接于所述第二节点，所述第一电容的第二端电性连接于所述第四节点；
所述第二电容的第一端电性连接于所述第一节点，所述第二电容的第二端电性连接于所述第三节点；
所述发光器件的阳极端电性连接于所述第三节点，所述发光器件的阴极端电性连接于第二电源信号。
在本申请所述的像素驱动电路中，所述第一控制信号、所述第二控制信号、所述第三控制信号以及所述第四控制信号相组合先后对应于初始化阶段、信号输入与阈值电压探测阶段、数据信号输入阶段、编程阶段以及发光阶段；其中，所述数据信号包括参考电位和显示电位，在所述初始化阶段和所述信号输入与阈值电压探测阶段，所述数据信号的电位为所述参考电位；在所述数据信号输入阶段，所述数据信号的电位为所述显示电位。
在本申请所述的像素驱动电路中，在所述初始化阶段，所述第一控制信号为低电位，所述第二控制信号为高电位，所述第三控制信号为高电位，所述第四控制信号为高电位。
在本申请所述的像素驱动电路中，在所述信号输入与阈值电压探测阶段，所述第一控制信号为低电位，所述第二控制信号为高电位，所述第三控制信号为高电位，所述第四控制信号为低电位。
在本申请所述的像素驱动电路中，在所述数据信号输入阶段，所述第一控制信号为低电位，所述第二控制信号为高电位，所述第三控制信号为高电位，所述第四控制信号为低电位。
在本申请所述的像素驱动电路中，在所述编程阶段，所述第一控制信号为低电位，所述第二控制信号为高电位，所述第三控制信号为低电位，所述第四控制信号为低电位。
在本申请所述的像素驱动电路中，在所述发光阶段，所述第一控制信号为高电位，所述第二控制信号为低电位，所述第三控制信号为低电位，所述第四控制信号为低电位。
在本申请所述的像素驱动电路中，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管以及所述第七晶体管均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管。
在本申请所述的像素驱动电路中，所述发光器件为有机发光二极管。
本申请实施例还提供一种显示面板，其包括像素驱动电路，所述像素驱动电路包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、第一电容、第二电容、第三电容以及发光器件；
所述第一晶体管的栅极电性连接于第一节点，所述第一晶体管的源极电性连接于第二节点，所述第一晶体管的漏极电性连接于第三节点；
所述第二晶体管的栅极电性连接于第一控制信号，所述第二晶体管的源极电性连接于所述第二节点，所述第二晶体管的漏极电性连接于所述第三节点；
所述第三晶体管的栅极电性连接于第四节点，所述第三晶体管的源极电性连接于第一电源信号，所述第三晶体管的漏极电性连接于所述第二节点；
所述第四晶体管的栅极电性连接于第二控制信号，所述第四晶体管的源极电性连接于所述第一电源信号，所述第四晶体管的漏极电性连接于所述第四节点；
所述第五晶体管的栅极电性连接于所述第一控制信号，所述第五晶体管的源极电性连接于所述第一节点，所述第五晶体管的漏极电性连接于所述第三节点；
所述第六晶体管的栅极电性连接于第四控制信号，所述第六晶体管的源极电性连接于所述第二节点，所述第六晶体管的漏极电性连接于所述第一节点；
所述第七晶体管的栅极电性连接于第三控制信号，所述第七晶体管的源极电性连接于数据信号，所述第七晶体管的漏极电性连接于所述第三电容的第二端；所述第三电容的第一端电性连接于所述第一节点；
所述第一电容的第一端电性连接于所述第二节点，所述第一电容的第二端电性连接于所述第四节点；
所述第二电容的第一端电性连接于所述第一节点，所述第二电容的第二端电性连接于所述第三节点；
所述发光器件的阳极端电性连接于所述第三节点，所述发光器件的阴极端电性连接于第二电源信号。
在本申请所述的显示面板中，所述第一控制信号、所述第二控制信号、所述第三控制信号以及所述第四控制信号相组合先后对应于初始化阶段、信号输入与阈值电压探测阶段、数据信号输入阶段、编程阶段以及发光阶段；其中，所述数据信号包括参考电位和显示电位，在所述初始化阶段和所述信号输入与阈值电压探测阶段，所述数据信号的电位为所述参考电位；在所述数据信号输入阶段，所述数据信号的电位为所述显示电位。
在本申请所述的显示面板中，在所述初始化阶段，所述第一控制信号为低电位，所述第二控制信号为高电位，所述第三控制信号为高电位，所述第四控制信号为高电位。
在本申请所述的显示面板中，在所述信号输入与阈值电压探测阶段，所述第一控制信号为低电位，所述第二控制信号为高电位，所述第三控制信号为高电位，所述第四控制信号为低电位。
 有益效果
本申请实施例提供的像素驱动电路及显示面板，采用7T3C结构的像素驱动电路对每一像素中的驱动晶体管的阈值电压进行有效补偿，该像素驱动电路的补偿结构较为简单，操作难度较低，且发光器件在编程阶段以及发光阶段发光，增加了发光器件的发光时间，从而提升显示面板的亮度和寿命。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的像素驱动电路的结构示意图；
图2为本申请实施例提供的像素驱动电路的时序图；
图3为申请实施例提供的像素驱动电路在图2所示的驱动时序下的初始化阶段的通路示意图；
图4为申请实施例提供的像素驱动电路在图2所示的驱动时序下的信号输入与阈值电压探测阶段的通路示意图；
图5为申请实施例提供的像素驱动电路在图2所示的驱动时序下的数据信号输入的通路示意图；
图6为申请实施例提供的像素驱动电路在图2所示的驱动时序下的编程阶段的通路示意图；以及
图7为申请实施例提供的像素驱动电路在图2所示的驱动时序下的发光阶段的通路示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请所有实施例中采用的晶体管可以为薄膜晶体管或场效应管或其他特性相同的器件，由于这里采用的晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本申请实施例中，为区分晶体管除栅极之外的两极，将其中一极称为源极，另一极称为漏极。按附图中的形态规定开关晶体管的中间端为栅极、信号输入端为源极、输出端为漏极。此外本申请实施例所采用的晶体管可以包括P 型晶体管和/或N 型晶体管两种，其中，P 型晶体管在栅极为低电平时导通，在栅极为高电平时截止，N 型晶体管为在栅极为高电平时导通，在栅极为低电平时截止。
请参阅图1，图1为本申请实施例提供的像素驱动电路的结构示意图。如图1所示，本申请实施例提供的像素驱动电路，包括：第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、第一电容C1、第二电容C2、第三电容C3以及发光器件D。该发光器件D可以为有机发光二极管。也即，本申请实施例采用7T3C结构的像素驱动电路对每一像素中的驱动晶体管的阈值电压进行有效补偿，用了较少的元器件，结构简单稳定，节约了成本。该像素驱动电路中的第一晶体管T1为驱动晶体管。
其中，第一晶体管T1的栅极电性连接于第一节点a1，第一晶体管T1的源极电性连接于第二节点a2，第一晶体管T1的漏极电性连接于第三节点a3。第二晶体管T2的栅极电性连接于第一控制信号EM2，第二晶体管T2的源极电性连接于第二节点a2，第二晶体管T2的漏极电性连接于第三节点a3。第三晶体管T3的栅极电性连接于第四节点a4，第三晶体管T3的源极电性连接于第一电源信号VDD，第三晶体管T3的漏极电性连接于第二节点a2。第四晶体管T4的栅极电性连接于第二控制信号EM1，第四晶体管T4的源极电性连接于第一电源信号VDD，第四晶体管T4的漏极电性连接于第四节点a4。第五晶体管T5的栅极电性连接于第一控制信号EM2，第五晶体管T5的源极电性连接于第一节点a1，第五晶体管T5的漏极电性连接于第三节点a3。第六晶体管T6的栅极电性连接于第四控制信号CTR，第六晶体管T6的源极电性连接于第二节点a2，第六晶体管T6的漏极电性连接于第一节点a1。第七晶体管T7的栅极电性连接于第三控制信号G，第七晶体管T7的源极电性连接于数据信号Data，第七晶体管T7的漏极电性连接于第三电容C3的第二端。第三电容C3的第一端电性连接于第一节点a1。第一电容C1的第一端电性连接于第二节点a2，第一电容C1的第二端电性连接于第四节点a4。第二电容C2的第一端电性连接于第一节点a1，第二电容C2的第二端电性连接于第三节点a3。发光器件D的阳极端电性连接于第三节点a3，发光器件D的阴极端电性连接于第二电源信号Vss。
在一些实施例中，第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6以及第七晶体管T7均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管。本申请实施例提供的像素驱动电路中的晶体管为同一种类型的晶体管，从而避免不同类型的晶体管之间的差异性对像素驱动电路造成的影响。
请参阅图2，图2为本申请实施例提供的像素驱动电路的时序图。如图2所示，第一控制信号EM2、第二控制信号EM1、第三控制信号G以及第四控制信号CTR相组合先后对应于初始化阶段t1、信号输入与阈值电压探测阶段t2、数据信号输入阶段t3、编程阶段t4以及发光阶段t5。其中，数据信号Data包括参考电位Vref和显示电位Vdata，且参考电位Vref的数值小于显示电位Vdata的数值。在初始化阶段t1和信号输入与阈值电压探测阶段t2，数据信号Data的电位为参考电位Vref。在数据信号输入阶段t3，数据信号Data的电位为显示电位Vdata。需要说明的是，本申请实施例的发光器件D在编程阶段t4以及发光阶段t5发光，增加了发光器件D的发光时间，从而提升显示面板的亮度和寿命。
在一些实施例中，在初始化阶段t1，第一控制信号EM2为低电位，第二控制信号EM1为高电位，第三控制信号G为高电位，第四控制信号CTR为高电位。
在一些实施例中，在信号输入与阈值电压探测阶段t2，第一控制信号EM2为低电位，第二控制信号EM1为高电位，第三控制信号G为高电位，第四控制信号CTR为低电位。
在一些实施例中，在数据信号输入阶段t3，第一控制信号EM2为低电位，第二控制信号EM1为高电位，第三控制信号G为高电位，第四控制信号CTR为低电位。
在一些实施例中，在编程阶段t4，第一控制信号EM2为低电位，第二控制信号EM1为高电位，第三控制信号G为低电位，第四控制信号CTR为低电位。
在一些实施例中，在发光阶段t5，第一控制信号EM2为高电位，第二控制信号EM1为低电位，第三控制信号G为低电位，第四控制信号CTR为低电位。
进一步的，第一电源信号VDD和第二电源信号Vss均为直流电压源，且第一电源信号VDD的电位大于第二电源信号Vss的电位。
请参阅图3，图3为申请实施例提供的像素驱动电路在图2所示的驱动时序下的初始化阶段的通路示意图。首先，结合图2、图3所示，在初始化阶段t1，第一控制信号EM2为低电位，第二控制信号EM1为高电位，第三控制信号G为高电位，第四控制信号CTR为高电位。此时，第一晶体管T1、第三晶体管T3、第四晶体管T4、第六晶体管T6以及第七晶体管T7打开，第二晶体管T2以及第五晶体管T5关闭。
具体的，由于第四控制信号CTR为高电位，使得第六晶体管T6打开，第一晶体管T1的栅极以及源极短接，电位基本相等。
由于第二控制信号EM1为高电位，使得第四晶体管T4打开，第一电源信号VDD经第四晶体管T4输出至第四节点a4，并存储在第一电容C1上。由于第四节点a4与第三晶体管T3的栅极电性连接，故此时第三晶体管T3打开，第一电源信号VDD再经第三晶体管T3输出至第二节点a2，并存储在第一电容C1上。也即，此时第三晶体管T3以及第四晶体管T4提供相应的电压至第一晶体管T1的栅极和源极，此时，第一晶体管T1打开。
由于第三控制信号G为高电位，使得第七晶体管T7打开，数据信号Data的参考电位Vref经第七晶体管T7输出至第三电容C3的第二端，并存储在第三电容C3上。另外，由于第一控制信号EM2为低电位，使得第二晶体管T2以及第五晶体管T5关闭。
接着，请参阅图4，图4为申请实施例提供的像素驱动电路在图2所示的驱动时序下的信号输入与阈值电压探测阶段的通路示意图。结合图2、图4所示，在信号输入与阈值电压探测阶段t2，第一控制信号EM2为低电位，第二控制信号EM1为高电位，第三控制信号G为高电位，第四控制信号CTR为低电位。此时，第三晶体管T3、第四晶体管T4以及第七晶体管T7打开，第二晶体管T2、第五晶体管T5以及第六晶体管T6关闭。第一晶体管T1的栅极与源极之间的压差下降至一定值后，第一晶体管T1关闭。也即，第一晶体管T1在信号输入与阈值电压探测阶段t2由打开状态转向关闭状态。
具体的，由于第三控制信号G为高电位，使得第七晶体管T7打开，数据信号Data的参考电位Vref经第七晶体管T7输出至第三电容C3的第二端，并存储在第三电容C3上。也即，此时，第三电容C3的第二端的电位仍保持初始化阶段t1时第三电容C3第二端的电位不变。
由于第二控制信号EM1为高电位，使得第四晶体管T4打开，第一电源信号VDD经第四晶体管T4输出至第四节点a4，并存储在第一电容C1上。由于第四节点a4与第三晶体管T3的栅极电性连接，故此时第三晶体管T3打开，第一电源信号VDD再经第三晶体管T3输出至第二节点a2，并存储在第一电容C1上。也即，此时第三晶体管T3以及第四晶体管T4提供相应的电压至第一晶体管T1的栅极和源极，此时，第一晶体管T1打开。
与此同时，第一晶体管T1的栅极与源极之间的压差下降至Voled+Vth后，第一晶体管T1关闭，其中，Voled为发光器件D的阈值电压，Vth为第一晶体管T1的阈值电压。也即，此时，第一晶体管T1的阈值电压被成功探测并存储在第一晶体管T1的栅极。且此时第三电容C3的第一端与第二端之间的压差为Vref-Voled-Vth。
另外，由于第一控制信号EM2和第四控制信号CTR均为低电位，使得第二晶体管T2、第五晶体管T5以及第六晶体管T6关闭。
紧接着，请参阅图5，图5为本申请实施例提供的像素驱动电路在图2所示的驱动时序下的数据信号输入阶段的通路示意图。结合图2、图5所示，在数据信号输入阶段t3，第一控制信号EM2为低电位，第二控制信号EM1为高电位，第三控制信号G为高电位，第四控制信号CTR为低电位。此时，第三晶体管T3、第四晶体管T4以及第七晶体管T7打开，第二晶体管T2、第五晶体管T5以及第六晶体管T6关闭。第一晶体管T1在数据信号输入阶段t3由关闭状态转向打开状态。
具体的，由于第三控制信号G为高电位，使得第七晶体管T7打开，数据信号Data的显示电位Vdata经第七晶体管T7输出至第三电容C3的第二端。由于电容耦合效应，第三电容C3的第一端也应相应变化，此时第三电容C3的第一端的电压为Vdata-Vref+Voled+Vth。也即，第一晶体管T1的栅极的电压为Vdata-Vref+Voled+Vth，至此，第一晶体管T1的阈值电压以及数据信号Data的显示电位Vdata都成功被存储在第一晶体管T1的栅极。
由于第一晶体管T1的栅极的电位跳变为Vdata-Vref+Voled+Vth，故，此时，第一晶体管T1打开。
随后，请参阅图6，图6为申请实施例提供的像素驱动电路在图2所示的驱动时序下的编程阶段的通路示意图。结合图2、图6所示，在编程阶段t4，第一控制信号EM2为低电位，第二控制信号EM1为高电位，第三控制信号G为低电位，第四控制信号CTR为低电位。此时，第一晶体管T1、第三晶体管T3以及第四晶体管T4打开，第二晶体管T2、第五晶体管T5、第六晶体管T6以及第七晶体管T7关闭。
具体的，由于第二电容C2的作用，使得第一晶体管T1的栅极的电位仍保持数据信号Data输入测阶段时第一晶体管T1栅极的电位，也即，此时，第一晶体管T1的栅极的电位仍为Vdata-Vref+Voled+Vth。
由于第二控制信号EM1为高电位，使得第四晶体管T4打开，第一电源信号VDD经第四晶体管T4输出至第四节点a4，并存储在第一电容C1上。由于第四节点a4与第三晶体管T3的栅极电性连接，故此时第三晶体管T3打开，第一电源信号VDD再经第三晶体管T3输出至第二节点a2，并存储在第一电容C1上，进而使得第三晶体管T3的栅极与漏极之间的压差慢慢调节至与发光器件D电流相适应，此时发光器件D可以正常发光。另外，由于第一控制信号EM2、第三控制信号G以及第四控制信号CTR均为低电位，使得第二晶体管T2、第五晶体管T5、第六晶体管T6以及第七晶体管T7关闭。
最后，请参阅图7，图7为申请实施例提供的像素驱动电路在图2所示的驱动时序下的发光阶段的通路示意图。结合图2、图7所示，在发光阶段t5t4，第一控制信号EM2为高电位，第二控制信号EM1为低电位，第三控制信号G为低电位，第四控制信号CTR为低电位。此时，第二晶体管T2、第三晶体管T3以及第五晶体管T5打开，第一晶体管T1、第四晶体管T4、第六晶体管T6以及第七晶体管T7关闭。
具体的，由于第三控制信号G为低电位，使得第六晶体管T6关闭。由于第一控制信号EM2为高电位，使得第五晶体管T5打开，进而使得第一节点a1与第三节点a3短接，第一晶体管T1关闭。
由于第二控制信号EM1为低电位，使得第四晶体管T4关闭。然而，由于第一电容C1的作用，使得第四节点a4的电位仍保持编程阶段t4阶段时第四节的电位。由于第四节点a4与第三晶体管T3的栅极电性连接，故此时第三晶体管T3也打开，第一电源信号VDD经第三晶体管T3输出至第二节点a2。也即，此时，第三晶体管T3的栅极与漏极之间的压差由第一电容C1维持，且第三晶体管T3的栅极与漏极之间的压差仍旧为编程阶段t4时第三晶体管T3的栅极与漏极之间的压差。从而保证流经发光器件D的电流不变。
另外，由于第一控制信号EM2为高电位，使得第二晶体管T2以及第五晶体管T5打开。由于第五晶体管T5打开，使得第一晶体管T1的栅极以及漏极短接，从而使得第一晶体管T1的栅极以及漏极之间的压差趋近于零，此时，第一晶体管T1并无应力作用。也即，流经发光器件D的电流与第一晶体管T1的阈值电压无关。由于第五晶体管T5打开，原本流经第一晶体管T1的的电流现在通过第五晶体管T5流向发光器件D，不影响发光器件D的正常发光。
本申请实施例还提供一种显示面板，其包括以上所述的像素驱动电路，具体可参照以上对该像素驱动电路的描述，在此不做赘述。
本申请实施例提供的像素驱动电路及显示面板，采用7T3C结构的像素驱动电路对每一像素中的驱动晶体管的阈值电压进行有效补偿，该像素驱动电路的补偿结构较为简单，操作难度较低，且发光器件在编程阶段以及发光阶段发光，增加了发光器件的发光时间，从而提升显示面板的亮度和寿命。
以上仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (20)

  1. 一种像素驱动电路，其包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、第一电容、第二电容、第三电容以及发光器件；
    所述第一晶体管的栅极电性连接于第一节点，所述第一晶体管的源极电性连接于第二节点，所述第一晶体管的漏极电性连接于第三节点；
    所述第二晶体管的栅极电性连接于第一控制信号，所述第二晶体管的源极电性连接于所述第二节点，所述第二晶体管的漏极电性连接于所述第三节点；
    所述第三晶体管的栅极电性连接于第四节点，所述第三晶体管的源极电性连接于第一电源信号，所述第三晶体管的漏极电性连接于所述第二节点；
    所述第四晶体管的栅极电性连接于第二控制信号，所述第四晶体管的源极电性连接于所述第一电源信号，所述第四晶体管的漏极电性连接于所述第四节点；
    所述第五晶体管的栅极电性连接于所述第一控制信号，所述第五晶体管的源极电性连接于所述第一节点，所述第五晶体管的漏极电性连接于所述第三节点；
    所述第六晶体管的栅极电性连接于第四控制信号，所述第六晶体管的源极电性连接于所述第二节点，所述第六晶体管的漏极电性连接于所述第一节点；
    所述第七晶体管的栅极电性连接于第三控制信号，所述第七晶体管的源极电性连接于数据信号，所述第七晶体管的漏极电性连接于所述第三电容的第二端；所述第三电容的第一端电性连接于所述第一节点；
    所述第一电容的第一端电性连接于所述第二节点，所述第一电容的第二端电性连接于所述第四节点；
    所述第二电容的第一端电性连接于所述第一节点，所述第二电容的第二端电性连接于所述第三节点；
    所述发光器件的阳极端电性连接于所述第三节点，所述发光器件的阴极端电性连接于第二电源信号；
    所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管以及所述第七晶体管均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管；所述发光器件为有机发光二极管。
  2. 根据权利要求1所述的像素驱动电路，其中，所述第一控制信号、所述第二控制信号、所述第三控制信号以及所述第四控制信号相组合先后对应于初始化阶段、信号输入与阈值电压探测阶段、数据信号输入阶段、编程阶段以及发光阶段；其中，所述数据信号包括参考电位和显示电位，在所述初始化阶段和所述信号输入与阈值电压探测阶段，所述数据信号的电位为所述参考电位；在所述数据信号输入阶段，所述数据信号的电位为所述显示电位。
  3. 根据权利要求2所述的像素驱动电路，其中，在所述初始化阶段，所述第一控制信号为低电位，所述第二控制信号为高电位，所述第三控制信号为高电位，所述第四控制信号为高电位。
  4. 根据权利要求2所述的像素驱动电路，其中，在所述信号输入与阈值电压探测阶段，所述第一控制信号为低电位，所述第二控制信号为高电位，所述第三控制信号为高电位，所述第四控制信号为低电位。
  5. 根据权利要求2所述的像素驱动电路，其中，在所述数据信号输入阶段，所述第一控制信号为低电位，所述第二控制信号为高电位，所述第三控制信号为高电位，所述第四控制信号为低电位。
  6. 根据权利要求2所述的像素驱动电路，其中，在所述编程阶段，所述第一控制信号为低电位，所述第二控制信号为高电位，所述第三控制信号为低电位，所述第四控制信号为低电位。
  7. 根据权利要2所述的像素驱动电路，其中，在所述发光阶段，所述第一控制信号为高电位，所述第二控制信号为低电位，所述第三控制信号为低电位，所述第四控制信号为低电位。
  8. 一种像素驱动电路，其包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、第一电容、第二电容、第三电容以及发光器件；
    所述第一晶体管的栅极电性连接于第一节点，所述第一晶体管的源极电性连接于第二节点，所述第一晶体管的漏极电性连接于第三节点；
    所述第二晶体管的栅极电性连接于第一控制信号，所述第二晶体管的源极电性连接于所述第二节点，所述第二晶体管的漏极电性连接于所述第三节点；
    所述第三晶体管的栅极电性连接于第四节点，所述第三晶体管的源极电性连接于第一电源信号，所述第三晶体管的漏极电性连接于所述第二节点；
    所述第四晶体管的栅极电性连接于第二控制信号，所述第四晶体管的源极电性连接于所述第一电源信号，所述第四晶体管的漏极电性连接于所述第四节点；
    所述第五晶体管的栅极电性连接于所述第一控制信号，所述第五晶体管的源极电性连接于所述第一节点，所述第五晶体管的漏极电性连接于所述第三节点；
    所述第六晶体管的栅极电性连接于第四控制信号，所述第六晶体管的源极电性连接于所述第二节点，所述第六晶体管的漏极电性连接于所述第一节点；
    所述第七晶体管的栅极电性连接于第三控制信号，所述第七晶体管的源极电性连接于数据信号，所述第七晶体管的漏极电性连接于所述第三电容的第二端；所述第三电容的第一端电性连接于所述第一节点；
    所述第一电容的第一端电性连接于所述第二节点，所述第一电容的第二端电性连接于所述第四节点；
    所述第二电容的第一端电性连接于所述第一节点，所述第二电容的第二端电性连接于所述第三节点；
    所述发光器件的阳极端电性连接于所述第三节点，所述发光器件的阴极端电性连接于第二电源信号。
  9. 根据权利要求8所述的像素驱动电路，其中，所述第一控制信号、所述第二控制信号、所述第三控制信号以及所述第四控制信号相组合先后对应于初始化阶段、信号输入与阈值电压探测阶段、数据信号输入阶段、编程阶段以及发光阶段；其中，所述数据信号包括参考电位和显示电位，在所述初始化阶段和所述信号输入与阈值电压探测阶段，所述数据信号的电位为所述参考电位；在所述数据信号输入阶段，所述数据信号的电位为所述显示电位。
  10. 根据权利要求9所述的像素驱动电路，其中，在所述初始化阶段，所述第一控制信号为低电位，所述第二控制信号为高电位，所述第三控制信号为高电位，所述第四控制信号为高电位。
  11. 根据权利要求9所述的像素驱动电路，其中，在所述信号输入与阈值电压探测阶段，所述第一控制信号为低电位，所述第二控制信号为高电位，所述第三控制信号为高电位，所述第四控制信号为低电位。
  12. 根据权利要求9所述的像素驱动电路，其中，在所述数据信号输入阶段，所述第一控制信号为低电位，所述第二控制信号为高电位，所述第三控制信号为高电位，所述第四控制信号为低电位。
  13. 根据权利要求9所述的像素驱动电路，其中，在所述编程阶段，所述第一控制信号为低电位，所述第二控制信号为高电位，所述第三控制信号为低电位，所述第四控制信号为低电位。
  14. 根据权利要求9所述的像素驱动电路，其中，在所述发光阶段，所述第一控制信号为高电位，所述第二控制信号为低电位，所述第三控制信号为低电位，所述第四控制信号为低电位。
  15. 根据权利要求8所述的像素驱动电路，其中，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管以及所述第七晶体管均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管。
  16. 根据权利要求8所述的像素驱动电路，其中，所述发光器件为有机发光二极管。
  17. 一种显示面板，其包括像素驱动电路，所述像素驱动电路包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、第一电容、第二电容、第三电容以及发光器件；
    所述第一晶体管的栅极电性连接于第一节点，所述第一晶体管的源极电性连接于第二节点，所述第一晶体管的漏极电性连接于第三节点；
    所述第二晶体管的栅极电性连接于第一控制信号，所述第二晶体管的源极电性连接于所述第二节点，所述第二晶体管的漏极电性连接于所述第三节点；
    所述第三晶体管的栅极电性连接于第四节点，所述第三晶体管的源极电性连接于第一电源信号，所述第三晶体管的漏极电性连接于所述第二节点；
    所述第四晶体管的栅极电性连接于第二控制信号，所述第四晶体管的源极电性连接于所述第一电源信号，所述第四晶体管的漏极电性连接于所述第四节点；
    所述第五晶体管的栅极电性连接于所述第一控制信号，所述第五晶体管的源极电性连接于所述第一节点，所述第五晶体管的漏极电性连接于所述第三节点；
    所述第六晶体管的栅极电性连接于第四控制信号，所述第六晶体管的源极电性连接于所述第二节点，所述第六晶体管的漏极电性连接于所述第一节点；
    所述第七晶体管的栅极电性连接于第三控制信号，所述第七晶体管的源极电性连接于数据信号，所述第七晶体管的漏极电性连接于所述第三电容的第二端；所述第三电容的第一端电性连接于所述第一节点；
    所述第一电容的第一端电性连接于所述第二节点，所述第一电容的第二端电性连接于所述第四节点；
    所述第二电容的第一端电性连接于所述第一节点，所述第二电容的第二端电性连接于所述第三节点；
    所述发光器件的阳极端电性连接于所述第三节点，所述发光器件的阴极端电性连接于第二电源信号。
  18. 根据权利要求17所述的显示面板，其中，所述第一控制信号、所述第二控制信号、所述第三控制信号以及所述第四控制信号相组合先后对应于初始化阶段、信号输入与阈值电压探测阶段、数据信号输入阶段、编程阶段以及发光阶段；其中，所述数据信号包括参考电位和显示电位，在所述初始化阶段和所述信号输入与阈值电压探测阶段，所述数据信号的电位为所述参考电位；在所述数据信号输入阶段，所述数据信号的电位为所述显示电位。
  19. 根据权利要求18所述的显示面板，其中，在所述初始化阶段，所述第一控制信号为低电位，所述第二控制信号为高电位，所述第三控制信号为高电位，所述第四控制信号为高电位。
  20. 根据权利要求18所述的显示面板，其中，在所述信号输入与阈值电压探测阶段，所述第一控制信号为低电位，所述第二控制信号为高电位，所述第三控制信号为高电位，所述第四控制信号为低电位。
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