WO2016150087A1 - 像素电路及其驱动方法、显示装置 - Google Patents

像素电路及其驱动方法、显示装置 Download PDF

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Publication number
WO2016150087A1
WO2016150087A1 PCT/CN2015/087636 CN2015087636W WO2016150087A1 WO 2016150087 A1 WO2016150087 A1 WO 2016150087A1 CN 2015087636 W CN2015087636 W CN 2015087636W WO 2016150087 A1 WO2016150087 A1 WO 2016150087A1
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Prior art keywords
transistor
voltage
control
control point
signal terminal
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PCT/CN2015/087636
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English (en)
French (fr)
Inventor
马占洁
孙亮
Original Assignee
京东方科技集团股份有限公司
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Priority to US14/908,835 priority Critical patent/US10319302B2/en
Publication of WO2016150087A1 publication Critical patent/WO2016150087A1/zh

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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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    • G09G3/3241—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror
    • G09G3/325—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror the data current flowing through the driving transistor during a setting phase, e.g. by using a switch for connecting the driving transistor to the data driver
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
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    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
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Definitions

  • the present invention relates to the field of display, and in particular, to a pixel circuit, a driving method thereof, and a display device.
  • OLED Organic Light Emitting Diode
  • the OLED pixel circuit structure is a circuit structure in which a driving transistor controls a current to drive an organic light emitting diode to emit light.
  • the structure of the organic light emitting diode pixel circuit generally includes a module for compensating for the threshold voltage.
  • the OLED pixel circuit structure realizes compensation of the OLED pixel through the reset phase, the compensation potential writing phase and the light-emitting phase. In the compensation potential writing phase, the driving transistor connected to the OLED is discharged to be turned off, thereby discharging the driving transistor to Vth (threshold value) Voltage) potential.
  • the driving transistor is required to discharge in a short period of time, and the discharge of the driving transistor has a specific function relationship with time.
  • the short discharging time may cause the driving transistor to be incompletely discharged, so The preset display brightness of the organic light emitting diode is realized.
  • the present invention provides a pixel circuit, a driving method thereof, and a display device.
  • the technical solution is as follows:
  • a pixel circuit in a first aspect, includes: a reset module, a compensation module, an energy storage module, a driving module, a driving control module, a power supply module, and a lighting module,
  • the reset module is respectively connected to the first power signal end, the second power signal end, the first control signal end, the first control point and the second control point, and is configured to be used according to the control signal input by the first control signal end Writing an input voltage of the first power signal terminal to the second control point, and writing an input voltage of the second power signal terminal to the first control point;
  • the compensation module is respectively connected to the first control signal end, the third power signal end, and the third control point, and is configured to input the input voltage of the third power signal end according to the control signal input by the first control signal end Writing to the third control point;
  • the driving control module is respectively connected to the first power signal end, the second control signal end, the third control signal end, the data signal end, the second control point, and the fourth control point, according to the third Controlling a signal input by the signal terminal, writing an input voltage of the data signal end to the fourth control point;
  • the power supply module is respectively connected to the second power signal end, the second control signal end, and the first control point, and is configured to perform, according to the control signal input by the second control signal end, the first control Point providing a voltage of the first power signal terminal;
  • the driving module is respectively connected to the first control point, the third control point, and the fourth control point, for a voltage at the first control point, a voltage of the third control point, and the Discharging under the control of the voltage of the fourth control point;
  • the energy storage module is respectively connected to the first control point and the second control point for storing voltages of the first control point and the second control point;
  • the light emitting module is respectively connected to the third control point and the fourth power signal end for emitting light under the control of the third control point voltage and the fourth power signal terminal voltage;
  • the input voltage of the third power signal terminal is greater than a difference between an input voltage of the data signal terminal and a threshold voltage of the driving module, and is smaller than an input voltage of the second power signal terminal.
  • the reset module includes: a first transistor and a second transistor,
  • a first pole of the first transistor is connected to the first power signal terminal, a second pole of the first transistor is connected to the second control point, and a gate of the first transistor is connected to the first control signal end;
  • a first pole of the second transistor is connected to the second power signal terminal, a second pole of the second transistor is connected to the first control point, and a gate of the second transistor is connected to the first control signal end.
  • the compensation module includes: a third transistor,
  • a first pole of the third transistor is connected to the third power signal terminal, a second pole of the third transistor is connected to the third control point, and a gate of the third transistor is connected to the first control signal end.
  • the driving control module includes: a fourth transistor, a fifth transistor, and a sixth transistor.
  • a first pole of the fourth transistor is connected to the first power signal terminal, a second pole of the fourth transistor is connected to the second control point, and a gate of the fourth transistor is connected to the third control signal End
  • a first pole of the fifth transistor is connected to the second control point, a second pole of the fifth transistor is connected to the fourth control point, and a gate of the fifth transistor is connected to the second control signal end ;
  • the first pole of the sixth transistor is connected to the fourth control point, the second pole of the sixth transistor is connected to the data signal end, and the gate of the sixth transistor is connected to the third control signal end.
  • the power supply module includes: a seventh transistor,
  • a first pole of the seventh transistor is connected to the second power signal terminal, a second pole of the seventh transistor is connected to the first control point, and a gate of the seventh transistor is connected to the second control signal end.
  • the driving module includes: an eighth transistor, a threshold voltage of the driving module includes: a threshold voltage of the eighth transistor,
  • the first pole of the eighth transistor is connected to the first control point
  • the second pole of the eighth transistor is connected to the third control point
  • the gate of the eighth transistor is connected to the fourth control point.
  • the energy storage module includes: a capacitor,
  • One end of the capacitor is connected to the first control point, and the other end of the capacitor is connected to the second control point.
  • the light emitting module comprises: an organic light emitting diode,
  • One end of the organic light emitting diode is connected to the third control point, and the other end of the organic light emitting diode is connected to the fourth power signal end.
  • the first power signal end is grounded.
  • the transistors are all N-type transistors; or the transistors are P-type transistors.
  • the transistor when the transistor is a P-type transistor, the first source of the transistor is the source, and the second terminal of the transistor is the drain.
  • a pixel circuit driving method for the pixel circuit according to the first aspect, wherein the pixel circuit comprises: a reset module, a compensation module, an energy storage module, a driving module, a driving control module, and a power supply module. And a light emitting module, the pixel circuit driving method includes:
  • the first control signal terminal inputs a conduction control signal
  • the first power signal terminal inputs a first voltage
  • the second power signal terminal inputs a second voltage
  • the third power signal terminal inputs a third voltage, so that the first voltage is written a second control point, the second voltage is written to the first control point, and the third voltage is written to the third control point;
  • the first control signal terminal inputs a shutdown control signal
  • the third control signal terminal inputs a conduction control signal
  • the data signal terminal inputs a data voltage
  • the first power signal terminal inputs the first voltage, such that Writing the data voltage to the fourth control point, the first voltage is written into the second control point, and the driving module passes the control of the first control point voltage and the fourth control point voltage
  • the light emitting module performs discharging;
  • the third control signal terminal inputs a shutdown control signal
  • the second control signal terminal inputs a conduction control signal
  • the second power signal terminal inputs the second voltage, so that the second voltage is written into the first control Pointing, driving, by the current of the driving module, the light emitting module to emit light;
  • the third voltage is greater than a difference between the data voltage and a threshold voltage of the driving module, and is smaller than the second voltage.
  • the reset module includes: a first transistor and a second transistor
  • the compensation module includes: a third transistor
  • the driving control module includes: a fourth transistor, a fifth transistor, and a sixth transistor
  • the power supply includes: a seventh transistor
  • the driving module includes: an eighth transistor
  • a threshold voltage of the driving module includes: a threshold voltage of the eighth transistor
  • the energy storage module includes: a capacitor
  • the light emitting module includes: Organic light emitting diode
  • the fourth transistor and the sixth transistor are turned off; when the second control signal terminal inputs a conduction control signal, the fifth transistor and the The seventh transistor is turned on.
  • the first power signal end is grounded.
  • the transistors are all N-type transistors; or the transistors are P-type transistors.
  • the transistors are all P-type transistors
  • the first poles of the transistors are all sources
  • the second poles of the transistors are all drains.
  • the timing of the control signals includes:
  • the first control signal end inputs a low level
  • the second control signal end and the third control signal end inputs a high level
  • the first power signal end inputs the first voltage
  • the second power signal terminal inputs the second voltage
  • the third power signal terminal inputs the third voltage
  • the third voltage is greater than a threshold voltage of the eighth transistor and less than the second voltage
  • the third control signal terminal inputs a low level, the first control signal end and the second control signal end input a high level, and the data signal end inputs the data voltage, the first a power signal terminal inputs the first voltage;
  • the third stage the second control signal end inputs a low level, the first control signal end and the third control signal end inputs a high level, and the second power signal end inputs the second voltage.
  • a display device comprising the pixel circuit of the first aspect.
  • the present invention provides a pixel circuit, a driving method thereof, and a display device.
  • the input voltage of the second power signal terminal is written into the first control point by the reset module, and the compensation module writes the input voltage of the third power signal terminal to the third control point.
  • the driving control module writes the input voltage of the data signal end to the fourth control point, so that the driving module discharges under the control of the voltage of the first control point, the voltage of the third control point, and the voltage of the fourth control point, due to the third
  • the input voltage of the power signal terminal is greater than the difference between the input voltage of the data signal terminal and the threshold voltage of the driving module, and is smaller than the input voltage of the second power signal terminal.
  • the voltage of the driving module is pre-compensated according to the voltage pre-compensation principle, and the driving can be accelerated.
  • the speed at which the module discharges to the Vth potential reduces the time during which the drive module discharges to the Vth potential to ensure that the drive module is fully discharged in a short period of time.
  • FIG. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention.
  • FIG. 3 is a timing diagram of a control signal according to an embodiment of the present invention.
  • FIG. 4 is an equivalent circuit diagram of a pixel circuit according to an embodiment of the present invention.
  • FIG. 5 is an equivalent circuit diagram of another pixel circuit according to an embodiment of the present invention.
  • FIG. 6 is a circuit diagram of an equivalent circuit of a pixel circuit according to an embodiment of the present invention.
  • the transistors employed in all embodiments of the present invention may each be a thin film transistor or a field effect transistor or other device having the same characteristics, and the transistors employed in the embodiments of the present invention are mainly switching transistors according to their roles in the circuit. Since the source and drain of the switching transistor used here are symmetrical, the source and the drain are interchangeable. In the embodiment of the present invention, in order to distinguish the two poles of the transistor except the gate, the source is referred to as a first pole, and the drain is referred to as a second pole. According to the form in the drawing, the middle end of the transistor is the gate, the signal input end is the source, and the signal output end is the drain.
  • the switching transistor used in the embodiment of the present invention includes two types of a P-type switching transistor and an N-type switching transistor, wherein the P-type switching transistor is turned on when the gate is at a low level, and is turned off when the gate is at a high level, and the N-type switching transistor is turned off.
  • the driving transistor includes a P type and an N type, wherein the P type driving transistor has a low level at the gate voltage (the gate voltage is less than the source voltage), And the absolute value of the voltage difference of the gate source is greater than the threshold voltage in an amplified state or a saturated state; wherein the gate voltage of the N-type driving transistor is at a high level (the gate voltage is greater than the source voltage), and the gate source When the absolute value of the differential pressure is greater than the threshold voltage, it is in an amplified state or a saturated state.
  • an embodiment of the present invention provides a pixel circuit 00, which may include: a reset module 001, a compensation module 002, an energy storage module 003, a driving module 004, a driving control module 005, and a power supply module 006. And the light module 007.
  • the reset module 001 is respectively connected to the first power signal terminal VREF, the second power signal terminal VDD, the first control signal terminal Gn-1, the first control point A and the second control point B, according to the first control signal end
  • the control signal input by Gn-1 writes the input voltage of the first power signal terminal VREF to the second control point B, and writes the input voltage of the second power signal terminal VDD to the first control point A.
  • the compensation module 002 is connected to the first control signal terminal Gn-1, the third power signal terminal VINI and the third control point C, respectively, for using the third power signal terminal according to the control signal input by the first control signal terminal Gn-1.
  • the input voltage of the VINI is written to the third control point C.
  • the driving control module 005 is respectively connected to the first power signal terminal VREF, the second control signal terminal EM, the third control signal terminal Gn, the data signal terminal DATA, the second control point B and the fourth control point D, according to the third
  • the control signal input by the control signal terminal Gn writes the input voltage of the data signal terminal DATA to the fourth control point D.
  • the power supply module 006 is respectively connected to the second power signal terminal VDD, the second control signal terminal EM and the first control point A for providing the first power to the first control point A according to the control signal input by the second control signal terminal EM.
  • the voltage at the signal terminal VREF is respectively connected to the second power signal terminal VDD, the second control signal terminal EM and the first control point A for providing the first power to the first control point A according to the control signal input by the second control signal terminal EM.
  • the voltage at the signal terminal VREF The voltage at the signal terminal VREF.
  • the driving module 004 is connected to the first control point A, the third control point C and the fourth control point D, respectively, for the voltage at the first control point A, the voltage of the third control point C and the voltage of the fourth control point D Discharge under control.
  • the energy storage module 003 is connected to the first control point A and the second control point B, respectively, for storing voltages of the first control point A and the second control point B.
  • the light emitting module 007 is connected to the third control point C and the fourth power signal terminal VSS, respectively, for emitting light under the control of the third control point C voltage and the fourth power signal end VSS voltage.
  • the input voltage of the third power signal terminal VINI may be greater than the difference between the input voltage of the data signal terminal DATA and the threshold voltage of the driving module 004, and smaller than the input voltage of the second power signal terminal VDD.
  • the voltage pre-compensation principle refers to discharging the high voltage port to the low voltage port, so that the voltage of the high voltage port becomes a preset voltage, and it is assumed that before the high voltage port voltage is discharged, a voltage greater than the preset voltage and less than the high voltage port voltage is set at the low voltage port. The voltage at which the high voltage port voltage is discharged to the preset voltage is accelerated when the voltage of the high voltage port is discharged.
  • the voltage of the first control point A is the input voltage of the second power signal terminal VDD. If the driving module 004 is discharged to the threshold voltage, the voltage of the first control point A needs to be discharged to the input of the data signal terminal DATA.
  • the input voltage of the third power signal terminal VINI is greater than the difference between the input voltage of the data signal terminal DATA and the threshold voltage of the driving module 004, and is smaller than The input voltage of the second power signal terminal VDD.
  • the first control point A is a high voltage port
  • the third control point C is a low voltage port
  • the difference between the input voltage of the data signal terminal DATA and the threshold voltage of the driving module 004 is the first control point A discharge.
  • the preset voltage, the voltage on the third control point C is greater than the preset voltage, and is less than the high voltage port voltage. Therefore, when the driving module 004 is discharged to the threshold voltage, the first control point A
  • the speed at which the voltage is discharged to the preset voltage is increased, that is, the speed at which the driving module 004 is discharged to the threshold voltage is accelerated, and the time during which the driving module is discharged to the threshold voltage is reduced.
  • the input voltage of the second power signal terminal is written into the first control point by the reset module, and the compensation module writes the input voltage of the third power signal terminal to the third control point.
  • the driving control module writes the input voltage of the data signal end to the fourth control point, so that the driving module discharges under the control of the voltage of the first control point, the voltage of the third control point, and the voltage of the fourth control point, because the third power source
  • the input voltage of the signal terminal is greater than the difference between the input voltage of the data signal terminal and the threshold voltage of the driving module, and is smaller than the input voltage of the second power signal terminal.
  • the voltage of the driving module is pre-compensated according to the voltage pre-compensation principle, and the driving module can be accelerated.
  • the speed of discharge to the Vth potential reduces the time during which the drive module discharges to the Vth potential to ensure that the drive module is fully discharged in a short period of time.
  • the embodiment of the present invention provides another pixel circuit 00, which may include: a first transistor M1 and a second transistor M2.
  • the first pole of the first transistor M1 is connected to the first power signal terminal VREF
  • the second pole of the first transistor M1 is connected to the second control point B
  • the gate of the first transistor M1 is connected to the first control signal end. Gn-1.
  • the first electrode of the second transistor M2 is connected to the second power signal terminal VDD
  • the second electrode of the second transistor M2 is connected to the first control point A
  • the gate of the second transistor M2 is connected to the first control signal terminal Gn-1.
  • the compensation module 002 can include a third transistor M3.
  • the first pole of the third transistor M3 is connected to the third power signal terminal VINI
  • the second pole of the third transistor M3 is connected to the third control point C
  • the gate of the third transistor M3 is connected to the first control signal end. Gn-1.
  • the drive control module 005 can include a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6.
  • the first pole of the fourth transistor M4 is connected to the first power signal terminal VREF
  • the second pole of the fourth transistor M4 is connected to the second control point B
  • the gate of the fourth transistor M4 is connected to the third control signal end. Gn.
  • the first pole of the fifth transistor M5 is connected to the second control point B
  • the second pole of the fifth transistor M5 is connected to the fourth control point D
  • the gate of the fifth transistor M5 is connected to the second control signal terminal EM.
  • the first pole of the sixth transistor M6 is connected to the fourth control point D.
  • the second pole of the sixth transistor M6 is connected to the data signal terminal DATA
  • the gate of the sixth transistor M6 is connected to the third control signal terminal Gn.
  • the power supply module 006 can include a seventh transistor M7.
  • the first electrode of the seventh transistor M7 is connected to the second power signal terminal VDD, the second electrode of the seventh transistor M7 is connected to the first control point A, and the gate of the seventh transistor M7 is connected to the second control signal terminal EM.
  • the driving module 004 may include an eighth transistor M8.
  • the threshold voltage of the driving module 004 may include: a threshold voltage Vth of the eighth transistor M8.
  • the first pole of the eighth transistor M8 is connected to the first control point A
  • the second pole of the eighth transistor M8 is connected to the third control point C
  • the gate of the eighth transistor M8 is connected to the fourth control point D.
  • the energy storage module 003 can include a capacitor CST, one end of the capacitor CST is connected to the first control point A, and the other end of the capacitor CST is connected to the second control point B.
  • the light emitting module 007 may include an organic light emitting diode D1. One end of the organic light emitting diode D1 is connected to the third control point C, and the other end of the organic light emitting diode D1 is connected to the fourth power signal terminal VSS.
  • the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 may both be N.
  • Type transistors, or both P-type transistors when the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth
  • the transistor M8 is a P-type transistor
  • the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 a first extreme source
  • the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 The second is extremely drain.
  • the first power signal terminal VREF can be grounded. At this time, the input voltage of the first power signal terminal VREF is 0 volts.
  • the input voltage of the second power signal terminal is written into the first control point by the reset module, and the compensation module writes the input voltage of the third power signal terminal to the third control point.
  • the driving control module writes the input voltage of the data signal end to the fourth control point, so that the driving module discharges under the control of the voltage of the first control point, the voltage of the third control point, and the voltage of the fourth control point, because the third power source
  • the input voltage of the signal terminal is greater than the difference between the input voltage of the data signal terminal and the threshold voltage of the driving module, and is smaller than the input voltage of the second power signal terminal.
  • the voltage of the driving module is pre-compensated according to the voltage pre-compensation principle, and the driving module can be accelerated.
  • the speed of discharge to the Vth potential reduces the time during which the drive module discharges to the Vth potential to ensure that the drive module is fully discharged in a short period of time.
  • Embodiments of the present invention provide a pixel circuit driving method, and the pixel circuit driving method can be used
  • the pixel circuit 00 may include: a reset module 001, a compensation module 002, an energy storage module 003, a driving module 004, a driving control module 005, a power supply module 006, and a lighting module 007.
  • the pixel circuit driving method may include:
  • Step 301 The first control signal terminal Gn-1 inputs a conduction control signal, the first power signal terminal VREF inputs a first voltage, the second power signal terminal VDD inputs a second voltage, and the third power signal terminal VINI inputs a third voltage.
  • the first voltage is written to the second control point B, the second voltage is written to the first control point A, and the third voltage is written to the third control point C.
  • the third voltage is greater than a difference between the data voltage and the threshold voltage of the driving module 004, and is smaller than the second voltage.
  • Step 302 The first control signal terminal Gn-1 inputs a shutdown control signal, the third control signal terminal Gn inputs a conduction control signal, the data signal terminal DATA inputs a data voltage, and the first power signal terminal VREF inputs the first voltage, so that the data voltage
  • the fourth control point D is written, the first voltage is written to the second control point B, and the driving module 004 is discharged by the light emitting module 007 under the control of the first control point A voltage and the fourth control point D voltage.
  • Step 303 the third control signal terminal Gn inputs a shutdown control signal, the second control signal terminal EM inputs a conduction control signal, and the second power signal terminal VDD inputs a second voltage, so that the second voltage is written into the first control point A,
  • the current of the driving module 004 drives the light emitting module 007 to emit light.
  • the input voltage of the second power signal terminal is written into the first control point by the reset module, and the compensation module writes the input voltage of the third power signal terminal into the third control.
  • a driving control module writes an input voltage of the data signal end to the fourth control point, so that the driving module discharges under the control of the voltage of the first control point, the voltage of the third control point, and the voltage of the fourth control point,
  • the input voltage of the three power signal terminals is greater than the difference between the input voltage of the data signal terminal and the threshold voltage of the driving module, and is smaller than the input voltage of the second power signal terminal.
  • the voltage of the driving module is pre-compensated according to the voltage pre-compensation principle, which can be accelerated.
  • the speed at which the drive module discharges to the Vth potential reduces the time during which the drive module discharges to the Vth potential to ensure that the drive module is fully discharged in a short period of time.
  • the reset module 001 can include: a first transistor M1 and a second transistor M2, the compensation module 002 can include: a third transistor M3, the drive control module 005 can include: a fourth transistor M4
  • the power supply module 006 may include: a seventh transistor M7
  • the driving module 004 may include: an eighth transistor M8, wherein the threshold voltage of the driving module 004 may include: The threshold voltage Vth of the transistor M8, the energy storage module 003 may include: a capacitor CST, and the light emitting module 007 may include: an organic light emitting diode D1.
  • the first transistor M1, the second transistor M2, and the third transistor M3 are turned on.
  • the first control signal terminal Gn-1 inputs a shutdown control signal
  • the first transistor M1, the second transistor M2, and the third transistor M3 are turned off.
  • the fourth transistor M4 and the sixth transistor M6 are turned on.
  • the third control signal terminal Gn inputs a shutdown control signal
  • the fourth transistor M4 and the sixth transistor M6 are turned off.
  • the second control signal terminal EM inputs the conduction control signal
  • the fifth transistor M5 and the seventh transistor M7 are turned on.
  • the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 may both be N.
  • Type transistors, or both P-type transistors when the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth
  • the transistor M8 is a P-type transistor
  • the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 a first extreme source
  • the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 The second is extremely drain.
  • the timing of the control signals can include:
  • the first stage the first control signal terminal Gn-1 inputs a low level, the second control signal terminal EM and the third control signal terminal Gn input a high level, the first power signal terminal VREF inputs a first voltage, and the second power signal
  • the terminal VDD inputs a second voltage
  • the third power signal terminal VINI inputs a third voltage
  • the third voltage is greater than a threshold voltage of the eighth transistor M8 and smaller than the second voltage.
  • the second stage the third control signal terminal Gn inputs a low level, the first control signal terminal Gn-1 and the second control signal terminal EM input a high level, the data signal terminal DATA inputs a data voltage, and the first power signal terminal VREF inputs The first voltage.
  • the third stage the second control signal terminal EM inputs a low level, the first control signal terminal Gn-1 and the third control signal terminal Gn input a high level, and the second power signal terminal VDD inputs a second voltage.
  • the embodiment of the present invention uses the first transistor M1, the second transistor M2, and the third transistor M3.
  • the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 are all P-type transistors as an example.
  • the working process may be specifically It is divided into three phases, namely: reset phase, compensation potential writing phase and lighting phase.
  • FIG. 3 is a timing diagram of respective control signal lines during the operation of the pixel circuit shown in FIG. As shown in FIG. 3, the reset phase, the compensation potential writing phase, and the light-emitting phase are correspondingly represented by P1, P2, and P3, respectively, in FIG.
  • the P1 phase is a reset phase, and the equivalent circuit of this phase is as shown in FIG. 4 .
  • the first control signal terminal Gn-1 inputs a low level
  • the second control signal terminal EM and the third control signal terminal Gn input a high level
  • the first power signal terminal VREF is input to the first voltage Vref
  • the second power signal terminal VDD is input to the second voltage Vdd
  • the third power signal terminal VINI is input to the third voltage Vini
  • the third voltage Vini is greater than the threshold voltage Vth of the eighth transistor M8 and smaller than the second voltage Vdd.
  • the first transistor M1, the second transistor M2, and the third transistor M3 are turned on, the first voltage Vref input by the first power signal terminal VREF is written to the second control point B, and the second power signal terminal VDD is input second.
  • the voltage Vdd is written to the first control point A, and the third voltage Vini input by the third power signal terminal VINI is written to the third control point C.
  • the P2 phase is the compensation potential writing phase, and the equivalent circuit of this phase is shown in FIG. 5.
  • the third control signal terminal Gn inputs a low level
  • the first control signal terminal Gn-1 and the second control signal terminal EM input a high level
  • the data signal terminal DATA inputs a data voltage Data
  • a power signal terminal VREF is input to the first voltage Vref.
  • the fourth transistor M4 and the sixth transistor M6 are turned on, the first transistor M1, the second transistor M2, and the third transistor M3 are turned off, and the data voltage Data input by the data signal terminal DATA is written into the fourth control point D,
  • the first voltage Vref input by the power signal terminal VREF is written into the second control point B, so that the eighth transistor M8 is discharged through the organic light emitting diode D1 under the control of the voltage of the first control point A and the voltage of the fourth control point D. Until the eighth transistor M8 is turned off.
  • the voltage of the first control point A is the second voltage Vdd input by the second power signal terminal VDD
  • the voltage of the third control point C is the third voltage Vini input by the third power signal terminal VINI
  • the third voltage Vini input by the third power signal terminal VINI is greater than the threshold voltage Vth of the eighth transistor M8 and smaller than the second voltage Vdd input by the second power signal terminal VDD, therefore, the voltage of the first control point A and the third The voltage of the control point C can form a voltage difference, so that the first control point A is discharged to the third control point C, and the difference between the voltage of the first control point A and the voltage of the third control point C is smaller than the current There is a difference between the voltage of the first control point A and the voltage of the third control point C in the technology.
  • the voltage of the first control point A is determined by the second power signal compared to the prior art. End The second voltage Vdd of the VDD input becomes a faster speed of Data-Vth, and the required time is shorter, achieving the effect that the driving transistor is discharged to the Vth potential in a short time in the case of high resolution.
  • the potentials of the capacitor CST are respectively the voltage first voltage Vref of the second control point B and the voltage Data-Vth of the first control point A, and the voltage difference between the capacitor CST is Vref-(Data-Vth) .
  • the P3 phase is the lighting phase, and the equivalent circuit of this phase is shown in Figure 6.
  • the second control signal terminal EM inputs a low level
  • the first control signal terminal Gn-1 and the third control signal terminal Gn input a high level
  • the second power signal terminal VDD inputs a second voltage Vdd.
  • the fourth transistor M4 and the sixth transistor M6 are turned off
  • the fifth transistor M5 and the seventh transistor M7 are turned on
  • the second voltage Vdd input by the second power signal terminal VDD is written to the first control point A. Since the second voltage Vdd is written into the first control point A in the illuminating phase, the voltage of the first control point A is Vdd at this time.
  • the fifth transistor M5 is turned on such that the voltage of the second control point B and the voltage of the fourth control point D are equal, in order to keep the voltage difference across the capacitor CST from the voltage difference Vref- in the previous stage ( Data-Vth), the voltage of the second control point B and the voltage of the fourth control point D become Vdd+Vref-(Data-Vth), that is, the voltage of the gate of the eighth transistor M8 is Vdd+Vref-( Data-Vth), the voltage of the source of the eighth transistor M8 is the voltage Vdd of the first control point A.
  • the eighth transistor M8 since the eighth transistor M8 is in the saturation phase, the current flowing through the eighth transistor M8 is:
  • ⁇ is the carrier mobility of the eighth transistor M8
  • C is the capacitance of the gate insulating layer of the eighth transistor M8, and W/L is the aspect ratio of the eighth transistor M8.
  • the organic light emitting diode D1 is driven to emit light by the current of the eighth transistor M8.
  • the current flowing through the eighth transistor M8 is independent of the threshold voltage Vth and the voltage Vdd input by the second power signal terminal VDD, and only the data voltage Data input with the data signal terminal DATA And the first voltage Vref input by the first power signal terminal VREF is related to the situation that the discharge is incomplete due to the short discharge time of the eighth transistor M8, thereby causing the display brightness of the organic light emitting diode D1 to be different from the preset display brightness. , improve the display.
  • the first power signal terminal VREF can be grounded.
  • the first voltage Vref input by the first power signal terminal VREF is 0 volts, and flows through the eighth transistor M8 and the organic light emitting diode D1.
  • the current is only related to the data voltage Data input by the data signal terminal DATA, and the display brightness of the organic light emitting diode D1 caused by the first voltage Vref is prevented from being different from the preset display brightness, thereby further improving the display effect.
  • the third power signal terminal VINI and the pixel circuit cannot form a loop, the voltage drop caused by the third voltage Vini input by the third power signal terminal VINI is avoided.
  • the eighth transistor M8 is an example of a P-type transistor.
  • the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 may also adopt a P-type transistor.
  • the timing of the signal lines may be opposite to the timing of the respective control signal lines in FIG. 3 (ie, the phase difference between the two is 180 degrees).
  • the input voltage of the second power signal terminal is written into the first control point by the reset module, and the compensation module writes the input voltage of the third power signal terminal into the third control.
  • a driving control module writes an input voltage of the data signal end to the fourth control point, so that the driving module discharges under the control of the voltage of the first control point, the voltage of the third control point, and the voltage of the fourth control point,
  • the input voltage of the three power signal terminals is greater than the difference between the input voltage of the data signal terminal and the threshold voltage of the driving module, and is smaller than the input voltage of the second power signal terminal.
  • the voltage of the driving module is pre-compensated according to the voltage pre-compensation principle, which can be accelerated.
  • the speed at which the drive module discharges to the Vth potential reduces the time during which the drive module discharges to the Vth potential to ensure that the drive module is fully discharged in a short period of time.
  • the embodiment of the invention provides a display device, which may include a pixel circuit, and the pixel circuit may be the pixel circuit 00 shown in FIG. 1 or FIG.
  • the input voltage of the second power signal terminal is written into the first control point by the reset module, and the compensation module writes the input voltage of the third power signal terminal to the third control point.
  • the driving control module writes the input voltage of the data signal end to the fourth control point, so that the driving module discharges under the control of the voltage of the first control point, the voltage of the third control point, and the voltage of the fourth control point, because the third power source
  • the input voltage of the signal terminal is greater than the input voltage of the data signal terminal and the driving mode
  • the difference between the threshold voltage of the block is smaller than the input voltage of the second power signal terminal.
  • the voltage of the driving module is pre-compensated according to the voltage pre-compensation principle, which can speed up the discharge of the driving module to the Vth potential, and reduce the driving module.
  • the time to discharge to the Vth potential to ensure that the drive module is fully discharged in a short time.

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Abstract

一种像素电路(00)及其驱动方法、显示装置，解决了在短时间内将驱动晶体管放电至Vth电位的问题，能够保证驱动晶体管在短时间内完全放电。所述像素电路(00)包括：复位模块(001)、补偿模块(002)、储能模块(003)、驱动模块(004)、驱动控制模块(005)、供电模块(006)和发光模块(007)，第三电源信号端(VINI)的输入电压大于数据信号端(DATA)的输入电压与驱动模块(004)的阈值电压之差，且小于第二电源信号端(VDD)的输入电压。

Description

像素电路及其驱动方法、显示装置 技术领域
本发明涉及显示领域，特别涉及一种像素电路及其驱动方法、显示装置。
背景技术
随着显示技术的发展，有机发光二极管(Organic Light Emitting Diode；OLED)作为一种电流型发光器件，因其所具有的自发光、快速响应、宽视角和可制作在柔性衬底上等特点而越来越多地被应用于高性能显示领域当中。
OLED像素电路结构是一种通过驱动晶体管控制电流来驱动有机发光二极管进行发光的的电路结构。为了消除驱动晶体管的阈值电压不均匀造成的影响，通常有机发光二极管像素电路的结构还包括用于补偿阈值电压的模块。OLED像素电路结构通过复位阶段、补偿电位写入阶段和发光阶段实现OLED像素的补偿，在补偿电位写入阶段中，与OLED相连的驱动晶体管放电至关断，实现将驱动晶体管放电至Vth(阈值电压)电位。
但是，随着分辨率的提高，要求驱动晶体管在较短的时间内进行放电，而驱动晶体管的放电与时间存在特定的函数关系，放电时间较短会出现驱动晶体管放电不完全的现象，因此无法实现有机发光二极管的预设显示亮度。
发明内容
为了解决在短时间内将驱动晶体管放电至Vth电位的问题，本发明提供了一种像素电路及其驱动方法、显示装置。所述技术方案如下：
第一方面，提供了一种像素电路，所述像素电路包括:复位模块、补偿模块、储能模块、驱动模块、驱动控制模块、供电模块和发光模块，
所述复位模块分别连接第一电源信号端、第二电源信号端、第一控制信号端、第一控制点和第二控制点，用于根据所述第一控制信号端输入的控制信号，将所述第一电源信号端的输入电压写入所述第二控制点，将所述第二电源信号端的输入电压写入所述第一控制点；
所述补偿模块分别连接所述第一控制信号端、第三电源信号端和第三控制点，用于根据所述第一控制信号端输入的控制信号，将所述第三电源信号端的输入电压写入所述第三控制点；
所述驱动控制模块分别连接所述第一电源信号端、第二控制信号端、第三控制信号端、数据信号端、所述第二控制点和第四控制点，用于根据所述第三控制信号端输入的控制信号，将所述数据信号端的输入电压写入所述第四控制点；
所述供电模块分别连接所述第二电源信号端、所述第二控制信号端和所述第一控制点，用于根据所述第二控制信号端输入的控制信号，向所述第一控制点提供所述第一电源信号端的电压；
所述驱动模块分别连接所述第一控制点、所述第三控制点和所述第四控制点，用于在所述第一控制点的电压、所述第三控制点的电压和所述第四控制点的电压的控制下放电；
所述储能模块分别连接所述第一控制点和所述第二控制点，用于存储所述第一控制点和第二控制点的电压；
所述发光模块分别连接所述第三控制点和第四电源信号端，用于在所述第三控制点电压和所述第四电源信号端电压的控制下发光；
其中，所述第三电源信号端的输入电压大于所述数据信号端的输入电压与所述驱动模块的阈值电压之差，且小于所述第二电源信号端的输入电压。
可选的，所述复位模块包括：第一晶体管和第二晶体管，
所述第一晶体管的第一极连接所述第一电源信号端，所述第一晶体管的第二极连接所述第二控制点，所述第一晶体管的栅极连接所述第一控制信号端；
所述第二晶体管的第一极连接所述第二电源信号端，所述第二晶体管的第二极连接所述第一控制点，所述第二晶体管的栅极连接所述第一控制信号端。
可选的，所述补偿模块包括：第三晶体管，
所述第三晶体管的第一极连接所述第三电源信号端，所述第三晶体管的第二极连接所述第三控制点，所述第三晶体管的栅极连接所述第一控制信号端。
可选的，所述驱动控制模块包括：第四晶体管、第五晶体管和第六晶体管，
所述第四晶体管的第一极连接所述第一电源信号端，所述第四晶体管的第二极连接所述第二控制点，所述第四晶体管的栅极连接所述第三控制信号端；
所述第五晶体管的第一极连接所述第二控制点，所述第五晶体管的第二极连接所述第四控制点，所述第五晶体管的栅极连接所述第二控制信号端；
所述第六晶体管的第一极连接所述第四控制点，所述第六晶体管的第二极连接数据信号端，所述第六晶体管的栅极连接所述第三控制信号端。
可选的，所述供电模块包括：第七晶体管，
所述第七晶体管的第一极连接所述第二电源信号端，所述第七晶体管的第二极连接所述第一控制点，所述第七晶体管的栅极连接所述第二控制信号端。
可选的，所述驱动模块包括：第八晶体管，所述驱动模块的阈值电压包括：所述第八晶体管的阈值电压，
所述第八晶体管的第一极连接所述第一控制点，所述第八晶体管的第二极连接所述第三控制点，所述第八晶体管的栅极连接所述第四控制点。
可选的，所述储能模块包括：电容，
所述电容的一端连接所述第一控制点，所述电容的另一端连接所述第二控制点。
可选的，所述发光模块包括：有机发光二极管，
所述有机发光二极管的一端连接所述第三控制点，所述有机发光二极管的另一端连接所述第四电源信号端。
可选的，所述第一电源信号端接地。
可选的，所述晶体管均为N型晶体管；或者所述晶体管均为P型晶体管。
可选的，当所述晶体管为P型晶体管时，所述晶体管的第一极为源极，所述晶体管的第二极为漏极。
第二方面，提供了一种像素电路驱动方法，用于如第一方面所述的像素电路，所述像素电路包括:复位模块、补偿模块、储能模块、驱动模块、驱动控制模块、供电模块和发光模块，所述像素电路驱动方法包括：
第一控制信号端输入导通控制信号，第一电源信号端输入第一电压，第二电源信号端输入第二电压，第三电源信号端输入第三电压，使得所述第一电压写入第二控制点，所述第二电压写入第一控制点，所述第三电压写入第三控制点；
所述第一控制信号端输入关闭控制信号，第三控制信号端输入导通控制信号，数据信号端输入数据电压，所述第一电源信号端输入所述第一电压，使得 所述数据电压写入第四控制点，所述第一电压写入所述第二控制点，所述驱动模块在所述第一控制点电压和所述第四控制点电压的控制下通过所述发光模块进行放电；
所述第三控制信号端输入关闭控制信号，第二控制信号端输入导通控制信号，所述第二电源信号端输入所述第二电压，使得所述第二电压写入所述第一控制点，通过所述驱动模块的电流驱动所述发光模块发光；
其中，所述第三电压大于所述数据电压与所述驱动模块的阈值电压之差，且小于所述第二电压。
可选的，所述复位模块包括：第一晶体管和第二晶体管，所述补偿模块包括：第三晶体管，所述驱动控制模块包括：第四晶体管、第五晶体管和第六晶体管，所述供电模块包括：第七晶体管，所述驱动模块包括：第八晶体管，所述驱动模块的阈值电压包括：所述第八晶体管的阈值电压，所述储能模块包括：电容，所述发光模块包括：有机发光二极管，
当所述第一控制信号端输入导通控制信号时，所述第一晶体管、所述第二晶体管和所述第三晶体管导通；
当所述第一控制信号端输入关闭控制信号时，所述第一晶体管、所述第二晶体管和所述第三晶体管关闭；
当所述第三控制信号端输入导通控制信号时，所述第四晶体管和所述第六晶体管导通；
当所述第三控制信号端输入关闭控制信号时，所述第四晶体管和所述第六晶体管关闭；当所述第二控制信号端输入导通控制信号时，所述第五晶体管和所述第七晶体管导通。
可选的，所述第一电源信号端接地。
可选的，所述晶体管均为N型晶体管；或者所述晶体管均为P型晶体管。
可选的，当所述晶体管均为P型晶体管时，所述晶体管的第一极均为源极，所述晶体管的第二极均为漏极。
可选的，当所述晶体管均为P型晶体管时，控制信号的时序包括：
第一阶段：所述第一控制信号端输入低电平，所述第二控制信号端和所述第三控制信号端输入高电平，所述第一电源信号端输入所述第一电压，所述第二电源信号端输入所述第二电压，所述第三电源信号端输入所述第三电压，所 述第三电压大于所述第八晶体管的阈值电压，且小于所述第二电压；
第二阶段：所述第三控制信号端输入低电平，所述第一控制信号端和所述第二控制信号端输入高电平，所述数据信号端输入所述数据电压，所述第一电源信号端输入所述第一电压；
第三阶段：所述第二控制信号端输入低电平，所述第一控制信号端和所述第三控制信号端输入高电平，所述第二电源信号端输入所述第二电压。
第三方面，提供了一种显示装置，包括第一方面所述的像素电路。
本发明提供了一种像素电路及其驱动方法、显示装置，通过复位模块将第二电源信号端的输入电压写入第一控制点，补偿模块将第三电源信号端的输入电压写入第三控制点，驱动控制模块将数据信号端的输入电压写入第四控制点，使得该驱动模块在第一控制点的电压、第三控制点的电压和第四控制点的电压的控制下放电，由于第三电源信号端的输入电压大于数据信号端的输入电压与驱动模块的阈值电压之差，且小于第二电源信号端的输入电压，所以，根据电压预补偿原理对驱动模块的电压进行了预补偿，可以加快驱动模块放电到Vth电位的速度，减小了驱动模块放电至Vth电位的时间，以保证驱动模块在短时间内完全放电。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本发明。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明实施例提供的一种像素电路的结构示意图；
图2是本发明实施例提供的另一种像素电路的结构示意图；
图3是本发明实施例提供的一种控制信号的时序图；
图4是本发明实施例提供的一种像素电路的等效电路图；
图5是本发明实施例提供的另一种像素电路的等效电路图；
图6为本发明实施例提供的又一种像素电路等效电路图。
通过上述附图，已示出本发明明确的实施例，后文中将有更详细的描述。这些附图和文字描述并不是为了通过任何方式限制本发明构思的范围，而是通过参考特定实施例为本领域技术人员说明本发明的概念。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明实施方式作进一步地详细描述。
本发明所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件，根据在电路中的作用本发明的实施例所采用的晶体管主要为开关晶体管。由于这里采用的开关晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本发明实施例中，为区分晶体管除栅极之外的两极，将其中源极称为第一极，漏极称为第二极。按附图中的形态规定晶体管的中间端为栅极、信号输入端为源极、信号输出端为漏极。此外本发明实施例所采用的开关晶体管包括P型开关晶体管和N型开关晶体管两种，其中，P型开关晶体管在栅极为低电平时导通，在栅极为高电平时截止，N型开关晶体管为在栅极为高电平时导通，在栅极为低电平时截止；驱动晶体管包括P型和N型，其中P型驱动晶体管在栅极电压为低电平(栅极电压小于源极电压)，且栅极源极的压差的绝对值大于阈值电压时处于放大状态或饱和状态；其中N型驱动晶体管的栅极电压为高电平(栅极电压大于源极电压)，且栅极源极的压差的绝对值大于阈值电压时处于放大状态或饱和状态。
如图1所示，本发明实施例提供了一种像素电路00，该像素电路00可以包括:复位模块001、补偿模块002、储能模块003、驱动模块004、驱动控制模块005、供电模块006和发光模块007。
该复位模块001分别连接第一电源信号端VREF、第二电源信号端VDD、第一控制信号端Gn-1、第一控制点A和第二控制点B，用于根据该第一控制信号端Gn-1输入的控制信号，将第一电源信号端VREF的输入电压写入第二控制点B，将第二电源信号端VDD的输入电压写入第一控制点A。
该补偿模块002分别连接第一控制信号端Gn-1、第三电源信号端VINI和第三控制点C，用于根据第一控制信号端Gn-1输入的控制信号，将第三电源信号端VINI的输入电压写入第三控制点C。
该驱动控制模块005分别连接第一电源信号端VREF、第二控制信号端EM、第三控制信号端Gn、数据信号端DATA、第二控制点B和第四控制点D，用于根据第三控制信号端Gn输入的控制信号，将数据信号端DATA的输入电压写入第四控制点D。
该供电模块006分别连接第二电源信号端VDD、第二控制信号端EM和第一控制点A，用于根据第二控制信号端EM输入的控制信号，向第一控制点A提供第一电源信号端VREF的电压。
该驱动模块004分别连接第一控制点A、第三控制点C和第四控制点D，用于在第一控制点A的电压、第三控制点C的电压和第四控制点D的电压的控制下放电。
该储能模块003分别连接第一控制点A和第二控制点B，用于存储第一控制点A和第二控制点B的电压。
该发光模块007分别连接第三控制点C和第四电源信号端VSS，用于在第三控制点C电压和第四电源信号端VSS电压的控制下发光。
需要说明的是，该第三电源信号端VINI的输入电压可以大于数据信号端DATA的输入电压与驱动模块004的阈值电压之差，且小于第二电源信号端VDD的输入电压。
电压预补偿原理指的是高压端口向低压端口放电，使得该高压端口的电压变为预设电压，假设在该高压端口电压放电之前，在该低压端口设置一个大于预设电压且小于高压端口电压的电压，在该高压端口电压放电时，该高压端口电压放电至预设电压的速度就会加快。在本发明实施例中，第一控制点A的电压为第二电源信号端VDD的输入电压，若驱动模块004放电至阈值电压，第一控制点A的电压需放电至数据信号端DATA的输入电压与驱动模块004的阈值电压之差。将该第三电源信号端VINI的输入电压写入该第三控制点C，该第三电源信号端VINI的输入电压大于数据信号端DATA的输入电压与驱动模块004的阈值电压之差，且小于第二电源信号端VDD的输入电压。
根据电压预补偿原理，该第一控制点A为高压端口，该第三控制点C为低压端口，数据信号端DATA的输入电压与驱动模块004的阈值电压之差为该第一控制点A放电的预设电压，该第三控制点C上的电压大于该预设电压，且小于高压端口电压。所以，在该驱动模块004放电至阈值电压时，该第一控制点A 放电至预设电压的速度就会加快，即加快了该驱动模块004放电到阈值电压的速度，减小了驱动模块放电至阈值电压的时间。
综上所述，本发明实施例提供的像素电路中，通过复位模块将第二电源信号端的输入电压写入第一控制点，补偿模块将第三电源信号端的输入电压写入第三控制点，驱动控制模块将数据信号端的输入电压写入第四控制点，使得该驱动模块在第一控制点的电压、第三控制点的电压和第四控制点的电压的控制下放电，由于第三电源信号端的输入电压大于数据信号端的输入电压与驱动模块的阈值电压之差，且小于第二电源信号端的输入电压，所以，根据电压预补偿原理对驱动模块的电压进行了预补偿，可以加快驱动模块放电到Vth电位的速度，减小了驱动模块放电至Vth电位的时间，以保证驱动模块在短时间内完全放电。
进一步的，如图2所示，本发明实施例提供了另一种像素电路00，该复位模块001可以包括：第一晶体管M1和第二晶体管M2。具体的，该第一晶体管M1的第一极连接第一电源信号端VREF，该第一晶体管M1的第二极连接第二控制点B，该第一晶体管M1的栅极连接第一控制信号端Gn-1。第二晶体管M2的第一极连接第二电源信号端VDD，第二晶体管M2的第二极连接第一控制点A，第二晶体管M2的栅极连接第一控制信号端Gn-1。
该补偿模块002可以包括：第三晶体管M3。示例的，该第三晶体管M3的第一极连接第三电源信号端VINI，该第三晶体管M3的第二极连接第三控制点C，该第三晶体管M3的栅极连接第一控制信号端Gn-1。
该驱动控制模块005可以包括：第四晶体管M4、第五晶体管M5和第六晶体管M6。具体的，该第四晶体管M4的第一极连接第一电源信号端VREF，该第四晶体管M4的第二极连接第二控制点B，该第四晶体管M4的栅极连接第三控制信号端Gn。该第五晶体管M5的第一极连接第二控制点B，该第五晶体管M5的第二极连接第四控制点D，该第五晶体管M5的栅极连接第二控制信号端EM。该第六晶体管M6的第一极连接第四控制点D，该第六晶体管M6的第二极连接数据信号端DATA，该第六晶体管M6的栅极连接第三控制信号端Gn。
该供电模块006可以包括：第七晶体管M7。该第七晶体管M7的第一极连接第二电源信号端VDD，该第七晶体管M7的第二极连接第一控制点A，该第七晶体管M7的栅极连接第二控制信号端EM。
该驱动模块004可以包括：第八晶体管M8，此时，该驱动模块004的阈值电压可以包括：该第八晶体管M8的阈值电压Vth。具体的，该第八晶体管M8的第一极连接第一控制点A，该第八晶体管M8的第二极连接第三控制点C，该第八晶体管M8的栅极连接第四控制点D。
该储能模块003可以包括：电容CST，该电容CST的一端连接第一控制点A，该电容CST的另一端连接第二控制点B。
该发光模块007可以包括：有机发光二极管D1，该有机发光二极管D1的一端连接第三控制点C，该有机发光二极管D1的另一端连接第四电源信号端VSS。
需要说明的是，该第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4、第五晶体管M5、第六晶体管M6、第七晶体管M7和该第八晶体管M8可以均为N型晶体管，或者均为P型晶体管，当该第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4、第五晶体管M5、第六晶体管M6、第七晶体管M7和该第八晶体管M8均为P型晶体管时，该第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4、第五晶体管M5、第六晶体管M6、第七晶体管M7和该第八晶体管M8的第一极为源极，该第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4、第五晶体管M5、第六晶体管M6、第七晶体管M7和该第八晶体管M8的第二极为漏极。
可选的，可以将该第一电源信号端VREF接地，此时，该第一电源信号端VREF的输入电压为0伏，
综上所述，本发明实施例提供的像素电路中，通过复位模块将第二电源信号端的输入电压写入第一控制点，补偿模块将第三电源信号端的输入电压写入第三控制点，驱动控制模块将数据信号端的输入电压写入第四控制点，使得该驱动模块在第一控制点的电压、第三控制点的电压和第四控制点的电压的控制下放电，由于第三电源信号端的输入电压大于数据信号端的输入电压与驱动模块的阈值电压之差，且小于第二电源信号端的输入电压，所以，根据电压预补偿原理对驱动模块的电压进行了预补偿，可以加快驱动模块放电到Vth电位的速度，减小了驱动模块放电至Vth电位的时间，以保证驱动模块在短时间内完全放电。
本发明实施例提供了一种像素电路驱动方法，该像素电路驱动方法可以用 于驱动图1或图2所示的像素电路00，该像素电路00可以包括:复位模块001、补偿模块002、储能模块003、驱动模块004、驱动控制模块005、供电模块006和发光模块007，该像素电路驱动方法可以包括：
步骤301、第一控制信号端Gn-1输入导通控制信号，第一电源信号端VREF输入第一电压，第二电源信号端VDD输入第二电压，第三电源信号端VINI输入第三电压，使得第一电压写入第二控制点B，第二电压写入第一控制点A，第三电压写入第三控制点C。其中，第三电压大于数据电压与驱动模块004的阈值电压之差，且小于第二电压。
步骤302、第一控制信号端Gn-1输入关闭控制信号，第三控制信号端Gn输入导通控制信号，数据信号端DATA输入数据电压，第一电源信号端VREF输入第一电压，使得数据电压写入第四控制点D，第一电压写入第二控制点B，驱动模块004在第一控制点A电压和第四控制点D电压的控制下通过发光模块007进行放电。
步骤303、第三控制信号端Gn输入关闭控制信号，第二控制信号端EM输入导通控制信号，第二电源信号端VDD输入第二电压，使得第二电压写入第一控制点A，通过驱动模块004的电流驱动发光模块007发光。
综上所述，本发明实施例提供的像素电路驱动方法中，通过复位模块将第二电源信号端的输入电压写入第一控制点，补偿模块将第三电源信号端的输入电压写入第三控制点，驱动控制模块将数据信号端的输入电压写入第四控制点，使得该驱动模块在第一控制点的电压、第三控制点的电压和第四控制点的电压的控制下放电，由于第三电源信号端的输入电压大于数据信号端的输入电压与驱动模块的阈值电压之差，且小于第二电源信号端的输入电压，所以，根据电压预补偿原理对驱动模块的电压进行了预补偿，可以加快驱动模块放电到Vth电位的速度，减小了驱动模块放电至Vth电位的时间，以保证驱动模块在短时间内完全放电。
示例的，如图2所示，该复位模块001可以包括：第一晶体管M1和第二晶体管M2，该补偿模块002可以包括：第三晶体管M3，该驱动控制模块005可以包括：第四晶体管M4、第五晶体管M5和第六晶体管M6，该供电模块006可以包括：第七晶体管M7，该驱动模块004可以包括：第八晶体管M8，此时，该驱动模块004的阈值电压可以包括：第八晶体管M8的阈值电压Vth，该储能模块 003可以包括：电容CST，该发光模块007可以包括：有机发光二极管D1。
当该第一控制信号端Gn-1输入导通控制信号时，该第一晶体管M1、该第二晶体管M2和该第三晶体管M3导通。当该第一控制信号端Gn-1输入关闭控制信号时，该第一晶体管M1、该第二晶体管M2和该第三晶体管M3关闭。当该第三控制信号端Gn输入导通控制信号时，该第四晶体管M4和第六晶体管M6导通。当该第三控制信号端Gn输入关闭控制信号时，该第四晶体管M4和第六晶体管M6关闭。当该第二控制信号端EM输入导通控制信号时，该第五晶体管M5和第七晶体管M7导通。
需要说明的是，该第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4、第五晶体管M5、第六晶体管M6、第七晶体管M7和该第八晶体管M8可以均为N型晶体管，或者均为P型晶体管，当该第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4、第五晶体管M5、第六晶体管M6、第七晶体管M7和该第八晶体管M8均为P型晶体管时，该第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4、第五晶体管M5、第六晶体管M6、第七晶体管M7和该第八晶体管M8的第一极为源极，该第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4、第五晶体管M5、第六晶体管M6、第七晶体管M7和该第八晶体管M8的第二极为漏极。
当该第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4、第五晶体管M5、第六晶体管M6、第七晶体管M7和该第八晶体管M8均为P型晶体管时，该控制信号的时序可以包括：
第一阶段：第一控制信号端Gn-1输入低电平，第二控制信号端EM和第三控制信号端Gn输入高电平，第一电源信号端VREF输入第一电压，第二电源信号端VDD输入第二电压，第三电源信号端VINI输入第三电压，第三电压大于第八晶体管M8的阈值电压，且小于第二电压。
第二阶段：第三控制信号端Gn输入低电平，第一控制信号端Gn-1和第二控制信号端EM输入高电平，数据信号端DATA输入数据电压，第一电源信号端VREF输入第一电压。
第三阶段：第二控制信号端EM输入低电平，第一控制信号端Gn-1和第三控制信号端Gn输入高电平，第二电源信号端VDD输入第二电压。
具体的，本发明实施例以第一晶体管M1、第二晶体管M2、第三晶体管M3、 第四晶体管M4、第五晶体管M5、第六晶体管M6、第七晶体管M7和该第八晶体管M8均为P型晶体管为例，在图2所示的像素电路的工作时，其工作过程具体可以分为三个阶段，分别为：复位阶段、补偿电位写入阶段以及发光阶段。图3是图2所示像素电路工作过程中各个控制信号线的时序图。如图3所示，在图3中分别用P1、P2和P3来相应地表示复位阶段、补偿电位写入阶段以及发光阶段。
具体的，P1阶段为复位阶段，该阶段的等效电路如图4所示。在该复位阶段中，第一控制信号端Gn-1输入低电平，第二控制信号端EM和第三控制信号端Gn输入高电平，第一电源信号端VREF输入第一电压Vref，第二电源信号端VDD输入第二电压Vdd，第三电源信号端VINI输入第三电压Vini，第三电压Vini大于第八晶体管M8的阈值电压Vth，且小于第二电压Vdd。此时，第一晶体管M1、第二晶体管M2和第三晶体管M3导通，第一电源信号端VREF输入的第一电压Vref写入第二控制点B，第二电源信号端VDD输入的第二电压Vdd写入第一控制点A，第三电源信号端VINI输入的第三电压Vini写入第三控制点C。
P2阶段为补偿电位写入阶段，该阶段的等效电路如图5所示。在该补偿电位写入阶段中，第三控制信号端Gn输入低电平，第一控制信号端Gn-1和第二控制信号端EM输入高电平，数据信号端DATA输入数据电压Data，第一电源信号端VREF输入第一电压Vref。此时，第四晶体管M4和第六晶体管M6导通，第一晶体管M1、第二晶体管M2和第三晶体管M3关断，数据信号端DATA输入的数据电压Data写入第四控制点D，第一电源信号端VREF输入的第一电压Vref写入第二控制点B，使得第八晶体管M8在第一控制点A电压和第四控制点D电压的控制下通过该有机发光二极管D1进行放电，直至该第八晶体管M8关断。
第一控制点A的电压为该第二电源信号端VDD输入的第二电压Vdd，第三控制点C的电压为该第三电源信号端VINI输入的第三电压Vini，由于在复位阶段中，第三电源信号端VINI输入的第三电压Vini大于该第八晶体管M8的阈值电压Vth，且小于第二电源信号端VDD输入的第二电压Vdd，因此，第一控制点A的电压和第三控制点C的电压能够形成电压差，使得利于第一控制点A向第三控制点C放电，且该第一控制点A的电压和第三控制点C的电压之间的差值，小于现有技术中第一控制点A的电压与第三控制点C的电压之间的差值，根据电压预补偿原理，相较于现有技术，该第一控制点A的电压由第二电源信号端 VDD输入的第二电压Vdd变为Data-Vth的速度更快，所需的时间更短，实现了在高分辨率的情况下，驱动晶体管在短时间内放电至Vth电位的效果。此时，该电容CST两端的电位分别为第二控制点B的电压第一电压Vref和第一控制点A的电压Data-Vth，该电容CST两端的电压差值为Vref-(Data-Vth)。
P3阶段为发光阶段，该阶段的等效电路如图6所示。在该发光阶段中，第二控制信号端EM输入低电平，第一控制信号端Gn-1和第三控制信号端Gn输入高电平，第二电源信号端VDD输入第二电压Vdd，此时，第四晶体管M4和第六晶体管M6关断，第五晶体管M5和第七晶体管M7导通，第二电源信号端VDD输入的第二电压Vdd写入第一控制点A。由于该发光阶段中该第二电压Vdd写入第一控制点A，所以，此时该第一控制点A的电压为Vdd。该第五晶体管M5的导通，使得该第二控制点B的电压和该第四控制点D的电压相等，为了使得电容CST两端的电压差值保持上一阶段中的电压差值Vref-(Data-Vth)，该第二控制点B的电压和该第四控制点D的电压变为Vdd+Vref-(Data-Vth)，即该第八晶体管M8栅极的电压为Vdd+Vref-(Data-Vth)，该第八晶体管M8源极的电压为该第一控制点A的电压Vdd，此时，由于该第八晶体管M8处于饱和阶段，流经该第八晶体管M8的电流为：
Figure PCTCN2015087636-appb-000001
其中，
Figure PCTCN2015087636-appb-000002
具体的，μ为该第八晶体管M8的载流子迁移率，C为该第八晶体管M8的栅极绝缘层的电容，W/L为该第八晶体管M8的宽长比。通过该第八晶体管M8的电流驱动该有机发光二极管D1发光。由此可见，在有机发光二极管D1正常工作时，流经该第八晶体管M8的电流与其阈值电压Vth和第二电源信号端VDD输入的电压Vdd无关，仅仅与数据信号端DATA输入的数据电压Data以及第一电源信号端VREF输入的第一电压Vref有关，避免了由于第八晶体管M8的放电时间较短而出现放电不完全、进而导致有机发光二极管D1的显示亮度不同于预设显示亮度的情况，提高显示效果。
可选的，可以将该第一电源信号端VREF接地，此时，该第一电源信号端VREF输入的第一电压Vref为0伏，流经该第八晶体管M8和该有机发光二极管D1的 电流仅仅与数据信号端DATA输入的数据电压Data相关，避免了该第一电压Vref引起的该有机发光二极管D1的显示亮度不同于预设显示亮度的情况，进一步的提高了显示效果。示例的，由于该第三电源信号端VINI与该像素电路无法构成回路，所以，避免了由于该第三电源信号端VINI输入的第三电压Vini引起的压降问题。
需要说明的是，在上述实施例中，均是以第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4、第五晶体管M5、第六晶体管M6、第七晶体管M7和该第八晶体管M8为P型晶体管为例进行的说明。当然，该第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4、第五晶体管M5、第六晶体管M6、第七晶体管M7和该第八晶体管M8还可以采用P型晶体管，当第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4、第五晶体管M5、第六晶体管M6、第七晶体管M7和该第八晶体管M8为P型晶体管时，该各个控制信号线的时序可以与图3中各个控制信号线的时序相反(即二者的相位差为180度)。
综上所述，本发明实施例提供的像素电路驱动方法中，通过复位模块将第二电源信号端的输入电压写入第一控制点，补偿模块将第三电源信号端的输入电压写入第三控制点，驱动控制模块将数据信号端的输入电压写入第四控制点，使得该驱动模块在第一控制点的电压、第三控制点的电压和第四控制点的电压的控制下放电，由于第三电源信号端的输入电压大于数据信号端的输入电压与驱动模块的阈值电压之差，且小于第二电源信号端的输入电压，所以，根据电压预补偿原理对驱动模块的电压进行了预补偿，可以加快驱动模块放电到Vth电位的速度，减小了驱动模块放电至Vth电位的时间，以保证驱动模块在短时间内完全放电。
本发明实施例提供了一种显示装置，该显示装置可以包括像素电路，该像素电路可以为图1或图2所示的像素电路00。
综上所述，本发明实施例提供的显示装置中，通过复位模块将第二电源信号端的输入电压写入第一控制点，补偿模块将第三电源信号端的输入电压写入第三控制点，驱动控制模块将数据信号端的输入电压写入第四控制点，使得该驱动模块在第一控制点的电压、第三控制点的电压和第四控制点的电压的控制下放电，由于第三电源信号端的输入电压大于数据信号端的输入电压与驱动模 块的阈值电压之差，且小于第二电源信号端的输入电压，所以，根据电压预补偿原理对驱动模块的电压进行了预补偿，可以加快驱动模块放电到Vth电位的速度，减小了驱动模块放电至Vth电位的时间，以保证驱动模块在短时间内完全放电。
以上所述仅为本发明的较佳实施例，并不用以限制本发明，凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (15)

  1. 一种像素电路，其特征在于，所述像素电路包括:复位模块、补偿模块、储能模块、驱动模块、驱动控制模块、供电模块和发光模块，
    所述复位模块分别连接第一电源信号端、第二电源信号端、第一控制信号端、第一控制点和第二控制点，用于根据所述第一控制信号端输入的控制信号，将所述第一电源信号端的输入电压写入所述第二控制点，将所述第二电源信号端的输入电压写入所述第一控制点；
    所述补偿模块分别连接所述第一控制信号端、第三电源信号端和第三控制点，用于根据所述第一控制信号端输入的控制信号，将所述第三电源信号端的输入电压写入所述第三控制点；
    所述驱动控制模块分别连接所述第一电源信号端、第二控制信号端、第三控制信号端、数据信号端、所述第二控制点和第四控制点，用于根据所述第三控制信号端输入的控制信号，将所述数据信号端的输入电压写入所述第四控制点；
    所述供电模块分别连接所述第二电源信号端、所述第二控制信号端和所述第一控制点，用于根据所述第二控制信号端输入的控制信号，向所述第一控制点提供所述第一电源信号端的电压；
    所述驱动模块分别连接所述第一控制点、所述第三控制点和所述第四控制点，用于在所述第一控制点的电压、所述第三控制点的电压和所述第四控制点的电压的控制下放电；
    所述储能模块分别连接所述第一控制点和所述第二控制点，用于存储所述第一控制点和第二控制点的电压；
    所述发光模块分别连接所述第三控制点和第四电源信号端，用于在所述第三控制点电压和所述第四电源信号端电压的控制下发光；
    其中，所述第三电源信号端的输入电压大于所述数据信号端的输入电压与所述驱动模块的阈值电压之差，且小于所述第二电源信号端的输入电压。
  2. 根据权利要求1所述的像素电路，其特征在于，
    所述复位模块包括：第一晶体管和第二晶体管，
    所述第一晶体管的第一极连接所述第一电源信号端，所述第一晶体管的第二极连接所述第二控制点，所述第一晶体管的栅极连接所述第一控制信号端；
    所述第二晶体管的第一极连接所述第二电源信号端，所述第二晶体管的第二极连接所述第一控制点，所述第二晶体管的栅极连接所述第一控制信号端。
  3. 根据权利要求1所述的像素电路，其特征在于，
    所述补偿模块包括：第三晶体管，
    所述第三晶体管的第一极连接所述第三电源信号端，所述第三晶体管的第二极连接所述第三控制点，所述第三晶体管的栅极连接所述第一控制信号端。
  4. 根据权利要求1所述的像素电路，其特征在于，
    所述驱动控制模块包括：第四晶体管、第五晶体管和第六晶体管，
    所述第四晶体管的第一极连接所述第一电源信号端，所述第四晶体管的第二极连接所述第二控制点，所述第四晶体管的栅极连接所述第三控制信号端；
    所述第五晶体管的第一极连接所述第二控制点，所述第五晶体管的第二极连接所述第四控制点，所述第五晶体管的栅极连接所述第二控制信号端；
    所述第六晶体管的第一极连接所述第四控制点，所述第六晶体管的第二极连接数据信号端，所述第六晶体管的栅极连接所述第三控制信号端。
  5. 根据权利要求1所述的像素电路，其特征在于，
    所述供电模块包括：第七晶体管，
    所述第七晶体管的第一极连接所述第二电源信号端，所述第七晶体管的第二极连接所述第一控制点，所述第七晶体管的栅极连接所述第二控制信号端。
  6. 根据权利要求1所述的像素电路，其特征在于，
    所述驱动模块包括：第八晶体管，所述驱动模块的阈值电压包括：所述第八晶体管的阈值电压，
    所述第八晶体管的第一极连接所述第一控制点，所述第八晶体管的第二极连接所述第三控制点，所述第八晶体管的栅极连接所述第四控制点。
  7. 根据权利要求1所述的像素电路，其特征在于，
    所述储能模块包括：电容，
    所述电容的一端连接所述第一控制点，所述电容的另一端连接所述第二控制点。
  8. 根据权利要求1所述的像素电路，其特征在于，
    所述发光模块包括：有机发光二极管，
    所述有机发光二极管的一端连接所述第三控制点，所述有机发光二极管的另一端连接所述第四电源信号端。
  9. 根据权利要求1至8任一权利要求所述的像素电路，其特征在于，
    所述第一电源信号端接地。
  10. 根据权利要求2至8任一权利要求所述的像素电路，其特征在于，
    所述晶体管均为N型晶体管；或者所述晶体管均为P型晶体管。
  11. 根据权利要求10所述的像素电路，其特征在于，
    当所述晶体管为P型晶体管时，所述晶体管的第一极为源极，所述晶体管的第二极为漏极。
  12. 一种用于如权利要求1所述的像素电路的像素电路驱动方法，，所述像素电路驱动方法包括：
    第一控制信号端输入导通控制信号，第一电源信号端输入第一电压，第二电源信号端输入第二电压，第三电源信号端输入第三电压，使得所述第一电压写入第二控制点，所述第二电压写入第一控制点，所述第三电压写入第三控制点；
    所述第一控制信号端输入关闭控制信号，第三控制信号端输入导通控制信号，数据信号端输入数据电压，所述第一电源信号端输入所述第一电压，使得所述数据电压写入第四控制点，所述第一电压写入所述第二控制点，所述驱动 模块在所述第一控制点电压和所述第四控制点电压的控制下通过所述发光模块进行放电；
    所述第三控制信号端输入关闭控制信号，第二控制信号端输入导通控制信号，所述第二电源信号端输入所述第二电压，使得所述第二电压写入所述第一控制点，通过所述驱动模块的电流驱动所述发光模块发光；
    其中，所述第三电压大于所述数据电压与所述驱动模块的阈值电压之差，且小于所述第二电压。
  13. 根据权利要求12的像素电路驱动方法，其特征在于，
    所述复位模块包括：第一晶体管和第二晶体管，所述补偿模块包括：第三晶体管，所述驱动控制模块包括：第四晶体管、第五晶体管和第六晶体管，所述供电模块包括：第七晶体管，所述驱动模块包括：第八晶体管，所述储能模块包括：电容，所述发光模块包括：有机发光二极管，
    当所述第一控制信号端输入导通控制信号时，所述第一晶体管、所述第二晶体管和所述第三晶体管导通；
    当所述第一控制信号端输入关闭控制信号时，所述第一晶体管、所述第二晶体管和所述第三晶体管关闭；
    当所述第三控制信号端输入导通控制信号时，所述第四晶体管和所述第六晶体管导通；
    当所述第三控制信号端输入关闭控制信号时，所述第四晶体管和所述第六晶体管关闭；当所述第二控制信号端输入导通控制信号时，所述第五晶体管和所述第七晶体管导通。
  14. 根据权利要求13所述的像素电路驱动方法，其特征在于，当所述晶体管均为P型晶体管时，控制信号的时序包括：
    第一阶段：所述第一控制信号端输入低电平，所述第二控制信号端和所述第三控制信号端输入高电平，所述第一电源信号端输入所述第一电压，所述第二电源信号端输入所述第二电压，所述第三电源信号端输入所述第三电压，所述第三电压大于所述第八晶体管的阈值电压，且小于所述第二电压；
    第二阶段：所述第三控制信号端输入低电平，所述第一控制信号端和所述 第二控制信号端输入高电平，所述数据信号端输入所述数据电压，所述第一电源信号端输入所述第一电压；
    第三阶段：所述第二控制信号端输入低电平，所述第一控制信号端和所述第三控制信号端输入高电平，所述第二电源信号端输入所述第二电压。
  15. 一种显示装置，其特征在于，包括权利要求1至11任一所述的像素电路。
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